VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 9062

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1/* $Id: HWACCM.cpp 9062 2008-05-23 07:39:08Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48
49/* Uncomment to enable experimental nested paging. */
50//#define VBOX_WITH_NESTED_PAGING
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
56static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
57
58
59/**
60 * Initializes the HWACCM.
61 *
62 * @returns VBox status code.
63 * @param pVM The VM to operate on.
64 */
65HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
66{
67 LogFlow(("HWACCMR3Init\n"));
68
69 /*
70 * Assert alignment and sizes.
71 */
72 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
73 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
74
75 /* Some structure checks. */
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
80
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
85 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
86 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
87 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
88
89
90 /*
91 * Register the saved state data unit.
92 */
93 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
94 NULL, hwaccmR3Save, NULL,
95 NULL, hwaccmR3Load, NULL);
96 if (VBOX_FAILURE(rc))
97 return rc;
98
99 /* Misc initialisation. */
100 pVM->hwaccm.s.vmx.fSupported = false;
101 pVM->hwaccm.s.svm.fSupported = false;
102 pVM->hwaccm.s.vmx.fEnabled = false;
103 pVM->hwaccm.s.svm.fEnabled = false;
104
105 pVM->hwaccm.s.fActive = false;
106 pVM->hwaccm.s.fNestedPaging = false;
107
108 /* On first entry we'll sync everything. */
109 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
110
111 pVM->hwaccm.s.vmx.cr0_mask = 0;
112 pVM->hwaccm.s.vmx.cr4_mask = 0;
113
114 /*
115 * Statistics.
116 */
117 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
118 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
119 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
120
121 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
122 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
123 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
124 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
125 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
126 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
127 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
128 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
129 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
130 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
131 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
132 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
133 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
134 STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
135 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
136 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
137 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
138 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
139 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
140 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
141 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
142 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
143 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
144 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
145 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
146 STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
147
148 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
149 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
150
151 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
152 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
153 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
154
155 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
157 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
158 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
159 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
160 STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
161 STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
162
163 pVM->hwaccm.s.pStatExitReason = 0;
164
165#ifdef VBOX_WITH_STATISTICS
166 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
167 AssertRC(rc);
168 if (VBOX_SUCCESS(rc))
169 {
170 for (int i=0;i<MAX_EXITREASON_STAT;i++)
171 {
172 char szName[64];
173 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
174 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
175 AssertRC(rc);
176 }
177 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
178 AssertRC(rc);
179 }
180 pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
181 Assert(pVM->hwaccm.s.pStatExitReasonR0);
182#endif
183
184 /* Disabled by default. */
185 pVM->fHWACCMEnabled = false;
186
187 /* HWACCM support must be explicitely enabled in the configuration file. */
188 pVM->hwaccm.s.fAllowed = false;
189 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
190
191 return VINF_SUCCESS;
192}
193
194
195/**
196 * Turns off normal raw mode features
197 *
198 * @param pVM The VM to operate on.
199 */
200static void hwaccmr3DisableRawMode(PVM pVM)
201{
202 /* Disable PATM & CSAM. */
203 PATMR3AllowPatching(pVM, false);
204 CSAMDisableScanning(pVM);
205
206 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
207 SELMR3DisableMonitoring(pVM);
208 TRPMR3DisableMonitoring(pVM);
209
210 /* The hidden selector registers are now valid. */
211 CPUMSetHiddenSelRegsValid(pVM, true);
212
213 /* Disable the switcher code (safety precaution). */
214 VMMR3DisableSwitcher(pVM);
215
216 /* Disable mapping of the hypervisor into the shadow page table. */
217 PGMR3ChangeShwPDMappings(pVM, false);
218
219 /* Disable the switcher */
220 VMMR3DisableSwitcher(pVM);
221
222 if (pVM->hwaccm.s.fNestedPaging)
223 {
224 /* Reinit the paging mode to force the new shadow mode. */
225 PGMR3ChangeMode(pVM, PGMMODE_REAL);
226 }
227}
228
229/**
230 * Initialize VT-x or AMD-V.
231 *
232 * @returns VBox status code.
233 * @param pVM The VM handle.
234 */
235HWACCMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
236{
237 int rc;
238
239 if ( !pVM->hwaccm.s.vmx.fSupported
240 && !pVM->hwaccm.s.svm.fSupported)
241 {
242 LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
243 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
244 return VINF_SUCCESS;
245 }
246
247 /*
248 * Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
249 * because it turns off paging, which is not allowed in VMX root mode.
250 *
251 * To simplify matters we'll just force all running VMs to either use raw or hwaccm mode. No mixing allowed.
252 *
253 */
254 /* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
255 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
256 if (VBOX_FAILURE(rc))
257 {
258 LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
259 LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
260 /* Invert the selection */
261 pVM->hwaccm.s.fAllowed ^= 1;
262 LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
263
264 if (pVM->hwaccm.s.fAllowed)
265 {
266 if (pVM->hwaccm.s.vmx.fSupported)
267 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
268 else
269 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
270 }
271 else
272 VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
273 }
274
275 if (pVM->hwaccm.s.fAllowed == false)
276 return VINF_SUCCESS; /* disabled */
277
278 Assert(!pVM->fHWACCMEnabled);
279
280 if (pVM->hwaccm.s.vmx.fSupported)
281 {
282 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
283
284 if ( pVM->hwaccm.s.fInitialized == false
285 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
286 {
287 uint64_t val;
288
289 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
290 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
291 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
292 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
293 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
294 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
295 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297
298 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
299 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
300 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
301 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
302 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
303 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
304 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
305 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
306 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
307 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
308 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
309
310 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
311 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
312 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
313 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
314 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
315 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
316 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
317 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
318 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
319 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
320 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
321 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
322 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
323 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
324 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
325 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
326 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
327 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
328 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
329 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
330 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
331 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
332 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
333 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
334 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
335 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
336 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
337 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
338 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
339 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
340 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
341 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
342 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
343 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
344 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
345 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
346 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
347 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
348 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
349 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
350 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
351 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
352 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
353 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
354 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
355 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
356 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
357 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
358 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
359 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
360 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
361 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
362 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
363 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
364 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
365 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
366 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
367 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
368 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
369 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
370 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
371 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
372 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
373 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
374 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
375 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
376 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
377
378 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
379 val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
380 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
381 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
382 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
383 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
384 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
385 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
386 val = pVM->hwaccm.s.vmx.msr.vmx_entry;
387 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
388 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
389 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
390 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
391 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
392 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
393
394 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
395 val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
396 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
397 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
398 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
399 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
400 val = pVM->hwaccm.s.vmx.msr.vmx_exit;
401 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
402 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
403 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
404 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
405
406 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
407 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
408 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
409 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
410 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411
412 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
413 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
414 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
415 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
416 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
417
418 /* Only try once. */
419 pVM->hwaccm.s.fInitialized = true;
420
421 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
422 AssertRC(rc);
423 if (rc == VINF_SUCCESS)
424 {
425 pVM->fHWACCMEnabled = true;
426 pVM->hwaccm.s.vmx.fEnabled = true;
427 hwaccmr3DisableRawMode(pVM);
428
429 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
430 LogRel(("HWACCM: VMX enabled!\n"));
431 }
432 else
433 {
434 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
435 LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
436 pVM->fHWACCMEnabled = false;
437 }
438 }
439 }
440 else
441 if (pVM->hwaccm.s.svm.fSupported)
442 {
443 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
444
445 if (pVM->hwaccm.s.fInitialized == false)
446 {
447 /* Erratum 170 which requires a forced TLB flush for each world switch:
448 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
449 *
450 * All BH-G1/2 and DH-G1/2 models include a fix:
451 * Athlon X2: 0x6b 1/2
452 * 0x68 1/2
453 * Athlon 64: 0x7f 1
454 * 0x6f 2
455 * Sempron: 0x7f 1/2
456 * 0x6f 2
457 * 0x6c 2
458 * 0x7c 2
459 * Turion 64: 0x68 2
460 *
461 */
462 uint32_t u32Dummy;
463 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
464 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
465 u32BaseFamily= (u32Version >> 8) & 0xf;
466 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
467 u32Model = ((u32Version >> 4) & 0xf);
468 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
469 u32Stepping = u32Version & 0xf;
470 if ( u32Family == 0xf
471 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
472 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
473 {
474 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
475 }
476
477 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
478 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
479 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
480 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
481 LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
482
483 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
484 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
485 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
486 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
487 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
488 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
489 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
490 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
491 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
492 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
493
494 /* Only try once. */
495 pVM->hwaccm.s.fInitialized = true;
496
497#ifdef VBOX_WITH_NESTED_PAGING
498 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
499 pVM->hwaccm.s.fNestedPaging = true;
500#endif
501
502 rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
503 AssertRC(rc);
504 if (rc == VINF_SUCCESS)
505 {
506 pVM->fHWACCMEnabled = true;
507 pVM->hwaccm.s.svm.fEnabled = true;
508
509 hwaccmr3DisableRawMode(pVM);
510 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
511 }
512 else
513 {
514 pVM->fHWACCMEnabled = false;
515 }
516 }
517 }
518 return VINF_SUCCESS;
519}
520
521/**
522 * Applies relocations to data and code managed by this
523 * component. This function will be called at init and
524 * whenever the VMM need to relocate it self inside the GC.
525 *
526 * @param pVM The VM.
527 */
528HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
529{
530 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
531 return;
532}
533
534
535/**
536 * Checks hardware accelerated raw mode is allowed.
537 *
538 * @returns boolean
539 * @param pVM The VM to operate on.
540 */
541HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
542{
543 return pVM->hwaccm.s.fAllowed;
544}
545
546
547/**
548 * Notification callback which is called whenever there is a chance that a CR3
549 * value might have changed.
550 * This is called by PGM.
551 *
552 * @param pVM The VM to operate on.
553 * @param enmShadowMode New paging mode.
554 */
555HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
556{
557 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
558}
559
560/**
561 * Terminates the HWACCM.
562 *
563 * Termination means cleaning up and freeing all resources,
564 * the VM it self is at this point powered off or suspended.
565 *
566 * @returns VBox status code.
567 * @param pVM The VM to operate on.
568 */
569HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
570{
571 if (pVM->hwaccm.s.pStatExitReason)
572 {
573 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
574 pVM->hwaccm.s.pStatExitReason = 0;
575 }
576 return 0;
577}
578
579
580/**
581 * The VM is being reset.
582 *
583 * For the HWACCM component this means that any GDT/LDT/TSS monitors
584 * needs to be removed.
585 *
586 * @param pVM VM handle.
587 */
588HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
589{
590 LogFlow(("HWACCMR3Reset:\n"));
591
592 if (pVM->fHWACCMEnabled)
593 hwaccmr3DisableRawMode(pVM);
594
595 /* On first entry we'll sync everything. */
596 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
597
598 pVM->hwaccm.s.vmx.cr0_mask = 0;
599 pVM->hwaccm.s.vmx.cr4_mask = 0;
600
601 pVM->hwaccm.s.Event.fPending = false;
602}
603
604/**
605 * Checks if we can currently use hardware accelerated raw mode.
606 *
607 * @returns boolean
608 * @param pVM The VM to operate on.
609 * @param pCtx Partial VM execution context
610 */
611HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
612{
613 Assert(pVM->fHWACCMEnabled);
614
615 /* AMD SVM supports real & protected mode with or without paging. */
616 if (pVM->hwaccm.s.svm.fEnabled)
617 {
618 pVM->hwaccm.s.fActive = true;
619 return true;
620 }
621
622 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
623 * (but do we really care?)
624 */
625
626 pVM->hwaccm.s.fActive = false;
627
628 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
629
630#ifndef HWACCM_VMX_EMULATE_ALL
631 /* Too early for VMX. */
632 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
633 return false;
634
635 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
636 if (pCtx->csHid.Attr.n.u1Present == 0)
637 return false;
638 if (pCtx->ssHid.Attr.n.u1Present == 0)
639 return false;
640#endif
641
642 if (pVM->hwaccm.s.vmx.fEnabled)
643 {
644 uint32_t mask;
645
646 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
647 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
648 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
649 mask &= ~X86_CR0_NE;
650#ifdef HWACCM_VMX_EMULATE_ALL
651 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
652 mask &= ~(X86_CR0_PG|X86_CR0_PE);
653#endif
654 if ((pCtx->cr0 & mask) != mask)
655 return false;
656
657 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
658 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
659 if ((pCtx->cr0 & mask) != 0)
660 return false;
661
662 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
663 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
664 mask &= ~X86_CR4_VMXE;
665 if ((pCtx->cr4 & mask) != mask)
666 return false;
667
668 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
669 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
670 if ((pCtx->cr4 & mask) != 0)
671 return false;
672
673 pVM->hwaccm.s.fActive = true;
674 return true;
675 }
676
677 return false;
678}
679
680/**
681 * Checks if we are currently using hardware accelerated raw mode.
682 *
683 * @returns boolean
684 * @param pVM The VM to operate on.
685 */
686HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
687{
688 return pVM->hwaccm.s.fActive;
689}
690
691/**
692 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
693 *
694 * @returns boolean
695 * @param pVM The VM to operate on.
696 */
697HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
698{
699 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
700}
701
702/**
703 * Execute state save operation.
704 *
705 * @returns VBox status code.
706 * @param pVM VM Handle.
707 * @param pSSM SSM operation handle.
708 */
709static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
710{
711 int rc;
712
713 Log(("hwaccmR3Save:\n"));
714
715 /*
716 * Save the basic bits - fortunately all the other things can be resynced on load.
717 */
718 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
719 AssertRCReturn(rc, rc);
720 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
721 AssertRCReturn(rc, rc);
722 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
723 AssertRCReturn(rc, rc);
724
725 return VINF_SUCCESS;
726}
727
728
729/**
730 * Execute state load operation.
731 *
732 * @returns VBox status code.
733 * @param pVM VM Handle.
734 * @param pSSM SSM operation handle.
735 * @param u32Version Data layout version.
736 */
737static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
738{
739 int rc;
740
741 Log(("hwaccmR3Load:\n"));
742
743 /*
744 * Validate version.
745 */
746 if (u32Version != HWACCM_SSM_VERSION)
747 {
748 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
749 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
750 }
751 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
752 AssertRCReturn(rc, rc);
753 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
754 AssertRCReturn(rc, rc);
755 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
756 AssertRCReturn(rc, rc);
757
758 return VINF_SUCCESS;
759}
760
761
762
763
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