HWACCM.cpp@ 4000

Last change on this file since 4000 was 4000, checked in by vboxsync, 17 years ago
uint32_t -> int32_t
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 34.1 KB

Line
1	/* $Id: HWACCM.cpp 4000 2007-08-02 11:27:42Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57	/**
58	* Initializes the HWACCM.
59	*
60	* @returns VBox status code.
61	* @param pVM The VM to operate on.
62	*/
63	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
64	{
65	LogFlow(("HWACCMR3Init\n"));
66
67	/*
68	* Assert alignment and sizes.
69	*/
70	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73	/* Some structure checks. */
74	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88	/*
89	* Register the saved state data unit.
90	*/
91	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92	NULL, hwaccmR3Save, NULL,
93	NULL, hwaccmR3Load, NULL);
94	if (VBOX_FAILURE(rc))
95	return rc;
96
97	/** @todo Make sure both pages are either not accessible or readonly! */
98	/* Allocate one page for VMXON. */
99	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
100	if (pVM->hwaccm.s.vmx.pVMXON == 0)
101	{
102	AssertMsgFailed(("SUPContAlloc failed!!\n"));
103	return VERR_NO_MEMORY;
104	}
105	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
106
107	/* Allocate one page for the VM control structure (VMCS). */
108	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
109	if (pVM->hwaccm.s.vmx.pVMCS == 0)
110	{
111	AssertMsgFailed(("SUPContAlloc failed!!\n"));
112	return VERR_NO_MEMORY;
113	}
114	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
115
116	/* Allocate one page for the TSS we need for real mode emulation. */
117	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)SUPContAlloc(1, &pVM->hwaccm.s.vmx.pRealModeTSSPhys);
118	if (pVM->hwaccm.s.vmx.pRealModeTSS == 0)
119	{
120	AssertMsgFailed(("SUPContAlloc failed!!\n"));
121	return VERR_NO_MEMORY;
122	}
123	/* We initialize it properly later as we can reuse it for SVM */
124	memset(pVM->hwaccm.s.vmx.pRealModeTSS, 0, PAGE_SIZE);
125
126	/* Reuse those three pages for AMD SVM. (one is active; never both) */
127	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
128	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
129	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
130	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
131	pVM->hwaccm.s.svm.pVMCBHost = pVM->hwaccm.s.vmx.pRealModeTSS;
132	pVM->hwaccm.s.svm.pVMCBHostPhys = pVM->hwaccm.s.vmx.pRealModeTSSPhys;
133
134	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
135	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
136	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
137	{
138	AssertMsgFailed(("SUPContAlloc failed!!\n"));
139	return VERR_NO_MEMORY;
140	}
141	/* Set all bits to intercept all IO accesses. */
142	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
143
144	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
145	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
146	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
147	{
148	AssertMsgFailed(("SUPContAlloc failed!!\n"));
149	return VERR_NO_MEMORY;
150	}
151	/* Set all bits to intercept all MSR accesses. */
152	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
153
154	/* Misc initialisation. */
155	pVM->hwaccm.s.vmx.fSupported = false;
156	pVM->hwaccm.s.svm.fSupported = false;
157	pVM->hwaccm.s.vmx.fEnabled = false;
158	pVM->hwaccm.s.svm.fEnabled = false;
159
160	pVM->hwaccm.s.fActive = false;
161
162	/* On first entry we'll sync everything. */
163	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
164
165	pVM->hwaccm.s.vmx.cr0_mask = 0;
166	pVM->hwaccm.s.vmx.cr4_mask = 0;
167
168	/*
169	* Statistics.
170	*/
171	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
172	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
173	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
174
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
195	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
196	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
198	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
199	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
200
201	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
202	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
203
204	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
205	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
206	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
207
208	pVM->hwaccm.s.pStatExitReason = 0;
209
210	#ifdef VBOX_WITH_STATISTICS
211	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
212	AssertRC(rc);
213	if (VBOX_SUCCESS(rc))
214	{
215	for (int i=0;i<MAX_EXITREASON_STAT;i++)
216	{
217	char szName[64];
218	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
219	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
220	AssertRC(rc);
221	}
222	}
223	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
224	Assert(pVM->hwaccm.s.pStatExitReasonR0);
225	#endif
226
227	/* Disabled by default. */
228	pVM->fHWACCMEnabled = false;
229
230	/* HWACCM support must be explicitely enabled in the configuration file. */
231	pVM->hwaccm.s.fAllowed = false;
232	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
233
234	return VINF_SUCCESS;
235	}
236
237
238	/**
239	* Turns off normal raw mode features
240	*
241	* @param pVM The VM to operate on.
242	*/
243	static void hwaccmr3DisableRawMode(PVM pVM)
244	{
245	/* Disable PATM & CSAM. */
246	PATMR3AllowPatching(pVM, false);
247	CSAMDisableScanning(pVM);
248
249	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
250	SELMR3DisableMonitoring(pVM);
251	TRPMR3DisableMonitoring(pVM);
252
253	/* The hidden selector registers are now valid. */
254	CPUMSetHiddenSelRegsValid(pVM, true);
255
256	/* Disable the switcher code (safety precaution). */
257	VMMR3DisableSwitcher(pVM);
258
259	/* Disable mapping of the hypervisor into the shadow page table. */
260	PGMR3ChangeShwPDMappings(pVM, false);
261
262	/* Disable the switcher */
263	VMMR3DisableSwitcher(pVM);
264	}
265
266	/**
267	* Applies relocations to data and code managed by this
268	* component. This function will be called at init and
269	* whenever the VMM need to relocate it self inside the GC.
270	*
271	* @param pVM The VM.
272	*/
273	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
274	{
275	#ifdef LOG_ENABLED
276	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
277	#endif
278
279	if (pVM->hwaccm.s.fAllowed == false)
280	return ;
281
282	if (pVM->hwaccm.s.vmx.fSupported)
283	{
284	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
285
286	if ( pVM->hwaccm.s.fInitialized == false
287	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
288	{
289	uint64_t val;
290
291	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
292	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
293	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
294	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
295	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
297	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
298	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
299
300	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
301	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
302	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
303	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
304	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
305	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
306	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
307	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
308	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
309	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
310	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
311
312	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
313	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
314	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
315	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
316	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
317	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
318	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
319	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
320	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
321	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
322	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
323	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
324	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
325	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
326	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
327	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
328	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
329	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
330	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
331	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
332	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
333	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
334	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
335	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
336	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
337	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
338	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
339	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
340	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
341	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
342	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
343	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
344	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
345	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
346	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
347	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
348	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
349	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
350	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
351	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
352	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
353	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
354	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
355	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
356	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
357	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
358	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
359	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
360	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
361	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
362	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
363	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
364	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
365	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
366	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
367	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
368	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
369	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
370	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
371	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
372	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
373	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
374	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
375	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
376	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
377	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
378	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
379
380	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
381	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
382	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
383	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
384	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
385	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
386	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
387	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
388	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
389	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
390	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
391	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
392	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
393	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
394	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
395
396	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
397	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
398	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
399	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
400	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
401	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
402	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
403	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
404	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
405	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
406	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
407
408	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
409	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
410	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
412	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
413
414	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
415	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
416	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
417	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
418	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
419
420	/* Only try once. */
421	pVM->hwaccm.s.fInitialized = true;
422
423	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
424	* for I/O operations. */
425	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
426	/* Bit set to 0 means redirection enabled. */
427	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
428
429	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
430	AssertRC(rc);
431	if (rc == VINF_SUCCESS)
432	{
433	hwaccmr3DisableRawMode(pVM);
434
435	pVM->fHWACCMEnabled = true;
436	pVM->hwaccm.s.vmx.fEnabled = true;
437	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
438	LogRel(("HWACCM: VMX enabled!\n"));
439	}
440	else
441	{
442	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
443	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
444	pVM->fHWACCMEnabled = false;
445	}
446	}
447	}
448	else
449	if (pVM->hwaccm.s.svm.fSupported)
450	{
451	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
452
453	if (pVM->hwaccm.s.fInitialized == false)
454	{
455	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
456	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
457	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
458	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
459
460	/* Only try once. */
461	pVM->hwaccm.s.fInitialized = true;
462
463	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
464	AssertRC(rc);
465	if (rc == VINF_SUCCESS)
466	{
467	hwaccmr3DisableRawMode(pVM);
468	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
469
470	pVM->fHWACCMEnabled = true;
471	pVM->hwaccm.s.svm.fEnabled = true;
472	}
473	else
474	{
475	pVM->fHWACCMEnabled = false;
476	}
477	}
478	}
479	else
480	if (pVM->hwaccm.s.fHWACCMR0Init)
481	{
482	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
483	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
484	}
485
486	}
487
488
489	/**
490	* Checks hardware accelerated raw mode is allowed.
491	*
492	* @returns boolean
493	* @param pVM The VM to operate on.
494	*/
495	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
496	{
497	return pVM->hwaccm.s.fAllowed;
498	}
499
500
501	/**
502	* Notification callback which is called whenever there is a chance that a CR3
503	* value might have changed.
504	* This is called by PGM.
505	*
506	* @param pVM The VM to operate on.
507	* @param enmShadowMode New paging mode.
508	*/
509	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
510	{
511	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
512	}
513
514	/**
515	* Terminates the HWACCM.
516	*
517	* Termination means cleaning up and freeing all resources,
518	* the VM it self is at this point powered off or suspended.
519	*
520	* @returns VBox status code.
521	* @param pVM The VM to operate on.
522	*/
523	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
524	{
525	if (pVM->hwaccm.s.pStatExitReason)
526	{
527	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
528	pVM->hwaccm.s.pStatExitReason = 0;
529	}
530
531	if (pVM->hwaccm.s.vmx.pVMXON)
532	{
533	SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
534	pVM->hwaccm.s.vmx.pVMXON = 0;
535	}
536	if (pVM->hwaccm.s.vmx.pVMCS)
537	{
538	SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
539	pVM->hwaccm.s.vmx.pVMCS = 0;
540	}
541	if (pVM->hwaccm.s.vmx.pRealModeTSS)
542	{
543	SUPContFree(pVM->hwaccm.s.vmx.pRealModeTSS, 1);
544	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
545	}
546	if (pVM->hwaccm.s.svm.pIOBitmap)
547	{
548	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
549	pVM->hwaccm.s.svm.pIOBitmap = 0;
550	}
551	if (pVM->hwaccm.s.svm.pMSRBitmap)
552	{
553	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
554	pVM->hwaccm.s.svm.pMSRBitmap = 0;
555	}
556	return 0;
557	}
558
559
560	/**
561	* The VM is being reset.
562	*
563	* For the HWACCM component this means that any GDT/LDT/TSS monitors
564	* needs to be removed.
565	*
566	* @param pVM VM handle.
567	*/
568	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
569	{
570	LogFlow(("HWACCMR3Reset:\n"));
571
572	if (pVM->fHWACCMEnabled)
573	hwaccmr3DisableRawMode(pVM);
574
575	/* On first entry we'll sync everything. */
576	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
577
578	pVM->hwaccm.s.vmx.cr0_mask = 0;
579	pVM->hwaccm.s.vmx.cr4_mask = 0;
580
581	pVM->hwaccm.s.Event.fPending = false;
582	}
583
584	/**
585	* Checks if we can currently use hardware accelerated raw mode.
586	*
587	* @returns boolean
588	* @param pVM The VM to operate on.
589	* @param pCtx Partial VM execution context
590	*/
591	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
592	{
593	uint32_t mask;
594
595	Assert(pVM->fHWACCMEnabled);
596
597	/* AMD SVM supports real & protected mode with or without paging. */
598	if (pVM->hwaccm.s.svm.fEnabled)
599	{
600	pVM->hwaccm.s.fActive = true;
601	return true;
602	}
603
604	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
605	* (but do we really care?)
606	*/
607
608	pVM->hwaccm.s.fActive = false;
609
610	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
611
612	#ifndef HWACCM_VMX_EMULATE_ALL
613	/* Too early for VMX. */
614	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
615	return false;
616
617	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
618	if (pCtx->csHid.Attr.n.u1Present == 0)
619	return false;
620	if (pCtx->ssHid.Attr.n.u1Present == 0)
621	return false;
622
623	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
624	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
625	return false;
626	#endif
627
628	if (pVM->hwaccm.s.vmx.fEnabled)
629	{
630	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
631	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
632	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
633	mask &= ~X86_CR0_NE;
634	#ifdef HWACCM_VMX_EMULATE_ALL
635	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
636	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
637	#endif
638	if ((pCtx->cr0 & mask) != mask)
639	return false;
640
641	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
642	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
643	if ((pCtx->cr0 & mask) != 0)
644	return false;
645
646	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
647	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
648	mask &= ~X86_CR4_VMXE;
649	if ((pCtx->cr4 & mask) != mask)
650	return false;
651
652	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
653	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
654	if ((pCtx->cr4 & mask) != 0)
655	return false;
656
657	pVM->hwaccm.s.fActive = true;
658	return true;
659	}
660
661	return false;
662	}
663
664	/**
665	* Checks if we are currently using hardware accelerated raw mode.
666	*
667	* @returns boolean
668	* @param pVM The VM to operate on.
669	*/
670	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
671	{
672	return pVM->hwaccm.s.fActive;
673	}
674
675	/**
676	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
677	*
678	* @returns boolean
679	* @param pVM The VM to operate on.
680	*/
681	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
682	{
683	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
684	}
685
686	/**
687	* Execute state save operation.
688	*
689	* @returns VBox status code.
690	* @param pVM VM Handle.
691	* @param pSSM SSM operation handle.
692	*/
693	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
694	{
695	int rc;
696
697	Log(("hwaccmR3Save:\n"));
698
699	/*
700	* Save the basic bits - fortunately all the other things can be resynced on load.
701	*/
702	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
703	AssertRCReturn(rc, rc);
704	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
705	AssertRCReturn(rc, rc);
706	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
707	AssertRCReturn(rc, rc);
708
709	return VINF_SUCCESS;
710	}
711
712
713	/**
714	* Execute state load operation.
715	*
716	* @returns VBox status code.
717	* @param pVM VM Handle.
718	* @param pSSM SSM operation handle.
719	* @param u32Version Data layout version.
720	*/
721	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
722	{
723	int rc;
724
725	Log(("hwaccmR3Load:\n"));
726
727	/*
728	* Validate version.
729	*/
730	if (u32Version != HWACCM_SSM_VERSION)
731	{
732	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
733	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
734	}
735	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
736	AssertRCReturn(rc, rc);
737	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
738	AssertRCReturn(rc, rc);
739	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
740	AssertRCReturn(rc, rc);
741
742	return VINF_SUCCESS;
743	}
744
745
746
747

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 4000

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