1 | /* $Id: HWACCM.cpp 397 2007-01-28 02:34:06Z vboxsync $ */
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2 | /** @file
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3 | * HWACCM - Intel/AMD VM Hardware Support Manager
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006 InnoTek Systemberatung GmbH
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License as published by the Free Software Foundation,
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13 | * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
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14 | * distribution. VirtualBox OSE is distributed in the hope that it will
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15 | * be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * If you received this file as part of a commercial VirtualBox
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18 | * distribution, then only the terms of your commercial VirtualBox
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19 | * license agreement apply instead of the previous paragraph.
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20 | */
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21 |
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22 | /*******************************************************************************
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23 | * Header Files *
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24 | *******************************************************************************/
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25 | #define LOG_GROUP LOG_GROUP_HWACCM
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26 | #include <VBox/cpum.h>
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27 | #include <VBox/stam.h>
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28 | #include <VBox/mm.h>
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29 | #include <VBox/pdm.h>
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30 | #include <VBox/pgm.h>
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31 | #include <VBox/trpm.h>
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32 | #include <VBox/dbgf.h>
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33 | #include <VBox/hwacc_vmx.h>
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34 | #include <VBox/hwacc_svm.h>
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35 | #include "HWACCMInternal.h"
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36 | #include <VBox/vm.h>
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37 | #include <VBox/err.h>
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38 | #include <VBox/param.h>
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39 | #include <VBox/patm.h>
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40 | #include <VBox/csam.h>
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41 | #include <VBox/selm.h>
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42 |
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43 | #include <iprt/assert.h>
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44 | #include <VBox/log.h>
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45 | #include <iprt/asm.h>
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46 | #include <iprt/string.h>
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47 | #include <iprt/thread.h>
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48 | #include "x86context.h"
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49 |
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50 |
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51 | /*******************************************************************************
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52 | * Internal Functions *
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53 | *******************************************************************************/
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54 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
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55 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
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56 |
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57 |
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58 | /**
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59 | * Initializes the HWACCM.
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60 | *
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61 | * @returns VBox status code.
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62 | * @param pVM The VM to operate on.
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63 | */
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64 | HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
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65 | {
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66 | LogFlow(("HWACCMR3Init\n"));
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67 |
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68 | /*
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69 | * Assert alignment and sizes.
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70 | */
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71 | AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
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72 | AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
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73 |
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74 | /* Some structure checks. */
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75 | AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
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76 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
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77 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
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78 | AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
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79 |
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80 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
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81 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
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82 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
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83 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
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84 | AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
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85 | AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
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86 | AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
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87 |
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88 |
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89 | /*
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90 | * Register the saved state data unit.
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91 | */
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92 | int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
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93 | NULL, hwaccmR3Save, NULL,
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94 | NULL, hwaccmR3Load, NULL);
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95 | if (VBOX_FAILURE(rc))
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96 | return rc;
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97 |
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98 | /** @todo Make sure both pages are either not accessible or readonly! */
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99 | /* Allocate one page for VMXON. */
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100 | pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMXONPhys);
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101 | if (pVM->hwaccm.s.vmx.pVMXON == 0)
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102 | {
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103 | AssertMsgFailed(("SUPContAlloc failed!!\n"));
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104 | return VERR_NO_MEMORY;
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105 | }
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106 | memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
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107 |
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108 | /* Allocate one page for the VM control structure (VMCS). */
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109 | pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMCSPhys);
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110 | if (pVM->hwaccm.s.vmx.pVMCS == 0)
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111 | {
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112 | AssertMsgFailed(("SUPContAlloc failed!!\n"));
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113 | return VERR_NO_MEMORY;
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114 | }
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115 | memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
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116 |
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117 | /* Reuse those two pages for AMD SVM. (one is active; never both) */
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118 | pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
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119 | pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
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120 | pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
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121 | pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
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122 |
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123 | /* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
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124 | pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.svm.pVMCBHostPhys);
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125 | if (pVM->hwaccm.s.svm.pVMCBHost == 0)
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126 | {
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127 | AssertMsgFailed(("SUPContAlloc failed!!\n"));
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128 | return VERR_NO_MEMORY;
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129 | }
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130 | memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
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131 |
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132 | /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
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133 | pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(PAGE_SIZE*3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
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134 | if (pVM->hwaccm.s.svm.pIOBitmap == 0)
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135 | {
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136 | AssertMsgFailed(("SUPContAlloc failed!!\n"));
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137 | return VERR_NO_MEMORY;
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138 | }
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139 | /* Set all bits to intercept all IO accesses. */
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140 | memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
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141 |
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142 | /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
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143 | pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(PAGE_SIZE*2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
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144 | if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
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145 | {
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146 | AssertMsgFailed(("SUPContAlloc failed!!\n"));
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147 | return VERR_NO_MEMORY;
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148 | }
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149 | /* Set all bits to intercept all MSR accesses. */
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150 | memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
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151 |
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152 | /* Misc initialisation. */
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153 | pVM->hwaccm.s.vmx.fSupported = false;
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154 | pVM->hwaccm.s.svm.fSupported = false;
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155 | pVM->hwaccm.s.vmx.fEnabled = false;
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156 | pVM->hwaccm.s.svm.fEnabled = false;
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157 |
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158 | pVM->hwaccm.s.fActive = false;
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159 |
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160 | /* On first entry we'll sync everything. */
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161 | pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
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162 |
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163 | pVM->hwaccm.s.vmx.cr0_mask = 0;
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164 | pVM->hwaccm.s.vmx.cr4_mask = 0;
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165 |
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166 | /*
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167 | * Statistics.
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168 | */
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169 | STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
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170 | STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
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171 | STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
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172 |
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173 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
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174 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
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175 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
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176 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
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177 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
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178 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
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179 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
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180 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
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181 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
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182 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
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183 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
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184 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
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185 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
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186 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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187 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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188 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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189 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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190 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
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191 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
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192 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
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193 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
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194 | STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
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195 |
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196 | STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
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197 | STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
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198 |
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199 | STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
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200 | STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
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201 | STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
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202 |
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203 | pVM->hwaccm.s.pStatExitReason = 0;
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204 |
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205 | #ifdef VBOX_WITH_STATISTICS
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206 | rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
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207 | AssertRC(rc);
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208 | if (VBOX_SUCCESS(rc))
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209 | {
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210 | for (int i=0;i<MAX_EXITREASON_STAT;i++)
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211 | {
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212 | char szName[64];
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213 | RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
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214 | int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
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215 | AssertRC(rc);
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216 | }
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217 | }
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218 | #endif
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219 |
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220 | /* Disabled by default. */
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221 | pVM->fHWACCMEnabled = false;
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222 |
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223 | /* HWACCM support must be explicitely enabled in the configuration file. */
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224 | pVM->hwaccm.s.fAllowed = false;
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225 | CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
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226 |
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227 | return VINF_SUCCESS;
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228 | }
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229 |
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230 |
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231 | /**
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232 | * Turns off normal raw mode features
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233 | *
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234 | * @param pVM The VM to operate on.
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235 | */
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236 | static void hwaccmr3DisableRawMode(PVM pVM)
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237 | {
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238 | /* Disable PATM & CSAM. */
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239 | PATMR3AllowPatching(pVM, false);
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240 | CSAMDisableScanning(pVM);
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241 |
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242 | /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
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243 | SELMR3DisableMonitoring(pVM);
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244 | TRPMR3DisableMonitoring(pVM);
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245 |
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246 | /* The hidden selector registers are now valid. */
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247 | CPUMSetHiddenSelRegsValid(pVM, true);
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248 |
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249 | /* Disable the switcher code (safety precaution). */
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250 | VMMR3DisableSwitcher(pVM);
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251 |
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252 | /* Disable mapping of the hypervisor into the shadow page table. */
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253 | PGMR3RemoveMappingsFromShwPD(pVM);
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254 | }
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255 |
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256 | /**
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257 | * Applies relocations to data and code managed by this
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258 | * component. This function will be called at init and
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259 | * whenever the VMM need to relocate it self inside the GC.
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260 | *
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261 | * @param pVM The VM.
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262 | */
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263 | HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
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264 | {
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265 | #ifdef LOG_ENABLED
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266 | Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
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267 | #endif
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268 |
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269 | if (pVM->hwaccm.s.fAllowed == false)
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270 | return ;
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271 |
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272 | if (pVM->hwaccm.s.vmx.fSupported)
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273 | {
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274 | Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
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275 | LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
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276 | LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
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277 | LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
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278 | LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
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279 | LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
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280 | LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
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281 | LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
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282 | LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
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283 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
|
---|
284 | LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
|
---|
285 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
|
---|
286 | LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
|
---|
287 | LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
|
---|
288 |
|
---|
289 | if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
|
---|
290 | {
|
---|
291 | /* Only try once. */
|
---|
292 | pVM->hwaccm.s.fInitialized = true;
|
---|
293 |
|
---|
294 | int rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_SETUP_VM, NULL);
|
---|
295 | AssertRC(rc);
|
---|
296 | if (rc == VINF_SUCCESS)
|
---|
297 | {
|
---|
298 | hwaccmr3DisableRawMode(pVM);
|
---|
299 |
|
---|
300 | pVM->fHWACCMEnabled = true;
|
---|
301 | pVM->hwaccm.s.vmx.fEnabled = true;
|
---|
302 | LogRel(("HWACCM: VMX enabled!\n"));
|
---|
303 | }
|
---|
304 | else
|
---|
305 | {
|
---|
306 | LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
|
---|
307 | pVM->fHWACCMEnabled = false;
|
---|
308 | }
|
---|
309 | }
|
---|
310 | }
|
---|
311 | else
|
---|
312 | if (pVM->hwaccm.s.svm.fSupported)
|
---|
313 | {
|
---|
314 | Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
|
---|
315 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
|
---|
316 | LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
|
---|
317 | LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
|
---|
318 | LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
|
---|
319 |
|
---|
320 | if (pVM->hwaccm.s.fInitialized == false)
|
---|
321 | {
|
---|
322 | /* Only try once. */
|
---|
323 | pVM->hwaccm.s.fInitialized = true;
|
---|
324 |
|
---|
325 | int rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_SETUP_VM, NULL);
|
---|
326 | AssertRC(rc);
|
---|
327 | if (rc == VINF_SUCCESS)
|
---|
328 | {
|
---|
329 | #if 1
|
---|
330 | LogRel(("HWACCM: SVM supported; disabled currently\n"));
|
---|
331 | #else
|
---|
332 | hwaccmr3DisableRawMode(pVM);
|
---|
333 |
|
---|
334 | pVM->fHWACCMEnabled = true;
|
---|
335 | pVM->hwaccm.s.svm.fEnabled = true;
|
---|
336 | #endif
|
---|
337 | }
|
---|
338 | else
|
---|
339 | {
|
---|
340 | pVM->fHWACCMEnabled = false;
|
---|
341 | }
|
---|
342 | }
|
---|
343 | }
|
---|
344 |
|
---|
345 | }
|
---|
346 |
|
---|
347 |
|
---|
348 | /**
|
---|
349 | * Checks hardware accelerated raw mode is allowed.
|
---|
350 | *
|
---|
351 | * @returns boolean
|
---|
352 | * @param pVM The VM to operate on.
|
---|
353 | */
|
---|
354 | HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
|
---|
355 | {
|
---|
356 | return pVM->hwaccm.s.fAllowed;
|
---|
357 | }
|
---|
358 |
|
---|
359 |
|
---|
360 | /**
|
---|
361 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
362 | * value might have changed.
|
---|
363 | * This is called by PGM.
|
---|
364 | *
|
---|
365 | * @param pVM The VM to operate on.
|
---|
366 | * @param enmShadowMode New paging mode.
|
---|
367 | */
|
---|
368 | HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
|
---|
369 | {
|
---|
370 | pVM->hwaccm.s.enmShadowMode = enmShadowMode;
|
---|
371 | }
|
---|
372 |
|
---|
373 | /**
|
---|
374 | * Terminates the HWACCM.
|
---|
375 | *
|
---|
376 | * Termination means cleaning up and freeing all resources,
|
---|
377 | * the VM it self is at this point powered off or suspended.
|
---|
378 | *
|
---|
379 | * @returns VBox status code.
|
---|
380 | * @param pVM The VM to operate on.
|
---|
381 | */
|
---|
382 | HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
|
---|
383 | {
|
---|
384 | if (pVM->hwaccm.s.pStatExitReason)
|
---|
385 | {
|
---|
386 | MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
|
---|
387 | pVM->hwaccm.s.pStatExitReason = 0;
|
---|
388 | }
|
---|
389 |
|
---|
390 | if (pVM->hwaccm.s.vmx.pVMXON)
|
---|
391 | {
|
---|
392 | SUPContFree(pVM->hwaccm.s.vmx.pVMXON);
|
---|
393 | pVM->hwaccm.s.vmx.pVMXON = 0;
|
---|
394 | }
|
---|
395 | if (pVM->hwaccm.s.vmx.pVMCS)
|
---|
396 | {
|
---|
397 | SUPContFree(pVM->hwaccm.s.vmx.pVMCS);
|
---|
398 | pVM->hwaccm.s.vmx.pVMCS = 0;
|
---|
399 | }
|
---|
400 | if (pVM->hwaccm.s.svm.pVMCBHost)
|
---|
401 | {
|
---|
402 | SUPContFree(pVM->hwaccm.s.svm.pVMCBHost);
|
---|
403 | pVM->hwaccm.s.svm.pVMCBHost = 0;
|
---|
404 | }
|
---|
405 | if (pVM->hwaccm.s.svm.pIOBitmap)
|
---|
406 | {
|
---|
407 | SUPContFree(pVM->hwaccm.s.svm.pIOBitmap);
|
---|
408 | pVM->hwaccm.s.svm.pIOBitmap = 0;
|
---|
409 | }
|
---|
410 | if (pVM->hwaccm.s.svm.pMSRBitmap)
|
---|
411 | {
|
---|
412 | SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap);
|
---|
413 | pVM->hwaccm.s.svm.pMSRBitmap = 0;
|
---|
414 | }
|
---|
415 | return 0;
|
---|
416 | }
|
---|
417 |
|
---|
418 |
|
---|
419 | /**
|
---|
420 | * The VM is being reset.
|
---|
421 | *
|
---|
422 | * For the HWACCM component this means that any GDT/LDT/TSS monitors
|
---|
423 | * needs to be removed.
|
---|
424 | *
|
---|
425 | * @param pVM VM handle.
|
---|
426 | */
|
---|
427 | HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
|
---|
428 | {
|
---|
429 | LogFlow(("HWACCMR3Reset:\n"));
|
---|
430 |
|
---|
431 | if (pVM->fHWACCMEnabled)
|
---|
432 | hwaccmr3DisableRawMode(pVM);
|
---|
433 |
|
---|
434 | /* On first entry we'll sync everything. */
|
---|
435 | pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
|
---|
436 |
|
---|
437 | pVM->hwaccm.s.vmx.cr0_mask = 0;
|
---|
438 | pVM->hwaccm.s.vmx.cr4_mask = 0;
|
---|
439 | }
|
---|
440 |
|
---|
441 | /**
|
---|
442 | * Checks if we can currently use hardware accelerated raw mode.
|
---|
443 | *
|
---|
444 | * @returns boolean
|
---|
445 | * @param pVM The VM to operate on.
|
---|
446 | * @param pCtx Partial VM execution context
|
---|
447 | */
|
---|
448 | HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
|
---|
449 | {
|
---|
450 | uint32_t mask;
|
---|
451 |
|
---|
452 | Assert(pVM->fHWACCMEnabled);
|
---|
453 |
|
---|
454 | /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
|
---|
455 | * (but do we really care?)
|
---|
456 | */
|
---|
457 |
|
---|
458 | pVM->hwaccm.s.fActive = false;
|
---|
459 |
|
---|
460 | /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
|
---|
461 |
|
---|
462 | /* Too early for VMX and SVN (?). */
|
---|
463 | if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
|
---|
464 | return false;
|
---|
465 |
|
---|
466 | /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
|
---|
467 | if (pCtx->csHid.Attr.n.u1Present == 0)
|
---|
468 | return false;
|
---|
469 | if (pCtx->ssHid.Attr.n.u1Present == 0)
|
---|
470 | return false;
|
---|
471 |
|
---|
472 | /** @todo if we remove this check, then Windows XP install fails during the textmode phase */
|
---|
473 | if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
|
---|
474 | return false;
|
---|
475 |
|
---|
476 | if (pVM->hwaccm.s.vmx.fEnabled)
|
---|
477 | {
|
---|
478 | /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
|
---|
479 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
|
---|
480 | /** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
|
---|
481 | mask &= ~X86_CR0_NE;
|
---|
482 |
|
---|
483 | if ((pCtx->cr0 & mask) != mask)
|
---|
484 | return false;
|
---|
485 |
|
---|
486 | /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
|
---|
487 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
|
---|
488 | if ((pCtx->cr0 & mask) != 0)
|
---|
489 | return false;
|
---|
490 |
|
---|
491 | /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
|
---|
492 | mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
|
---|
493 | mask &= ~X86_CR4_VMXE;
|
---|
494 | if ((pCtx->cr4 & mask) != mask)
|
---|
495 | return false;
|
---|
496 |
|
---|
497 | /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
|
---|
498 | mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
|
---|
499 | if ((pCtx->cr4 & mask) != 0)
|
---|
500 | return false;
|
---|
501 |
|
---|
502 | pVM->hwaccm.s.fActive = true;
|
---|
503 | return true;
|
---|
504 | }
|
---|
505 | else
|
---|
506 | {
|
---|
507 | Assert(pVM->hwaccm.s.svm.fEnabled);
|
---|
508 |
|
---|
509 | /* Let's start with protected mode with paging enabled first. */
|
---|
510 | if ((pCtx->cr0 & (X86_CR0_PE|X86_CR0_PG)) == (X86_CR0_PE|X86_CR0_PG))
|
---|
511 | {
|
---|
512 | pVM->hwaccm.s.fActive = true;
|
---|
513 | return true;
|
---|
514 | }
|
---|
515 | }
|
---|
516 |
|
---|
517 | return false;
|
---|
518 | }
|
---|
519 |
|
---|
520 | /**
|
---|
521 | * Checks if we are currently using hardware accelerated raw mode.
|
---|
522 | *
|
---|
523 | * @returns boolean
|
---|
524 | * @param pVM The VM to operate on.
|
---|
525 | */
|
---|
526 | HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
|
---|
527 | {
|
---|
528 | return pVM->hwaccm.s.fActive;
|
---|
529 | }
|
---|
530 |
|
---|
531 | /**
|
---|
532 | * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
|
---|
533 | *
|
---|
534 | * @returns boolean
|
---|
535 | * @param pVM The VM to operate on.
|
---|
536 | */
|
---|
537 | HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
|
---|
538 | {
|
---|
539 | return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
|
---|
540 | }
|
---|
541 |
|
---|
542 | /**
|
---|
543 | * Execute state save operation.
|
---|
544 | *
|
---|
545 | * @returns VBox status code.
|
---|
546 | * @param pVM VM Handle.
|
---|
547 | * @param pSSM SSM operation handle.
|
---|
548 | */
|
---|
549 | static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
|
---|
550 | {
|
---|
551 | int rc;
|
---|
552 |
|
---|
553 | Log(("hwaccmR3Save:\n"));
|
---|
554 |
|
---|
555 | /*
|
---|
556 | * Save the basic bits - fortunately all the other things can be resynced on load.
|
---|
557 | */
|
---|
558 | rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
|
---|
559 | AssertRCReturn(rc, rc);
|
---|
560 | rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
|
---|
561 | AssertRCReturn(rc, rc);
|
---|
562 | rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
|
---|
563 | AssertRCReturn(rc, rc);
|
---|
564 |
|
---|
565 | return VINF_SUCCESS;
|
---|
566 | }
|
---|
567 |
|
---|
568 |
|
---|
569 | /**
|
---|
570 | * Execute state load operation.
|
---|
571 | *
|
---|
572 | * @returns VBox status code.
|
---|
573 | * @param pVM VM Handle.
|
---|
574 | * @param pSSM SSM operation handle.
|
---|
575 | * @param u32Version Data layout version.
|
---|
576 | */
|
---|
577 | static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
|
---|
578 | {
|
---|
579 | int rc;
|
---|
580 |
|
---|
581 | Log(("hwaccmR3Load:\n"));
|
---|
582 |
|
---|
583 | /*
|
---|
584 | * Validate version.
|
---|
585 | */
|
---|
586 | if (u32Version != HWACCM_SSM_VERSION)
|
---|
587 | {
|
---|
588 | Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
|
---|
589 | return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
|
---|
590 | }
|
---|
591 |
|
---|
592 | rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
|
---|
593 | AssertRCReturn(rc, rc);
|
---|
594 | rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
|
---|
595 | AssertRCReturn(rc, rc);
|
---|
596 | rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
|
---|
597 | AssertRCReturn(rc, rc);
|
---|
598 |
|
---|
599 | return VINF_SUCCESS;
|
---|
600 | }
|
---|
601 |
|
---|
602 |
|
---|
603 |
|
---|
604 |
|
---|