VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 32488

Last change on this file since 32488 was 32378, checked in by vboxsync, 14 years ago

HWACCM.cpp: logging typo.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 131.9 KB
Line 
1/* $Id: HWACCM.cpp 32378 2010-09-10 09:39:52Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46#include <iprt/string.h>
47#include <iprt/env.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
221 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
295
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326 pVM->hwaccm.s.fLargePages = false;
327
328 /* Disabled by default. */
329 pVM->fHWACCMEnabled = false;
330
331 /*
332 * Check CFGM options.
333 */
334 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
335 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
336 /* Nested paging: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
338 AssertRC(rc);
339
340 /* Large pages: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
342 AssertRC(rc);
343
344 /* VT-x VPID: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
346 AssertRC(rc);
347
348 /* HWACCM support must be explicitely enabled in the configuration file. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
350 AssertRC(rc);
351
352 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
354 AssertRC(rc);
355
356#ifdef RT_OS_DARWIN
357 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
358#else
359 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
360#endif
361 {
362 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
363 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
364 return VERR_HWACCM_CONFIG_MISMATCH;
365 }
366
367 if (VMMIsHwVirtExtForced(pVM))
368 pVM->fHWACCMEnabled = true;
369
370#if HC_ARCH_BITS == 32
371 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
372 * (To use the default, don't set 64bitEnabled in CFGM.) */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
374 AssertLogRelRCReturn(rc, rc);
375 if (pVM->hwaccm.s.fAllow64BitGuests)
376 {
377# ifdef RT_OS_DARWIN
378 if (!VMMIsHwVirtExtForced(pVM))
379# else
380 if (!pVM->hwaccm.s.fAllowed)
381# endif
382 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
383 }
384#else
385 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
386 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
387 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391
392 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
393 * or local init each time we wish to execute guest code.
394 *
395 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
396 */
397 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
398#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
399 false
400#else
401 true
402#endif
403 );
404
405 /* Max number of resume loops. */
406 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
407 AssertRC(rc);
408
409 return VINF_SUCCESS;
410}
411
412/**
413 * Initializes the per-VCPU HWACCM.
414 *
415 * @returns VBox status code.
416 * @param pVM The VM to operate on.
417 */
418VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
419{
420 LogFlow(("HWACCMR3InitCPU\n"));
421
422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
423 {
424 PVMCPU pVCpu = &pVM->aCpus[i];
425
426 pVCpu->hwaccm.s.fActive = false;
427 }
428
429#ifdef VBOX_WITH_STATISTICS
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
433 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
434
435 /*
436 * Statistics.
437 */
438 for (VMCPUID i = 0; i < pVM->cCpus; i++)
439 {
440 PVMCPU pVCpu = &pVM->aCpus[i];
441 int rc;
442
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
444 "/PROF/HWACCM/CPU%d/Poke", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
447 "/PROF/HWACCM/CPU%d/PokeWait", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
450 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
453 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
460 AssertRC(rc);
461# if 1 /* temporary for tracking down darwin holdup. */
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
467 AssertRC(rc);
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
469 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
470 AssertRC(rc);
471# endif
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
473 "/PROF/HWACCM/CPU%d/InGC", i);
474 AssertRC(rc);
475
476# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
478 "/PROF/HWACCM/CPU%d/Switcher3264", i);
479 AssertRC(rc);
480# endif
481
482# define HWACCM_REG_COUNTER(a, b) \
483 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
484 AssertRC(rc);
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
524
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
527
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
531
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
545
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
549
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
553
554#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
556 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
557#endif
558
559 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
560 {
561 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
562 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
563 AssertRC(rc);
564 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
565 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
566 AssertRC(rc);
567 }
568
569#undef HWACCM_REG_COUNTER
570
571 pVCpu->hwaccm.s.paStatExitReason = NULL;
572
573 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
574 AssertRC(rc);
575 if (RT_SUCCESS(rc))
576 {
577 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
578 for (int j=0;j<MAX_EXITREASON_STAT;j++)
579 {
580 if (papszDesc[j])
581 {
582 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
583 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
584 AssertRC(rc);
585 }
586 }
587 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
588 AssertRC(rc);
589 }
590 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
591# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
592 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
593# else
594 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
595# endif
596
597 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
598 AssertRCReturn(rc, rc);
599 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
600# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
601 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
602# else
603 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
604# endif
605 for (unsigned j = 0; j < 255; j++)
606 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
607 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
608
609 }
610#endif /* VBOX_WITH_STATISTICS */
611
612#ifdef VBOX_WITH_CRASHDUMP_MAGIC
613 /* Magic marker for searching in crash dumps. */
614 for (VMCPUID i = 0; i < pVM->cCpus; i++)
615 {
616 PVMCPU pVCpu = &pVM->aCpus[i];
617
618 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
619 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
620 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
621 }
622#endif
623 return VINF_SUCCESS;
624}
625
626/**
627 * Turns off normal raw mode features
628 *
629 * @param pVM The VM to operate on.
630 */
631static void hwaccmR3DisableRawMode(PVM pVM)
632{
633 /* Disable PATM & CSAM. */
634 PATMR3AllowPatching(pVM, false);
635 CSAMDisableScanning(pVM);
636
637 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
638 SELMR3DisableMonitoring(pVM);
639 TRPMR3DisableMonitoring(pVM);
640
641 /* Disable the switcher code (safety precaution). */
642 VMMR3DisableSwitcher(pVM);
643
644 /* Disable mapping of the hypervisor into the shadow page table. */
645 PGMR3MappingsDisable(pVM);
646
647 /* Disable the switcher */
648 VMMR3DisableSwitcher(pVM);
649
650 /* Reinit the paging mode to force the new shadow mode. */
651 for (VMCPUID i = 0; i < pVM->cCpus; i++)
652 {
653 PVMCPU pVCpu = &pVM->aCpus[i];
654
655 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
656 }
657}
658
659/**
660 * Initialize VT-x or AMD-V.
661 *
662 * @returns VBox status code.
663 * @param pVM The VM handle.
664 */
665VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
666{
667 int rc;
668
669 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
670 * is already using AMD-V.
671 */
672 if ( !pVM->hwaccm.s.vmx.fSupported
673 && !pVM->hwaccm.s.svm.fSupported
674 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
675 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
676 {
677 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
678 pVM->hwaccm.s.svm.fSupported = true;
679 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
680 }
681 else
682 if ( !pVM->hwaccm.s.vmx.fSupported
683 && !pVM->hwaccm.s.svm.fSupported)
684 {
685 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
686 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
687
688 if (VMMIsHwVirtExtForced(pVM))
689 {
690 switch (pVM->hwaccm.s.lLastError)
691 {
692 case VERR_VMX_NO_VMX:
693 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
694 case VERR_VMX_IN_VMX_ROOT_MODE:
695 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
696 case VERR_SVM_IN_USE:
697 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
698 case VERR_SVM_NO_SVM:
699 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
700 case VERR_SVM_DISABLED:
701 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
702 default:
703 return pVM->hwaccm.s.lLastError;
704 }
705 }
706 return VINF_SUCCESS;
707 }
708
709 if (pVM->hwaccm.s.vmx.fSupported)
710 {
711 rc = SUPR3QueryVTxSupported();
712 if (RT_FAILURE(rc))
713 {
714#ifdef RT_OS_LINUX
715 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
716#else
717 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
718#endif
719 if ( pVM->cCpus > 1
720 || VMMIsHwVirtExtForced(pVM))
721 return rc;
722
723 /* silently fall back to raw mode */
724 return VINF_SUCCESS;
725 }
726 }
727
728 if (!pVM->hwaccm.s.fAllowed)
729 return VINF_SUCCESS; /* nothing to do */
730
731 /* Enable VT-x or AMD-V on all host CPUs. */
732 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
733 if (RT_FAILURE(rc))
734 {
735 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
736 return rc;
737 }
738 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
739
740 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
741 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
742 if (!pVM->hwaccm.s.fHasIoApic)
743 {
744 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
745 pVM->hwaccm.s.fTRPPatchingAllowed = false;
746 }
747
748 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
749 if (pVM->hwaccm.s.vmx.fSupported)
750 {
751 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
752
753 if ( pVM->hwaccm.s.fInitialized == false
754 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
755 {
756 uint64_t val;
757 RTGCPHYS GCPhys = 0;
758
759 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
760 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
761 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
762 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
763 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
764 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
765 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
766 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
767
768 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
769 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
770 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
772 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
774 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
776 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
778 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
779 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
780 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
781 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
782 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
783 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
784 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
785 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
786 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
787
788 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
789 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
806 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
808 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
810 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
812 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
814 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
816 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
818 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
820 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
822 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
826 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
832
833 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
876
877 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
878 {
879 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
880 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
881 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
888 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
890 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
899
900 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
901 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
908 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
909 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
910 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
913 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
915 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
917 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
919 }
920
921 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
922 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
923 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
924 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
925 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
926 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
927 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
928 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
929 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
931 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
933 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
935 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
937 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
938 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
940 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
941 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
942 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
943 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
944 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
945 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
946 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
947 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
948 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
949 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
950 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
951 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
952
953 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
954 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
955 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
957 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
959 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
960 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
961 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
962 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
963 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
964 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
965 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
966 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
967 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
968 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
969 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
970 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
971 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
976 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
977 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
978 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
979 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
980 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
981 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
982 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
983 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
984 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
985 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
986 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
987 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
988
989 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
990 {
991 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
992
993 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
995 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
996 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
997 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
998 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
999 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1000 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1001 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1002 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1003 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1004 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1005 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1006 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1007 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1008 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1009 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1010 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1011 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1012 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1013 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1014 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1015 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1016 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1018 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1019 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1020 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1031 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1032 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1033 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1034 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1035 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1036 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1037 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1038 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1039 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1040 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1041 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1042 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1043 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1044 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1045 }
1046
1047 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1048 if ( !pVM->hwaccm.s.vmx.fUsePreemptTimer
1049 || MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1050 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1051 else
1052 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1053 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1054 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1055 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1056 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1057
1058 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1059 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1060 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1061 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1062 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1063
1064 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1065
1066 /* Paranoia */
1067 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1068
1069 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1070 {
1071 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1072 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1073 }
1074
1075#ifdef HWACCM_VTX_WITH_EPT
1076 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1077 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1078#endif /* HWACCM_VTX_WITH_EPT */
1079#ifdef HWACCM_VTX_WITH_VPID
1080 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1081 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1082 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1083#endif /* HWACCM_VTX_WITH_VPID */
1084
1085 /* Unrestricted guest execution relies on EPT. */
1086 if ( pVM->hwaccm.s.fNestedPaging
1087 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1088 {
1089 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1090 }
1091
1092 /* Only try once. */
1093 pVM->hwaccm.s.fInitialized = true;
1094
1095 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1096 {
1097 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1098 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1099 if (RT_SUCCESS(rc))
1100 {
1101 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1102 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1103 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1104 /* Bit set to 0 means redirection enabled. */
1105 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1106 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1107 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1108 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1109
1110 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1111 * real and protected mode without paging with EPT.
1112 */
1113 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1114 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1115 {
1116 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1117 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1118 }
1119
1120 /* We convert it here every time as pci regions could be reconfigured. */
1121 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1122 AssertRC(rc);
1123 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1124
1125 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1126 AssertRC(rc);
1127 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1128 }
1129 else
1130 {
1131 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1132 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1133 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1134 }
1135 }
1136
1137 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1138 AssertRC(rc);
1139 if (rc == VINF_SUCCESS)
1140 {
1141 pVM->fHWACCMEnabled = true;
1142 pVM->hwaccm.s.vmx.fEnabled = true;
1143 hwaccmR3DisableRawMode(pVM);
1144
1145 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1146#ifdef VBOX_ENABLE_64_BITS_GUESTS
1147 if (pVM->hwaccm.s.fAllow64BitGuests)
1148 {
1149 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1150 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1151 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1152 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1153 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1154 }
1155 else
1156 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1157 /* Todo: this needs to be fixed properly!! */
1158 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1159 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1160 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1161
1162 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1163 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1164 : "HWACCM: 32-bit guests supported.\n"));
1165#else
1166 LogRel(("HWACCM: 32-bit guests supported.\n"));
1167#endif
1168 LogRel(("HWACCM: VMX enabled!\n"));
1169 if (pVM->hwaccm.s.fNestedPaging)
1170 {
1171 LogRel(("HWACCM: Enabled nested paging\n"));
1172 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1173 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1174 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1175
1176#if HC_ARCH_BITS == 64
1177 if (pVM->hwaccm.s.fLargePages)
1178 {
1179 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1180 PGMSetLargePageUsage(pVM, true);
1181 LogRel(("HWACCM: Large page support enabled!\n"));
1182 }
1183#endif
1184 }
1185 else
1186 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1187
1188 if (pVM->hwaccm.s.vmx.fVPID)
1189 LogRel(("HWACCM: Enabled VPID\n"));
1190
1191 if ( pVM->hwaccm.s.fNestedPaging
1192 || pVM->hwaccm.s.vmx.fVPID)
1193 {
1194 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1195 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1196 }
1197
1198 /* TPR patching status logging. */
1199 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1200 {
1201 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1202 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1203 {
1204 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1205 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1206 }
1207 else
1208 {
1209 uint32_t u32Eax, u32Dummy;
1210
1211 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1212 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1213 if ( u32Eax < 0x80000001
1214 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1215 {
1216 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1217 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1218 }
1219 }
1220 }
1221 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1222 }
1223 else
1224 {
1225 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1226 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1227 pVM->fHWACCMEnabled = false;
1228 }
1229 }
1230 }
1231 else
1232 if (pVM->hwaccm.s.svm.fSupported)
1233 {
1234 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1235
1236 if (pVM->hwaccm.s.fInitialized == false)
1237 {
1238 /* Erratum 170 which requires a forced TLB flush for each world switch:
1239 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1240 *
1241 * All BH-G1/2 and DH-G1/2 models include a fix:
1242 * Athlon X2: 0x6b 1/2
1243 * 0x68 1/2
1244 * Athlon 64: 0x7f 1
1245 * 0x6f 2
1246 * Sempron: 0x7f 1/2
1247 * 0x6f 2
1248 * 0x6c 2
1249 * 0x7c 2
1250 * Turion 64: 0x68 2
1251 *
1252 */
1253 uint32_t u32Dummy;
1254 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1255 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1256 u32BaseFamily= (u32Version >> 8) & 0xf;
1257 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1258 u32Model = ((u32Version >> 4) & 0xf);
1259 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1260 u32Stepping = u32Version & 0xf;
1261 if ( u32Family == 0xf
1262 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1263 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1264 {
1265 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1266 }
1267
1268 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1269 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1270 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1271 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1272 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1273 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1274
1275 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1276 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1277 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1278 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1279 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1280 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1281 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1282 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1283 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1284 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1285 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1286 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1287
1288 /* Only try once. */
1289 pVM->hwaccm.s.fInitialized = true;
1290
1291 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1292 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1293
1294 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1295 AssertRC(rc);
1296 if (rc == VINF_SUCCESS)
1297 {
1298 pVM->fHWACCMEnabled = true;
1299 pVM->hwaccm.s.svm.fEnabled = true;
1300
1301 if (pVM->hwaccm.s.fNestedPaging)
1302 {
1303 LogRel(("HWACCM: Enabled nested paging\n"));
1304#if HC_ARCH_BITS == 64
1305 if (pVM->hwaccm.s.fLargePages)
1306 {
1307 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1308 PGMSetLargePageUsage(pVM, true);
1309 LogRel(("HWACCM: Large page support enabled!\n"));
1310 }
1311#endif
1312 }
1313
1314 hwaccmR3DisableRawMode(pVM);
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1316 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1317 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1318#ifdef VBOX_ENABLE_64_BITS_GUESTS
1319 if (pVM->hwaccm.s.fAllow64BitGuests)
1320 {
1321 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1322 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1323 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1324 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1325 }
1326 else
1327 /* Turn on NXE if PAE has been enabled. */
1328 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1329 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1330#endif
1331
1332 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1333 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1334 : "HWACCM: 32-bit guest supported.\n"));
1335
1336 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1337 }
1338 else
1339 {
1340 pVM->fHWACCMEnabled = false;
1341 }
1342 }
1343 }
1344 if (pVM->fHWACCMEnabled)
1345 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1346 RTLogRelSetBuffering(fOldBuffered);
1347 return VINF_SUCCESS;
1348}
1349
1350/**
1351 * Applies relocations to data and code managed by this
1352 * component. This function will be called at init and
1353 * whenever the VMM need to relocate it self inside the GC.
1354 *
1355 * @param pVM The VM.
1356 */
1357VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1358{
1359 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1360
1361 /* Fetch the current paging mode during the relocate callback during state loading. */
1362 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1363 {
1364 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1365 {
1366 PVMCPU pVCpu = &pVM->aCpus[i];
1367
1368 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1369 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1370 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1371 }
1372 }
1373#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1374 if (pVM->fHWACCMEnabled)
1375 {
1376 int rc;
1377
1378 switch(PGMGetHostMode(pVM))
1379 {
1380 case PGMMODE_32_BIT:
1381 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1382 break;
1383
1384 case PGMMODE_PAE:
1385 case PGMMODE_PAE_NX:
1386 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1387 break;
1388
1389 default:
1390 AssertFailed();
1391 break;
1392 }
1393 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1394 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1395
1396 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1397 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1398
1399 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1400 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1401
1402 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1403 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1404
1405# ifdef DEBUG
1406 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1407 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1408# endif
1409 }
1410#endif
1411 return;
1412}
1413
1414/**
1415 * Checks hardware accelerated raw mode is allowed.
1416 *
1417 * @returns boolean
1418 * @param pVM The VM to operate on.
1419 */
1420VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1421{
1422 return pVM->hwaccm.s.fAllowed;
1423}
1424
1425/**
1426 * Notification callback which is called whenever there is a chance that a CR3
1427 * value might have changed.
1428 *
1429 * This is called by PGM.
1430 *
1431 * @param pVM The VM to operate on.
1432 * @param pVCpu The VMCPU to operate on.
1433 * @param enmShadowMode New shadow paging mode.
1434 * @param enmGuestMode New guest paging mode.
1435 */
1436VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1437{
1438 /* Ignore page mode changes during state loading. */
1439 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1440 return;
1441
1442 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1443
1444 if ( pVM->hwaccm.s.vmx.fEnabled
1445 && pVM->fHWACCMEnabled)
1446 {
1447 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1448 && enmGuestMode >= PGMMODE_PROTECTED)
1449 {
1450 PCPUMCTX pCtx;
1451
1452 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1453
1454 /* After a real mode switch to protected mode we must force
1455 * CPL to 0. Our real mode emulation had to set it to 3.
1456 */
1457 pCtx->ssHid.Attr.n.u2Dpl = 0;
1458 }
1459 }
1460
1461 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1462 {
1463 /* Keep track of paging mode changes. */
1464 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1465 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1466
1467 /* Did we miss a change, because all code was executed in the recompiler? */
1468 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1469 {
1470 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1471 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1472 }
1473 }
1474
1475 /* Reset the contents of the read cache. */
1476 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1477 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1478 pCache->Read.aFieldVal[j] = 0;
1479}
1480
1481/**
1482 * Terminates the HWACCM.
1483 *
1484 * Termination means cleaning up and freeing all resources,
1485 * the VM it self is at this point powered off or suspended.
1486 *
1487 * @returns VBox status code.
1488 * @param pVM The VM to operate on.
1489 */
1490VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1491{
1492 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1493 {
1494 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1495 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1496 }
1497 HWACCMR3TermCPU(pVM);
1498 return 0;
1499}
1500
1501/**
1502 * Terminates the per-VCPU HWACCM.
1503 *
1504 * Termination means cleaning up and freeing all resources,
1505 * the VM it self is at this point powered off or suspended.
1506 *
1507 * @returns VBox status code.
1508 * @param pVM The VM to operate on.
1509 */
1510VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1511{
1512 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1513 {
1514 PVMCPU pVCpu = &pVM->aCpus[i];
1515
1516#ifdef VBOX_WITH_STATISTICS
1517 if (pVCpu->hwaccm.s.paStatExitReason)
1518 {
1519 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1520 pVCpu->hwaccm.s.paStatExitReason = NULL;
1521 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1522 }
1523 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1524 {
1525 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1526 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1527 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1528 }
1529#endif
1530
1531#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1532 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1533 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1534 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1535#endif
1536 }
1537 return 0;
1538}
1539
1540/**
1541 * Resets a virtual CPU.
1542 *
1543 * Used by HWACCMR3Reset and CPU hot plugging.
1544 *
1545 * @param pVCpu The CPU to reset.
1546 */
1547VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1548{
1549 /* On first entry we'll sync everything. */
1550 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1551
1552 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1553 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1554
1555 pVCpu->hwaccm.s.fActive = false;
1556 pVCpu->hwaccm.s.Event.fPending = false;
1557
1558 /* Reset state information for real-mode emulation in VT-x. */
1559 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1560 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1561 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1562
1563 /* Reset the contents of the read cache. */
1564 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1565 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1566 pCache->Read.aFieldVal[j] = 0;
1567
1568#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1569 /* Magic marker for searching in crash dumps. */
1570 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1571 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1572#endif
1573}
1574
1575/**
1576 * The VM is being reset.
1577 *
1578 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1579 * needs to be removed.
1580 *
1581 * @param pVM VM handle.
1582 */
1583VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1584{
1585 LogFlow(("HWACCMR3Reset:\n"));
1586
1587 if (pVM->fHWACCMEnabled)
1588 hwaccmR3DisableRawMode(pVM);
1589
1590 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1591 {
1592 PVMCPU pVCpu = &pVM->aCpus[i];
1593
1594 HWACCMR3ResetCpu(pVCpu);
1595 }
1596
1597 /* Clear all patch information. */
1598 pVM->hwaccm.s.pGuestPatchMem = 0;
1599 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1600 pVM->hwaccm.s.cbGuestPatchMem = 0;
1601 pVM->hwaccm.s.cPatches = 0;
1602 pVM->hwaccm.s.PatchTree = 0;
1603 pVM->hwaccm.s.fTPRPatchingActive = false;
1604 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1605}
1606
1607/**
1608 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1609 *
1610 * @returns VBox strict status code.
1611 * @param pVM The VM handle.
1612 * @param pVCpu The VMCPU for the EMT we're being called on.
1613 * @param pvUser Unused
1614 *
1615 */
1616DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1617{
1618 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1619
1620 /* Only execute the handler on the VCPU the original patch request was issued. */
1621 if (pVCpu->idCpu != idCpu)
1622 return VINF_SUCCESS;
1623
1624 Log(("hwaccmR3RemovePatches\n"));
1625 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1626 {
1627 uint8_t szInstr[15];
1628 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1629 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1630 int rc;
1631
1632#ifdef LOG_ENABLED
1633 char szOutput[256];
1634
1635 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1636 szOutput, sizeof(szOutput), NULL);
1637 if (RT_SUCCESS(rc))
1638 Log(("Patched instr: %s\n", szOutput));
1639#endif
1640
1641 /* Check if the instruction is still the same. */
1642 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1643 if (rc != VINF_SUCCESS)
1644 {
1645 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1646 continue; /* swapped out or otherwise removed; skip it. */
1647 }
1648
1649 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1650 {
1651 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1652 continue; /* skip it. */
1653 }
1654
1655 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1656 AssertRC(rc);
1657
1658#ifdef LOG_ENABLED
1659 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1660 szOutput, sizeof(szOutput), NULL);
1661 if (RT_SUCCESS(rc))
1662 Log(("Original instr: %s\n", szOutput));
1663#endif
1664 }
1665 pVM->hwaccm.s.cPatches = 0;
1666 pVM->hwaccm.s.PatchTree = 0;
1667 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1668 pVM->hwaccm.s.fTPRPatchingActive = false;
1669 return VINF_SUCCESS;
1670}
1671
1672/**
1673 * Enable patching in a VT-x/AMD-V guest
1674 *
1675 * @returns VBox status code.
1676 * @param pVM The VM to operate on.
1677 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1678 * @param pPatchMem Patch memory range
1679 * @param cbPatchMem Size of the memory range
1680 */
1681int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1682{
1683 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1684 AssertRC(rc);
1685
1686 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1687 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1688 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1689 return VINF_SUCCESS;
1690}
1691
1692/**
1693 * Enable patching in a VT-x/AMD-V guest
1694 *
1695 * @returns VBox status code.
1696 * @param pVM The VM to operate on.
1697 * @param pPatchMem Patch memory range
1698 * @param cbPatchMem Size of the memory range
1699 */
1700VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1701{
1702 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1703 if (pVM->cCpus > 1)
1704 {
1705 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1706 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1707 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1708 AssertRC(rc);
1709 return rc;
1710 }
1711 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1712}
1713
1714/**
1715 * Disable patching in a VT-x/AMD-V guest
1716 *
1717 * @returns VBox status code.
1718 * @param pVM The VM to operate on.
1719 * @param pPatchMem Patch memory range
1720 * @param cbPatchMem Size of the memory range
1721 */
1722VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1723{
1724 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1725
1726 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1727 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1728
1729 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1730 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1731 AssertRC(rc);
1732
1733 pVM->hwaccm.s.pGuestPatchMem = 0;
1734 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1735 pVM->hwaccm.s.cbGuestPatchMem = 0;
1736 pVM->hwaccm.s.fTPRPatchingActive = false;
1737 return VINF_SUCCESS;
1738}
1739
1740
1741/**
1742 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1743 *
1744 * @returns VBox strict status code.
1745 * @param pVM The VM handle.
1746 * @param pVCpu The VMCPU for the EMT we're being called on.
1747 * @param pvUser User specified CPU context
1748 *
1749 */
1750DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1751{
1752 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1753 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1754 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1755 unsigned cbOp;
1756
1757 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1758 if (pVCpu->idCpu != idCpu)
1759 return VINF_SUCCESS;
1760
1761 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1762
1763 /* Two or more VCPUs were racing to patch this instruction. */
1764 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1765 if (pPatch)
1766 return VINF_SUCCESS;
1767
1768 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1769
1770 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1771 AssertRC(rc);
1772 if ( rc == VINF_SUCCESS
1773 && pDis->pCurInstr->opcode == OP_MOV
1774 && cbOp >= 3)
1775 {
1776 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1777 uint32_t idx = pVM->hwaccm.s.cPatches;
1778
1779 pPatch = &pVM->hwaccm.s.aPatches[idx];
1780
1781 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1782 AssertRC(rc);
1783
1784 pPatch->cbOp = cbOp;
1785
1786 if (pDis->param1.flags == USE_DISPLACEMENT32)
1787 {
1788 /* write. */
1789 if (pDis->param2.flags == USE_REG_GEN32)
1790 {
1791 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1792 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1793 }
1794 else
1795 {
1796 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1797 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1798 pPatch->uSrcOperand = pDis->param2.parval;
1799 }
1800 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1801 AssertRC(rc);
1802
1803 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1804 pPatch->cbNewOp = sizeof(aVMMCall);
1805 }
1806 else
1807 {
1808 RTGCPTR oldrip = pCtx->rip;
1809 uint32_t oldcbOp = cbOp;
1810 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1811
1812 /* read */
1813 Assert(pDis->param1.flags == USE_REG_GEN32);
1814
1815 /* Found:
1816 * mov eax, dword [fffe0080] (5 bytes)
1817 * Check if next instruction is:
1818 * shr eax, 4
1819 */
1820 pCtx->rip += cbOp;
1821 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1822 pCtx->rip = oldrip;
1823 if ( rc == VINF_SUCCESS
1824 && pDis->pCurInstr->opcode == OP_SHR
1825 && pDis->param1.flags == USE_REG_GEN32
1826 && pDis->param1.base.reg_gen == uMmioReg
1827 && pDis->param2.flags == USE_IMMEDIATE8
1828 && pDis->param2.parval == 4
1829 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1830 {
1831 uint8_t szInstr[15];
1832
1833 /* Replacing two instructions now. */
1834 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1835 AssertRC(rc);
1836
1837 pPatch->cbOp = oldcbOp + cbOp;
1838
1839 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1840 szInstr[0] = 0xF0;
1841 szInstr[1] = 0x0F;
1842 szInstr[2] = 0x20;
1843 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1844 for (unsigned i = 4; i < pPatch->cbOp; i++)
1845 szInstr[i] = 0x90; /* nop */
1846
1847 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1848 AssertRC(rc);
1849
1850 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1851 pPatch->cbNewOp = pPatch->cbOp;
1852
1853 Log(("Acceptable read/shr candidate!\n"));
1854 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1855 }
1856 else
1857 {
1858 pPatch->enmType = HWACCMTPRINSTR_READ;
1859 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1860
1861 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1862 AssertRC(rc);
1863
1864 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1865 pPatch->cbNewOp = sizeof(aVMMCall);
1866 }
1867 }
1868
1869 pPatch->Core.Key = pCtx->eip;
1870 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1871 AssertRC(rc);
1872
1873 pVM->hwaccm.s.cPatches++;
1874 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1875 return VINF_SUCCESS;
1876 }
1877
1878 /* Save invalid patch, so we will not try again. */
1879 uint32_t idx = pVM->hwaccm.s.cPatches;
1880
1881#ifdef LOG_ENABLED
1882 char szOutput[256];
1883 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1884 szOutput, sizeof(szOutput), NULL);
1885 if (RT_SUCCESS(rc))
1886 Log(("Failed to patch instr: %s\n", szOutput));
1887#endif
1888
1889 pPatch = &pVM->hwaccm.s.aPatches[idx];
1890 pPatch->Core.Key = pCtx->eip;
1891 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1892 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1893 AssertRC(rc);
1894 pVM->hwaccm.s.cPatches++;
1895 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1896 return VINF_SUCCESS;
1897}
1898
1899/**
1900 * Callback to patch a TPR instruction (jump to generated code)
1901 *
1902 * @returns VBox strict status code.
1903 * @param pVM The VM handle.
1904 * @param pVCpu The VMCPU for the EMT we're being called on.
1905 * @param pvUser User specified CPU context
1906 *
1907 */
1908DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1909{
1910 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1911 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1912 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1913 unsigned cbOp;
1914 int rc;
1915#ifdef LOG_ENABLED
1916 RTGCPTR pInstr;
1917 char szOutput[256];
1918#endif
1919
1920 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1921 if (pVCpu->idCpu != idCpu)
1922 return VINF_SUCCESS;
1923
1924 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1925
1926 /* Two or more VCPUs were racing to patch this instruction. */
1927 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1928 if (pPatch)
1929 {
1930 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1931 return VINF_SUCCESS;
1932 }
1933
1934 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1935
1936 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1937 AssertRC(rc);
1938 if ( rc == VINF_SUCCESS
1939 && pDis->pCurInstr->opcode == OP_MOV
1940 && cbOp >= 5)
1941 {
1942 uint32_t idx = pVM->hwaccm.s.cPatches;
1943 uint8_t aPatch[64];
1944 uint32_t off = 0;
1945
1946 pPatch = &pVM->hwaccm.s.aPatches[idx];
1947
1948#ifdef LOG_ENABLED
1949 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1950 szOutput, sizeof(szOutput), NULL);
1951 if (RT_SUCCESS(rc))
1952 Log(("Original instr: %s\n", szOutput));
1953#endif
1954
1955 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1956 AssertRC(rc);
1957
1958 pPatch->cbOp = cbOp;
1959 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1960
1961 if (pDis->param1.flags == USE_DISPLACEMENT32)
1962 {
1963 /*
1964 * TPR write:
1965 *
1966 * push ECX [51]
1967 * push EDX [52]
1968 * push EAX [50]
1969 * xor EDX,EDX [31 D2]
1970 * mov EAX,EAX [89 C0]
1971 * or
1972 * mov EAX,0000000CCh [B8 CC 00 00 00]
1973 * mov ECX,0C0000082h [B9 82 00 00 C0]
1974 * wrmsr [0F 30]
1975 * pop EAX [58]
1976 * pop EDX [5A]
1977 * pop ECX [59]
1978 * jmp return_address [E9 return_address]
1979 *
1980 */
1981 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1982
1983 aPatch[off++] = 0x51; /* push ecx */
1984 aPatch[off++] = 0x52; /* push edx */
1985 if (!fUsesEax)
1986 aPatch[off++] = 0x50; /* push eax */
1987 aPatch[off++] = 0x31; /* xor edx, edx */
1988 aPatch[off++] = 0xD2;
1989 if (pDis->param2.flags == USE_REG_GEN32)
1990 {
1991 if (!fUsesEax)
1992 {
1993 aPatch[off++] = 0x89; /* mov eax, src_reg */
1994 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1995 }
1996 }
1997 else
1998 {
1999 Assert(pDis->param2.flags == USE_IMMEDIATE32);
2000 aPatch[off++] = 0xB8; /* mov eax, immediate */
2001 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
2002 off += sizeof(uint32_t);
2003 }
2004 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2005 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2006 off += sizeof(uint32_t);
2007
2008 aPatch[off++] = 0x0F; /* wrmsr */
2009 aPatch[off++] = 0x30;
2010 if (!fUsesEax)
2011 aPatch[off++] = 0x58; /* pop eax */
2012 aPatch[off++] = 0x5A; /* pop edx */
2013 aPatch[off++] = 0x59; /* pop ecx */
2014 }
2015 else
2016 {
2017 /*
2018 * TPR read:
2019 *
2020 * push ECX [51]
2021 * push EDX [52]
2022 * push EAX [50]
2023 * mov ECX,0C0000082h [B9 82 00 00 C0]
2024 * rdmsr [0F 32]
2025 * mov EAX,EAX [89 C0]
2026 * pop EAX [58]
2027 * pop EDX [5A]
2028 * pop ECX [59]
2029 * jmp return_address [E9 return_address]
2030 *
2031 */
2032 Assert(pDis->param1.flags == USE_REG_GEN32);
2033
2034 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2035 aPatch[off++] = 0x51; /* push ecx */
2036 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2037 aPatch[off++] = 0x52; /* push edx */
2038 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2039 aPatch[off++] = 0x50; /* push eax */
2040
2041 aPatch[off++] = 0x31; /* xor edx, edx */
2042 aPatch[off++] = 0xD2;
2043
2044 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2045 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2046 off += sizeof(uint32_t);
2047
2048 aPatch[off++] = 0x0F; /* rdmsr */
2049 aPatch[off++] = 0x32;
2050
2051 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2052 {
2053 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2054 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2055 }
2056
2057 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2058 aPatch[off++] = 0x58; /* pop eax */
2059 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2060 aPatch[off++] = 0x5A; /* pop edx */
2061 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2062 aPatch[off++] = 0x59; /* pop ecx */
2063 }
2064 aPatch[off++] = 0xE9; /* jmp return_address */
2065 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2066 off += sizeof(RTRCUINTPTR);
2067
2068 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2069 {
2070 /* Write new code to the patch buffer. */
2071 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2072 AssertRC(rc);
2073
2074#ifdef LOG_ENABLED
2075 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2076 while (true)
2077 {
2078 uint32_t cb;
2079
2080 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2081 szOutput, sizeof(szOutput), &cb);
2082 if (RT_SUCCESS(rc))
2083 Log(("Patch instr %s\n", szOutput));
2084
2085 pInstr += cb;
2086
2087 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2088 break;
2089 }
2090#endif
2091
2092 pPatch->aNewOpcode[0] = 0xE9;
2093 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2094
2095 /* Overwrite the TPR instruction with a jump. */
2096 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2097 AssertRC(rc);
2098
2099#ifdef LOG_ENABLED
2100 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2101 szOutput, sizeof(szOutput), NULL);
2102 if (RT_SUCCESS(rc))
2103 Log(("Jump: %s\n", szOutput));
2104#endif
2105 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2106 pPatch->cbNewOp = 5;
2107
2108 pPatch->Core.Key = pCtx->eip;
2109 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2110 AssertRC(rc);
2111
2112 pVM->hwaccm.s.cPatches++;
2113 pVM->hwaccm.s.fTPRPatchingActive = true;
2114 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2115 return VINF_SUCCESS;
2116 }
2117 else
2118 Log(("Ran out of space in our patch buffer!\n"));
2119 }
2120
2121 /* Save invalid patch, so we will not try again. */
2122 uint32_t idx = pVM->hwaccm.s.cPatches;
2123
2124#ifdef LOG_ENABLED
2125 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2126 szOutput, sizeof(szOutput), NULL);
2127 if (RT_SUCCESS(rc))
2128 Log(("Failed to patch instr: %s\n", szOutput));
2129#endif
2130
2131 pPatch = &pVM->hwaccm.s.aPatches[idx];
2132 pPatch->Core.Key = pCtx->eip;
2133 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2134 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2135 AssertRC(rc);
2136 pVM->hwaccm.s.cPatches++;
2137 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2138 return VINF_SUCCESS;
2139}
2140
2141/**
2142 * Attempt to patch TPR mmio instructions
2143 *
2144 * @returns VBox status code.
2145 * @param pVM The VM to operate on.
2146 * @param pVCpu The VM CPU to operate on.
2147 * @param pCtx CPU context
2148 */
2149VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2150{
2151 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2152 AssertRC(rc);
2153 return rc;
2154}
2155
2156/**
2157 * Force execution of the current IO code in the recompiler
2158 *
2159 * @returns VBox status code.
2160 * @param pVM The VM to operate on.
2161 * @param pCtx Partial VM execution context
2162 */
2163VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2164{
2165 PVMCPU pVCpu = VMMGetCpu(pVM);
2166
2167 Assert(pVM->fHWACCMEnabled);
2168 Log(("HWACCMR3EmulateIoBlock\n"));
2169
2170 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2171 if (HWACCMCanEmulateIoBlockEx(pCtx))
2172 {
2173 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2174 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2175 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2176 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2177 return VINF_EM_RESCHEDULE_REM;
2178 }
2179 return VINF_SUCCESS;
2180}
2181
2182/**
2183 * Checks if we can currently use hardware accelerated raw mode.
2184 *
2185 * @returns boolean
2186 * @param pVM The VM to operate on.
2187 * @param pCtx Partial VM execution context
2188 */
2189VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2190{
2191 PVMCPU pVCpu = VMMGetCpu(pVM);
2192
2193 Assert(pVM->fHWACCMEnabled);
2194
2195 /* If we're still executing the IO code, then return false. */
2196 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2197 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2198 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2199 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2200 return false;
2201
2202 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2203
2204 /* AMD-V supports real & protected mode with or without paging. */
2205 if (pVM->hwaccm.s.svm.fEnabled)
2206 {
2207 pVCpu->hwaccm.s.fActive = true;
2208 return true;
2209 }
2210
2211 pVCpu->hwaccm.s.fActive = false;
2212
2213 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2214 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2215
2216 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2217 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2218 {
2219 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2220 if (fSupportsRealMode)
2221 {
2222 if (CPUMIsGuestInRealModeEx(pCtx))
2223 {
2224 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2225 * The base must also be equal to (sel << 4).
2226 */
2227 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2228 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2229 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2230 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2231 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2232 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2233 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2234 {
2235 return false;
2236 }
2237 }
2238 else
2239 {
2240 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2241 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2242 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2243 */
2244 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2245 && enmGuestMode >= PGMMODE_PROTECTED)
2246 {
2247 if ( (pCtx->cs & X86_SEL_RPL)
2248 || (pCtx->ds & X86_SEL_RPL)
2249 || (pCtx->es & X86_SEL_RPL)
2250 || (pCtx->fs & X86_SEL_RPL)
2251 || (pCtx->gs & X86_SEL_RPL)
2252 || (pCtx->ss & X86_SEL_RPL))
2253 {
2254 return false;
2255 }
2256 }
2257 }
2258 }
2259 else
2260 {
2261 if ( !CPUMIsGuestInLongModeEx(pCtx)
2262 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2263 {
2264 /** @todo This should (probably) be set on every excursion to the REM,
2265 * however it's too risky right now. So, only apply it when we go
2266 * back to REM for real mode execution. (The XP hack below doesn't
2267 * work reliably without this.)
2268 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2269 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2270
2271 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2272 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2273 return false;
2274
2275 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2276 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2277 return false;
2278
2279 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2280 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2281 * hidden registers (possible recompiler bug; see load_seg_vm) */
2282 if (pCtx->csHid.Attr.n.u1Present == 0)
2283 return false;
2284 if (pCtx->ssHid.Attr.n.u1Present == 0)
2285 return false;
2286
2287 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2288 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2289 /** @todo This check is actually wrong, it doesn't take the direction of the
2290 * stack segment into account. But, it does the job for now. */
2291 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2292 return false;
2293 #if 0
2294 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2295 || pCtx->ss >= pCtx->gdtr.cbGdt
2296 || pCtx->ds >= pCtx->gdtr.cbGdt
2297 || pCtx->es >= pCtx->gdtr.cbGdt
2298 || pCtx->fs >= pCtx->gdtr.cbGdt
2299 || pCtx->gs >= pCtx->gdtr.cbGdt)
2300 return false;
2301 #endif
2302 }
2303 }
2304 }
2305
2306 if (pVM->hwaccm.s.vmx.fEnabled)
2307 {
2308 uint32_t mask;
2309
2310 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2311 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2312 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2313 mask &= ~X86_CR0_NE;
2314
2315 if (fSupportsRealMode)
2316 {
2317 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2318 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2319 }
2320 else
2321 {
2322 /* We support protected mode without paging using identity mapping. */
2323 mask &= ~X86_CR0_PG;
2324 }
2325 if ((pCtx->cr0 & mask) != mask)
2326 return false;
2327
2328 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2329 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2330 if ((pCtx->cr0 & mask) != 0)
2331 return false;
2332
2333 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2334 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2335 mask &= ~X86_CR4_VMXE;
2336 if ((pCtx->cr4 & mask) != mask)
2337 return false;
2338
2339 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2340 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2341 if ((pCtx->cr4 & mask) != 0)
2342 return false;
2343
2344 pVCpu->hwaccm.s.fActive = true;
2345 return true;
2346 }
2347
2348 return false;
2349}
2350
2351/**
2352 * Checks if we need to reschedule due to VMM device heap changes
2353 *
2354 * @returns boolean
2355 * @param pVM The VM to operate on.
2356 * @param pCtx VM execution context
2357 */
2358VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2359{
2360 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2361 if ( pVM->hwaccm.s.vmx.fEnabled
2362 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2363 && !PDMVMMDevHeapIsEnabled(pVM)
2364 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2365 return true;
2366
2367 return false;
2368}
2369
2370
2371/**
2372 * Notifcation from EM about a rescheduling into hardware assisted execution
2373 * mode.
2374 *
2375 * @param pVCpu Pointer to the current virtual cpu structure.
2376 */
2377VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2378{
2379 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2380}
2381
2382/**
2383 * Notifcation from EM about returning from instruction emulation (REM / EM).
2384 *
2385 * @param pVCpu Pointer to the current virtual cpu structure.
2386 */
2387VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2388{
2389 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2390}
2391
2392/**
2393 * Checks if we are currently using hardware accelerated raw mode.
2394 *
2395 * @returns boolean
2396 * @param pVCpu The VMCPU to operate on.
2397 */
2398VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2399{
2400 return pVCpu->hwaccm.s.fActive;
2401}
2402
2403/**
2404 * Checks if we are currently using nested paging.
2405 *
2406 * @returns boolean
2407 * @param pVM The VM to operate on.
2408 */
2409VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2410{
2411 return pVM->hwaccm.s.fNestedPaging;
2412}
2413
2414/**
2415 * Checks if we are currently using VPID in VT-x mode.
2416 *
2417 * @returns boolean
2418 * @param pVM The VM to operate on.
2419 */
2420VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2421{
2422 return pVM->hwaccm.s.vmx.fVPID;
2423}
2424
2425
2426/**
2427 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2428 *
2429 * @returns boolean
2430 * @param pVM The VM to operate on.
2431 */
2432VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2433{
2434 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2435}
2436
2437/**
2438 * Restart an I/O instruction that was refused in ring-0
2439 *
2440 * @returns Strict VBox status code. Informational status codes other than the one documented
2441 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2442 * @retval VINF_SUCCESS Success.
2443 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2444 * status code must be passed on to EM.
2445 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2446 *
2447 * @param pVM The VM to operate on.
2448 * @param pVCpu The VMCPU to operate on.
2449 * @param pCtx VCPU register context
2450 */
2451VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2452{
2453 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2454
2455 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2456
2457 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2458 || enmType == HWACCMPENDINGIO_INVALID)
2459 return VERR_NOT_FOUND;
2460
2461 VBOXSTRICTRC rcStrict;
2462 switch (enmType)
2463 {
2464 case HWACCMPENDINGIO_PORT_READ:
2465 {
2466 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2467 uint32_t u32Val = 0;
2468
2469 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2470 &u32Val,
2471 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2472 if (IOM_SUCCESS(rcStrict))
2473 {
2474 /* Write back to the EAX register. */
2475 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2476 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2477 }
2478 break;
2479 }
2480
2481 case HWACCMPENDINGIO_PORT_WRITE:
2482 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2483 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2484 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2485 if (IOM_SUCCESS(rcStrict))
2486 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2487 break;
2488
2489 default:
2490 AssertFailed();
2491 return VERR_INTERNAL_ERROR;
2492 }
2493
2494 return rcStrict;
2495}
2496
2497/**
2498 * Inject an NMI into a running VM (only VCPU 0!)
2499 *
2500 * @returns boolean
2501 * @param pVM The VM to operate on.
2502 */
2503VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2504{
2505 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2506 return VINF_SUCCESS;
2507}
2508
2509/**
2510 * Check fatal VT-x/AMD-V error and produce some meaningful
2511 * log release message.
2512 *
2513 * @param pVM The VM to operate on.
2514 * @param iStatusCode VBox status code
2515 */
2516VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2517{
2518 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2519 {
2520 switch(iStatusCode)
2521 {
2522 case VERR_VMX_INVALID_VMCS_FIELD:
2523 break;
2524
2525 case VERR_VMX_INVALID_VMCS_PTR:
2526 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2527 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2528 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2529 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2530 break;
2531
2532 case VERR_VMX_UNABLE_TO_START_VM:
2533 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2534 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2535#if 0 /* @todo dump the current control fields to the release log */
2536 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2537 {
2538
2539 }
2540#endif
2541 break;
2542
2543 case VERR_VMX_UNABLE_TO_RESUME_VM:
2544 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2545 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2546 break;
2547
2548 case VERR_VMX_INVALID_VMXON_PTR:
2549 break;
2550 }
2551 }
2552}
2553
2554/**
2555 * Execute state save operation.
2556 *
2557 * @returns VBox status code.
2558 * @param pVM VM Handle.
2559 * @param pSSM SSM operation handle.
2560 */
2561static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2562{
2563 int rc;
2564
2565 Log(("hwaccmR3Save:\n"));
2566
2567 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2568 {
2569 /*
2570 * Save the basic bits - fortunately all the other things can be resynced on load.
2571 */
2572 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2573 AssertRCReturn(rc, rc);
2574 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2575 AssertRCReturn(rc, rc);
2576 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2577 AssertRCReturn(rc, rc);
2578
2579 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2580 AssertRCReturn(rc, rc);
2581 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2582 AssertRCReturn(rc, rc);
2583 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2584 AssertRCReturn(rc, rc);
2585 }
2586#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2587 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2588 AssertRCReturn(rc, rc);
2589 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2590 AssertRCReturn(rc, rc);
2591 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2592 AssertRCReturn(rc, rc);
2593
2594 /* Store all the guest patch records too. */
2595 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2596 AssertRCReturn(rc, rc);
2597
2598 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2599 {
2600 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2601
2602 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2603 AssertRCReturn(rc, rc);
2604
2605 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2606 AssertRCReturn(rc, rc);
2607
2608 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2609 AssertRCReturn(rc, rc);
2610
2611 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2612 AssertRCReturn(rc, rc);
2613
2614 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2615 AssertRCReturn(rc, rc);
2616
2617 AssertCompileSize(HWACCMTPRINSTR, 4);
2618 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2619 AssertRCReturn(rc, rc);
2620
2621 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2622 AssertRCReturn(rc, rc);
2623
2624 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2625 AssertRCReturn(rc, rc);
2626
2627 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2628 AssertRCReturn(rc, rc);
2629
2630 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2631 AssertRCReturn(rc, rc);
2632 }
2633#endif
2634 return VINF_SUCCESS;
2635}
2636
2637/**
2638 * Execute state load operation.
2639 *
2640 * @returns VBox status code.
2641 * @param pVM VM Handle.
2642 * @param pSSM SSM operation handle.
2643 * @param uVersion Data layout version.
2644 * @param uPass The data pass.
2645 */
2646static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2647{
2648 int rc;
2649
2650 Log(("hwaccmR3Load:\n"));
2651 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2652
2653 /*
2654 * Validate version.
2655 */
2656 if ( uVersion != HWACCM_SSM_VERSION
2657 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2658 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2659 {
2660 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2661 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2662 }
2663 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2664 {
2665 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2666 AssertRCReturn(rc, rc);
2667 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2668 AssertRCReturn(rc, rc);
2669 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2670 AssertRCReturn(rc, rc);
2671
2672 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2673 {
2674 uint32_t val;
2675
2676 rc = SSMR3GetU32(pSSM, &val);
2677 AssertRCReturn(rc, rc);
2678 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2679
2680 rc = SSMR3GetU32(pSSM, &val);
2681 AssertRCReturn(rc, rc);
2682 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2683
2684 rc = SSMR3GetU32(pSSM, &val);
2685 AssertRCReturn(rc, rc);
2686 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2687 }
2688 }
2689#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2690 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2691 {
2692 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2693 AssertRCReturn(rc, rc);
2694 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2695 AssertRCReturn(rc, rc);
2696 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2697 AssertRCReturn(rc, rc);
2698
2699 /* Fetch all TPR patch records. */
2700 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2701 AssertRCReturn(rc, rc);
2702
2703 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2704 {
2705 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2706
2707 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2708 AssertRCReturn(rc, rc);
2709
2710 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2711 AssertRCReturn(rc, rc);
2712
2713 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2714 AssertRCReturn(rc, rc);
2715
2716 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2717 AssertRCReturn(rc, rc);
2718
2719 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2723 AssertRCReturn(rc, rc);
2724
2725 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2726 pVM->hwaccm.s.fTPRPatchingActive = true;
2727
2728 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2729
2730 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2731 AssertRCReturn(rc, rc);
2732
2733 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2734 AssertRCReturn(rc, rc);
2735
2736 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2737 AssertRCReturn(rc, rc);
2738
2739 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2740 AssertRCReturn(rc, rc);
2741
2742 Log(("hwaccmR3Load: patch %d\n", i));
2743 Log(("Key = %x\n", pPatch->Core.Key));
2744 Log(("cbOp = %d\n", pPatch->cbOp));
2745 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2746 Log(("type = %d\n", pPatch->enmType));
2747 Log(("srcop = %d\n", pPatch->uSrcOperand));
2748 Log(("dstop = %d\n", pPatch->uDstOperand));
2749 Log(("cFaults = %d\n", pPatch->cFaults));
2750 Log(("target = %x\n", pPatch->pJumpTarget));
2751 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2752 AssertRC(rc);
2753 }
2754 }
2755#endif
2756
2757 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2758 if (HWACCMIsEnabled(pVM))
2759 {
2760 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2761 {
2762 PVMCPU pVCpu = &pVM->aCpus[i];
2763
2764 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2765 }
2766 }
2767 return VINF_SUCCESS;
2768}
2769
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette