VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 31173

Last change on this file since 31173 was 30791, checked in by vboxsync, 14 years ago

fixed HWACCM structure assertions.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 131.4 KB
Line 
1/* $Id: HWACCM.cpp 30791 2010-07-12 12:17:19Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/cpum.h>
23#include <VBox/stam.h>
24#include <VBox/mm.h>
25#include <VBox/pdmapi.h>
26#include <VBox/pgm.h>
27#include <VBox/ssm.h>
28#include <VBox/trpm.h>
29#include <VBox/dbgf.h>
30#include <VBox/iom.h>
31#include <VBox/patm.h>
32#include <VBox/csam.h>
33#include <VBox/selm.h>
34#include <VBox/rem.h>
35#include <VBox/hwacc_vmx.h>
36#include <VBox/hwacc_svm.h>
37#include "HWACCMInternal.h"
38#include <VBox/vm.h>
39#include <VBox/err.h>
40#include <VBox/param.h>
41
42#include <iprt/assert.h>
43#include <VBox/log.h>
44#include <iprt/asm.h>
45#include <iprt/asm-amd64-x86.h>
46#include <iprt/string.h>
47#include <iprt/env.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Virtual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
295
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326 pVM->hwaccm.s.fLargePages = false;
327
328 /* Disabled by default. */
329 pVM->fHWACCMEnabled = false;
330
331 /*
332 * Check CFGM options.
333 */
334 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
335 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
336 /* Nested paging: disabled by default. */
337 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
338 AssertRC(rc);
339
340 /* Large pages: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
342 AssertRC(rc);
343
344 /* VT-x VPID: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
346 AssertRC(rc);
347
348 /* HWACCM support must be explicitely enabled in the configuration file. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
350 AssertRC(rc);
351
352 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
354 AssertRC(rc);
355
356#ifdef RT_OS_DARWIN
357 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
358#else
359 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
360#endif
361 {
362 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
363 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
364 return VERR_HWACCM_CONFIG_MISMATCH;
365 }
366
367 if (VMMIsHwVirtExtForced(pVM))
368 pVM->fHWACCMEnabled = true;
369
370#if HC_ARCH_BITS == 32
371 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
372 * (To use the default, don't set 64bitEnabled in CFGM.) */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
374 AssertLogRelRCReturn(rc, rc);
375 if (pVM->hwaccm.s.fAllow64BitGuests)
376 {
377# ifdef RT_OS_DARWIN
378 if (!VMMIsHwVirtExtForced(pVM))
379# else
380 if (!pVM->hwaccm.s.fAllowed)
381# endif
382 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
383 }
384#else
385 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
386 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
387 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391
392 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
393 * or local init each time we wish to execute guest code.
394 *
395 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
396 */
397 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
398#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
399 false
400#else
401 true
402#endif
403 );
404
405 /* Max number of resume loops. */
406 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
407 AssertRC(rc);
408
409 return VINF_SUCCESS;
410}
411
412/**
413 * Initializes the per-VCPU HWACCM.
414 *
415 * @returns VBox status code.
416 * @param pVM The VM to operate on.
417 */
418VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
419{
420 LogFlow(("HWACCMR3InitCPU\n"));
421
422 for (VMCPUID i = 0; i < pVM->cCpus; i++)
423 {
424 PVMCPU pVCpu = &pVM->aCpus[i];
425
426 pVCpu->hwaccm.s.fActive = false;
427 }
428
429#ifdef VBOX_WITH_STATISTICS
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
433 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
434
435 /*
436 * Statistics.
437 */
438 for (VMCPUID i = 0; i < pVM->cCpus; i++)
439 {
440 PVMCPU pVCpu = &pVM->aCpus[i];
441 int rc;
442
443 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
444 "/PROF/HWACCM/CPU%d/Poke", i);
445 AssertRC(rc);
446 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
447 "/PROF/HWACCM/CPU%d/PokeWait", i);
448 AssertRC(rc);
449 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
450 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
451 AssertRC(rc);
452 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
453 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
454 AssertRC(rc);
455 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
456 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
457 AssertRC(rc);
458 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
459 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
460 AssertRC(rc);
461# if 1 /* temporary for tracking down darwin holdup. */
462 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
463 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
466 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
467 AssertRC(rc);
468 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
469 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
470 AssertRC(rc);
471# endif
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
473 "/PROF/HWACCM/CPU%d/InGC", i);
474 AssertRC(rc);
475
476# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
478 "/PROF/HWACCM/CPU%d/Switcher3264", i);
479 AssertRC(rc);
480# endif
481
482# define HWACCM_REG_COUNTER(a, b) \
483 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
484 AssertRC(rc);
485
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
524
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
527
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
531
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
545
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
549
550 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
553
554#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
556 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
557#endif
558
559 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
560 {
561 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
562 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
563 AssertRC(rc);
564 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
565 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
566 AssertRC(rc);
567 }
568
569#undef HWACCM_REG_COUNTER
570
571 pVCpu->hwaccm.s.paStatExitReason = NULL;
572
573 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
574 AssertRC(rc);
575 if (RT_SUCCESS(rc))
576 {
577 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
578 for (int j=0;j<MAX_EXITREASON_STAT;j++)
579 {
580 if (papszDesc[j])
581 {
582 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
583 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
584 AssertRC(rc);
585 }
586 }
587 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
588 AssertRC(rc);
589 }
590 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
591# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
592 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
593# else
594 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
595# endif
596
597 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
598 AssertRCReturn(rc, rc);
599 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
600# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
601 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
602# else
603 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
604# endif
605 for (unsigned j = 0; j < 255; j++)
606 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
607 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
608
609 }
610#endif /* VBOX_WITH_STATISTICS */
611
612#ifdef VBOX_WITH_CRASHDUMP_MAGIC
613 /* Magic marker for searching in crash dumps. */
614 for (VMCPUID i = 0; i < pVM->cCpus; i++)
615 {
616 PVMCPU pVCpu = &pVM->aCpus[i];
617
618 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
619 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
620 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
621 }
622#endif
623 return VINF_SUCCESS;
624}
625
626/**
627 * Turns off normal raw mode features
628 *
629 * @param pVM The VM to operate on.
630 */
631static void hwaccmR3DisableRawMode(PVM pVM)
632{
633 /* Disable PATM & CSAM. */
634 PATMR3AllowPatching(pVM, false);
635 CSAMDisableScanning(pVM);
636
637 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
638 SELMR3DisableMonitoring(pVM);
639 TRPMR3DisableMonitoring(pVM);
640
641 /* Disable the switcher code (safety precaution). */
642 VMMR3DisableSwitcher(pVM);
643
644 /* Disable mapping of the hypervisor into the shadow page table. */
645 PGMR3MappingsDisable(pVM);
646
647 /* Disable the switcher */
648 VMMR3DisableSwitcher(pVM);
649
650 /* Reinit the paging mode to force the new shadow mode. */
651 for (VMCPUID i = 0; i < pVM->cCpus; i++)
652 {
653 PVMCPU pVCpu = &pVM->aCpus[i];
654
655 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
656 }
657}
658
659/**
660 * Initialize VT-x or AMD-V.
661 *
662 * @returns VBox status code.
663 * @param pVM The VM handle.
664 */
665VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
666{
667 int rc;
668
669 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
670 * is already using AMD-V.
671 */
672 if ( !pVM->hwaccm.s.vmx.fSupported
673 && !pVM->hwaccm.s.svm.fSupported
674 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
675 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
676 {
677 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
678 pVM->hwaccm.s.svm.fSupported = true;
679 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
680 }
681 else
682 if ( !pVM->hwaccm.s.vmx.fSupported
683 && !pVM->hwaccm.s.svm.fSupported)
684 {
685 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
686 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
687
688 if (VMMIsHwVirtExtForced(pVM))
689 {
690 switch (pVM->hwaccm.s.lLastError)
691 {
692 case VERR_VMX_NO_VMX:
693 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
694 case VERR_VMX_IN_VMX_ROOT_MODE:
695 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
696 case VERR_SVM_IN_USE:
697 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
698 case VERR_SVM_NO_SVM:
699 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
700 case VERR_SVM_DISABLED:
701 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
702 default:
703 return pVM->hwaccm.s.lLastError;
704 }
705 }
706 return VINF_SUCCESS;
707 }
708
709 if (pVM->hwaccm.s.vmx.fSupported)
710 {
711 rc = SUPR3QueryVTxSupported();
712 if (RT_FAILURE(rc))
713 {
714#ifdef RT_OS_LINUX
715 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
716#else
717 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
718#endif
719 if ( pVM->cCpus > 1
720 || VMMIsHwVirtExtForced(pVM))
721 return rc;
722
723 /* silently fall back to raw mode */
724 return VINF_SUCCESS;
725 }
726 }
727
728 if (!pVM->hwaccm.s.fAllowed)
729 return VINF_SUCCESS; /* nothing to do */
730
731 /* Enable VT-x or AMD-V on all host CPUs. */
732 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
733 if (RT_FAILURE(rc))
734 {
735 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
736 return rc;
737 }
738 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
739
740 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
741 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
742 if (!pVM->hwaccm.s.fHasIoApic)
743 {
744 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
745 pVM->hwaccm.s.fTRPPatchingAllowed = false;
746 }
747
748 if (pVM->hwaccm.s.vmx.fSupported)
749 {
750 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
751
752 if ( pVM->hwaccm.s.fInitialized == false
753 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
754 {
755 uint64_t val;
756 RTGCPHYS GCPhys = 0;
757
758 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
759 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
760 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
761 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
762 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
763 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
764 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
765 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
766
767 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
768 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
771 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
775 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
776 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
777 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
778 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
780 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
782 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
784 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
786
787 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
788 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
789 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
790 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
791 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
803 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
804 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
805 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
821 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
823 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
825 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
831
832 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
833 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
836 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
838 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
875
876 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
877 {
878 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
879 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
880 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
898
899 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
900 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
905 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
907 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
909 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
911 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
913 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
915 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
916 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
917 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
918 }
919
920 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
921 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
922 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
923 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
924 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
925 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
936 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
937 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
945 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
947 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
949 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
951
952 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
953 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
954 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
955 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
956 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
957 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
958 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
959 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
970 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
971 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
972 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
974 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
976 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
978 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
980 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
981 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
982 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
983 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
984 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
985 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
986 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
987
988 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
989 {
990 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
991
992 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
993 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
994 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
995 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
996 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
997 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
998 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
999 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1000 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1001 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1002 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1003 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1004 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1005 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1006 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1007 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1008 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1009 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1010 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1011 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1012 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1013 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1014 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1015 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1016 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1017 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1018 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1020 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1021 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1022 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1023 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1024 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1025 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1026 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1027 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1028 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1029 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1030 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1031 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1032 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1033 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1034 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1035 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1036 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1037 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1038 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1039 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1040 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1041 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1042 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1043 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1044 }
1045
1046 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1047 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1048 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1049 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1050 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1051 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1052
1053 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1054 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1055 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1056 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1057 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1058
1059 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1060
1061 /* Paranoia */
1062 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1063
1064 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1065 {
1066 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1067 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1068 }
1069
1070#ifdef HWACCM_VTX_WITH_EPT
1071 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1072 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1073#endif /* HWACCM_VTX_WITH_EPT */
1074#ifdef HWACCM_VTX_WITH_VPID
1075 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1076 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1077 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1078#endif /* HWACCM_VTX_WITH_VPID */
1079
1080 /* Unrestricted guest execution relies on EPT. */
1081 if ( pVM->hwaccm.s.fNestedPaging
1082 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1083 {
1084 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1085 }
1086
1087 /* Only try once. */
1088 pVM->hwaccm.s.fInitialized = true;
1089
1090 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1091 {
1092 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1093 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1094 if (RT_SUCCESS(rc))
1095 {
1096 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1097 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1098 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1099 /* Bit set to 0 means redirection enabled. */
1100 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1101 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1102 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1103 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1104
1105 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1106 * real and protected mode without paging with EPT.
1107 */
1108 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1109 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1110 {
1111 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1112 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1113 }
1114
1115 /* We convert it here every time as pci regions could be reconfigured. */
1116 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1117 AssertRC(rc);
1118 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1119
1120 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1121 AssertRC(rc);
1122 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1123 }
1124 else
1125 {
1126 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1127 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1128 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1129 }
1130 }
1131
1132 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1133 AssertRC(rc);
1134 if (rc == VINF_SUCCESS)
1135 {
1136 pVM->fHWACCMEnabled = true;
1137 pVM->hwaccm.s.vmx.fEnabled = true;
1138 hwaccmR3DisableRawMode(pVM);
1139
1140 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1141#ifdef VBOX_ENABLE_64_BITS_GUESTS
1142 if (pVM->hwaccm.s.fAllow64BitGuests)
1143 {
1144 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1145 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1146 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1147 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1148 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1149 }
1150 else
1151 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1152 /* Todo: this needs to be fixed properly!! */
1153 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1154 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1155 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1156
1157 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1158 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1159 : "HWACCM: 32-bit guests supported.\n"));
1160#else
1161 LogRel(("HWACCM: 32-bit guests supported.\n"));
1162#endif
1163 LogRel(("HWACCM: VMX enabled!\n"));
1164 if (pVM->hwaccm.s.fNestedPaging)
1165 {
1166 LogRel(("HWACCM: Enabled nested paging\n"));
1167 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1168 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1169 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1170
1171#if HC_ARCH_BITS == 64
1172 if (pVM->hwaccm.s.fLargePages)
1173 {
1174 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1175 PGMSetLargePageUsage(pVM, true);
1176 LogRel(("HWACCM: Large page support enabled!\n"));
1177 }
1178#endif
1179 }
1180 else
1181 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1182
1183 if (pVM->hwaccm.s.vmx.fVPID)
1184 LogRel(("HWACCM: Enabled VPID\n"));
1185
1186 if ( pVM->hwaccm.s.fNestedPaging
1187 || pVM->hwaccm.s.vmx.fVPID)
1188 {
1189 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1190 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1191 }
1192
1193 /* TPR patching status logging. */
1194 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1195 {
1196 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1197 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1198 {
1199 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1200 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1201 }
1202 else
1203 {
1204 uint32_t u32Eax, u32Dummy;
1205
1206 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1207 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1208 if ( u32Eax < 0x80000001
1209 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1210 {
1211 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1212 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1213 }
1214 }
1215 }
1216 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1217 }
1218 else
1219 {
1220 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1221 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1222 pVM->fHWACCMEnabled = false;
1223 }
1224 }
1225 }
1226 else
1227 if (pVM->hwaccm.s.svm.fSupported)
1228 {
1229 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1230
1231 if (pVM->hwaccm.s.fInitialized == false)
1232 {
1233 /* Erratum 170 which requires a forced TLB flush for each world switch:
1234 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1235 *
1236 * All BH-G1/2 and DH-G1/2 models include a fix:
1237 * Athlon X2: 0x6b 1/2
1238 * 0x68 1/2
1239 * Athlon 64: 0x7f 1
1240 * 0x6f 2
1241 * Sempron: 0x7f 1/2
1242 * 0x6f 2
1243 * 0x6c 2
1244 * 0x7c 2
1245 * Turion 64: 0x68 2
1246 *
1247 */
1248 uint32_t u32Dummy;
1249 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1250 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1251 u32BaseFamily= (u32Version >> 8) & 0xf;
1252 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1253 u32Model = ((u32Version >> 4) & 0xf);
1254 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1255 u32Stepping = u32Version & 0xf;
1256 if ( u32Family == 0xf
1257 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1258 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1259 {
1260 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1261 }
1262
1263 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1264 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1265 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1266 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1267 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1268 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1269
1270 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1271 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1272 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1273 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1274 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1275 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1276 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1277 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1278 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1279 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1280 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1281 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1282
1283 /* Only try once. */
1284 pVM->hwaccm.s.fInitialized = true;
1285
1286 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1287 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1288
1289 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1290 AssertRC(rc);
1291 if (rc == VINF_SUCCESS)
1292 {
1293 pVM->fHWACCMEnabled = true;
1294 pVM->hwaccm.s.svm.fEnabled = true;
1295
1296 if (pVM->hwaccm.s.fNestedPaging)
1297 {
1298 LogRel(("HWACCM: Enabled nested paging\n"));
1299#if HC_ARCH_BITS == 64
1300 if (pVM->hwaccm.s.fLargePages)
1301 {
1302 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1303 PGMSetLargePageUsage(pVM, true);
1304 LogRel(("HWACCM: Large page support enabled!\n"));
1305 }
1306#endif
1307 }
1308
1309 hwaccmR3DisableRawMode(pVM);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1312 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1313#ifdef VBOX_ENABLE_64_BITS_GUESTS
1314 if (pVM->hwaccm.s.fAllow64BitGuests)
1315 {
1316 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1317 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1318 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1319 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1320 }
1321 else
1322 /* Turn on NXE if PAE has been enabled. */
1323 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1324 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1325#endif
1326
1327 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1328 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1329 : "HWACCM: 32-bit guest supported.\n"));
1330
1331 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1332 }
1333 else
1334 {
1335 pVM->fHWACCMEnabled = false;
1336 }
1337 }
1338 }
1339 if (pVM->fHWACCMEnabled)
1340 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1341 return VINF_SUCCESS;
1342}
1343
1344/**
1345 * Applies relocations to data and code managed by this
1346 * component. This function will be called at init and
1347 * whenever the VMM need to relocate it self inside the GC.
1348 *
1349 * @param pVM The VM.
1350 */
1351VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1352{
1353 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1354
1355 /* Fetch the current paging mode during the relocate callback during state loading. */
1356 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1357 {
1358 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1359 {
1360 PVMCPU pVCpu = &pVM->aCpus[i];
1361
1362 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1363 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1364 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1365 }
1366 }
1367#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1368 if (pVM->fHWACCMEnabled)
1369 {
1370 int rc;
1371
1372 switch(PGMGetHostMode(pVM))
1373 {
1374 case PGMMODE_32_BIT:
1375 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1376 break;
1377
1378 case PGMMODE_PAE:
1379 case PGMMODE_PAE_NX:
1380 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1381 break;
1382
1383 default:
1384 AssertFailed();
1385 break;
1386 }
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1388 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1389
1390 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1391 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1392
1393 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1394 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1395
1396 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1397 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1398
1399# ifdef DEBUG
1400 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1401 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1402# endif
1403 }
1404#endif
1405 return;
1406}
1407
1408/**
1409 * Checks hardware accelerated raw mode is allowed.
1410 *
1411 * @returns boolean
1412 * @param pVM The VM to operate on.
1413 */
1414VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1415{
1416 return pVM->hwaccm.s.fAllowed;
1417}
1418
1419/**
1420 * Notification callback which is called whenever there is a chance that a CR3
1421 * value might have changed.
1422 *
1423 * This is called by PGM.
1424 *
1425 * @param pVM The VM to operate on.
1426 * @param pVCpu The VMCPU to operate on.
1427 * @param enmShadowMode New shadow paging mode.
1428 * @param enmGuestMode New guest paging mode.
1429 */
1430VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1431{
1432 /* Ignore page mode changes during state loading. */
1433 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1434 return;
1435
1436 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1437
1438 if ( pVM->hwaccm.s.vmx.fEnabled
1439 && pVM->fHWACCMEnabled)
1440 {
1441 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1442 && enmGuestMode >= PGMMODE_PROTECTED)
1443 {
1444 PCPUMCTX pCtx;
1445
1446 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1447
1448 /* After a real mode switch to protected mode we must force
1449 * CPL to 0. Our real mode emulation had to set it to 3.
1450 */
1451 pCtx->ssHid.Attr.n.u2Dpl = 0;
1452 }
1453 }
1454
1455 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1456 {
1457 /* Keep track of paging mode changes. */
1458 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1459 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1460
1461 /* Did we miss a change, because all code was executed in the recompiler? */
1462 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1463 {
1464 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1465 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1466 }
1467 }
1468
1469 /* Reset the contents of the read cache. */
1470 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1471 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1472 pCache->Read.aFieldVal[j] = 0;
1473}
1474
1475/**
1476 * Terminates the HWACCM.
1477 *
1478 * Termination means cleaning up and freeing all resources,
1479 * the VM it self is at this point powered off or suspended.
1480 *
1481 * @returns VBox status code.
1482 * @param pVM The VM to operate on.
1483 */
1484VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1485{
1486 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1487 {
1488 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1489 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1490 }
1491 HWACCMR3TermCPU(pVM);
1492 return 0;
1493}
1494
1495/**
1496 * Terminates the per-VCPU HWACCM.
1497 *
1498 * Termination means cleaning up and freeing all resources,
1499 * the VM it self is at this point powered off or suspended.
1500 *
1501 * @returns VBox status code.
1502 * @param pVM The VM to operate on.
1503 */
1504VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1505{
1506 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1507 {
1508 PVMCPU pVCpu = &pVM->aCpus[i];
1509
1510#ifdef VBOX_WITH_STATISTICS
1511 if (pVCpu->hwaccm.s.paStatExitReason)
1512 {
1513 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1514 pVCpu->hwaccm.s.paStatExitReason = NULL;
1515 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1516 }
1517 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1518 {
1519 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1520 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1521 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1522 }
1523#endif
1524
1525#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1526 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1527 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1528 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1529#endif
1530 }
1531 return 0;
1532}
1533
1534/**
1535 * Resets a virtual CPU.
1536 *
1537 * Used by HWACCMR3Reset and CPU hot plugging.
1538 *
1539 * @param pVCpu The CPU to reset.
1540 */
1541VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1542{
1543 /* On first entry we'll sync everything. */
1544 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1545
1546 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1547 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1548
1549 pVCpu->hwaccm.s.fActive = false;
1550 pVCpu->hwaccm.s.Event.fPending = false;
1551
1552 /* Reset state information for real-mode emulation in VT-x. */
1553 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1554 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1555 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1556
1557 /* Reset the contents of the read cache. */
1558 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1559 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1560 pCache->Read.aFieldVal[j] = 0;
1561
1562#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1563 /* Magic marker for searching in crash dumps. */
1564 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1565 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1566#endif
1567}
1568
1569/**
1570 * The VM is being reset.
1571 *
1572 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1573 * needs to be removed.
1574 *
1575 * @param pVM VM handle.
1576 */
1577VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1578{
1579 LogFlow(("HWACCMR3Reset:\n"));
1580
1581 if (pVM->fHWACCMEnabled)
1582 hwaccmR3DisableRawMode(pVM);
1583
1584 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1585 {
1586 PVMCPU pVCpu = &pVM->aCpus[i];
1587
1588 HWACCMR3ResetCpu(pVCpu);
1589 }
1590
1591 /* Clear all patch information. */
1592 pVM->hwaccm.s.pGuestPatchMem = 0;
1593 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1594 pVM->hwaccm.s.cbGuestPatchMem = 0;
1595 pVM->hwaccm.s.cPatches = 0;
1596 pVM->hwaccm.s.PatchTree = 0;
1597 pVM->hwaccm.s.fTPRPatchingActive = false;
1598 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1599}
1600
1601/**
1602 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1603 *
1604 * @returns VBox strict status code.
1605 * @param pVM The VM handle.
1606 * @param pVCpu The VMCPU for the EMT we're being called on.
1607 * @param pvUser Unused
1608 *
1609 */
1610DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1611{
1612 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1613
1614 /* Only execute the handler on the VCPU the original patch request was issued. */
1615 if (pVCpu->idCpu != idCpu)
1616 return VINF_SUCCESS;
1617
1618 Log(("hwaccmR3RemovePatches\n"));
1619 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1620 {
1621 uint8_t szInstr[15];
1622 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1623 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1624 int rc;
1625
1626#ifdef LOG_ENABLED
1627 char szOutput[256];
1628
1629 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1630 szOutput, sizeof(szOutput), NULL);
1631 if (RT_SUCCESS(rc))
1632 Log(("Patched instr: %s\n", szOutput));
1633#endif
1634
1635 /* Check if the instruction is still the same. */
1636 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1637 if (rc != VINF_SUCCESS)
1638 {
1639 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1640 continue; /* swapped out or otherwise removed; skip it. */
1641 }
1642
1643 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1644 {
1645 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1646 continue; /* skip it. */
1647 }
1648
1649 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1650 AssertRC(rc);
1651
1652#ifdef LOG_ENABLED
1653 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1654 szOutput, sizeof(szOutput), NULL);
1655 if (RT_SUCCESS(rc))
1656 Log(("Original instr: %s\n", szOutput));
1657#endif
1658 }
1659 pVM->hwaccm.s.cPatches = 0;
1660 pVM->hwaccm.s.PatchTree = 0;
1661 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1662 pVM->hwaccm.s.fTPRPatchingActive = false;
1663 return VINF_SUCCESS;
1664}
1665
1666/**
1667 * Enable patching in a VT-x/AMD-V guest
1668 *
1669 * @returns VBox status code.
1670 * @param pVM The VM to operate on.
1671 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1672 * @param pPatchMem Patch memory range
1673 * @param cbPatchMem Size of the memory range
1674 */
1675int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1676{
1677 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1678 AssertRC(rc);
1679
1680 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1681 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1682 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1683 return VINF_SUCCESS;
1684}
1685
1686/**
1687 * Enable patching in a VT-x/AMD-V guest
1688 *
1689 * @returns VBox status code.
1690 * @param pVM The VM to operate on.
1691 * @param pPatchMem Patch memory range
1692 * @param cbPatchMem Size of the memory range
1693 */
1694VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1695{
1696 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1697 if (pVM->cCpus > 1)
1698 {
1699 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1700 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1701 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1702 AssertRC(rc);
1703 return rc;
1704 }
1705 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1706}
1707
1708/**
1709 * Disable patching in a VT-x/AMD-V guest
1710 *
1711 * @returns VBox status code.
1712 * @param pVM The VM to operate on.
1713 * @param pPatchMem Patch memory range
1714 * @param cbPatchMem Size of the memory range
1715 */
1716VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1717{
1718 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1719
1720 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1721 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1722
1723 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1724 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1725 AssertRC(rc);
1726
1727 pVM->hwaccm.s.pGuestPatchMem = 0;
1728 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1729 pVM->hwaccm.s.cbGuestPatchMem = 0;
1730 pVM->hwaccm.s.fTPRPatchingActive = false;
1731 return VINF_SUCCESS;
1732}
1733
1734
1735/**
1736 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1737 *
1738 * @returns VBox strict status code.
1739 * @param pVM The VM handle.
1740 * @param pVCpu The VMCPU for the EMT we're being called on.
1741 * @param pvUser User specified CPU context
1742 *
1743 */
1744DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1745{
1746 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1747 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1748 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1749 unsigned cbOp;
1750
1751 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1752 if (pVCpu->idCpu != idCpu)
1753 return VINF_SUCCESS;
1754
1755 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1756
1757 /* Two or more VCPUs were racing to patch this instruction. */
1758 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1759 if (pPatch)
1760 return VINF_SUCCESS;
1761
1762 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1763
1764 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1765 AssertRC(rc);
1766 if ( rc == VINF_SUCCESS
1767 && pDis->pCurInstr->opcode == OP_MOV
1768 && cbOp >= 3)
1769 {
1770 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1771 uint32_t idx = pVM->hwaccm.s.cPatches;
1772
1773 pPatch = &pVM->hwaccm.s.aPatches[idx];
1774
1775 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1776 AssertRC(rc);
1777
1778 pPatch->cbOp = cbOp;
1779
1780 if (pDis->param1.flags == USE_DISPLACEMENT32)
1781 {
1782 /* write. */
1783 if (pDis->param2.flags == USE_REG_GEN32)
1784 {
1785 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1786 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1787 }
1788 else
1789 {
1790 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1791 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1792 pPatch->uSrcOperand = pDis->param2.parval;
1793 }
1794 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1795 AssertRC(rc);
1796
1797 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1798 pPatch->cbNewOp = sizeof(aVMMCall);
1799 }
1800 else
1801 {
1802 RTGCPTR oldrip = pCtx->rip;
1803 uint32_t oldcbOp = cbOp;
1804 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1805
1806 /* read */
1807 Assert(pDis->param1.flags == USE_REG_GEN32);
1808
1809 /* Found:
1810 * mov eax, dword [fffe0080] (5 bytes)
1811 * Check if next instruction is:
1812 * shr eax, 4
1813 */
1814 pCtx->rip += cbOp;
1815 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1816 pCtx->rip = oldrip;
1817 if ( rc == VINF_SUCCESS
1818 && pDis->pCurInstr->opcode == OP_SHR
1819 && pDis->param1.flags == USE_REG_GEN32
1820 && pDis->param1.base.reg_gen == uMmioReg
1821 && pDis->param2.flags == USE_IMMEDIATE8
1822 && pDis->param2.parval == 4
1823 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1824 {
1825 uint8_t szInstr[15];
1826
1827 /* Replacing two instructions now. */
1828 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1829 AssertRC(rc);
1830
1831 pPatch->cbOp = oldcbOp + cbOp;
1832
1833 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1834 szInstr[0] = 0xF0;
1835 szInstr[1] = 0x0F;
1836 szInstr[2] = 0x20;
1837 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1838 for (unsigned i = 4; i < pPatch->cbOp; i++)
1839 szInstr[i] = 0x90; /* nop */
1840
1841 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1842 AssertRC(rc);
1843
1844 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1845 pPatch->cbNewOp = pPatch->cbOp;
1846
1847 Log(("Acceptable read/shr candidate!\n"));
1848 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1849 }
1850 else
1851 {
1852 pPatch->enmType = HWACCMTPRINSTR_READ;
1853 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1854
1855 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1856 AssertRC(rc);
1857
1858 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1859 pPatch->cbNewOp = sizeof(aVMMCall);
1860 }
1861 }
1862
1863 pPatch->Core.Key = pCtx->eip;
1864 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1865 AssertRC(rc);
1866
1867 pVM->hwaccm.s.cPatches++;
1868 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1869 return VINF_SUCCESS;
1870 }
1871
1872 /* Save invalid patch, so we will not try again. */
1873 uint32_t idx = pVM->hwaccm.s.cPatches;
1874
1875#ifdef LOG_ENABLED
1876 char szOutput[256];
1877 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1878 szOutput, sizeof(szOutput), NULL);
1879 if (RT_SUCCESS(rc))
1880 Log(("Failed to patch instr: %s\n", szOutput));
1881#endif
1882
1883 pPatch = &pVM->hwaccm.s.aPatches[idx];
1884 pPatch->Core.Key = pCtx->eip;
1885 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1886 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1887 AssertRC(rc);
1888 pVM->hwaccm.s.cPatches++;
1889 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1890 return VINF_SUCCESS;
1891}
1892
1893/**
1894 * Callback to patch a TPR instruction (jump to generated code)
1895 *
1896 * @returns VBox strict status code.
1897 * @param pVM The VM handle.
1898 * @param pVCpu The VMCPU for the EMT we're being called on.
1899 * @param pvUser User specified CPU context
1900 *
1901 */
1902DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1903{
1904 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1905 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1906 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1907 unsigned cbOp;
1908 int rc;
1909#ifdef LOG_ENABLED
1910 RTGCPTR pInstr;
1911 char szOutput[256];
1912#endif
1913
1914 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1915 if (pVCpu->idCpu != idCpu)
1916 return VINF_SUCCESS;
1917
1918 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1919
1920 /* Two or more VCPUs were racing to patch this instruction. */
1921 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1922 if (pPatch)
1923 {
1924 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1925 return VINF_SUCCESS;
1926 }
1927
1928 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1929
1930 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1931 AssertRC(rc);
1932 if ( rc == VINF_SUCCESS
1933 && pDis->pCurInstr->opcode == OP_MOV
1934 && cbOp >= 5)
1935 {
1936 uint32_t idx = pVM->hwaccm.s.cPatches;
1937 uint8_t aPatch[64];
1938 uint32_t off = 0;
1939
1940 pPatch = &pVM->hwaccm.s.aPatches[idx];
1941
1942#ifdef LOG_ENABLED
1943 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1944 szOutput, sizeof(szOutput), NULL);
1945 if (RT_SUCCESS(rc))
1946 Log(("Original instr: %s\n", szOutput));
1947#endif
1948
1949 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1950 AssertRC(rc);
1951
1952 pPatch->cbOp = cbOp;
1953 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1954
1955 if (pDis->param1.flags == USE_DISPLACEMENT32)
1956 {
1957 /*
1958 * TPR write:
1959 *
1960 * push ECX [51]
1961 * push EDX [52]
1962 * push EAX [50]
1963 * xor EDX,EDX [31 D2]
1964 * mov EAX,EAX [89 C0]
1965 * or
1966 * mov EAX,0000000CCh [B8 CC 00 00 00]
1967 * mov ECX,0C0000082h [B9 82 00 00 C0]
1968 * wrmsr [0F 30]
1969 * pop EAX [58]
1970 * pop EDX [5A]
1971 * pop ECX [59]
1972 * jmp return_address [E9 return_address]
1973 *
1974 */
1975 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1976
1977 aPatch[off++] = 0x51; /* push ecx */
1978 aPatch[off++] = 0x52; /* push edx */
1979 if (!fUsesEax)
1980 aPatch[off++] = 0x50; /* push eax */
1981 aPatch[off++] = 0x31; /* xor edx, edx */
1982 aPatch[off++] = 0xD2;
1983 if (pDis->param2.flags == USE_REG_GEN32)
1984 {
1985 if (!fUsesEax)
1986 {
1987 aPatch[off++] = 0x89; /* mov eax, src_reg */
1988 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1989 }
1990 }
1991 else
1992 {
1993 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1994 aPatch[off++] = 0xB8; /* mov eax, immediate */
1995 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1996 off += sizeof(uint32_t);
1997 }
1998 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1999 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2000 off += sizeof(uint32_t);
2001
2002 aPatch[off++] = 0x0F; /* wrmsr */
2003 aPatch[off++] = 0x30;
2004 if (!fUsesEax)
2005 aPatch[off++] = 0x58; /* pop eax */
2006 aPatch[off++] = 0x5A; /* pop edx */
2007 aPatch[off++] = 0x59; /* pop ecx */
2008 }
2009 else
2010 {
2011 /*
2012 * TPR read:
2013 *
2014 * push ECX [51]
2015 * push EDX [52]
2016 * push EAX [50]
2017 * mov ECX,0C0000082h [B9 82 00 00 C0]
2018 * rdmsr [0F 32]
2019 * mov EAX,EAX [89 C0]
2020 * pop EAX [58]
2021 * pop EDX [5A]
2022 * pop ECX [59]
2023 * jmp return_address [E9 return_address]
2024 *
2025 */
2026 Assert(pDis->param1.flags == USE_REG_GEN32);
2027
2028 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2029 aPatch[off++] = 0x51; /* push ecx */
2030 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2031 aPatch[off++] = 0x52; /* push edx */
2032 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2033 aPatch[off++] = 0x50; /* push eax */
2034
2035 aPatch[off++] = 0x31; /* xor edx, edx */
2036 aPatch[off++] = 0xD2;
2037
2038 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2039 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2040 off += sizeof(uint32_t);
2041
2042 aPatch[off++] = 0x0F; /* rdmsr */
2043 aPatch[off++] = 0x32;
2044
2045 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2046 {
2047 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2048 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2049 }
2050
2051 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2052 aPatch[off++] = 0x58; /* pop eax */
2053 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2054 aPatch[off++] = 0x5A; /* pop edx */
2055 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2056 aPatch[off++] = 0x59; /* pop ecx */
2057 }
2058 aPatch[off++] = 0xE9; /* jmp return_address */
2059 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2060 off += sizeof(RTRCUINTPTR);
2061
2062 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2063 {
2064 /* Write new code to the patch buffer. */
2065 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2066 AssertRC(rc);
2067
2068#ifdef LOG_ENABLED
2069 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2070 while (true)
2071 {
2072 uint32_t cb;
2073
2074 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2075 szOutput, sizeof(szOutput), &cb);
2076 if (RT_SUCCESS(rc))
2077 Log(("Patch instr %s\n", szOutput));
2078
2079 pInstr += cb;
2080
2081 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2082 break;
2083 }
2084#endif
2085
2086 pPatch->aNewOpcode[0] = 0xE9;
2087 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2088
2089 /* Overwrite the TPR instruction with a jump. */
2090 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2091 AssertRC(rc);
2092
2093#ifdef LOG_ENABLED
2094 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2095 szOutput, sizeof(szOutput), NULL);
2096 if (RT_SUCCESS(rc))
2097 Log(("Jump: %s\n", szOutput));
2098#endif
2099 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2100 pPatch->cbNewOp = 5;
2101
2102 pPatch->Core.Key = pCtx->eip;
2103 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2104 AssertRC(rc);
2105
2106 pVM->hwaccm.s.cPatches++;
2107 pVM->hwaccm.s.fTPRPatchingActive = true;
2108 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2109 return VINF_SUCCESS;
2110 }
2111 else
2112 Log(("Ran out of space in our patch buffer!\n"));
2113 }
2114
2115 /* Save invalid patch, so we will not try again. */
2116 uint32_t idx = pVM->hwaccm.s.cPatches;
2117
2118#ifdef LOG_ENABLED
2119 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2120 szOutput, sizeof(szOutput), NULL);
2121 if (RT_SUCCESS(rc))
2122 Log(("Failed to patch instr: %s\n", szOutput));
2123#endif
2124
2125 pPatch = &pVM->hwaccm.s.aPatches[idx];
2126 pPatch->Core.Key = pCtx->eip;
2127 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2128 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2129 AssertRC(rc);
2130 pVM->hwaccm.s.cPatches++;
2131 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2132 return VINF_SUCCESS;
2133}
2134
2135/**
2136 * Attempt to patch TPR mmio instructions
2137 *
2138 * @returns VBox status code.
2139 * @param pVM The VM to operate on.
2140 * @param pVCpu The VM CPU to operate on.
2141 * @param pCtx CPU context
2142 */
2143VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2144{
2145 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2146 AssertRC(rc);
2147 return rc;
2148}
2149
2150/**
2151 * Force execution of the current IO code in the recompiler
2152 *
2153 * @returns VBox status code.
2154 * @param pVM The VM to operate on.
2155 * @param pCtx Partial VM execution context
2156 */
2157VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2158{
2159 PVMCPU pVCpu = VMMGetCpu(pVM);
2160
2161 Assert(pVM->fHWACCMEnabled);
2162 Log(("HWACCMR3EmulateIoBlock\n"));
2163
2164 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2165 if (HWACCMCanEmulateIoBlockEx(pCtx))
2166 {
2167 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2168 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2169 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2170 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2171 return VINF_EM_RESCHEDULE_REM;
2172 }
2173 return VINF_SUCCESS;
2174}
2175
2176/**
2177 * Checks if we can currently use hardware accelerated raw mode.
2178 *
2179 * @returns boolean
2180 * @param pVM The VM to operate on.
2181 * @param pCtx Partial VM execution context
2182 */
2183VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2184{
2185 PVMCPU pVCpu = VMMGetCpu(pVM);
2186
2187 Assert(pVM->fHWACCMEnabled);
2188
2189 /* If we're still executing the IO code, then return false. */
2190 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2191 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2192 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2193 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2194 return false;
2195
2196 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2197
2198 /* AMD-V supports real & protected mode with or without paging. */
2199 if (pVM->hwaccm.s.svm.fEnabled)
2200 {
2201 pVCpu->hwaccm.s.fActive = true;
2202 return true;
2203 }
2204
2205 pVCpu->hwaccm.s.fActive = false;
2206
2207 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2208 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2209
2210 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2211 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2212 {
2213 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2214 if (fSupportsRealMode)
2215 {
2216 if (CPUMIsGuestInRealModeEx(pCtx))
2217 {
2218 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2219 * The base must also be equal to (sel << 4).
2220 */
2221 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2222 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2223 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2224 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2225 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2226 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2227 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2228 {
2229 return false;
2230 }
2231 }
2232 else
2233 {
2234 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2235 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2236 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2237 */
2238 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2239 && enmGuestMode >= PGMMODE_PROTECTED)
2240 {
2241 if ( (pCtx->cs & X86_SEL_RPL)
2242 || (pCtx->ds & X86_SEL_RPL)
2243 || (pCtx->es & X86_SEL_RPL)
2244 || (pCtx->fs & X86_SEL_RPL)
2245 || (pCtx->gs & X86_SEL_RPL)
2246 || (pCtx->ss & X86_SEL_RPL))
2247 {
2248 return false;
2249 }
2250 }
2251 }
2252 }
2253 else
2254 {
2255 if ( !CPUMIsGuestInLongModeEx(pCtx)
2256 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2257 {
2258 /** @todo This should (probably) be set on every excursion to the REM,
2259 * however it's too risky right now. So, only apply it when we go
2260 * back to REM for real mode execution. (The XP hack below doesn't
2261 * work reliably without this.)
2262 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2263 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2264
2265 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2266 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2267 return false;
2268
2269 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2270 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2271 return false;
2272
2273 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2274 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2275 * hidden registers (possible recompiler bug; see load_seg_vm) */
2276 if (pCtx->csHid.Attr.n.u1Present == 0)
2277 return false;
2278 if (pCtx->ssHid.Attr.n.u1Present == 0)
2279 return false;
2280
2281 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2282 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2283 /** @todo This check is actually wrong, it doesn't take the direction of the
2284 * stack segment into account. But, it does the job for now. */
2285 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2286 return false;
2287 #if 0
2288 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2289 || pCtx->ss >= pCtx->gdtr.cbGdt
2290 || pCtx->ds >= pCtx->gdtr.cbGdt
2291 || pCtx->es >= pCtx->gdtr.cbGdt
2292 || pCtx->fs >= pCtx->gdtr.cbGdt
2293 || pCtx->gs >= pCtx->gdtr.cbGdt)
2294 return false;
2295 #endif
2296 }
2297 }
2298 }
2299
2300 if (pVM->hwaccm.s.vmx.fEnabled)
2301 {
2302 uint32_t mask;
2303
2304 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2305 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2306 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2307 mask &= ~X86_CR0_NE;
2308
2309 if (fSupportsRealMode)
2310 {
2311 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2312 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2313 }
2314 else
2315 {
2316 /* We support protected mode without paging using identity mapping. */
2317 mask &= ~X86_CR0_PG;
2318 }
2319 if ((pCtx->cr0 & mask) != mask)
2320 return false;
2321
2322 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2323 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2324 if ((pCtx->cr0 & mask) != 0)
2325 return false;
2326
2327 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2328 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2329 mask &= ~X86_CR4_VMXE;
2330 if ((pCtx->cr4 & mask) != mask)
2331 return false;
2332
2333 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2334 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2335 if ((pCtx->cr4 & mask) != 0)
2336 return false;
2337
2338 pVCpu->hwaccm.s.fActive = true;
2339 return true;
2340 }
2341
2342 return false;
2343}
2344
2345/**
2346 * Checks if we need to reschedule due to VMM device heap changes
2347 *
2348 * @returns boolean
2349 * @param pVM The VM to operate on.
2350 * @param pCtx VM execution context
2351 */
2352VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2353{
2354 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2355 if ( pVM->hwaccm.s.vmx.fEnabled
2356 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2357 && !PDMVMMDevHeapIsEnabled(pVM)
2358 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2359 return true;
2360
2361 return false;
2362}
2363
2364
2365/**
2366 * Notifcation from EM about a rescheduling into hardware assisted execution
2367 * mode.
2368 *
2369 * @param pVCpu Pointer to the current virtual cpu structure.
2370 */
2371VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2372{
2373 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2374}
2375
2376/**
2377 * Notifcation from EM about returning from instruction emulation (REM / EM).
2378 *
2379 * @param pVCpu Pointer to the current virtual cpu structure.
2380 */
2381VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2382{
2383 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2384}
2385
2386/**
2387 * Checks if we are currently using hardware accelerated raw mode.
2388 *
2389 * @returns boolean
2390 * @param pVCpu The VMCPU to operate on.
2391 */
2392VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2393{
2394 return pVCpu->hwaccm.s.fActive;
2395}
2396
2397/**
2398 * Checks if we are currently using nested paging.
2399 *
2400 * @returns boolean
2401 * @param pVM The VM to operate on.
2402 */
2403VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2404{
2405 return pVM->hwaccm.s.fNestedPaging;
2406}
2407
2408/**
2409 * Checks if we are currently using VPID in VT-x mode.
2410 *
2411 * @returns boolean
2412 * @param pVM The VM to operate on.
2413 */
2414VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2415{
2416 return pVM->hwaccm.s.vmx.fVPID;
2417}
2418
2419
2420/**
2421 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2422 *
2423 * @returns boolean
2424 * @param pVM The VM to operate on.
2425 */
2426VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2427{
2428 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2429}
2430
2431/**
2432 * Restart an I/O instruction that was refused in ring-0
2433 *
2434 * @returns Strict VBox status code. Informational status codes other than the one documented
2435 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2436 * @retval VINF_SUCCESS Success.
2437 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2438 * status code must be passed on to EM.
2439 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2440 *
2441 * @param pVM The VM to operate on.
2442 * @param pVCpu The VMCPU to operate on.
2443 * @param pCtx VCPU register context
2444 */
2445VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2446{
2447 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2448
2449 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2450
2451 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2452 || enmType == HWACCMPENDINGIO_INVALID)
2453 return VERR_NOT_FOUND;
2454
2455 VBOXSTRICTRC rcStrict;
2456 switch (enmType)
2457 {
2458 case HWACCMPENDINGIO_PORT_READ:
2459 {
2460 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2461 uint32_t u32Val = 0;
2462
2463 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2464 &u32Val,
2465 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2466 if (IOM_SUCCESS(rcStrict))
2467 {
2468 /* Write back to the EAX register. */
2469 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2470 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2471 }
2472 break;
2473 }
2474
2475 case HWACCMPENDINGIO_PORT_WRITE:
2476 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2477 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2478 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2479 if (IOM_SUCCESS(rcStrict))
2480 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2481 break;
2482
2483 default:
2484 AssertFailed();
2485 return VERR_INTERNAL_ERROR;
2486 }
2487
2488 return rcStrict;
2489}
2490
2491/**
2492 * Inject an NMI into a running VM (only VCPU 0!)
2493 *
2494 * @returns boolean
2495 * @param pVM The VM to operate on.
2496 */
2497VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2498{
2499 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2500 return VINF_SUCCESS;
2501}
2502
2503/**
2504 * Check fatal VT-x/AMD-V error and produce some meaningful
2505 * log release message.
2506 *
2507 * @param pVM The VM to operate on.
2508 * @param iStatusCode VBox status code
2509 */
2510VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2511{
2512 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2513 {
2514 switch(iStatusCode)
2515 {
2516 case VERR_VMX_INVALID_VMCS_FIELD:
2517 break;
2518
2519 case VERR_VMX_INVALID_VMCS_PTR:
2520 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2521 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2522 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2523 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2524 break;
2525
2526 case VERR_VMX_UNABLE_TO_START_VM:
2527 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2528 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2529#if 0 /* @todo dump the current control fields to the release log */
2530 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2531 {
2532
2533 }
2534#endif
2535 break;
2536
2537 case VERR_VMX_UNABLE_TO_RESUME_VM:
2538 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2539 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2540 break;
2541
2542 case VERR_VMX_INVALID_VMXON_PTR:
2543 break;
2544 }
2545 }
2546}
2547
2548/**
2549 * Execute state save operation.
2550 *
2551 * @returns VBox status code.
2552 * @param pVM VM Handle.
2553 * @param pSSM SSM operation handle.
2554 */
2555static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2556{
2557 int rc;
2558
2559 Log(("hwaccmR3Save:\n"));
2560
2561 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2562 {
2563 /*
2564 * Save the basic bits - fortunately all the other things can be resynced on load.
2565 */
2566 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2567 AssertRCReturn(rc, rc);
2568 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2569 AssertRCReturn(rc, rc);
2570 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2571 AssertRCReturn(rc, rc);
2572
2573 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2574 AssertRCReturn(rc, rc);
2575 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2576 AssertRCReturn(rc, rc);
2577 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2578 AssertRCReturn(rc, rc);
2579 }
2580#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2581 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2582 AssertRCReturn(rc, rc);
2583 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2584 AssertRCReturn(rc, rc);
2585 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2586 AssertRCReturn(rc, rc);
2587
2588 /* Store all the guest patch records too. */
2589 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2590 AssertRCReturn(rc, rc);
2591
2592 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2593 {
2594 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2595
2596 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2597 AssertRCReturn(rc, rc);
2598
2599 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2600 AssertRCReturn(rc, rc);
2601
2602 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2603 AssertRCReturn(rc, rc);
2604
2605 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2606 AssertRCReturn(rc, rc);
2607
2608 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2609 AssertRCReturn(rc, rc);
2610
2611 AssertCompileSize(HWACCMTPRINSTR, 4);
2612 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2613 AssertRCReturn(rc, rc);
2614
2615 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2616 AssertRCReturn(rc, rc);
2617
2618 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2619 AssertRCReturn(rc, rc);
2620
2621 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2622 AssertRCReturn(rc, rc);
2623
2624 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2625 AssertRCReturn(rc, rc);
2626 }
2627#endif
2628 return VINF_SUCCESS;
2629}
2630
2631/**
2632 * Execute state load operation.
2633 *
2634 * @returns VBox status code.
2635 * @param pVM VM Handle.
2636 * @param pSSM SSM operation handle.
2637 * @param uVersion Data layout version.
2638 * @param uPass The data pass.
2639 */
2640static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2641{
2642 int rc;
2643
2644 Log(("hwaccmR3Load:\n"));
2645 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2646
2647 /*
2648 * Validate version.
2649 */
2650 if ( uVersion != HWACCM_SSM_VERSION
2651 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2652 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2653 {
2654 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2655 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2656 }
2657 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2658 {
2659 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2660 AssertRCReturn(rc, rc);
2661 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2662 AssertRCReturn(rc, rc);
2663 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2664 AssertRCReturn(rc, rc);
2665
2666 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2667 {
2668 uint32_t val;
2669
2670 rc = SSMR3GetU32(pSSM, &val);
2671 AssertRCReturn(rc, rc);
2672 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2673
2674 rc = SSMR3GetU32(pSSM, &val);
2675 AssertRCReturn(rc, rc);
2676 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2677
2678 rc = SSMR3GetU32(pSSM, &val);
2679 AssertRCReturn(rc, rc);
2680 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2681 }
2682 }
2683#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2684 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2685 {
2686 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2687 AssertRCReturn(rc, rc);
2688 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2689 AssertRCReturn(rc, rc);
2690 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2691 AssertRCReturn(rc, rc);
2692
2693 /* Fetch all TPR patch records. */
2694 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2695 AssertRCReturn(rc, rc);
2696
2697 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2698 {
2699 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2700
2701 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2702 AssertRCReturn(rc, rc);
2703
2704 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2705 AssertRCReturn(rc, rc);
2706
2707 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2708 AssertRCReturn(rc, rc);
2709
2710 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2711 AssertRCReturn(rc, rc);
2712
2713 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2714 AssertRCReturn(rc, rc);
2715
2716 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2717 AssertRCReturn(rc, rc);
2718
2719 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2720 pVM->hwaccm.s.fTPRPatchingActive = true;
2721
2722 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2723
2724 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2725 AssertRCReturn(rc, rc);
2726
2727 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2728 AssertRCReturn(rc, rc);
2729
2730 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2731 AssertRCReturn(rc, rc);
2732
2733 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2734 AssertRCReturn(rc, rc);
2735
2736 Log(("hwaccmR3Load: patch %d\n", i));
2737 Log(("Key = %x\n", pPatch->Core.Key));
2738 Log(("cbOp = %d\n", pPatch->cbOp));
2739 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2740 Log(("type = %d\n", pPatch->enmType));
2741 Log(("srcop = %d\n", pPatch->uSrcOperand));
2742 Log(("dstop = %d\n", pPatch->uDstOperand));
2743 Log(("cFaults = %d\n", pPatch->cFaults));
2744 Log(("target = %x\n", pPatch->pJumpTarget));
2745 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2746 AssertRC(rc);
2747 }
2748 }
2749#endif
2750
2751 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2752 if (HWACCMIsEnabled(pVM))
2753 {
2754 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2755 {
2756 PVMCPU pVCpu = &pVM->aCpus[i];
2757
2758 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2759 }
2760 }
2761 return VINF_SUCCESS;
2762}
2763
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