HWACCM.cpp@ 2981

Last change on this file since 2981 was 2981, checked in by vboxsync, 17 years ago
InnoTek -> innotek: all the headers and comments.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 33.8 KB

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1	/* $Id: HWACCM.cpp 2981 2007-06-01 16:01:28Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48	#include "x86context.h"
49
50
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58	/**
59	* Initializes the HWACCM.
60	*
61	* @returns VBox status code.
62	* @param pVM The VM to operate on.
63	*/
64	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65	{
66	LogFlow(("HWACCMR3Init\n"));
67
68	/*
69	* Assert alignment and sizes.
70	*/
71	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74	/* Some structure checks. */
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89	/*
90	* Register the saved state data unit.
91	*/
92	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93	NULL, hwaccmR3Save, NULL,
94	NULL, hwaccmR3Load, NULL);
95	if (VBOX_FAILURE(rc))
96	return rc;
97
98	/** @todo Make sure both pages are either not accessible or readonly! */
99	/* Allocate one page for VMXON. */
100	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
101	if (pVM->hwaccm.s.vmx.pVMXON == 0)
102	{
103	AssertMsgFailed(("SUPContAlloc failed!!\n"));
104	return VERR_NO_MEMORY;
105	}
106	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108	/* Allocate one page for the VM control structure (VMCS). */
109	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
110	if (pVM->hwaccm.s.vmx.pVMCS == 0)
111	{
112	AssertMsgFailed(("SUPContAlloc failed!!\n"));
113	return VERR_NO_MEMORY;
114	}
115	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117	/* Allocate one page for the TSS we need for real mode emulation. */
118	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)SUPContAlloc(1, &pVM->hwaccm.s.vmx.pRealModeTSSPhys);
119	if (pVM->hwaccm.s.vmx.pRealModeTSS == 0)
120	{
121	AssertMsgFailed(("SUPContAlloc failed!!\n"));
122	return VERR_NO_MEMORY;
123	}
124	/* We initialize it properly later as we can reuse it for SVM */
125	memset(pVM->hwaccm.s.vmx.pRealModeTSS, 0, PAGE_SIZE);
126
127	/* Reuse those three pages for AMD SVM. (one is active; never both) */
128	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
129	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
130	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
131	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
132	pVM->hwaccm.s.svm.pVMCBHost = pVM->hwaccm.s.vmx.pRealModeTSS;
133	pVM->hwaccm.s.svm.pVMCBHostPhys = pVM->hwaccm.s.vmx.pRealModeTSSPhys;
134
135	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
137	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
138	{
139	AssertMsgFailed(("SUPContAlloc failed!!\n"));
140	return VERR_NO_MEMORY;
141	}
142	/* Set all bits to intercept all IO accesses. */
143	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
144
145	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
146	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
147	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
148	{
149	AssertMsgFailed(("SUPContAlloc failed!!\n"));
150	return VERR_NO_MEMORY;
151	}
152	/* Set all bits to intercept all MSR accesses. */
153	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
154
155	/* Misc initialisation. */
156	pVM->hwaccm.s.vmx.fSupported = false;
157	pVM->hwaccm.s.svm.fSupported = false;
158	pVM->hwaccm.s.vmx.fEnabled = false;
159	pVM->hwaccm.s.svm.fEnabled = false;
160
161	pVM->hwaccm.s.fActive = false;
162
163	/* On first entry we'll sync everything. */
164	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
165
166	pVM->hwaccm.s.vmx.cr0_mask = 0;
167	pVM->hwaccm.s.vmx.cr4_mask = 0;
168
169	/*
170	* Statistics.
171	*/
172	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
175
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
195	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
196	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
198	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
199	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
200	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
201
202	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
203	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
204
205	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
206	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
207	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
208
209	pVM->hwaccm.s.pStatExitReason = 0;
210
211	#ifdef VBOX_WITH_STATISTICS
212	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
213	AssertRC(rc);
214	if (VBOX_SUCCESS(rc))
215	{
216	for (int i=0;i<MAX_EXITREASON_STAT;i++)
217	{
218	char szName[64];
219	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
220	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
221	AssertRC(rc);
222	}
223	}
224	pVM->hwaccm.s.pStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.pStatExitReason);
225	Assert(pVM->hwaccm.s.pStatExitReasonR0);
226	#endif
227
228	/* Disabled by default. */
229	pVM->fHWACCMEnabled = false;
230
231	/* HWACCM support must be explicitely enabled in the configuration file. */
232	pVM->hwaccm.s.fAllowed = false;
233	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
234
235	return VINF_SUCCESS;
236	}
237
238
239	/**
240	* Turns off normal raw mode features
241	*
242	* @param pVM The VM to operate on.
243	*/
244	static void hwaccmr3DisableRawMode(PVM pVM)
245	{
246	/* Disable PATM & CSAM. */
247	PATMR3AllowPatching(pVM, false);
248	CSAMDisableScanning(pVM);
249
250	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
251	SELMR3DisableMonitoring(pVM);
252	TRPMR3DisableMonitoring(pVM);
253
254	/* The hidden selector registers are now valid. */
255	CPUMSetHiddenSelRegsValid(pVM, true);
256
257	/* Disable the switcher code (safety precaution). */
258	VMMR3DisableSwitcher(pVM);
259
260	/* Disable mapping of the hypervisor into the shadow page table. */
261	PGMR3ChangeShwPDMappings(pVM, false);
262
263	/* Disable the switcher */
264	VMMR3DisableSwitcher(pVM);
265	}
266
267	/**
268	* Applies relocations to data and code managed by this
269	* component. This function will be called at init and
270	* whenever the VMM need to relocate it self inside the GC.
271	*
272	* @param pVM The VM.
273	*/
274	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
275	{
276	#ifdef LOG_ENABLED
277	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
278	#endif
279
280	if (pVM->hwaccm.s.fAllowed == false)
281	return ;
282
283	if (pVM->hwaccm.s.vmx.fSupported)
284	{
285	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
286
287	if ( pVM->hwaccm.s.fInitialized == false
288	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
289	{
290	uint64_t val;
291
292	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
293	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
294	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
295	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
296	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
297	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
298	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
299	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
300
301	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
302	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL;
303	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
304	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
305	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
306	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
307	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls;
308	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
309	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
310	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
311	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
312
313	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
314	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL;
315	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
316	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
317	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
318	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
319	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
320	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
321	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
322	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
323	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
324	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
325	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
326	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
327	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
328	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
329	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
330	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
331	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
332	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
333	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
334	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
335	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
336	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
337	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
338	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
339	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
340	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
341	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
342	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
343	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
344	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
345	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
346	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
347	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls;
348	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
349	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
350	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
351	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
352	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
353	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
354	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
355	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
356	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
357	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
358	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
359	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
360	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
361	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
362	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
363	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
364	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
365	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
366	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
367	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
368	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
369	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
370	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
371	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
372	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
373	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
374	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
375	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
376	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
377	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
378	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
379	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
380
381	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
382	val = pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL;
383	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
384	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
385	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
386	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
387	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
388	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
389	val = pVM->hwaccm.s.vmx.msr.vmx_entry;
390	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
391	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
392	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
393	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
394	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
395	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
396
397	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
398	val = pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL;
399	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
400	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
401	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
402	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
403	val = pVM->hwaccm.s.vmx.msr.vmx_exit;
404	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
405	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
406	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
407	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
408
409	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
410	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
411	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
412	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
413	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
414
415	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
416	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
417	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
418	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
419	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
420
421	/* Only try once. */
422	pVM->hwaccm.s.fInitialized = true;
423
424	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
425	* for I/O operations. */
426	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
427	/* Bit set to 0 means redirection enabled. */
428	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
429
430	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
431	AssertRC(rc);
432	if (rc == VINF_SUCCESS)
433	{
434	hwaccmr3DisableRawMode(pVM);
435
436	pVM->fHWACCMEnabled = true;
437	pVM->hwaccm.s.vmx.fEnabled = true;
438	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
439	LogRel(("HWACCM: VMX enabled!\n"));
440	}
441	else
442	{
443	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
444	pVM->fHWACCMEnabled = false;
445	}
446	}
447	}
448	else
449	if (pVM->hwaccm.s.svm.fSupported)
450	{
451	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
452
453	if (pVM->hwaccm.s.fInitialized == false)
454	{
455	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
456	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
457	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
458	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
459
460	/* Only try once. */
461	pVM->hwaccm.s.fInitialized = true;
462
463	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
464	AssertRC(rc);
465	if (rc == VINF_SUCCESS)
466	{
467	hwaccmr3DisableRawMode(pVM);
468	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
469
470	pVM->fHWACCMEnabled = true;
471	pVM->hwaccm.s.svm.fEnabled = true;
472	}
473	else
474	{
475	pVM->fHWACCMEnabled = false;
476	}
477	}
478	}
479
480	}
481
482
483	/**
484	* Checks hardware accelerated raw mode is allowed.
485	*
486	* @returns boolean
487	* @param pVM The VM to operate on.
488	*/
489	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
490	{
491	return pVM->hwaccm.s.fAllowed;
492	}
493
494
495	/**
496	* Notification callback which is called whenever there is a chance that a CR3
497	* value might have changed.
498	* This is called by PGM.
499	*
500	* @param pVM The VM to operate on.
501	* @param enmShadowMode New paging mode.
502	*/
503	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
504	{
505	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
506	}
507
508	/**
509	* Terminates the HWACCM.
510	*
511	* Termination means cleaning up and freeing all resources,
512	* the VM it self is at this point powered off or suspended.
513	*
514	* @returns VBox status code.
515	* @param pVM The VM to operate on.
516	*/
517	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
518	{
519	if (pVM->hwaccm.s.pStatExitReason)
520	{
521	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
522	pVM->hwaccm.s.pStatExitReason = 0;
523	}
524
525	if (pVM->hwaccm.s.vmx.pVMXON)
526	{
527	SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
528	pVM->hwaccm.s.vmx.pVMXON = 0;
529	}
530	if (pVM->hwaccm.s.vmx.pVMCS)
531	{
532	SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
533	pVM->hwaccm.s.vmx.pVMCS = 0;
534	}
535	if (pVM->hwaccm.s.vmx.pRealModeTSS)
536	{
537	SUPContFree(pVM->hwaccm.s.vmx.pRealModeTSS, 1);
538	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
539	}
540	if (pVM->hwaccm.s.svm.pIOBitmap)
541	{
542	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
543	pVM->hwaccm.s.svm.pIOBitmap = 0;
544	}
545	if (pVM->hwaccm.s.svm.pMSRBitmap)
546	{
547	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
548	pVM->hwaccm.s.svm.pMSRBitmap = 0;
549	}
550	return 0;
551	}
552
553
554	/**
555	* The VM is being reset.
556	*
557	* For the HWACCM component this means that any GDT/LDT/TSS monitors
558	* needs to be removed.
559	*
560	* @param pVM VM handle.
561	*/
562	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
563	{
564	LogFlow(("HWACCMR3Reset:\n"));
565
566	if (pVM->fHWACCMEnabled)
567	hwaccmr3DisableRawMode(pVM);
568
569	/* On first entry we'll sync everything. */
570	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
571
572	pVM->hwaccm.s.vmx.cr0_mask = 0;
573	pVM->hwaccm.s.vmx.cr4_mask = 0;
574
575	pVM->hwaccm.s.Event.fPending = false;
576	}
577
578	/**
579	* Checks if we can currently use hardware accelerated raw mode.
580	*
581	* @returns boolean
582	* @param pVM The VM to operate on.
583	* @param pCtx Partial VM execution context
584	*/
585	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
586	{
587	uint32_t mask;
588
589	Assert(pVM->fHWACCMEnabled);
590
591	/* AMD SVM supports real & protected mode with or without paging. */
592	if (pVM->hwaccm.s.svm.fEnabled)
593	{
594	pVM->hwaccm.s.fActive = true;
595	return true;
596	}
597
598	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
599	* (but do we really care?)
600	*/
601
602	pVM->hwaccm.s.fActive = false;
603
604	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
605
606	#ifndef HWACCM_VMX_EMULATE_ALL
607	/* Too early for VMX. */
608	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
609	return false;
610
611	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
612	if (pCtx->csHid.Attr.n.u1Present == 0)
613	return false;
614	if (pCtx->ssHid.Attr.n.u1Present == 0)
615	return false;
616
617	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
618	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
619	return false;
620	#endif
621
622	if (pVM->hwaccm.s.vmx.fEnabled)
623	{
624	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
625	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
626	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
627	mask &= ~X86_CR0_NE;
628	#ifdef HWACCM_VMX_EMULATE_ALL
629	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
630	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
631	#endif
632	if ((pCtx->cr0 & mask) != mask)
633	return false;
634
635	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
636	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
637	if ((pCtx->cr0 & mask) != 0)
638	return false;
639
640	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
641	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
642	mask &= ~X86_CR4_VMXE;
643	if ((pCtx->cr4 & mask) != mask)
644	return false;
645
646	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
647	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
648	if ((pCtx->cr4 & mask) != 0)
649	return false;
650
651	pVM->hwaccm.s.fActive = true;
652	return true;
653	}
654
655	return false;
656	}
657
658	/**
659	* Checks if we are currently using hardware accelerated raw mode.
660	*
661	* @returns boolean
662	* @param pVM The VM to operate on.
663	*/
664	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
665	{
666	return pVM->hwaccm.s.fActive;
667	}
668
669	/**
670	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
671	*
672	* @returns boolean
673	* @param pVM The VM to operate on.
674	*/
675	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
676	{
677	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
678	}
679
680	/**
681	* Execute state save operation.
682	*
683	* @returns VBox status code.
684	* @param pVM VM Handle.
685	* @param pSSM SSM operation handle.
686	*/
687	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
688	{
689	int rc;
690
691	Log(("hwaccmR3Save:\n"));
692
693	/*
694	* Save the basic bits - fortunately all the other things can be resynced on load.
695	*/
696	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
697	AssertRCReturn(rc, rc);
698	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
699	AssertRCReturn(rc, rc);
700	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
701	AssertRCReturn(rc, rc);
702
703	return VINF_SUCCESS;
704	}
705
706
707	/**
708	* Execute state load operation.
709	*
710	* @returns VBox status code.
711	* @param pVM VM Handle.
712	* @param pSSM SSM operation handle.
713	* @param u32Version Data layout version.
714	*/
715	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
716	{
717	int rc;
718
719	Log(("hwaccmR3Load:\n"));
720
721	/*
722	* Validate version.
723	*/
724	if (u32Version != HWACCM_SSM_VERSION)
725	{
726	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
727	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
728	}
729	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
730	AssertRCReturn(rc, rc);
731	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
732	AssertRCReturn(rc, rc);
733	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
734	AssertRCReturn(rc, rc);
735
736	return VINF_SUCCESS;
737	}
738
739
740
741

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 2981

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