VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 2251

Last change on this file since 2251 was 2237, checked in by vboxsync, 18 years ago

Enabled SVM for real and protected mode without paging again.
  • Property svn:eol-style set to native
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File size: 23.6 KB
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1/* $Id: HWACCM.cpp 2237 2007-04-19 15:37:57Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48#include "x86context.h"
49
50
51/*******************************************************************************
52* Internal Functions *
53*******************************************************************************/
54static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58/**
59 * Initializes the HWACCM.
60 *
61 * @returns VBox status code.
62 * @param pVM The VM to operate on.
63 */
64HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65{
66 LogFlow(("HWACCMR3Init\n"));
67
68 /*
69 * Assert alignment and sizes.
70 */
71 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74 /* Some structure checks. */
75 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89 /*
90 * Register the saved state data unit.
91 */
92 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93 NULL, hwaccmR3Save, NULL,
94 NULL, hwaccmR3Load, NULL);
95 if (VBOX_FAILURE(rc))
96 return rc;
97
98 /** @todo Make sure both pages are either not accessible or readonly! */
99 /* Allocate one page for VMXON. */
100 pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMXONPhys);
101 if (pVM->hwaccm.s.vmx.pVMXON == 0)
102 {
103 AssertMsgFailed(("SUPContAlloc failed!!\n"));
104 return VERR_NO_MEMORY;
105 }
106 memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108 /* Allocate one page for the VM control structure (VMCS). */
109 pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(1, &pVM->hwaccm.s.vmx.pVMCSPhys);
110 if (pVM->hwaccm.s.vmx.pVMCS == 0)
111 {
112 AssertMsgFailed(("SUPContAlloc failed!!\n"));
113 return VERR_NO_MEMORY;
114 }
115 memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117 /* Reuse those two pages for AMD SVM. (one is active; never both) */
118 pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119 pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120 pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121 pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123 /* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124 pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(1, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125 if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126 {
127 AssertMsgFailed(("SUPContAlloc failed!!\n"));
128 return VERR_NO_MEMORY;
129 }
130 memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133 pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134 if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135 {
136 AssertMsgFailed(("SUPContAlloc failed!!\n"));
137 return VERR_NO_MEMORY;
138 }
139 /* Set all bits to intercept all IO accesses. */
140 memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143 pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144 if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145 {
146 AssertMsgFailed(("SUPContAlloc failed!!\n"));
147 return VERR_NO_MEMORY;
148 }
149 /* Set all bits to intercept all MSR accesses. */
150 memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152 /* Misc initialisation. */
153 pVM->hwaccm.s.vmx.fSupported = false;
154 pVM->hwaccm.s.svm.fSupported = false;
155 pVM->hwaccm.s.vmx.fEnabled = false;
156 pVM->hwaccm.s.svm.fEnabled = false;
157
158 pVM->hwaccm.s.fActive = false;
159
160 /* On first entry we'll sync everything. */
161 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163 pVM->hwaccm.s.vmx.cr0_mask = 0;
164 pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166 /*
167 * Statistics.
168 */
169 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
187 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
188 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
189 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
190 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
191 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
192 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
193 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
194 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
195 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
196 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
197
198 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
199 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
200
201 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
202 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
203 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
204
205 pVM->hwaccm.s.pStatExitReason = 0;
206
207#ifdef VBOX_WITH_STATISTICS
208 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
209 AssertRC(rc);
210 if (VBOX_SUCCESS(rc))
211 {
212 for (int i=0;i<MAX_EXITREASON_STAT;i++)
213 {
214 char szName[64];
215 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
216 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
217 AssertRC(rc);
218 }
219 }
220#endif
221
222 /* Disabled by default. */
223 pVM->fHWACCMEnabled = false;
224
225 /* HWACCM support must be explicitely enabled in the configuration file. */
226 pVM->hwaccm.s.fAllowed = false;
227 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
228
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * Turns off normal raw mode features
235 *
236 * @param pVM The VM to operate on.
237 */
238static void hwaccmr3DisableRawMode(PVM pVM)
239{
240 /* Disable PATM & CSAM. */
241 PATMR3AllowPatching(pVM, false);
242 CSAMDisableScanning(pVM);
243
244 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
245 SELMR3DisableMonitoring(pVM);
246 TRPMR3DisableMonitoring(pVM);
247
248 /* The hidden selector registers are now valid. */
249 CPUMSetHiddenSelRegsValid(pVM, true);
250
251 /* Disable the switcher code (safety precaution). */
252 VMMR3DisableSwitcher(pVM);
253
254 /* Disable mapping of the hypervisor into the shadow page table. */
255 PGMR3ChangeShwPDMappings(pVM, false);
256
257 /* Disable the switcher */
258 VMMR3DisableSwitcher(pVM);
259}
260
261/**
262 * Applies relocations to data and code managed by this
263 * component. This function will be called at init and
264 * whenever the VMM need to relocate it self inside the GC.
265 *
266 * @param pVM The VM.
267 */
268HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
269{
270#ifdef LOG_ENABLED
271 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
272#endif
273
274 if (pVM->hwaccm.s.fAllowed == false)
275 return ;
276
277 if (pVM->hwaccm.s.vmx.fSupported)
278 {
279 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
280 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
281 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
282 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
283 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
284 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
285 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
286 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
287 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
288 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
289 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
290 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
291 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
292 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
293
294 if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
295 {
296 /* Only try once. */
297 pVM->hwaccm.s.fInitialized = true;
298
299 int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
300 AssertRC(rc);
301 if (rc == VINF_SUCCESS)
302 {
303 hwaccmr3DisableRawMode(pVM);
304
305 pVM->fHWACCMEnabled = true;
306 pVM->hwaccm.s.vmx.fEnabled = true;
307 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
308 LogRel(("HWACCM: VMX enabled!\n"));
309 }
310 else
311 {
312 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
313 pVM->fHWACCMEnabled = false;
314 }
315 }
316 }
317 else
318 if (pVM->hwaccm.s.svm.fSupported)
319 {
320 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
321 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
322 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
323 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
324 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
325
326 if (pVM->hwaccm.s.fInitialized == false)
327 {
328 /* Only try once. */
329 pVM->hwaccm.s.fInitialized = true;
330
331 int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
332 AssertRC(rc);
333 if (rc == VINF_SUCCESS)
334 {
335 hwaccmr3DisableRawMode(pVM);
336 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
337
338 pVM->fHWACCMEnabled = true;
339 pVM->hwaccm.s.svm.fEnabled = true;
340 }
341 else
342 {
343 pVM->fHWACCMEnabled = false;
344 }
345 }
346 }
347
348}
349
350
351/**
352 * Checks hardware accelerated raw mode is allowed.
353 *
354 * @returns boolean
355 * @param pVM The VM to operate on.
356 */
357HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
358{
359 return pVM->hwaccm.s.fAllowed;
360}
361
362
363/**
364 * Notification callback which is called whenever there is a chance that a CR3
365 * value might have changed.
366 * This is called by PGM.
367 *
368 * @param pVM The VM to operate on.
369 * @param enmShadowMode New paging mode.
370 */
371HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
372{
373 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
374}
375
376/**
377 * Terminates the HWACCM.
378 *
379 * Termination means cleaning up and freeing all resources,
380 * the VM it self is at this point powered off or suspended.
381 *
382 * @returns VBox status code.
383 * @param pVM The VM to operate on.
384 */
385HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
386{
387 if (pVM->hwaccm.s.pStatExitReason)
388 {
389 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
390 pVM->hwaccm.s.pStatExitReason = 0;
391 }
392
393 if (pVM->hwaccm.s.vmx.pVMXON)
394 {
395 SUPContFree(pVM->hwaccm.s.vmx.pVMXON, 1);
396 pVM->hwaccm.s.vmx.pVMXON = 0;
397 }
398 if (pVM->hwaccm.s.vmx.pVMCS)
399 {
400 SUPContFree(pVM->hwaccm.s.vmx.pVMCS, 1);
401 pVM->hwaccm.s.vmx.pVMCS = 0;
402 }
403 if (pVM->hwaccm.s.svm.pVMCBHost)
404 {
405 SUPContFree(pVM->hwaccm.s.svm.pVMCBHost, 1);
406 pVM->hwaccm.s.svm.pVMCBHost = 0;
407 }
408 if (pVM->hwaccm.s.svm.pIOBitmap)
409 {
410 SUPContFree(pVM->hwaccm.s.svm.pIOBitmap, 3);
411 pVM->hwaccm.s.svm.pIOBitmap = 0;
412 }
413 if (pVM->hwaccm.s.svm.pMSRBitmap)
414 {
415 SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap, 2);
416 pVM->hwaccm.s.svm.pMSRBitmap = 0;
417 }
418 return 0;
419}
420
421
422/**
423 * The VM is being reset.
424 *
425 * For the HWACCM component this means that any GDT/LDT/TSS monitors
426 * needs to be removed.
427 *
428 * @param pVM VM handle.
429 */
430HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
431{
432 LogFlow(("HWACCMR3Reset:\n"));
433
434 if (pVM->fHWACCMEnabled)
435 hwaccmr3DisableRawMode(pVM);
436
437 /* On first entry we'll sync everything. */
438 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
439
440 pVM->hwaccm.s.vmx.cr0_mask = 0;
441 pVM->hwaccm.s.vmx.cr4_mask = 0;
442
443 pVM->hwaccm.s.Event.fPending = false;
444}
445
446/**
447 * Checks if we can currently use hardware accelerated raw mode.
448 *
449 * @returns boolean
450 * @param pVM The VM to operate on.
451 * @param pCtx Partial VM execution context
452 */
453HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
454{
455 uint32_t mask;
456
457 Assert(pVM->fHWACCMEnabled);
458
459 /* AMD SVM supports real & protected mode with or without paging. */
460 if (pVM->hwaccm.s.svm.fEnabled)
461 {
462 pVM->hwaccm.s.fActive = true;
463 return true;
464 }
465
466 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
467 * (but do we really care?)
468 */
469
470 pVM->hwaccm.s.fActive = false;
471
472 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
473
474 /* Too early for VMX. */
475 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
476 return false;
477
478 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
479 if (pCtx->csHid.Attr.n.u1Present == 0)
480 return false;
481 if (pCtx->ssHid.Attr.n.u1Present == 0)
482 return false;
483
484 /** @todo if we remove this check, then Windows XP install fails during the textmode phase */
485 if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
486 return false;
487
488 if (pVM->hwaccm.s.vmx.fEnabled)
489 {
490 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
491 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
492 /** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
493 mask &= ~X86_CR0_NE;
494
495 if ((pCtx->cr0 & mask) != mask)
496 return false;
497
498 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
499 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
500 if ((pCtx->cr0 & mask) != 0)
501 return false;
502
503 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
504 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
505 mask &= ~X86_CR4_VMXE;
506 if ((pCtx->cr4 & mask) != mask)
507 return false;
508
509 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
510 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
511 if ((pCtx->cr4 & mask) != 0)
512 return false;
513
514 pVM->hwaccm.s.fActive = true;
515 return true;
516 }
517#if 0
518 else
519 if (pVM->hwaccm.s.svm.fEnabled)
520 {
521 pVM->hwaccm.s.fActive = true;
522 return true;
523 }
524#endif
525
526 return false;
527}
528
529/**
530 * Checks if we are currently using hardware accelerated raw mode.
531 *
532 * @returns boolean
533 * @param pVM The VM to operate on.
534 */
535HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
536{
537 return pVM->hwaccm.s.fActive;
538}
539
540/**
541 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
542 *
543 * @returns boolean
544 * @param pVM The VM to operate on.
545 */
546HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
547{
548 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
549}
550
551/**
552 * Execute state save operation.
553 *
554 * @returns VBox status code.
555 * @param pVM VM Handle.
556 * @param pSSM SSM operation handle.
557 */
558static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
559{
560 int rc;
561
562 Log(("hwaccmR3Save:\n"));
563
564 /*
565 * Save the basic bits - fortunately all the other things can be resynced on load.
566 */
567 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
568 AssertRCReturn(rc, rc);
569 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
570 AssertRCReturn(rc, rc);
571 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
572 AssertRCReturn(rc, rc);
573
574 return VINF_SUCCESS;
575}
576
577
578/**
579 * Execute state load operation.
580 *
581 * @returns VBox status code.
582 * @param pVM VM Handle.
583 * @param pSSM SSM operation handle.
584 * @param u32Version Data layout version.
585 */
586static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
587{
588 int rc;
589
590 Log(("hwaccmR3Load:\n"));
591
592 /*
593 * Validate version.
594 */
595 if (u32Version != HWACCM_SSM_VERSION)
596 {
597 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
598 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
599 }
600 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
601 AssertRCReturn(rc, rc);
602 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
603 AssertRCReturn(rc, rc);
604 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
605 AssertRCReturn(rc, rc);
606
607 return VINF_SUCCESS;
608}
609
610
611
612
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