VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 22264

Last change on this file since 22264 was 22264, checked in by vboxsync, 16 years ago

Move the TPR patching decision logic to Main.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 118.6 KB
Line 
1/* $Id: HWACCM.cpp 22264 2009-08-14 15:23:54Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
331 /* Nested paging: disabled by default. */
332 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
333 AssertRC(rc);
334
335 /* VT-x VPID: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
337 AssertRC(rc);
338
339 /* HWACCM support must be explicitely enabled in the configuration file. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
341 AssertRC(rc);
342
343 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
344 rc = CFGMR3QueryBoolDef(pRoot, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
345 AssertRC(rc);
346
347#ifdef RT_OS_DARWIN
348 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
349#else
350 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
351#endif
352 {
353 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
354 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
355 return VERR_HWACCM_CONFIG_MISMATCH;
356 }
357
358 if (VMMIsHwVirtExtForced(pVM))
359 pVM->fHWACCMEnabled = true;
360
361#if HC_ARCH_BITS == 32
362 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
363 * (To use the default, don't set 64bitEnabled in CFGM.) */
364 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
365 AssertLogRelRCReturn(rc, rc);
366 if (pVM->hwaccm.s.fAllow64BitGuests)
367 {
368# ifdef RT_OS_DARWIN
369 if (!VMMIsHwVirtExtForced(pVM))
370# else
371 if (!pVM->hwaccm.s.fAllowed)
372# endif
373 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
374 }
375#else
376 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
377 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
378 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
379 AssertLogRelRCReturn(rc, rc);
380#endif
381
382 /* Max number of resume loops. */
383 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
384 AssertRC(rc);
385
386 return VINF_SUCCESS;
387}
388
389/**
390 * Initializes the per-VCPU HWACCM.
391 *
392 * @returns VBox status code.
393 * @param pVM The VM to operate on.
394 */
395VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
396{
397 LogFlow(("HWACCMR3InitCPU\n"));
398
399 for (unsigned i=0;i<pVM->cCPUs;i++)
400 {
401 PVMCPU pVCpu = &pVM->aCpus[i];
402
403 pVCpu->hwaccm.s.fActive = false;
404 }
405
406#ifdef VBOX_WITH_STATISTICS
407 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
408 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
409 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
410 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
411
412 /*
413 * Statistics.
414 */
415 for (unsigned i=0;i<pVM->cCPUs;i++)
416 {
417 PVMCPU pVCpu = &pVM->aCpus[i];
418 int rc;
419
420 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
421 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
422 AssertRC(rc);
423 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
424 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
425 AssertRC(rc);
426 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
427 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
428 AssertRC(rc);
429# if 1 /* temporary for tracking down darwin holdup. */
430 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
431 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
432 AssertRC(rc);
433 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
434 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
435 AssertRC(rc);
436 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
437 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
438 AssertRC(rc);
439# endif
440 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
441 "/PROF/HWACCM/CPU%d/InGC", i);
442 AssertRC(rc);
443
444# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
445 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
446 "/PROF/HWACCM/CPU%d/Switcher3264", i);
447 AssertRC(rc);
448# endif
449
450# define HWACCM_REG_COUNTER(a, b) \
451 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
452 AssertRC(rc);
453
454 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
455 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
456 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
457 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
458 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
459 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
460 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
461 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
462 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
463 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
464 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
465 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
466 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
467 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
468 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
469 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
470 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
471 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
472 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
473 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
474 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
491
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
494
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
498
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
510
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
514
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
518
519 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
520 {
521 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
522 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
523 AssertRC(rc);
524 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
525 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
526 AssertRC(rc);
527 }
528
529#undef HWACCM_REG_COUNTER
530
531 pVCpu->hwaccm.s.paStatExitReason = NULL;
532
533 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
534 AssertRC(rc);
535 if (RT_SUCCESS(rc))
536 {
537 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
538 for (int j=0;j<MAX_EXITREASON_STAT;j++)
539 {
540 if (papszDesc[j])
541 {
542 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
543 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
544 AssertRC(rc);
545 }
546 }
547 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
548 AssertRC(rc);
549 }
550 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
551# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
552 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
553# else
554 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
555# endif
556
557 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
558 AssertRCReturn(rc, rc);
559 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
560# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
561 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
562# else
563 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
564# endif
565 for (unsigned j = 0; j < 255; j++)
566 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
567 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
568
569 }
570#endif /* VBOX_WITH_STATISTICS */
571
572#ifdef VBOX_WITH_CRASHDUMP_MAGIC
573 /* Magic marker for searching in crash dumps. */
574 for (unsigned i=0;i<pVM->cCPUs;i++)
575 {
576 PVMCPU pVCpu = &pVM->aCpus[i];
577
578 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
579 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
580 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
581 }
582#endif
583 return VINF_SUCCESS;
584}
585
586/**
587 * Turns off normal raw mode features
588 *
589 * @param pVM The VM to operate on.
590 */
591static void hwaccmR3DisableRawMode(PVM pVM)
592{
593 /* Disable PATM & CSAM. */
594 PATMR3AllowPatching(pVM, false);
595 CSAMDisableScanning(pVM);
596
597 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
598 SELMR3DisableMonitoring(pVM);
599 TRPMR3DisableMonitoring(pVM);
600
601 /* Disable the switcher code (safety precaution). */
602 VMMR3DisableSwitcher(pVM);
603
604 /* Disable mapping of the hypervisor into the shadow page table. */
605 PGMR3MappingsDisable(pVM);
606
607 /* Disable the switcher */
608 VMMR3DisableSwitcher(pVM);
609
610 /* Reinit the paging mode to force the new shadow mode. */
611 for (unsigned i=0;i<pVM->cCPUs;i++)
612 {
613 PVMCPU pVCpu = &pVM->aCpus[i];
614
615 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
616 }
617}
618
619/**
620 * Initialize VT-x or AMD-V.
621 *
622 * @returns VBox status code.
623 * @param pVM The VM handle.
624 */
625VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
626{
627 int rc;
628
629 if ( !pVM->hwaccm.s.vmx.fSupported
630 && !pVM->hwaccm.s.svm.fSupported)
631 {
632 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
633 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
634 if (VMMIsHwVirtExtForced(pVM))
635 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
636 return VINF_SUCCESS;
637 }
638
639 if (!pVM->hwaccm.s.fAllowed)
640 return VINF_SUCCESS; /* nothing to do */
641
642 /* Enable VT-x or AMD-V on all host CPUs. */
643 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
644 if (RT_FAILURE(rc))
645 {
646 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
647 return rc;
648 }
649 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
650
651 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
652 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
653 if (!pVM->hwaccm.s.fHasIoApic)
654 {
655 Assert(pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
656 pVM->hwaccm.s.fTRPPatchingAllowed = false;
657 }
658
659 if (pVM->hwaccm.s.vmx.fSupported)
660 {
661 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
662
663 if ( pVM->hwaccm.s.fInitialized == false
664 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
665 {
666 uint64_t val;
667 RTGCPHYS GCPhys = 0;
668
669 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
670 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
671 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
672 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
673 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
674 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
675 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
676 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
677
678 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
679 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
680 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
681 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
682 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
683 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
684 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
685 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
686 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
687 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
688 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
689 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
690 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
691 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
692 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
693 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
694 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
695 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
696 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
697
698 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
699 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
700 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
701 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
702 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
703 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
704 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
705 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
706 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
707 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
708 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
709 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
710 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
711 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
712 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
713 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
714 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
715 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
716 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
717 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
718 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
719 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
720 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
721 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
722 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
723 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
724 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
725 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
726 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
727 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
728 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
729 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
730 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
731 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
732 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
733 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
734 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
736 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
738 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
740 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
742
743 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
744 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
745 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
746 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
747 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
748 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
749 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
750 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
751 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
752 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
753 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
754 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
755 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
756 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
757 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
758 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
760 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
762 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
764 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
766 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
768 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
769 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
770 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
772 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
776 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
778 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
786
787 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
788 {
789 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
790 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
791 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
792 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
793 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
794 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
795 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
796 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
797 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
798 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
799 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
800 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
801 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
802 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
803
804 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
805 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
806 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
807 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
809 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
817 }
818
819 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
820 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
821 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
822 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
823 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
825 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
827 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
829 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
831 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
833 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
835 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
836 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
850
851 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
852 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
853 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
854 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
855 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
856 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
857 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
858 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
859 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
860 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
861 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
862 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
863 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
864 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
865 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
866 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
867 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
868 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
869 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
870 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
872 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
874 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
876 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
877 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
878 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
880 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
882 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
884 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
886
887 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
888 {
889 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
890
891 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
892 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
893 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
894 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
895 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
896 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
897 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
898 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
899 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
900 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
901 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
902 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
903 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
904 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
905 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
906 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
907 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
908 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
909 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
910 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
911 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
912 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
913 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
914 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
915 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
916 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
917 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
918 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
919 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
920 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
921 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
922 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
923 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
924 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
925 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
926 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
927 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
928 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
929 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
930 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
931 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
932 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
933 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
934 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
935 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
936 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
937 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
938 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
939 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
940 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
941 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
942 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
943 }
944
945 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
946 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
947 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
948 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
949 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
950 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
951
952 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
953 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
954 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
955 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
956 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
957
958 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
959
960 /* Paranoia */
961 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
962
963 for (unsigned i=0;i<pVM->cCPUs;i++)
964 {
965 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
966 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
967 }
968
969#ifdef HWACCM_VTX_WITH_EPT
970 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
971 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
972#endif /* HWACCM_VTX_WITH_EPT */
973#ifdef HWACCM_VTX_WITH_VPID
974 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
975 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
976 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
977#endif /* HWACCM_VTX_WITH_VPID */
978
979 /* Only try once. */
980 pVM->hwaccm.s.fInitialized = true;
981
982 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
983#if 1
984 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
985#else
986 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
987#endif
988 if (RT_SUCCESS(rc))
989 {
990 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
991 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
992 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
993 /* Bit set to 0 means redirection enabled. */
994 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
995 /* Allow all port IO, so the VT-x IO intercepts do their job. */
996 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
997 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
998
999 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1000 * real and protected mode without paging with EPT.
1001 */
1002 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1003 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1004 {
1005 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1006 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1007 }
1008
1009 /* We convert it here every time as pci regions could be reconfigured. */
1010 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1011 AssertRC(rc);
1012 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1013
1014 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1015 AssertRC(rc);
1016 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1017 }
1018 else
1019 {
1020 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1021 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1022 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1023 }
1024
1025 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1026 AssertRC(rc);
1027 if (rc == VINF_SUCCESS)
1028 {
1029 pVM->fHWACCMEnabled = true;
1030 pVM->hwaccm.s.vmx.fEnabled = true;
1031 hwaccmR3DisableRawMode(pVM);
1032
1033 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1034#ifdef VBOX_ENABLE_64_BITS_GUESTS
1035 if (pVM->hwaccm.s.fAllow64BitGuests)
1036 {
1037 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1038 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1039 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1040 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1041 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1042 }
1043 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1044 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1045 : "HWACCM: 32-bit guests supported.\n"));
1046#else
1047 LogRel(("HWACCM: 32-bit guests supported.\n"));
1048#endif
1049 LogRel(("HWACCM: VMX enabled!\n"));
1050 if (pVM->hwaccm.s.fNestedPaging)
1051 {
1052 LogRel(("HWACCM: Enabled nested paging\n"));
1053 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1054 }
1055 if (pVM->hwaccm.s.vmx.fVPID)
1056 LogRel(("HWACCM: Enabled VPID\n"));
1057
1058 if ( pVM->hwaccm.s.fNestedPaging
1059 || pVM->hwaccm.s.vmx.fVPID)
1060 {
1061 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1062 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1063 }
1064 }
1065 else
1066 {
1067 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1068 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1069 pVM->fHWACCMEnabled = false;
1070 }
1071 }
1072 }
1073 else
1074 if (pVM->hwaccm.s.svm.fSupported)
1075 {
1076 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1077
1078 if (pVM->hwaccm.s.fInitialized == false)
1079 {
1080 /* Erratum 170 which requires a forced TLB flush for each world switch:
1081 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1082 *
1083 * All BH-G1/2 and DH-G1/2 models include a fix:
1084 * Athlon X2: 0x6b 1/2
1085 * 0x68 1/2
1086 * Athlon 64: 0x7f 1
1087 * 0x6f 2
1088 * Sempron: 0x7f 1/2
1089 * 0x6f 2
1090 * 0x6c 2
1091 * 0x7c 2
1092 * Turion 64: 0x68 2
1093 *
1094 */
1095 uint32_t u32Dummy;
1096 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1097 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1098 u32BaseFamily= (u32Version >> 8) & 0xf;
1099 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1100 u32Model = ((u32Version >> 4) & 0xf);
1101 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1102 u32Stepping = u32Version & 0xf;
1103 if ( u32Family == 0xf
1104 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1105 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1106 {
1107 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1108 }
1109
1110 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1111 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1112 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1113 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1114 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1115
1116 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1117 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1118 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1119 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1120 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1121 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1122 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1123 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1124 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1125 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1126
1127 /* Only try once. */
1128 pVM->hwaccm.s.fInitialized = true;
1129
1130 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1131 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1132
1133 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1134 AssertRC(rc);
1135 if (rc == VINF_SUCCESS)
1136 {
1137 pVM->fHWACCMEnabled = true;
1138 pVM->hwaccm.s.svm.fEnabled = true;
1139
1140 if (pVM->hwaccm.s.fNestedPaging)
1141 LogRel(("HWACCM: Enabled nested paging\n"));
1142
1143 hwaccmR3DisableRawMode(pVM);
1144 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1145 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1146 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1147#ifdef VBOX_ENABLE_64_BITS_GUESTS
1148 if (pVM->hwaccm.s.fAllow64BitGuests)
1149 {
1150 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1151 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1152 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1153 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1154 }
1155#endif
1156 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1157 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1158 : "HWACCM: 32-bit guest supported.\n"));
1159 }
1160 else
1161 {
1162 pVM->fHWACCMEnabled = false;
1163 }
1164 }
1165 }
1166 return VINF_SUCCESS;
1167}
1168
1169/**
1170 * Applies relocations to data and code managed by this
1171 * component. This function will be called at init and
1172 * whenever the VMM need to relocate it self inside the GC.
1173 *
1174 * @param pVM The VM.
1175 */
1176VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1177{
1178 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1179
1180 /* Fetch the current paging mode during the relocate callback during state loading. */
1181 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1182 {
1183 for (unsigned i=0;i<pVM->cCPUs;i++)
1184 {
1185 PVMCPU pVCpu = &pVM->aCpus[i];
1186
1187 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1188 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1189 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1190 }
1191 }
1192#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1193 if (pVM->fHWACCMEnabled)
1194 {
1195 int rc;
1196
1197 switch(PGMGetHostMode(pVM))
1198 {
1199 case PGMMODE_32_BIT:
1200 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1201 break;
1202
1203 case PGMMODE_PAE:
1204 case PGMMODE_PAE_NX:
1205 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1206 break;
1207
1208 default:
1209 AssertFailed();
1210 break;
1211 }
1212 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1213 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1214
1215 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1216 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1217
1218 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1219 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1220
1221 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1222 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1223
1224# ifdef DEBUG
1225 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1226 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1227# endif
1228 }
1229#endif
1230 return;
1231}
1232
1233/**
1234 * Checks hardware accelerated raw mode is allowed.
1235 *
1236 * @returns boolean
1237 * @param pVM The VM to operate on.
1238 */
1239VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1240{
1241 return pVM->hwaccm.s.fAllowed;
1242}
1243
1244/**
1245 * Notification callback which is called whenever there is a chance that a CR3
1246 * value might have changed.
1247 *
1248 * This is called by PGM.
1249 *
1250 * @param pVM The VM to operate on.
1251 * @param pVCpu The VMCPU to operate on.
1252 * @param enmShadowMode New shadow paging mode.
1253 * @param enmGuestMode New guest paging mode.
1254 */
1255VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1256{
1257 /* Ignore page mode changes during state loading. */
1258 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1259 return;
1260
1261 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1262
1263 if ( pVM->hwaccm.s.vmx.fEnabled
1264 && pVM->fHWACCMEnabled)
1265 {
1266 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1267 && enmGuestMode >= PGMMODE_PROTECTED)
1268 {
1269 PCPUMCTX pCtx;
1270
1271 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1272
1273 /* After a real mode switch to protected mode we must force
1274 * CPL to 0. Our real mode emulation had to set it to 3.
1275 */
1276 pCtx->ssHid.Attr.n.u2Dpl = 0;
1277 }
1278 }
1279
1280 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1281 {
1282 /* Keep track of paging mode changes. */
1283 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1284 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1285
1286 /* Did we miss a change, because all code was executed in the recompiler? */
1287 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1288 {
1289 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1290 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1291 }
1292 }
1293
1294 /* Reset the contents of the read cache. */
1295 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1296 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1297 pCache->Read.aFieldVal[j] = 0;
1298}
1299
1300/**
1301 * Terminates the HWACCM.
1302 *
1303 * Termination means cleaning up and freeing all resources,
1304 * the VM it self is at this point powered off or suspended.
1305 *
1306 * @returns VBox status code.
1307 * @param pVM The VM to operate on.
1308 */
1309VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1310{
1311 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1312 {
1313 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1314 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1315 }
1316 HWACCMR3TermCPU(pVM);
1317 return 0;
1318}
1319
1320/**
1321 * Terminates the per-VCPU HWACCM.
1322 *
1323 * Termination means cleaning up and freeing all resources,
1324 * the VM it self is at this point powered off or suspended.
1325 *
1326 * @returns VBox status code.
1327 * @param pVM The VM to operate on.
1328 */
1329VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1330{
1331 for (unsigned i=0;i<pVM->cCPUs;i++)
1332 {
1333 PVMCPU pVCpu = &pVM->aCpus[i];
1334
1335#ifdef VBOX_WITH_STATISTICS
1336 if (pVCpu->hwaccm.s.paStatExitReason)
1337 {
1338 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1339 pVCpu->hwaccm.s.paStatExitReason = NULL;
1340 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1341 }
1342 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1343 {
1344 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1345 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1346 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1347 }
1348#endif
1349
1350#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1351 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1352 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1353 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1354#endif
1355 }
1356 return 0;
1357}
1358
1359/**
1360 * The VM is being reset.
1361 *
1362 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1363 * needs to be removed.
1364 *
1365 * @param pVM VM handle.
1366 */
1367VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1368{
1369 LogFlow(("HWACCMR3Reset:\n"));
1370
1371 if (pVM->fHWACCMEnabled)
1372 hwaccmR3DisableRawMode(pVM);
1373
1374 for (unsigned i=0;i<pVM->cCPUs;i++)
1375 {
1376 PVMCPU pVCpu = &pVM->aCpus[i];
1377
1378 /* On first entry we'll sync everything. */
1379 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1380
1381 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1382 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1383
1384 pVCpu->hwaccm.s.fActive = false;
1385 pVCpu->hwaccm.s.Event.fPending = false;
1386
1387 /* Reset state information for real-mode emulation in VT-x. */
1388 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1389 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1390 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1391
1392 /* Reset the contents of the read cache. */
1393 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1394 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1395 pCache->Read.aFieldVal[j] = 0;
1396
1397#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1398 /* Magic marker for searching in crash dumps. */
1399 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1400 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1401#endif
1402 }
1403
1404 /* Clear all patch information. */
1405 pVM->hwaccm.s.pGuestPatchMem = 0;
1406 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1407 pVM->hwaccm.s.cbGuestPatchMem = 0;
1408 pVM->hwaccm.s.svm.cPatches = 0;
1409 pVM->hwaccm.s.svm.PatchTree = 0;
1410 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1411 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1412}
1413
1414/**
1415 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1416 *
1417 * @returns VBox status code.
1418 * @param pVM The VM handle.
1419 * @param pVCpu The VMCPU for the EMT we're being called on.
1420 * @param pvUser Unused
1421 *
1422 */
1423DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1424{
1425 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1426
1427 /* Only execute the handler on the VCPU the original patch request was issued. */
1428 if (pVCpu->idCpu != idCpu)
1429 return VINF_SUCCESS;
1430
1431 Log(("hwaccmR3RemovePatches\n"));
1432 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1433 {
1434 uint8_t szInstr[15];
1435 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1436 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1437 int rc;
1438
1439#ifdef LOG_ENABLED
1440 char szOutput[256];
1441
1442 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1443 if (VBOX_SUCCESS(rc))
1444 Log(("Patched instr: %s\n", szOutput));
1445#endif
1446
1447 /* Check if the instruction is still the same. */
1448 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1449 if (rc != VINF_SUCCESS)
1450 {
1451 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1452 continue; /* swapped out or otherwise removed; skip it. */
1453 }
1454
1455 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1456 {
1457 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1458 continue; /* skip it. */
1459 }
1460
1461 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1462 AssertRC(rc);
1463
1464#ifdef LOG_ENABLED
1465 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1466 if (VBOX_SUCCESS(rc))
1467 Log(("Original instr: %s\n", szOutput));
1468#endif
1469 }
1470 pVM->hwaccm.s.svm.cPatches = 0;
1471 pVM->hwaccm.s.svm.PatchTree = 0;
1472 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1473 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1474 return VINF_SUCCESS;
1475}
1476
1477/**
1478 * Enable patching in a VT-x/AMD-V guest
1479 *
1480 * @returns VBox status code.
1481 * @param pVM The VM to operate on.
1482 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1483 * @param pPatchMem Patch memory range
1484 * @param cbPatchMem Size of the memory range
1485 */
1486int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1487{
1488 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1489 AssertRC(rc);
1490
1491 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1492 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1493 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1494 return VINF_SUCCESS;
1495}
1496
1497/**
1498 * Enable patching in a VT-x/AMD-V guest
1499 *
1500 * @returns VBox status code.
1501 * @param pVM The VM to operate on.
1502 * @param pPatchMem Patch memory range
1503 * @param cbPatchMem Size of the memory range
1504 */
1505VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1506{
1507 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1508
1509 /* Current TPR patching only applies to AMD cpus.
1510 * Needs to be extended to Intel CPUs without the APIC TPR hardware optimization.
1511 */
1512 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1513 return VERR_NOT_SUPPORTED;
1514
1515 if (pVM->cCPUs > 1)
1516 {
1517 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1518 PVMREQ pReq;
1519 int rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
1520 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1521 AssertRC(rc);
1522 return rc;
1523 }
1524 else
1525 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1526}
1527
1528/**
1529 * Disable patching in a VT-x/AMD-V guest
1530 *
1531 * @returns VBox status code.
1532 * @param pVM The VM to operate on.
1533 * @param pPatchMem Patch memory range
1534 * @param cbPatchMem Size of the memory range
1535 */
1536VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1537{
1538 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1539
1540 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1541 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1542
1543 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1544 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1545 AssertRC(rc);
1546
1547 pVM->hwaccm.s.pGuestPatchMem = 0;
1548 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1549 pVM->hwaccm.s.cbGuestPatchMem = 0;
1550 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1551 return VINF_SUCCESS;
1552}
1553
1554
1555/**
1556 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1557 *
1558 * @returns VBox status code.
1559 * @param pVM The VM handle.
1560 * @param pVCpu The VMCPU for the EMT we're being called on.
1561 * @param pvUser User specified CPU context
1562 *
1563 */
1564DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1565{
1566 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1567 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1568 RTGCPTR oldrip = pCtx->rip;
1569 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1570 unsigned cbOp;
1571
1572 /* Only execute the handler on the VCPU the original patch request was issued. */
1573 if (pVCpu->idCpu != idCpu)
1574 return VINF_SUCCESS;
1575
1576 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1577
1578 /* Two or more VCPUs were racing to patch this instruction. */
1579 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1580 if (pPatch)
1581 return VINF_SUCCESS;
1582
1583 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1584
1585 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1586 AssertRC(rc);
1587 if ( rc == VINF_SUCCESS
1588 && pDis->pCurInstr->opcode == OP_MOV
1589 && cbOp >= 3)
1590 {
1591 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1592 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1593 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1594
1595 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1596 AssertRC(rc);
1597
1598 pPatch->cbOp = cbOp;
1599
1600 if (pDis->param1.flags == USE_DISPLACEMENT32)
1601 {
1602 /* write. */
1603 if (pDis->param2.flags == USE_REG_GEN32)
1604 {
1605 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1606 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1607 }
1608 else
1609 {
1610 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1611 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1612 pPatch->uSrcOperand = pDis->param2.parval;
1613 }
1614 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1615 AssertRC(rc);
1616
1617 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1618 pPatch->cbNewOp = sizeof(aVMMCall);
1619 }
1620 else
1621 {
1622 RTGCPTR oldrip = pCtx->rip;
1623 uint32_t oldcbOp = cbOp;
1624 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1625
1626 /* read */
1627 Assert(pDis->param1.flags == USE_REG_GEN32);
1628
1629 /* Found:
1630 * mov eax, dword [fffe0080] (5 bytes)
1631 * Check if next instruction is:
1632 * shr eax, 4
1633 */
1634 pCtx->rip += cbOp;
1635 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1636 pCtx->rip = oldrip;
1637 if ( rc == VINF_SUCCESS
1638 && pDis->pCurInstr->opcode == OP_SHR
1639 && pDis->param1.flags == USE_REG_GEN32
1640 && pDis->param1.base.reg_gen == uMmioReg
1641 && pDis->param2.flags == USE_IMMEDIATE8
1642 && pDis->param2.parval == 4
1643 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1644 {
1645 uint8_t szInstr[15];
1646
1647 /* Replacing two instructions now. */
1648 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1649 AssertRC(rc);
1650
1651 pPatch->cbOp = oldcbOp + cbOp;
1652
1653 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1654 szInstr[0] = 0xF0;
1655 szInstr[1] = 0x0F;
1656 szInstr[2] = 0x20;
1657 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1658 for (unsigned i = 4; i < pPatch->cbOp; i++)
1659 szInstr[i] = 0x90; /* nop */
1660
1661 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1662 AssertRC(rc);
1663
1664 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1665 pPatch->cbNewOp = pPatch->cbOp;
1666
1667 Log(("Acceptable read/shr candidate!\n"));
1668 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1669 }
1670 else
1671 {
1672 pPatch->enmType = HWACCMTPRINSTR_READ;
1673 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1674
1675 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1676 AssertRC(rc);
1677
1678 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1679 pPatch->cbNewOp = sizeof(aVMMCall);
1680 }
1681 }
1682
1683 pPatch->Core.Key = pCtx->eip;
1684 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1685 AssertRC(rc);
1686
1687 pVM->hwaccm.s.svm.cPatches++;
1688 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1689 return VINF_SUCCESS;
1690 }
1691
1692 /* Save invalid patch, so we will not try again. */
1693 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1694
1695#ifdef LOG_ENABLED
1696 char szOutput[256];
1697 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1698 if (VBOX_SUCCESS(rc))
1699 Log(("Failed to patch instr: %s\n", szOutput));
1700#endif
1701
1702 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1703 pPatch->Core.Key = pCtx->eip;
1704 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1705 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1706 AssertRC(rc);
1707 pVM->hwaccm.s.svm.cPatches++;
1708 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1709 return VINF_SUCCESS;
1710}
1711
1712/**
1713 * Callback to patch a TPR instruction (jump to generated code)
1714 *
1715 * @returns VBox status code.
1716 * @param pVM The VM handle.
1717 * @param pVCpu The VMCPU for the EMT we're being called on.
1718 * @param pvUser User specified CPU context
1719 *
1720 */
1721DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1722{
1723 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1724 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1725 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1726 unsigned cbOp;
1727 int rc;
1728#ifdef LOG_ENABLED
1729 RTGCPTR pInstr;
1730 char szOutput[256];
1731#endif
1732
1733 /* Only execute the handler on the VCPU the original patch request was issued. */
1734 if (pVCpu->idCpu != idCpu)
1735 return VINF_SUCCESS;
1736
1737 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1738
1739 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1740
1741 /* Two or more VCPUs were racing to patch this instruction. */
1742 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1743 if (pPatch)
1744 return VINF_SUCCESS;
1745
1746 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1747 AssertRC(rc);
1748 if ( rc == VINF_SUCCESS
1749 && pDis->pCurInstr->opcode == OP_MOV
1750 && cbOp >= 5)
1751 {
1752 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1753 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1754 uint8_t aPatch[64];
1755 uint32_t off = 0;
1756
1757#ifdef LOG_ENABLED
1758 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1759 if (VBOX_SUCCESS(rc))
1760 Log(("Original instr: %s\n", szOutput));
1761#endif
1762
1763 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1764 AssertRC(rc);
1765
1766 pPatch->cbOp = cbOp;
1767 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1768
1769 if (pDis->param1.flags == USE_DISPLACEMENT32)
1770 {
1771 /*
1772 * TPR write:
1773 *
1774 * push ECX [51]
1775 * push EDX [52]
1776 * push EAX [50]
1777 * xor EDX,EDX [31 D2]
1778 * mov EAX,EAX [89 C0]
1779 * or
1780 * mov EAX,0000000CCh [B8 CC 00 00 00]
1781 * mov ECX,0C0000082h [B9 82 00 00 C0]
1782 * wrmsr [0F 30]
1783 * pop EAX [58]
1784 * pop EDX [5A]
1785 * pop ECX [59]
1786 * jmp return_address [E9 return_address]
1787 *
1788 */
1789 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1790
1791 aPatch[off++] = 0x51; /* push ecx */
1792 aPatch[off++] = 0x52; /* push edx */
1793 if (!fUsesEax)
1794 aPatch[off++] = 0x50; /* push eax */
1795 aPatch[off++] = 0x31; /* xor edx, edx */
1796 aPatch[off++] = 0xD2;
1797 if (pDis->param2.flags == USE_REG_GEN32)
1798 {
1799 if (!fUsesEax)
1800 {
1801 aPatch[off++] = 0x89; /* mov eax, src_reg */
1802 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1803 }
1804 }
1805 else
1806 {
1807 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1808 aPatch[off++] = 0xB8; /* mov eax, immediate */
1809 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1810 off += sizeof(uint32_t);
1811 }
1812 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1813 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1814 off += sizeof(uint32_t);
1815
1816 aPatch[off++] = 0x0F; /* wrmsr */
1817 aPatch[off++] = 0x30;
1818 if (!fUsesEax)
1819 aPatch[off++] = 0x58; /* pop eax */
1820 aPatch[off++] = 0x5A; /* pop edx */
1821 aPatch[off++] = 0x59; /* pop ecx */
1822 }
1823 else
1824 {
1825 /*
1826 * TPR read:
1827 *
1828 * push ECX [51]
1829 * push EDX [52]
1830 * push EAX [50]
1831 * mov ECX,0C0000082h [B9 82 00 00 C0]
1832 * rdmsr [0F 32]
1833 * mov EAX,EAX [89 C0]
1834 * pop EAX [58]
1835 * pop EDX [5A]
1836 * pop ECX [59]
1837 * jmp return_address [E9 return_address]
1838 *
1839 */
1840 Assert(pDis->param1.flags == USE_REG_GEN32);
1841
1842 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1843 aPatch[off++] = 0x51; /* push ecx */
1844 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1845 aPatch[off++] = 0x52; /* push edx */
1846 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1847 aPatch[off++] = 0x50; /* push eax */
1848
1849 aPatch[off++] = 0x31; /* xor edx, edx */
1850 aPatch[off++] = 0xD2;
1851
1852 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1853 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1854 off += sizeof(uint32_t);
1855
1856 aPatch[off++] = 0x0F; /* rdmsr */
1857 aPatch[off++] = 0x32;
1858
1859 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1860 {
1861 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1862 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1863 }
1864
1865 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1866 aPatch[off++] = 0x58; /* pop eax */
1867 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1868 aPatch[off++] = 0x5A; /* pop edx */
1869 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1870 aPatch[off++] = 0x59; /* pop ecx */
1871 }
1872 aPatch[off++] = 0xE9; /* jmp return_address */
1873 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1874 off += sizeof(RTRCUINTPTR);
1875
1876 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1877 {
1878 /* Write new code to the patch buffer. */
1879 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1880 AssertRC(rc);
1881
1882#ifdef LOG_ENABLED
1883 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1884 while (true)
1885 {
1886 uint32_t cb;
1887
1888 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1889 if (VBOX_SUCCESS(rc))
1890 Log(("Patch instr %s\n", szOutput));
1891
1892 pInstr += cb;
1893
1894 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1895 break;
1896 }
1897#endif
1898
1899 pPatch->aNewOpcode[0] = 0xE9;
1900 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1901
1902 /* Overwrite the TPR instruction with a jump. */
1903 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1904 AssertRC(rc);
1905
1906#ifdef LOG_ENABLED
1907 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1908 if (VBOX_SUCCESS(rc))
1909 Log(("Jump: %s\n", szOutput));
1910#endif
1911 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1912 pPatch->cbNewOp = 5;
1913
1914 pPatch->Core.Key = pCtx->eip;
1915 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1916 AssertRC(rc);
1917
1918 pVM->hwaccm.s.svm.cPatches++;
1919 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1920 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
1921 return VINF_SUCCESS;
1922 }
1923 else
1924 Log(("Ran out of space in our patch buffer!\n"));
1925 }
1926
1927 /* Save invalid patch, so we will not try again. */
1928 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1929
1930#ifdef LOG_ENABLED
1931 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1932 if (VBOX_SUCCESS(rc))
1933 Log(("Failed to patch instr: %s\n", szOutput));
1934#endif
1935
1936 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1937 pPatch->Core.Key = pCtx->eip;
1938 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1939 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1940 AssertRC(rc);
1941 pVM->hwaccm.s.svm.cPatches++;
1942 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
1943 return VINF_SUCCESS;
1944}
1945
1946/**
1947 * Attempt to patch TPR mmio instructions
1948 *
1949 * @returns VBox status code.
1950 * @param pVM The VM to operate on.
1951 * @param pVCpu The VM CPU to operate on.
1952 * @param pCtx CPU context
1953 */
1954VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1955{
1956 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1957 AssertRC(rc);
1958 return rc;
1959}
1960
1961/**
1962 * Force execution of the current IO code in the recompiler
1963 *
1964 * @returns VBox status code.
1965 * @param pVM The VM to operate on.
1966 * @param pCtx Partial VM execution context
1967 */
1968VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1969{
1970 PVMCPU pVCpu = VMMGetCpu(pVM);
1971
1972 Assert(pVM->fHWACCMEnabled);
1973 Log(("HWACCMR3EmulateIoBlock\n"));
1974
1975 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1976 if (HWACCMCanEmulateIoBlockEx(pCtx))
1977 {
1978 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1979 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1980 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1981 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
1982 return VINF_EM_RESCHEDULE_REM;
1983 }
1984 return VINF_SUCCESS;
1985}
1986
1987/**
1988 * Checks if we can currently use hardware accelerated raw mode.
1989 *
1990 * @returns boolean
1991 * @param pVM The VM to operate on.
1992 * @param pCtx Partial VM execution context
1993 */
1994VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
1995{
1996 PVMCPU pVCpu = VMMGetCpu(pVM);
1997
1998 Assert(pVM->fHWACCMEnabled);
1999
2000 /* If we're still executing the IO code, then return false. */
2001 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2002 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2003 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2004 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2005 return false;
2006
2007 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2008
2009 /* AMD-V supports real & protected mode with or without paging. */
2010 if (pVM->hwaccm.s.svm.fEnabled)
2011 {
2012 pVCpu->hwaccm.s.fActive = true;
2013 return true;
2014 }
2015
2016 pVCpu->hwaccm.s.fActive = false;
2017
2018 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2019#ifdef HWACCM_VMX_EMULATE_REALMODE
2020 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2021 {
2022 if (CPUMIsGuestInRealModeEx(pCtx))
2023 {
2024 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2025 * The base must also be equal to (sel << 4).
2026 */
2027 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2028 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2029 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2030 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2031 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2032 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2033 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2034 {
2035 return false;
2036 }
2037 }
2038 else
2039 {
2040 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2041 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2042 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2043 */
2044 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2045 && enmGuestMode >= PGMMODE_PROTECTED)
2046 {
2047 if ( (pCtx->cs & X86_SEL_RPL)
2048 || (pCtx->ds & X86_SEL_RPL)
2049 || (pCtx->es & X86_SEL_RPL)
2050 || (pCtx->fs & X86_SEL_RPL)
2051 || (pCtx->gs & X86_SEL_RPL)
2052 || (pCtx->ss & X86_SEL_RPL))
2053 {
2054 return false;
2055 }
2056 }
2057 }
2058 }
2059 else
2060#endif /* HWACCM_VMX_EMULATE_REALMODE */
2061 {
2062 if (!CPUMIsGuestInLongModeEx(pCtx))
2063 {
2064 /** @todo This should (probably) be set on every excursion to the REM,
2065 * however it's too risky right now. So, only apply it when we go
2066 * back to REM for real mode execution. (The XP hack below doesn't
2067 * work reliably without this.)
2068 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2069 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2070
2071 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2072 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2073 return false;
2074
2075 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2076 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2077 * hidden registers (possible recompiler bug; see load_seg_vm) */
2078 if (pCtx->csHid.Attr.n.u1Present == 0)
2079 return false;
2080 if (pCtx->ssHid.Attr.n.u1Present == 0)
2081 return false;
2082
2083 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2084 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2085 /** @todo This check is actually wrong, it doesn't take the direction of the
2086 * stack segment into account. But, it does the job for now. */
2087 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2088 return false;
2089#if 0
2090 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2091 || pCtx->ss >= pCtx->gdtr.cbGdt
2092 || pCtx->ds >= pCtx->gdtr.cbGdt
2093 || pCtx->es >= pCtx->gdtr.cbGdt
2094 || pCtx->fs >= pCtx->gdtr.cbGdt
2095 || pCtx->gs >= pCtx->gdtr.cbGdt)
2096 return false;
2097#endif
2098 }
2099 }
2100
2101 if (pVM->hwaccm.s.vmx.fEnabled)
2102 {
2103 uint32_t mask;
2104
2105 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2106 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2107 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2108 mask &= ~X86_CR0_NE;
2109
2110#ifdef HWACCM_VMX_EMULATE_REALMODE
2111 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2112 {
2113 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2114 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2115 }
2116 else
2117#endif
2118 {
2119 /* We support protected mode without paging using identity mapping. */
2120 mask &= ~X86_CR0_PG;
2121 }
2122 if ((pCtx->cr0 & mask) != mask)
2123 return false;
2124
2125 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2126 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2127 if ((pCtx->cr0 & mask) != 0)
2128 return false;
2129
2130 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2131 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2132 mask &= ~X86_CR4_VMXE;
2133 if ((pCtx->cr4 & mask) != mask)
2134 return false;
2135
2136 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2137 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2138 if ((pCtx->cr4 & mask) != 0)
2139 return false;
2140
2141 pVCpu->hwaccm.s.fActive = true;
2142 return true;
2143 }
2144
2145 return false;
2146}
2147
2148/**
2149 * Notifcation from EM about a rescheduling into hardware assisted execution
2150 * mode.
2151 *
2152 * @param pVCpu Pointer to the current virtual cpu structure.
2153 */
2154VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2155{
2156 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2157}
2158
2159/**
2160 * Notifcation from EM about returning from instruction emulation (REM / EM).
2161 *
2162 * @param pVCpu Pointer to the current virtual cpu structure.
2163 */
2164VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2165{
2166 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2167}
2168
2169/**
2170 * Checks if we are currently using hardware accelerated raw mode.
2171 *
2172 * @returns boolean
2173 * @param pVCpu The VMCPU to operate on.
2174 */
2175VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2176{
2177 return pVCpu->hwaccm.s.fActive;
2178}
2179
2180/**
2181 * Checks if we are currently using nested paging.
2182 *
2183 * @returns boolean
2184 * @param pVM The VM to operate on.
2185 */
2186VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2187{
2188 return pVM->hwaccm.s.fNestedPaging;
2189}
2190
2191/**
2192 * Checks if we are currently using VPID in VT-x mode.
2193 *
2194 * @returns boolean
2195 * @param pVM The VM to operate on.
2196 */
2197VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2198{
2199 return pVM->hwaccm.s.vmx.fVPID;
2200}
2201
2202
2203/**
2204 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2205 *
2206 * @returns boolean
2207 * @param pVM The VM to operate on.
2208 */
2209VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2210{
2211 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2212}
2213
2214/**
2215 * Restart an I/O instruction that was refused in ring-0
2216 *
2217 * @returns VBox status code
2218 * @param pVM The VM to operate on.
2219 * @param pVCpu The VMCPU to operate on.
2220 * @param pCtx VCPU register context
2221 */
2222VMMR3DECL(int) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2223{
2224 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2225 int rc;
2226
2227 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2228
2229 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2230 || enmType == HWACCMPENDINGIO_INVALID)
2231 return VERR_NOT_FOUND;
2232
2233 switch (enmType)
2234 {
2235 case HWACCMPENDINGIO_PORT_READ:
2236 {
2237 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2238 uint32_t u32Val = 0;
2239
2240 rc = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2241 &u32Val,
2242 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2243 if (IOM_SUCCESS(rc))
2244 {
2245 /* Write back to the EAX register. */
2246 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2247 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2248 }
2249 break;
2250 }
2251
2252 case HWACCMPENDINGIO_PORT_WRITE:
2253 rc = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2254 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2255 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2256 if (IOM_SUCCESS(rc))
2257 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2258 break;
2259
2260 default:
2261 AssertFailed();
2262 return VERR_INTERNAL_ERROR;
2263 }
2264
2265 return rc;
2266}
2267
2268/**
2269 * Inject an NMI into a running VM (only VCPU 0!)
2270 *
2271 * @returns boolean
2272 * @param pVM The VM to operate on.
2273 */
2274VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2275{
2276 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2277 return VINF_SUCCESS;
2278}
2279
2280/**
2281 * Check fatal VT-x/AMD-V error and produce some meaningful
2282 * log release message.
2283 *
2284 * @param pVM The VM to operate on.
2285 * @param iStatusCode VBox status code
2286 */
2287VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2288{
2289 for (unsigned i=0;i<pVM->cCPUs;i++)
2290 {
2291 switch(iStatusCode)
2292 {
2293 case VERR_VMX_INVALID_VMCS_FIELD:
2294 break;
2295
2296 case VERR_VMX_INVALID_VMCS_PTR:
2297 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2298 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2299 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2300 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2301 break;
2302
2303 case VERR_VMX_UNABLE_TO_START_VM:
2304 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2305 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2306#if 0 /* @todo dump the current control fields to the release log */
2307 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2308 {
2309
2310 }
2311#endif
2312 break;
2313
2314 case VERR_VMX_UNABLE_TO_RESUME_VM:
2315 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2316 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2317 break;
2318
2319 case VERR_VMX_INVALID_VMXON_PTR:
2320 break;
2321 }
2322 }
2323}
2324
2325/**
2326 * Execute state save operation.
2327 *
2328 * @returns VBox status code.
2329 * @param pVM VM Handle.
2330 * @param pSSM SSM operation handle.
2331 */
2332static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2333{
2334 int rc;
2335
2336 Log(("hwaccmR3Save:\n"));
2337
2338 for (unsigned i=0;i<pVM->cCPUs;i++)
2339 {
2340 /*
2341 * Save the basic bits - fortunately all the other things can be resynced on load.
2342 */
2343 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2344 AssertRCReturn(rc, rc);
2345 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2346 AssertRCReturn(rc, rc);
2347 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2348 AssertRCReturn(rc, rc);
2349
2350 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2351 AssertRCReturn(rc, rc);
2352 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2353 AssertRCReturn(rc, rc);
2354 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2355 AssertRCReturn(rc, rc);
2356 }
2357#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2358 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2359 AssertRCReturn(rc, rc);
2360 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2361 AssertRCReturn(rc, rc);
2362 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2363 AssertRCReturn(rc, rc);
2364
2365 /* Store all the guest patch records too. */
2366 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2367 AssertRCReturn(rc, rc);
2368
2369 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2370 {
2371 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2372
2373 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2374 AssertRCReturn(rc, rc);
2375
2376 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2377 AssertRCReturn(rc, rc);
2378
2379 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2380 AssertRCReturn(rc, rc);
2381
2382 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2383 AssertRCReturn(rc, rc);
2384
2385 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2386 AssertRCReturn(rc, rc);
2387
2388 AssertCompileSize(HWACCMTPRINSTR, 4);
2389 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2390 AssertRCReturn(rc, rc);
2391
2392 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2393 AssertRCReturn(rc, rc);
2394
2395 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2396 AssertRCReturn(rc, rc);
2397
2398 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2399 AssertRCReturn(rc, rc);
2400
2401 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2402 AssertRCReturn(rc, rc);
2403 }
2404#endif
2405 return VINF_SUCCESS;
2406}
2407
2408/**
2409 * Execute state load operation.
2410 *
2411 * @returns VBox status code.
2412 * @param pVM VM Handle.
2413 * @param pSSM SSM operation handle.
2414 * @param u32Version Data layout version.
2415 */
2416static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2417{
2418 int rc;
2419
2420 Log(("hwaccmR3Load:\n"));
2421
2422 /*
2423 * Validate version.
2424 */
2425 if ( u32Version != HWACCM_SSM_VERSION
2426 && u32Version != HWACCM_SSM_VERSION_NO_PATCHING
2427 && u32Version != HWACCM_SSM_VERSION_2_0_X)
2428 {
2429 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
2430 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2431 }
2432 for (unsigned i=0;i<pVM->cCPUs;i++)
2433 {
2434 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2435 AssertRCReturn(rc, rc);
2436 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2437 AssertRCReturn(rc, rc);
2438 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2439 AssertRCReturn(rc, rc);
2440
2441 if (u32Version >= HWACCM_SSM_VERSION_NO_PATCHING)
2442 {
2443 uint32_t val;
2444
2445 rc = SSMR3GetU32(pSSM, &val);
2446 AssertRCReturn(rc, rc);
2447 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2448
2449 rc = SSMR3GetU32(pSSM, &val);
2450 AssertRCReturn(rc, rc);
2451 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2452
2453 rc = SSMR3GetU32(pSSM, &val);
2454 AssertRCReturn(rc, rc);
2455 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2456 }
2457 }
2458#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2459 if (u32Version > HWACCM_SSM_VERSION_NO_PATCHING)
2460 {
2461 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2462 AssertRCReturn(rc, rc);
2463 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2464 AssertRCReturn(rc, rc);
2465 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2466 AssertRCReturn(rc, rc);
2467
2468 /* Fetch all TPR patch records. */
2469 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2470 AssertRCReturn(rc, rc);
2471
2472 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2473 {
2474 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2475
2476 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2477 AssertRCReturn(rc, rc);
2478
2479 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2480 AssertRCReturn(rc, rc);
2481
2482 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2483 AssertRCReturn(rc, rc);
2484
2485 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2486 AssertRCReturn(rc, rc);
2487
2488 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2489 AssertRCReturn(rc, rc);
2490
2491 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2492 AssertRCReturn(rc, rc);
2493
2494 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2495 AssertRCReturn(rc, rc);
2496
2497 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2498 AssertRCReturn(rc, rc);
2499
2500 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2501 AssertRCReturn(rc, rc);
2502
2503 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2504 AssertRCReturn(rc, rc);
2505
2506 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2507 AssertRC(rc);
2508 }
2509 }
2510#endif
2511 return VINF_SUCCESS;
2512}
2513
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