VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 22263

Last change on this file since 22263 was 22263, checked in by vboxsync, 16 years ago

Selectively enable TPR patching for certain Windows guests.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 119.3 KB
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1/* $Id: HWACCM.cpp 22263 2009-08-14 15:10:12Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/csam.h>
35#include <VBox/selm.h>
36#include <VBox/rem.h>
37#include <VBox/hwacc_vmx.h>
38#include <VBox/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/string.h>
48#include <iprt/thread.h>
49
50/*******************************************************************************
51* Global Variables *
52*******************************************************************************/
53#ifdef VBOX_WITH_STATISTICS
54# define EXIT_REASON(def, val, str) #def " - " #val " - " str
55# define EXIT_REASON_NIL() NULL
56/** Exit reason descriptions for VT-x, used to describe statistics. */
57static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
58{
59 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
60 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
61 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
62 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
63 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
64 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
65 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
66 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
67 EXIT_REASON_NIL(),
68 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
69 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
72 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
73 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
74 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
75 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
76 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
77 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
78 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
79 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
80 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
81 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
82 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
83 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
84 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
85 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
86 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
87 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
88 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
89 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
90 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
91 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
92 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
93 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
94 EXIT_REASON_NIL(),
95 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
99 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
100 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
101 EXIT_REASON_NIL(),
102 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
103 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
106 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
107 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
108 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
109 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
110 EXIT_REASON_NIL(),
111 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
112 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
113 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
114 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
115 EXIT_REASON_NIL()
116};
117/** Exit reason descriptions for AMD-V, used to describe statistics. */
118static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
119{
120 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
121 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
122 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
123 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
124 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
125 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
126 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
127 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
128 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
129 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
130 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
131 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
132 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
133 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
134 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
135 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
136 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
137 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
152 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
153 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
154 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
155 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
156 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
157 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
158 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
159 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
160 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
161 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
162 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
163 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
164 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
165 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
166 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
167 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
184 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
185 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
230 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
231 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
232 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
233 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
234 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
235 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
236 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
237 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
238 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
239 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
240 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
241 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
242 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
243 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
244 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
245 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
246 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
247 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
248 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
249 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
250 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
251 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
259 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
260 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
261 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
262 EXIT_REASON_NIL()
263};
264# undef EXIT_REASON
265# undef EXIT_REASON_NIL
266#endif /* VBOX_WITH_STATISTICS */
267
268/*******************************************************************************
269* Internal Functions *
270*******************************************************************************/
271static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
272static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
273
274
275/**
276 * Initializes the HWACCM.
277 *
278 * @returns VBox status code.
279 * @param pVM The VM to operate on.
280 */
281VMMR3DECL(int) HWACCMR3Init(PVM pVM)
282{
283 LogFlow(("HWACCMR3Init\n"));
284
285 /*
286 * Assert alignment and sizes.
287 */
288 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
289 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
290
291 /* Some structure checks. */
292 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
293 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
294 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
296
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
303 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
304
305
306 /*
307 * Register the saved state data unit.
308 */
309 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
310 NULL, hwaccmR3Save, NULL,
311 NULL, hwaccmR3Load, NULL);
312 if (RT_FAILURE(rc))
313 return rc;
314
315 /* Misc initialisation. */
316 pVM->hwaccm.s.vmx.fSupported = false;
317 pVM->hwaccm.s.svm.fSupported = false;
318 pVM->hwaccm.s.vmx.fEnabled = false;
319 pVM->hwaccm.s.svm.fEnabled = false;
320
321 pVM->hwaccm.s.fNestedPaging = false;
322
323 /* Disabled by default. */
324 pVM->fHWACCMEnabled = false;
325
326 /*
327 * Check CFGM options.
328 */
329 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
330
331 char *pszOSType = NULL;
332 rc = CFGMR3QueryStringAlloc(pRoot, "OSType", &pszOSType);
333 AssertRC(rc);
334
335 pVM->hwaccm.s.fTRPPatchingAllowed = false;
336 if (pszOSType)
337 {
338 /* @todo Not exactly pretty to check strings; VBOXOSTYPE would be better, but that requires quite a bit of API change in Main. */
339 if ( !RTStrCmp(pszOSType, "WindowsNT4")
340 || !RTStrCmp(pszOSType, "WindowsNT")
341 || !RTStrCmp(pszOSType, "Windows 2000")
342 || !RTStrCmp(pszOSType, "WindowsXP")
343 || !RTStrCmp(pszOSType, "Windows 2003"))
344 {
345 /* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
346 * (IO-APIC presence is checked later on in HWACCMR3InitFinalizeR0)
347 *
348 * We may want to consider adding more guest OSes (Solaris) later on.
349 */
350 pVM->hwaccm.s.fTRPPatchingAllowed = true;
351 }
352 MMR3HeapFree(pszOSType);
353 }
354
355 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
356 /* Nested paging: disabled by default. */
357 rc = CFGMR3QueryBoolDef(pRoot, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
358 AssertRC(rc);
359
360 /* VT-x VPID: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pRoot, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
362 AssertRC(rc);
363
364 /* HWACCM support must be explicitely enabled in the configuration file. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
366 AssertRC(rc);
367
368#ifdef RT_OS_DARWIN
369 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
370#else
371 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
372#endif
373 {
374 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
375 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
376 return VERR_HWACCM_CONFIG_MISMATCH;
377 }
378
379 if (VMMIsHwVirtExtForced(pVM))
380 pVM->fHWACCMEnabled = true;
381
382#if HC_ARCH_BITS == 32
383 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
384 * (To use the default, don't set 64bitEnabled in CFGM.) */
385 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
386 AssertLogRelRCReturn(rc, rc);
387 if (pVM->hwaccm.s.fAllow64BitGuests)
388 {
389# ifdef RT_OS_DARWIN
390 if (!VMMIsHwVirtExtForced(pVM))
391# else
392 if (!pVM->hwaccm.s.fAllowed)
393# endif
394 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
395 }
396#else
397 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
398 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
399 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
400 AssertLogRelRCReturn(rc, rc);
401#endif
402
403 /* Max number of resume loops. */
404 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
405 AssertRC(rc);
406
407 return VINF_SUCCESS;
408}
409
410/**
411 * Initializes the per-VCPU HWACCM.
412 *
413 * @returns VBox status code.
414 * @param pVM The VM to operate on.
415 */
416VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
417{
418 LogFlow(("HWACCMR3InitCPU\n"));
419
420 for (unsigned i=0;i<pVM->cCPUs;i++)
421 {
422 PVMCPU pVCpu = &pVM->aCpus[i];
423
424 pVCpu->hwaccm.s.fActive = false;
425 }
426
427#ifdef VBOX_WITH_STATISTICS
428 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
429 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
430 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
431 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
432
433 /*
434 * Statistics.
435 */
436 for (unsigned i=0;i<pVM->cCPUs;i++)
437 {
438 PVMCPU pVCpu = &pVM->aCpus[i];
439 int rc;
440
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
442 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
443 AssertRC(rc);
444 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
445 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
446 AssertRC(rc);
447 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
448 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
449 AssertRC(rc);
450# if 1 /* temporary for tracking down darwin holdup. */
451 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
452 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
453 AssertRC(rc);
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
455 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
458 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
459 AssertRC(rc);
460# endif
461 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
462 "/PROF/HWACCM/CPU%d/InGC", i);
463 AssertRC(rc);
464
465# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
466 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
467 "/PROF/HWACCM/CPU%d/Switcher3264", i);
468 AssertRC(rc);
469# endif
470
471# define HWACCM_REG_COUNTER(a, b) \
472 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
473 AssertRC(rc);
474
475 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
476 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
477 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
478 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
479 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
480 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
512
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
515
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
519
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
531
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
535
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
539
540 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
541 {
542 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
543 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
544 AssertRC(rc);
545 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
546 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
547 AssertRC(rc);
548 }
549
550#undef HWACCM_REG_COUNTER
551
552 pVCpu->hwaccm.s.paStatExitReason = NULL;
553
554 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
555 AssertRC(rc);
556 if (RT_SUCCESS(rc))
557 {
558 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
559 for (int j=0;j<MAX_EXITREASON_STAT;j++)
560 {
561 if (papszDesc[j])
562 {
563 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
564 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
565 AssertRC(rc);
566 }
567 }
568 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
569 AssertRC(rc);
570 }
571 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
572# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
573 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
574# else
575 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
576# endif
577
578 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
579 AssertRCReturn(rc, rc);
580 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
581# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
582 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
583# else
584 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
585# endif
586 for (unsigned j = 0; j < 255; j++)
587 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
588 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
589
590 }
591#endif /* VBOX_WITH_STATISTICS */
592
593#ifdef VBOX_WITH_CRASHDUMP_MAGIC
594 /* Magic marker for searching in crash dumps. */
595 for (unsigned i=0;i<pVM->cCPUs;i++)
596 {
597 PVMCPU pVCpu = &pVM->aCpus[i];
598
599 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
600 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
601 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
602 }
603#endif
604 return VINF_SUCCESS;
605}
606
607/**
608 * Turns off normal raw mode features
609 *
610 * @param pVM The VM to operate on.
611 */
612static void hwaccmR3DisableRawMode(PVM pVM)
613{
614 /* Disable PATM & CSAM. */
615 PATMR3AllowPatching(pVM, false);
616 CSAMDisableScanning(pVM);
617
618 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
619 SELMR3DisableMonitoring(pVM);
620 TRPMR3DisableMonitoring(pVM);
621
622 /* Disable the switcher code (safety precaution). */
623 VMMR3DisableSwitcher(pVM);
624
625 /* Disable mapping of the hypervisor into the shadow page table. */
626 PGMR3MappingsDisable(pVM);
627
628 /* Disable the switcher */
629 VMMR3DisableSwitcher(pVM);
630
631 /* Reinit the paging mode to force the new shadow mode. */
632 for (unsigned i=0;i<pVM->cCPUs;i++)
633 {
634 PVMCPU pVCpu = &pVM->aCpus[i];
635
636 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
637 }
638}
639
640/**
641 * Initialize VT-x or AMD-V.
642 *
643 * @returns VBox status code.
644 * @param pVM The VM handle.
645 */
646VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
647{
648 int rc;
649
650 if ( !pVM->hwaccm.s.vmx.fSupported
651 && !pVM->hwaccm.s.svm.fSupported)
652 {
653 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
654 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
655 if (VMMIsHwVirtExtForced(pVM))
656 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
657 return VINF_SUCCESS;
658 }
659
660 if (!pVM->hwaccm.s.fAllowed)
661 return VINF_SUCCESS; /* nothing to do */
662
663 /* Enable VT-x or AMD-V on all host CPUs. */
664 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
665 if (RT_FAILURE(rc))
666 {
667 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
668 return rc;
669 }
670 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
671
672 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
673 /* No TPR patching is required when the IO-APIC is not enabled for this VM. */
674 if (!pVM->hwaccm.s.fHasIoApic)
675 pVM->hwaccm.s.fTRPPatchingAllowed = false;
676
677 if (pVM->hwaccm.s.vmx.fSupported)
678 {
679 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
680
681 if ( pVM->hwaccm.s.fInitialized == false
682 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
683 {
684 uint64_t val;
685 RTGCPHYS GCPhys = 0;
686
687 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
688 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
689 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
690 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
691 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
692 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
693 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
694 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
695
696 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
697 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
698 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
699 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
700 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
701 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
702 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
703 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
704 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
705 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
706 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
707 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
708 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
709 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
710 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
711 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
712 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
713 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
714 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
715
716 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
717 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
718 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
719 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
720 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
721 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
722 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
723 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
724 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
725 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
726 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
727 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
728 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
729 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
730 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
731 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
732 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
733 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
734 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
735 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
736 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
737 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
738 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
739 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
740 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
741 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
742 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
743 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
744 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
745 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
746 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
747 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
748 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
749 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
750 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
751 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
752 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
753 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
754 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
755 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
756 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
757 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
758 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
760
761 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
762 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
764 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
766 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
767 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
768 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
769 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
770 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
771 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
772 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
773 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
774 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
775 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
776 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
777 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
778 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
804
805 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
806 {
807 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
808 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
809 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
811 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
813 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
815 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
816 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
817 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
818 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
819 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
820 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
821
822 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
823 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
824 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
825 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
826 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
827 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
828 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
829 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
830 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
831 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
832 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
833 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
834 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
835 }
836
837 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
838 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
839 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
840 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
841 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
842 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
843 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
844 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
845 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
846 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
847 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
848 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
849 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
850 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
851 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
852 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
853 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
854 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
868
869 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
870 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
871 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
873 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
875 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
877 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
879 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
881 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
883 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
885 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
887 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
888 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
890 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
892 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
894 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
904
905 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
906 {
907 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
908
909 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
910 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
911 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
912 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
913 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
914 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
915 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
916 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
917 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
918 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
919 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
920 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
921 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
922 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
923 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
924 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
925 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
926 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
927 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
928 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
929 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
930 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
931 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
932 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
933 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
934 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
935 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
936 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
937 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
938 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
939 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
940 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
941 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
942 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
943 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
944 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
945 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
946 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
947 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
948 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
949 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
950 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
951 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
952 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
953 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
954 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
955 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
956 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
957 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
958 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
959 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
960 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
961 }
962
963 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
964 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
965 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
966 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
967 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
968 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
969
970 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
971 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
972 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
973 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
974 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
975
976 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
977
978 /* Paranoia */
979 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
980
981 for (unsigned i=0;i<pVM->cCPUs;i++)
982 {
983 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
984 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
985 }
986
987#ifdef HWACCM_VTX_WITH_EPT
988 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
989 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
990#endif /* HWACCM_VTX_WITH_EPT */
991#ifdef HWACCM_VTX_WITH_VPID
992 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
993 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
994 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
995#endif /* HWACCM_VTX_WITH_VPID */
996
997 /* Only try once. */
998 pVM->hwaccm.s.fInitialized = true;
999
1000 /* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
1001#if 1
1002 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1003#else
1004 rc = VERR_NO_MEMORY; /* simulation of no VMMDev Heap. */
1005#endif
1006 if (RT_SUCCESS(rc))
1007 {
1008 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1009 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1010 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1011 /* Bit set to 0 means redirection enabled. */
1012 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1013 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1014 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1015 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1016
1017 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1018 * real and protected mode without paging with EPT.
1019 */
1020 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1021 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1022 {
1023 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1024 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1025 }
1026
1027 /* We convert it here every time as pci regions could be reconfigured. */
1028 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1029 AssertRC(rc);
1030 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1031
1032 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1033 AssertRC(rc);
1034 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1035 }
1036 else
1037 {
1038 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1039 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1040 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1041 }
1042
1043 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1044 AssertRC(rc);
1045 if (rc == VINF_SUCCESS)
1046 {
1047 pVM->fHWACCMEnabled = true;
1048 pVM->hwaccm.s.vmx.fEnabled = true;
1049 hwaccmR3DisableRawMode(pVM);
1050
1051 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1052#ifdef VBOX_ENABLE_64_BITS_GUESTS
1053 if (pVM->hwaccm.s.fAllow64BitGuests)
1054 {
1055 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1056 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1057 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1058 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1059 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1060 }
1061 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1062 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1063 : "HWACCM: 32-bit guests supported.\n"));
1064#else
1065 LogRel(("HWACCM: 32-bit guests supported.\n"));
1066#endif
1067 LogRel(("HWACCM: VMX enabled!\n"));
1068 if (pVM->hwaccm.s.fNestedPaging)
1069 {
1070 LogRel(("HWACCM: Enabled nested paging\n"));
1071 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1072 }
1073 if (pVM->hwaccm.s.vmx.fVPID)
1074 LogRel(("HWACCM: Enabled VPID\n"));
1075
1076 if ( pVM->hwaccm.s.fNestedPaging
1077 || pVM->hwaccm.s.vmx.fVPID)
1078 {
1079 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1080 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1081 }
1082 }
1083 else
1084 {
1085 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1086 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1087 pVM->fHWACCMEnabled = false;
1088 }
1089 }
1090 }
1091 else
1092 if (pVM->hwaccm.s.svm.fSupported)
1093 {
1094 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1095
1096 if (pVM->hwaccm.s.fInitialized == false)
1097 {
1098 /* Erratum 170 which requires a forced TLB flush for each world switch:
1099 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1100 *
1101 * All BH-G1/2 and DH-G1/2 models include a fix:
1102 * Athlon X2: 0x6b 1/2
1103 * 0x68 1/2
1104 * Athlon 64: 0x7f 1
1105 * 0x6f 2
1106 * Sempron: 0x7f 1/2
1107 * 0x6f 2
1108 * 0x6c 2
1109 * 0x7c 2
1110 * Turion 64: 0x68 2
1111 *
1112 */
1113 uint32_t u32Dummy;
1114 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1115 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1116 u32BaseFamily= (u32Version >> 8) & 0xf;
1117 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1118 u32Model = ((u32Version >> 4) & 0xf);
1119 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1120 u32Stepping = u32Version & 0xf;
1121 if ( u32Family == 0xf
1122 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1123 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1124 {
1125 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1126 }
1127
1128 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1129 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1130 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1131 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1132 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1133
1134 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1135 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1136 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1137 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1138 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1139 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1140 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1141 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1142 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1143 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1144
1145 /* Only try once. */
1146 pVM->hwaccm.s.fInitialized = true;
1147
1148 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1149 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1150
1151 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1152 AssertRC(rc);
1153 if (rc == VINF_SUCCESS)
1154 {
1155 pVM->fHWACCMEnabled = true;
1156 pVM->hwaccm.s.svm.fEnabled = true;
1157
1158 if (pVM->hwaccm.s.fNestedPaging)
1159 LogRel(("HWACCM: Enabled nested paging\n"));
1160
1161 hwaccmR3DisableRawMode(pVM);
1162 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1163 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1164 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1165#ifdef VBOX_ENABLE_64_BITS_GUESTS
1166 if (pVM->hwaccm.s.fAllow64BitGuests)
1167 {
1168 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1169 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1170 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1171 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1172 }
1173#endif
1174 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1175 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1176 : "HWACCM: 32-bit guest supported.\n"));
1177 }
1178 else
1179 {
1180 pVM->fHWACCMEnabled = false;
1181 }
1182 }
1183 }
1184 return VINF_SUCCESS;
1185}
1186
1187/**
1188 * Applies relocations to data and code managed by this
1189 * component. This function will be called at init and
1190 * whenever the VMM need to relocate it self inside the GC.
1191 *
1192 * @param pVM The VM.
1193 */
1194VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1195{
1196 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1197
1198 /* Fetch the current paging mode during the relocate callback during state loading. */
1199 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1200 {
1201 for (unsigned i=0;i<pVM->cCPUs;i++)
1202 {
1203 PVMCPU pVCpu = &pVM->aCpus[i];
1204
1205 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1206 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1207 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1208 }
1209 }
1210#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1211 if (pVM->fHWACCMEnabled)
1212 {
1213 int rc;
1214
1215 switch(PGMGetHostMode(pVM))
1216 {
1217 case PGMMODE_32_BIT:
1218 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1219 break;
1220
1221 case PGMMODE_PAE:
1222 case PGMMODE_PAE_NX:
1223 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1224 break;
1225
1226 default:
1227 AssertFailed();
1228 break;
1229 }
1230 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1231 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1232
1233 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1234 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1235
1236 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1237 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1238
1239 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1240 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1241
1242# ifdef DEBUG
1243 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1244 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1245# endif
1246 }
1247#endif
1248 return;
1249}
1250
1251/**
1252 * Checks hardware accelerated raw mode is allowed.
1253 *
1254 * @returns boolean
1255 * @param pVM The VM to operate on.
1256 */
1257VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1258{
1259 return pVM->hwaccm.s.fAllowed;
1260}
1261
1262/**
1263 * Notification callback which is called whenever there is a chance that a CR3
1264 * value might have changed.
1265 *
1266 * This is called by PGM.
1267 *
1268 * @param pVM The VM to operate on.
1269 * @param pVCpu The VMCPU to operate on.
1270 * @param enmShadowMode New shadow paging mode.
1271 * @param enmGuestMode New guest paging mode.
1272 */
1273VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1274{
1275 /* Ignore page mode changes during state loading. */
1276 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1277 return;
1278
1279 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1280
1281 if ( pVM->hwaccm.s.vmx.fEnabled
1282 && pVM->fHWACCMEnabled)
1283 {
1284 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1285 && enmGuestMode >= PGMMODE_PROTECTED)
1286 {
1287 PCPUMCTX pCtx;
1288
1289 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1290
1291 /* After a real mode switch to protected mode we must force
1292 * CPL to 0. Our real mode emulation had to set it to 3.
1293 */
1294 pCtx->ssHid.Attr.n.u2Dpl = 0;
1295 }
1296 }
1297
1298 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1299 {
1300 /* Keep track of paging mode changes. */
1301 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1302 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1303
1304 /* Did we miss a change, because all code was executed in the recompiler? */
1305 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1306 {
1307 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1308 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1309 }
1310 }
1311
1312 /* Reset the contents of the read cache. */
1313 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1314 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1315 pCache->Read.aFieldVal[j] = 0;
1316}
1317
1318/**
1319 * Terminates the HWACCM.
1320 *
1321 * Termination means cleaning up and freeing all resources,
1322 * the VM it self is at this point powered off or suspended.
1323 *
1324 * @returns VBox status code.
1325 * @param pVM The VM to operate on.
1326 */
1327VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1328{
1329 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1330 {
1331 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1332 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1333 }
1334 HWACCMR3TermCPU(pVM);
1335 return 0;
1336}
1337
1338/**
1339 * Terminates the per-VCPU HWACCM.
1340 *
1341 * Termination means cleaning up and freeing all resources,
1342 * the VM it self is at this point powered off or suspended.
1343 *
1344 * @returns VBox status code.
1345 * @param pVM The VM to operate on.
1346 */
1347VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1348{
1349 for (unsigned i=0;i<pVM->cCPUs;i++)
1350 {
1351 PVMCPU pVCpu = &pVM->aCpus[i];
1352
1353#ifdef VBOX_WITH_STATISTICS
1354 if (pVCpu->hwaccm.s.paStatExitReason)
1355 {
1356 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1357 pVCpu->hwaccm.s.paStatExitReason = NULL;
1358 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1359 }
1360 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1361 {
1362 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1363 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1364 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1365 }
1366#endif
1367
1368#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1369 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1370 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1371 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1372#endif
1373 }
1374 return 0;
1375}
1376
1377/**
1378 * The VM is being reset.
1379 *
1380 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1381 * needs to be removed.
1382 *
1383 * @param pVM VM handle.
1384 */
1385VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1386{
1387 LogFlow(("HWACCMR3Reset:\n"));
1388
1389 if (pVM->fHWACCMEnabled)
1390 hwaccmR3DisableRawMode(pVM);
1391
1392 for (unsigned i=0;i<pVM->cCPUs;i++)
1393 {
1394 PVMCPU pVCpu = &pVM->aCpus[i];
1395
1396 /* On first entry we'll sync everything. */
1397 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1398
1399 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1400 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1401
1402 pVCpu->hwaccm.s.fActive = false;
1403 pVCpu->hwaccm.s.Event.fPending = false;
1404
1405 /* Reset state information for real-mode emulation in VT-x. */
1406 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1407 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1408 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1409
1410 /* Reset the contents of the read cache. */
1411 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1412 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1413 pCache->Read.aFieldVal[j] = 0;
1414
1415#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1416 /* Magic marker for searching in crash dumps. */
1417 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1418 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1419#endif
1420 }
1421
1422 /* Clear all patch information. */
1423 pVM->hwaccm.s.pGuestPatchMem = 0;
1424 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1425 pVM->hwaccm.s.cbGuestPatchMem = 0;
1426 pVM->hwaccm.s.svm.cPatches = 0;
1427 pVM->hwaccm.s.svm.PatchTree = 0;
1428 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1429 ASMMemZero32(pVM->hwaccm.s.svm.aPatches, sizeof(pVM->hwaccm.s.svm.aPatches));
1430}
1431
1432/**
1433 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1434 *
1435 * @returns VBox status code.
1436 * @param pVM The VM handle.
1437 * @param pVCpu The VMCPU for the EMT we're being called on.
1438 * @param pvUser Unused
1439 *
1440 */
1441DECLCALLBACK(int) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1442{
1443 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1444
1445 /* Only execute the handler on the VCPU the original patch request was issued. */
1446 if (pVCpu->idCpu != idCpu)
1447 return VINF_SUCCESS;
1448
1449 Log(("hwaccmR3RemovePatches\n"));
1450 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
1451 {
1452 uint8_t szInstr[15];
1453 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
1454 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1455 int rc;
1456
1457#ifdef LOG_ENABLED
1458 char szOutput[256];
1459
1460 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1461 if (VBOX_SUCCESS(rc))
1462 Log(("Patched instr: %s\n", szOutput));
1463#endif
1464
1465 /* Check if the instruction is still the same. */
1466 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1467 if (rc != VINF_SUCCESS)
1468 {
1469 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1470 continue; /* swapped out or otherwise removed; skip it. */
1471 }
1472
1473 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1474 {
1475 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1476 continue; /* skip it. */
1477 }
1478
1479 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1480 AssertRC(rc);
1481
1482#ifdef LOG_ENABLED
1483 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1484 if (VBOX_SUCCESS(rc))
1485 Log(("Original instr: %s\n", szOutput));
1486#endif
1487 }
1488 pVM->hwaccm.s.svm.cPatches = 0;
1489 pVM->hwaccm.s.svm.PatchTree = 0;
1490 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1491 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1492 return VINF_SUCCESS;
1493}
1494
1495/**
1496 * Enable patching in a VT-x/AMD-V guest
1497 *
1498 * @returns VBox status code.
1499 * @param pVM The VM to operate on.
1500 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1501 * @param pPatchMem Patch memory range
1502 * @param cbPatchMem Size of the memory range
1503 */
1504int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1505{
1506 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1507 AssertRC(rc);
1508
1509 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1510 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1511 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1512 return VINF_SUCCESS;
1513}
1514
1515/**
1516 * Enable patching in a VT-x/AMD-V guest
1517 *
1518 * @returns VBox status code.
1519 * @param pVM The VM to operate on.
1520 * @param pPatchMem Patch memory range
1521 * @param cbPatchMem Size of the memory range
1522 */
1523VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1524{
1525 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1526
1527 /* Current TPR patching only applies to AMD cpus.
1528 * Needs to be extended to Intel CPUs without the APIC TPR hardware optimization.
1529 */
1530 if (CPUMGetCPUVendor(pVM) != CPUMCPUVENDOR_AMD)
1531 return VERR_NOT_SUPPORTED;
1532
1533 if (pVM->cCPUs > 1)
1534 {
1535 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1536 PVMREQ pReq;
1537 int rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
1538 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1539 AssertRC(rc);
1540 return rc;
1541 }
1542 else
1543 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1544}
1545
1546/**
1547 * Disable patching in a VT-x/AMD-V guest
1548 *
1549 * @returns VBox status code.
1550 * @param pVM The VM to operate on.
1551 * @param pPatchMem Patch memory range
1552 * @param cbPatchMem Size of the memory range
1553 */
1554VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1555{
1556 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1557
1558 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1559 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1560
1561 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1562 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1563 AssertRC(rc);
1564
1565 pVM->hwaccm.s.pGuestPatchMem = 0;
1566 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1567 pVM->hwaccm.s.cbGuestPatchMem = 0;
1568 pVM->hwaccm.s.svm.fTPRPatchingActive = false;
1569 return VINF_SUCCESS;
1570}
1571
1572
1573/**
1574 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1575 *
1576 * @returns VBox status code.
1577 * @param pVM The VM handle.
1578 * @param pVCpu The VMCPU for the EMT we're being called on.
1579 * @param pvUser User specified CPU context
1580 *
1581 */
1582DECLCALLBACK(int) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1583{
1584 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1585 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1586 RTGCPTR oldrip = pCtx->rip;
1587 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1588 unsigned cbOp;
1589
1590 /* Only execute the handler on the VCPU the original patch request was issued. */
1591 if (pVCpu->idCpu != idCpu)
1592 return VINF_SUCCESS;
1593
1594 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1595
1596 /* Two or more VCPUs were racing to patch this instruction. */
1597 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1598 if (pPatch)
1599 return VINF_SUCCESS;
1600
1601 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1602
1603 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1604 AssertRC(rc);
1605 if ( rc == VINF_SUCCESS
1606 && pDis->pCurInstr->opcode == OP_MOV
1607 && cbOp >= 3)
1608 {
1609 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1610 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1611 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1612
1613 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1614 AssertRC(rc);
1615
1616 pPatch->cbOp = cbOp;
1617
1618 if (pDis->param1.flags == USE_DISPLACEMENT32)
1619 {
1620 /* write. */
1621 if (pDis->param2.flags == USE_REG_GEN32)
1622 {
1623 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1624 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1625 }
1626 else
1627 {
1628 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1629 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1630 pPatch->uSrcOperand = pDis->param2.parval;
1631 }
1632 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1633 AssertRC(rc);
1634
1635 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1636 pPatch->cbNewOp = sizeof(aVMMCall);
1637 }
1638 else
1639 {
1640 RTGCPTR oldrip = pCtx->rip;
1641 uint32_t oldcbOp = cbOp;
1642 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1643
1644 /* read */
1645 Assert(pDis->param1.flags == USE_REG_GEN32);
1646
1647 /* Found:
1648 * mov eax, dword [fffe0080] (5 bytes)
1649 * Check if next instruction is:
1650 * shr eax, 4
1651 */
1652 pCtx->rip += cbOp;
1653 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1654 pCtx->rip = oldrip;
1655 if ( rc == VINF_SUCCESS
1656 && pDis->pCurInstr->opcode == OP_SHR
1657 && pDis->param1.flags == USE_REG_GEN32
1658 && pDis->param1.base.reg_gen == uMmioReg
1659 && pDis->param2.flags == USE_IMMEDIATE8
1660 && pDis->param2.parval == 4
1661 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.svm.aPatches[idx].aOpcode))
1662 {
1663 uint8_t szInstr[15];
1664
1665 /* Replacing two instructions now. */
1666 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1667 AssertRC(rc);
1668
1669 pPatch->cbOp = oldcbOp + cbOp;
1670
1671 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1672 szInstr[0] = 0xF0;
1673 szInstr[1] = 0x0F;
1674 szInstr[2] = 0x20;
1675 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1676 for (unsigned i = 4; i < pPatch->cbOp; i++)
1677 szInstr[i] = 0x90; /* nop */
1678
1679 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1680 AssertRC(rc);
1681
1682 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1683 pPatch->cbNewOp = pPatch->cbOp;
1684
1685 Log(("Acceptable read/shr candidate!\n"));
1686 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1687 }
1688 else
1689 {
1690 pPatch->enmType = HWACCMTPRINSTR_READ;
1691 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1692
1693 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1694 AssertRC(rc);
1695
1696 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1697 pPatch->cbNewOp = sizeof(aVMMCall);
1698 }
1699 }
1700
1701 pPatch->Core.Key = pCtx->eip;
1702 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1703 AssertRC(rc);
1704
1705 pVM->hwaccm.s.svm.cPatches++;
1706 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1707 return VINF_SUCCESS;
1708 }
1709
1710 /* Save invalid patch, so we will not try again. */
1711 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1712
1713#ifdef LOG_ENABLED
1714 char szOutput[256];
1715 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1716 if (VBOX_SUCCESS(rc))
1717 Log(("Failed to patch instr: %s\n", szOutput));
1718#endif
1719
1720 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1721 pPatch->Core.Key = pCtx->eip;
1722 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1723 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1724 AssertRC(rc);
1725 pVM->hwaccm.s.svm.cPatches++;
1726 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1727 return VINF_SUCCESS;
1728}
1729
1730/**
1731 * Callback to patch a TPR instruction (jump to generated code)
1732 *
1733 * @returns VBox status code.
1734 * @param pVM The VM handle.
1735 * @param pVCpu The VMCPU for the EMT we're being called on.
1736 * @param pvUser User specified CPU context
1737 *
1738 */
1739DECLCALLBACK(int) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1740{
1741 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1742 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1743 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1744 unsigned cbOp;
1745 int rc;
1746#ifdef LOG_ENABLED
1747 RTGCPTR pInstr;
1748 char szOutput[256];
1749#endif
1750
1751 /* Only execute the handler on the VCPU the original patch request was issued. */
1752 if (pVCpu->idCpu != idCpu)
1753 return VINF_SUCCESS;
1754
1755 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1756
1757 Assert(pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches));
1758
1759 /* Two or more VCPUs were racing to patch this instruction. */
1760 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1761 if (pPatch)
1762 return VINF_SUCCESS;
1763
1764 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1765 AssertRC(rc);
1766 if ( rc == VINF_SUCCESS
1767 && pDis->pCurInstr->opcode == OP_MOV
1768 && cbOp >= 5)
1769 {
1770 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1771 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1772 uint8_t aPatch[64];
1773 uint32_t off = 0;
1774
1775#ifdef LOG_ENABLED
1776 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1777 if (VBOX_SUCCESS(rc))
1778 Log(("Original instr: %s\n", szOutput));
1779#endif
1780
1781 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1782 AssertRC(rc);
1783
1784 pPatch->cbOp = cbOp;
1785 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1786
1787 if (pDis->param1.flags == USE_DISPLACEMENT32)
1788 {
1789 /*
1790 * TPR write:
1791 *
1792 * push ECX [51]
1793 * push EDX [52]
1794 * push EAX [50]
1795 * xor EDX,EDX [31 D2]
1796 * mov EAX,EAX [89 C0]
1797 * or
1798 * mov EAX,0000000CCh [B8 CC 00 00 00]
1799 * mov ECX,0C0000082h [B9 82 00 00 C0]
1800 * wrmsr [0F 30]
1801 * pop EAX [58]
1802 * pop EDX [5A]
1803 * pop ECX [59]
1804 * jmp return_address [E9 return_address]
1805 *
1806 */
1807 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1808
1809 aPatch[off++] = 0x51; /* push ecx */
1810 aPatch[off++] = 0x52; /* push edx */
1811 if (!fUsesEax)
1812 aPatch[off++] = 0x50; /* push eax */
1813 aPatch[off++] = 0x31; /* xor edx, edx */
1814 aPatch[off++] = 0xD2;
1815 if (pDis->param2.flags == USE_REG_GEN32)
1816 {
1817 if (!fUsesEax)
1818 {
1819 aPatch[off++] = 0x89; /* mov eax, src_reg */
1820 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1821 }
1822 }
1823 else
1824 {
1825 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1826 aPatch[off++] = 0xB8; /* mov eax, immediate */
1827 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1828 off += sizeof(uint32_t);
1829 }
1830 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1831 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1832 off += sizeof(uint32_t);
1833
1834 aPatch[off++] = 0x0F; /* wrmsr */
1835 aPatch[off++] = 0x30;
1836 if (!fUsesEax)
1837 aPatch[off++] = 0x58; /* pop eax */
1838 aPatch[off++] = 0x5A; /* pop edx */
1839 aPatch[off++] = 0x59; /* pop ecx */
1840 }
1841 else
1842 {
1843 /*
1844 * TPR read:
1845 *
1846 * push ECX [51]
1847 * push EDX [52]
1848 * push EAX [50]
1849 * mov ECX,0C0000082h [B9 82 00 00 C0]
1850 * rdmsr [0F 32]
1851 * mov EAX,EAX [89 C0]
1852 * pop EAX [58]
1853 * pop EDX [5A]
1854 * pop ECX [59]
1855 * jmp return_address [E9 return_address]
1856 *
1857 */
1858 Assert(pDis->param1.flags == USE_REG_GEN32);
1859
1860 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1861 aPatch[off++] = 0x51; /* push ecx */
1862 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1863 aPatch[off++] = 0x52; /* push edx */
1864 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1865 aPatch[off++] = 0x50; /* push eax */
1866
1867 aPatch[off++] = 0x31; /* xor edx, edx */
1868 aPatch[off++] = 0xD2;
1869
1870 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1871 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1872 off += sizeof(uint32_t);
1873
1874 aPatch[off++] = 0x0F; /* rdmsr */
1875 aPatch[off++] = 0x32;
1876
1877 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1878 {
1879 aPatch[off++] = 0x89; /* mov dst_reg, eax */
1880 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
1881 }
1882
1883 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1884 aPatch[off++] = 0x58; /* pop eax */
1885 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1886 aPatch[off++] = 0x5A; /* pop edx */
1887 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1888 aPatch[off++] = 0x59; /* pop ecx */
1889 }
1890 aPatch[off++] = 0xE9; /* jmp return_address */
1891 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
1892 off += sizeof(RTRCUINTPTR);
1893
1894 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
1895 {
1896 /* Write new code to the patch buffer. */
1897 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
1898 AssertRC(rc);
1899
1900#ifdef LOG_ENABLED
1901 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
1902 while (true)
1903 {
1904 uint32_t cb;
1905
1906 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
1907 if (VBOX_SUCCESS(rc))
1908 Log(("Patch instr %s\n", szOutput));
1909
1910 pInstr += cb;
1911
1912 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
1913 break;
1914 }
1915#endif
1916
1917 pPatch->aNewOpcode[0] = 0xE9;
1918 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
1919
1920 /* Overwrite the TPR instruction with a jump. */
1921 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
1922 AssertRC(rc);
1923
1924#ifdef LOG_ENABLED
1925 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1926 if (VBOX_SUCCESS(rc))
1927 Log(("Jump: %s\n", szOutput));
1928#endif
1929 pVM->hwaccm.s.pFreeGuestPatchMem += off;
1930 pPatch->cbNewOp = 5;
1931
1932 pPatch->Core.Key = pCtx->eip;
1933 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1934 AssertRC(rc);
1935
1936 pVM->hwaccm.s.svm.cPatches++;
1937 pVM->hwaccm.s.svm.fTPRPatchingActive = true;
1938 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
1939 return VINF_SUCCESS;
1940 }
1941 else
1942 Log(("Ran out of space in our patch buffer!\n"));
1943 }
1944
1945 /* Save invalid patch, so we will not try again. */
1946 uint32_t idx = pVM->hwaccm.s.svm.cPatches;
1947
1948#ifdef LOG_ENABLED
1949 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1950 if (VBOX_SUCCESS(rc))
1951 Log(("Failed to patch instr: %s\n", szOutput));
1952#endif
1953
1954 pPatch = &pVM->hwaccm.s.svm.aPatches[idx];
1955 pPatch->Core.Key = pCtx->eip;
1956 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1957 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
1958 AssertRC(rc);
1959 pVM->hwaccm.s.svm.cPatches++;
1960 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
1961 return VINF_SUCCESS;
1962}
1963
1964/**
1965 * Attempt to patch TPR mmio instructions
1966 *
1967 * @returns VBox status code.
1968 * @param pVM The VM to operate on.
1969 * @param pVCpu The VM CPU to operate on.
1970 * @param pCtx CPU context
1971 */
1972VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1973{
1974 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
1975 AssertRC(rc);
1976 return rc;
1977}
1978
1979/**
1980 * Force execution of the current IO code in the recompiler
1981 *
1982 * @returns VBox status code.
1983 * @param pVM The VM to operate on.
1984 * @param pCtx Partial VM execution context
1985 */
1986VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
1987{
1988 PVMCPU pVCpu = VMMGetCpu(pVM);
1989
1990 Assert(pVM->fHWACCMEnabled);
1991 Log(("HWACCMR3EmulateIoBlock\n"));
1992
1993 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
1994 if (HWACCMCanEmulateIoBlockEx(pCtx))
1995 {
1996 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
1997 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
1998 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
1999 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2000 return VINF_EM_RESCHEDULE_REM;
2001 }
2002 return VINF_SUCCESS;
2003}
2004
2005/**
2006 * Checks if we can currently use hardware accelerated raw mode.
2007 *
2008 * @returns boolean
2009 * @param pVM The VM to operate on.
2010 * @param pCtx Partial VM execution context
2011 */
2012VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2013{
2014 PVMCPU pVCpu = VMMGetCpu(pVM);
2015
2016 Assert(pVM->fHWACCMEnabled);
2017
2018 /* If we're still executing the IO code, then return false. */
2019 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2020 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2021 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2022 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2023 return false;
2024
2025 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2026
2027 /* AMD-V supports real & protected mode with or without paging. */
2028 if (pVM->hwaccm.s.svm.fEnabled)
2029 {
2030 pVCpu->hwaccm.s.fActive = true;
2031 return true;
2032 }
2033
2034 pVCpu->hwaccm.s.fActive = false;
2035
2036 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2037#ifdef HWACCM_VMX_EMULATE_REALMODE
2038 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2039 {
2040 if (CPUMIsGuestInRealModeEx(pCtx))
2041 {
2042 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2043 * The base must also be equal to (sel << 4).
2044 */
2045 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2046 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2047 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2048 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2049 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2050 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2051 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2052 {
2053 return false;
2054 }
2055 }
2056 else
2057 {
2058 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2059 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2060 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2061 */
2062 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2063 && enmGuestMode >= PGMMODE_PROTECTED)
2064 {
2065 if ( (pCtx->cs & X86_SEL_RPL)
2066 || (pCtx->ds & X86_SEL_RPL)
2067 || (pCtx->es & X86_SEL_RPL)
2068 || (pCtx->fs & X86_SEL_RPL)
2069 || (pCtx->gs & X86_SEL_RPL)
2070 || (pCtx->ss & X86_SEL_RPL))
2071 {
2072 return false;
2073 }
2074 }
2075 }
2076 }
2077 else
2078#endif /* HWACCM_VMX_EMULATE_REALMODE */
2079 {
2080 if (!CPUMIsGuestInLongModeEx(pCtx))
2081 {
2082 /** @todo This should (probably) be set on every excursion to the REM,
2083 * however it's too risky right now. So, only apply it when we go
2084 * back to REM for real mode execution. (The XP hack below doesn't
2085 * work reliably without this.)
2086 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2087 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2088
2089 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2090 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2091 return false;
2092
2093 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2094 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2095 * hidden registers (possible recompiler bug; see load_seg_vm) */
2096 if (pCtx->csHid.Attr.n.u1Present == 0)
2097 return false;
2098 if (pCtx->ssHid.Attr.n.u1Present == 0)
2099 return false;
2100
2101 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2102 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2103 /** @todo This check is actually wrong, it doesn't take the direction of the
2104 * stack segment into account. But, it does the job for now. */
2105 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2106 return false;
2107#if 0
2108 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2109 || pCtx->ss >= pCtx->gdtr.cbGdt
2110 || pCtx->ds >= pCtx->gdtr.cbGdt
2111 || pCtx->es >= pCtx->gdtr.cbGdt
2112 || pCtx->fs >= pCtx->gdtr.cbGdt
2113 || pCtx->gs >= pCtx->gdtr.cbGdt)
2114 return false;
2115#endif
2116 }
2117 }
2118
2119 if (pVM->hwaccm.s.vmx.fEnabled)
2120 {
2121 uint32_t mask;
2122
2123 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2124 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2125 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2126 mask &= ~X86_CR0_NE;
2127
2128#ifdef HWACCM_VMX_EMULATE_REALMODE
2129 if (pVM->hwaccm.s.vmx.pRealModeTSS)
2130 {
2131 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2132 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2133 }
2134 else
2135#endif
2136 {
2137 /* We support protected mode without paging using identity mapping. */
2138 mask &= ~X86_CR0_PG;
2139 }
2140 if ((pCtx->cr0 & mask) != mask)
2141 return false;
2142
2143 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2144 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2145 if ((pCtx->cr0 & mask) != 0)
2146 return false;
2147
2148 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2149 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2150 mask &= ~X86_CR4_VMXE;
2151 if ((pCtx->cr4 & mask) != mask)
2152 return false;
2153
2154 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2155 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2156 if ((pCtx->cr4 & mask) != 0)
2157 return false;
2158
2159 pVCpu->hwaccm.s.fActive = true;
2160 return true;
2161 }
2162
2163 return false;
2164}
2165
2166/**
2167 * Notifcation from EM about a rescheduling into hardware assisted execution
2168 * mode.
2169 *
2170 * @param pVCpu Pointer to the current virtual cpu structure.
2171 */
2172VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2173{
2174 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2175}
2176
2177/**
2178 * Notifcation from EM about returning from instruction emulation (REM / EM).
2179 *
2180 * @param pVCpu Pointer to the current virtual cpu structure.
2181 */
2182VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2183{
2184 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2185}
2186
2187/**
2188 * Checks if we are currently using hardware accelerated raw mode.
2189 *
2190 * @returns boolean
2191 * @param pVCpu The VMCPU to operate on.
2192 */
2193VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2194{
2195 return pVCpu->hwaccm.s.fActive;
2196}
2197
2198/**
2199 * Checks if we are currently using nested paging.
2200 *
2201 * @returns boolean
2202 * @param pVM The VM to operate on.
2203 */
2204VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2205{
2206 return pVM->hwaccm.s.fNestedPaging;
2207}
2208
2209/**
2210 * Checks if we are currently using VPID in VT-x mode.
2211 *
2212 * @returns boolean
2213 * @param pVM The VM to operate on.
2214 */
2215VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2216{
2217 return pVM->hwaccm.s.vmx.fVPID;
2218}
2219
2220
2221/**
2222 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2223 *
2224 * @returns boolean
2225 * @param pVM The VM to operate on.
2226 */
2227VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2228{
2229 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2230}
2231
2232/**
2233 * Restart an I/O instruction that was refused in ring-0
2234 *
2235 * @returns VBox status code
2236 * @param pVM The VM to operate on.
2237 * @param pVCpu The VMCPU to operate on.
2238 * @param pCtx VCPU register context
2239 */
2240VMMR3DECL(int) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2241{
2242 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2243 int rc;
2244
2245 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2246
2247 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2248 || enmType == HWACCMPENDINGIO_INVALID)
2249 return VERR_NOT_FOUND;
2250
2251 switch (enmType)
2252 {
2253 case HWACCMPENDINGIO_PORT_READ:
2254 {
2255 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2256 uint32_t u32Val = 0;
2257
2258 rc = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2259 &u32Val,
2260 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2261 if (IOM_SUCCESS(rc))
2262 {
2263 /* Write back to the EAX register. */
2264 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2265 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2266 }
2267 break;
2268 }
2269
2270 case HWACCMPENDINGIO_PORT_WRITE:
2271 rc = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2272 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2273 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2274 if (IOM_SUCCESS(rc))
2275 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2276 break;
2277
2278 default:
2279 AssertFailed();
2280 return VERR_INTERNAL_ERROR;
2281 }
2282
2283 return rc;
2284}
2285
2286/**
2287 * Inject an NMI into a running VM (only VCPU 0!)
2288 *
2289 * @returns boolean
2290 * @param pVM The VM to operate on.
2291 */
2292VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2293{
2294 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2295 return VINF_SUCCESS;
2296}
2297
2298/**
2299 * Check fatal VT-x/AMD-V error and produce some meaningful
2300 * log release message.
2301 *
2302 * @param pVM The VM to operate on.
2303 * @param iStatusCode VBox status code
2304 */
2305VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2306{
2307 for (unsigned i=0;i<pVM->cCPUs;i++)
2308 {
2309 switch(iStatusCode)
2310 {
2311 case VERR_VMX_INVALID_VMCS_FIELD:
2312 break;
2313
2314 case VERR_VMX_INVALID_VMCS_PTR:
2315 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2316 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2317 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2318 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2319 break;
2320
2321 case VERR_VMX_UNABLE_TO_START_VM:
2322 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2323 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2324#if 0 /* @todo dump the current control fields to the release log */
2325 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2326 {
2327
2328 }
2329#endif
2330 break;
2331
2332 case VERR_VMX_UNABLE_TO_RESUME_VM:
2333 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2334 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2335 break;
2336
2337 case VERR_VMX_INVALID_VMXON_PTR:
2338 break;
2339 }
2340 }
2341}
2342
2343/**
2344 * Execute state save operation.
2345 *
2346 * @returns VBox status code.
2347 * @param pVM VM Handle.
2348 * @param pSSM SSM operation handle.
2349 */
2350static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2351{
2352 int rc;
2353
2354 Log(("hwaccmR3Save:\n"));
2355
2356 for (unsigned i=0;i<pVM->cCPUs;i++)
2357 {
2358 /*
2359 * Save the basic bits - fortunately all the other things can be resynced on load.
2360 */
2361 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2362 AssertRCReturn(rc, rc);
2363 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2364 AssertRCReturn(rc, rc);
2365 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2366 AssertRCReturn(rc, rc);
2367
2368 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2369 AssertRCReturn(rc, rc);
2370 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2371 AssertRCReturn(rc, rc);
2372 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2373 AssertRCReturn(rc, rc);
2374 }
2375#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2376 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2377 AssertRCReturn(rc, rc);
2378 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2379 AssertRCReturn(rc, rc);
2380 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2381 AssertRCReturn(rc, rc);
2382
2383 /* Store all the guest patch records too. */
2384 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.svm.cPatches);
2385 AssertRCReturn(rc, rc);
2386
2387 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2388 {
2389 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2390
2391 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2392 AssertRCReturn(rc, rc);
2393
2394 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2395 AssertRCReturn(rc, rc);
2396
2397 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2398 AssertRCReturn(rc, rc);
2399
2400 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2401 AssertRCReturn(rc, rc);
2402
2403 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2404 AssertRCReturn(rc, rc);
2405
2406 AssertCompileSize(HWACCMTPRINSTR, 4);
2407 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2408 AssertRCReturn(rc, rc);
2409
2410 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2411 AssertRCReturn(rc, rc);
2412
2413 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2414 AssertRCReturn(rc, rc);
2415
2416 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2417 AssertRCReturn(rc, rc);
2418
2419 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2420 AssertRCReturn(rc, rc);
2421 }
2422#endif
2423 return VINF_SUCCESS;
2424}
2425
2426/**
2427 * Execute state load operation.
2428 *
2429 * @returns VBox status code.
2430 * @param pVM VM Handle.
2431 * @param pSSM SSM operation handle.
2432 * @param u32Version Data layout version.
2433 */
2434static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2435{
2436 int rc;
2437
2438 Log(("hwaccmR3Load:\n"));
2439
2440 /*
2441 * Validate version.
2442 */
2443 if ( u32Version != HWACCM_SSM_VERSION
2444 && u32Version != HWACCM_SSM_VERSION_NO_PATCHING
2445 && u32Version != HWACCM_SSM_VERSION_2_0_X)
2446 {
2447 AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
2448 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2449 }
2450 for (unsigned i=0;i<pVM->cCPUs;i++)
2451 {
2452 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2453 AssertRCReturn(rc, rc);
2454 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2455 AssertRCReturn(rc, rc);
2456 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2457 AssertRCReturn(rc, rc);
2458
2459 if (u32Version >= HWACCM_SSM_VERSION_NO_PATCHING)
2460 {
2461 uint32_t val;
2462
2463 rc = SSMR3GetU32(pSSM, &val);
2464 AssertRCReturn(rc, rc);
2465 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2466
2467 rc = SSMR3GetU32(pSSM, &val);
2468 AssertRCReturn(rc, rc);
2469 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2470
2471 rc = SSMR3GetU32(pSSM, &val);
2472 AssertRCReturn(rc, rc);
2473 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2474 }
2475 }
2476#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2477 if (u32Version > HWACCM_SSM_VERSION_NO_PATCHING)
2478 {
2479 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2480 AssertRCReturn(rc, rc);
2481 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2482 AssertRCReturn(rc, rc);
2483 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2484 AssertRCReturn(rc, rc);
2485
2486 /* Fetch all TPR patch records. */
2487 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.svm.cPatches);
2488 AssertRCReturn(rc, rc);
2489
2490 for (unsigned i = 0; i < pVM->hwaccm.s.svm.cPatches; i++)
2491 {
2492 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.svm.aPatches[i];
2493
2494 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2495 AssertRCReturn(rc, rc);
2496
2497 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2498 AssertRCReturn(rc, rc);
2499
2500 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2501 AssertRCReturn(rc, rc);
2502
2503 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2504 AssertRCReturn(rc, rc);
2505
2506 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2507 AssertRCReturn(rc, rc);
2508
2509 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2510 AssertRCReturn(rc, rc);
2511
2512 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2513 AssertRCReturn(rc, rc);
2514
2515 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2516 AssertRCReturn(rc, rc);
2517
2518 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2519 AssertRCReturn(rc, rc);
2520
2521 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2522 AssertRCReturn(rc, rc);
2523
2524 rc = RTAvloU32Insert(&pVM->hwaccm.s.svm.PatchTree, &pPatch->Core);
2525 AssertRC(rc);
2526 }
2527 }
2528#endif
2529 return VINF_SUCCESS;
2530}
2531
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