HWACCM.cpp@ 13755

Last change on this file since 13755 was 13646, checked in by vboxsync, 16 years ago
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1	/* $Id: HWACCM.cpp 13646 2008-10-29 11:07:29Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/patm.h>
34	#include <VBox/csam.h>
35	#include <VBox/selm.h>
36	#include <VBox/rem.h>
37	#include <VBox/hwacc_vmx.h>
38	#include <VBox/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/string.h>
48	#include <iprt/thread.h>
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
54	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
55
56
57	/**
58	* Initializes the HWACCM.
59	*
60	* @returns VBox status code.
61	* @param pVM The VM to operate on.
62	*/
63	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
64	{
65	LogFlow(("HWACCMR3Init\n"));
66
67	/*
68	* Assert alignment and sizes.
69	*/
70	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
71	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
72
73	/* Some structure checks. */
74	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
78
79	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
85	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
86
87
88	/*
89	* Register the saved state data unit.
90	*/
91	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
92	NULL, hwaccmR3Save, NULL,
93	NULL, hwaccmR3Load, NULL);
94	if (VBOX_FAILURE(rc))
95	return rc;
96
97	/* Misc initialisation. */
98	pVM->hwaccm.s.vmx.fSupported = false;
99	pVM->hwaccm.s.svm.fSupported = false;
100	pVM->hwaccm.s.vmx.fEnabled = false;
101	pVM->hwaccm.s.svm.fEnabled = false;
102
103	pVM->hwaccm.s.fActive = false;
104	pVM->hwaccm.s.fNestedPaging = false;
105
106	/* On first entry we'll sync everything. */
107	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
108
109	pVM->hwaccm.s.vmx.cr0_mask = 0;
110	pVM->hwaccm.s.vmx.cr4_mask = 0;
111
112	/*
113	* Statistics.
114	*/
115	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
116	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
117	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
118
119	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
120	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
121	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
122	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
123	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
124	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
125	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
126	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
127	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
128	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
129	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDB, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DB", STAMUNIT_OCCURENCES, "Nr of occurances");
130	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
131	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
132	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
133	STAM_REG(pVM, &pVM->hwaccm.s.StatExitRdtsc, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Rdtsc", STAMUNIT_OCCURENCES, "Nr of occurances");
134	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
135	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
136	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
137	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
138	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
139	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
140	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
141	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
142	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/WriteString", STAMUNIT_OCCURENCES, "Nr of occurances");
143	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOStringRead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/ReadString", STAMUNIT_OCCURENCES, "Nr of occurances");
144	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
145	STAM_REG(pVM, &pVM->hwaccm.s.StatExitMaxResume, STAMTYPE_COUNTER, "/HWACCM/Exit/Safety/MaxResume", STAMUNIT_OCCURENCES, "Nr of occurances");
146
147	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
148	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
149
150	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
151	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
152	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
153
154	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Virt/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
155	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPhysPageManual, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Phys/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
156	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBManual, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Manual", STAMUNIT_OCCURENCES, "Nr of occurances");
157	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBCRxChange, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/CRx", STAMUNIT_OCCURENCES, "Nr of occurances");
158	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushPageInvlpg, STAMTYPE_COUNTER, "/HWACCM/Flush/Page/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
159	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Switch", STAMUNIT_OCCURENCES, "Nr of occurances");
160	STAM_REG(pVM, &pVM->hwaccm.s.StatNoFlushTLBWorldSwitch, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/Skipped", STAMUNIT_OCCURENCES, "Nr of occurances");
161	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushASID, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/ASID", STAMUNIT_OCCURENCES, "Nr of occurances");
162	STAM_REG(pVM, &pVM->hwaccm.s.StatFlushTLBInvlpga, STAMTYPE_COUNTER, "/HWACCM/Flush/TLB/PhysInvlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
163
164	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCOffset, STAMTYPE_COUNTER, "/HWACCM/TSC/Offset", STAMUNIT_OCCURENCES, "Nr of occurances");
165	STAM_REG(pVM, &pVM->hwaccm.s.StatTSCIntercept, STAMTYPE_COUNTER, "/HWACCM/TSC/Intercept", STAMUNIT_OCCURENCES, "Nr of occurances");
166
167	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxArmed, STAMTYPE_COUNTER, "/HWACCM/Debug/Armed", STAMUNIT_OCCURENCES, "Nr of occurances");
168	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxContextSwitch, STAMTYPE_COUNTER, "/HWACCM/Debug/ContextSwitch", STAMUNIT_OCCURENCES, "Nr of occurances");
169	STAM_REG(pVM, &pVM->hwaccm.s.StatDRxIOCheck, STAMTYPE_COUNTER, "/HWACCM/Debug/IOCheck", STAMUNIT_OCCURENCES, "Nr of occurances");
170
171	pVM->hwaccm.s.paStatExitReason = NULL;
172
173	#ifdef VBOX_WITH_STATISTICS
174	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.paStatExitReason);
175	AssertRC(rc);
176	if (VBOX_SUCCESS(rc))
177	{
178	for (int i=0;i<MAX_EXITREASON_STAT;i++)
179	{
180	int rc = STAMR3RegisterF(pVM, &pVM->hwaccm.s.paStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Exit reason",
181	"/HWACCM/Exit/Reason/%02x", i);
182	AssertRC(rc);
183	}
184	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, "/HWACCM/Exit/Reason/#NPF", STAMUNIT_OCCURENCES, "Exit reason");
185	AssertRC(rc);
186	}
187	pVM->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVM->hwaccm.s.paStatExitReason);
188	Assert(pVM->hwaccm.s.paStatExitReasonR0);
189	#endif
190
191	/* Disabled by default. */
192	pVM->fHWACCMEnabled = false;
193
194	/*
195	* Check CFGM options.
196	*/
197	/* Nested paging: disabled by default. */
198	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
199	AssertRC(rc);
200
201	/* VT-x VPID: disabled by default. */
202	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnableVPID", &pVM->hwaccm.s.fAllowVPID, false);
203	AssertRC(rc);
204
205	/* HWACCM support must be explicitely enabled in the configuration file. */
206	rc = CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed, false);
207	AssertRC(rc);
208
209	return VINF_SUCCESS;
210	}
211
212	/**
213	* Turns off normal raw mode features
214	*
215	* @param pVM The VM to operate on.
216	*/
217	static void hwaccmR3DisableRawMode(PVM pVM)
218	{
219	/* Disable PATM & CSAM. */
220	PATMR3AllowPatching(pVM, false);
221	CSAMDisableScanning(pVM);
222
223	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
224	SELMR3DisableMonitoring(pVM);
225	TRPMR3DisableMonitoring(pVM);
226
227	/* The hidden selector registers are now valid. */
228	CPUMSetHiddenSelRegsValid(pVM, true);
229
230	/* Disable the switcher code (safety precaution). */
231	VMMR3DisableSwitcher(pVM);
232
233	/* Disable mapping of the hypervisor into the shadow page table. */
234	PGMR3ChangeShwPDMappings(pVM, false);
235
236	/* Disable the switcher */
237	VMMR3DisableSwitcher(pVM);
238
239	if (pVM->hwaccm.s.fNestedPaging)
240	{
241	/* Reinit the paging mode to force the new shadow mode. */
242	PGMR3ChangeMode(pVM, PGMMODE_REAL);
243	}
244	}
245
246	/**
247	* Initialize VT-x or AMD-V.
248	*
249	* @returns VBox status code.
250	* @param pVM The VM handle.
251	*/
252	VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
253	{
254	int rc;
255
256	if ( !pVM->hwaccm.s.vmx.fSupported
257	&& !pVM->hwaccm.s.svm.fSupported)
258	{
259	LogRel(("HWACCM: No VMX or SVM CPU extension found. Reason %Vrc\n", pVM->hwaccm.s.lLastError));
260	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
261	return VINF_SUCCESS;
262	}
263
264	/*
265	* Note that we have a global setting for VT-x/AMD-V usage. VMX root mode changes the way the CPU operates. Our 64 bits switcher will trap
266	* because it turns off paging, which is not allowed in VMX root mode.
267	*
268	* To simplify matters we'll just force all running VMs to either use raw or VT-x mode. No mixing allowed in the VT-x case.
269	* There's no such problem with AMD-V. (@todo)
270	*
271	*/
272	/* If we enabled or disabled hwaccm mode, then it can't be changed until all the VMs are shutdown. */
273	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_ENABLE, (pVM->hwaccm.s.fAllowed) ? HWACCMSTATE_ENABLED : HWACCMSTATE_DISABLED, NULL);
274	if (VBOX_FAILURE(rc))
275	{
276	LogRel(("HWACCMR3InitFinalize: SUPCallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Vrc\n", rc));
277	LogRel(("HWACCMR3InitFinalize: disallowed %s of HWACCM\n", pVM->hwaccm.s.fAllowed ? "enabling" : "disabling"));
278	/* Invert the selection */
279	pVM->hwaccm.s.fAllowed ^= 1;
280	LogRel(("HWACCMR3InitFinalize: new HWACCM status = %s\n", pVM->hwaccm.s.fAllowed ? "enabled" : "disabled"));
281
282	if (pVM->hwaccm.s.fAllowed)
283	{
284	if (pVM->hwaccm.s.vmx.fSupported)
285	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses Intel VT-x hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using VT-x as well.\n");
286	else
287	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses AMD-V hardware acceleration. It is not allowed to simultaneously use software virtualization, therefore this VM will be run using AMD-V as well.\n");
288	}
289	else
290	VMSetRuntimeError(pVM, false, "HwAccmModeChangeDisallowed", "An active VM already uses software virtualization. It is not allowed to simultaneously use VT-x or AMD-V, therefore this VM will be run using software virtualization as well.\n");
291	}
292
293	if (pVM->hwaccm.s.fAllowed == false)
294	return VINF_SUCCESS; /* disabled */
295
296	Assert(!pVM->fHWACCMEnabled);
297
298	if (pVM->hwaccm.s.vmx.fSupported)
299	{
300	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
301
302	if ( pVM->hwaccm.s.fInitialized == false
303	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
304	{
305	uint64_t val;
306	RTGCPHYS GCPhys = 0;
307
308	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
309	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
310	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
311	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
312	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
313	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
314	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
315	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
316
317	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
318	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
319	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
320	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
321	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
322	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
323	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
324	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
325	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
326	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
327	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
328
329	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
330	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
331	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
332	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
333	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
334	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
335	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
336	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
337	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
338	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
339	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
340	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
341	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
342	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
343	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
344	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
345	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
346	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
347	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
348	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
349	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
350	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
351	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
352	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
353	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
354	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
355	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
356	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
357	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
358	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
359	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
360	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
361	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
362	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
363	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
364	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
365	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
366	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
367	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
368	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
369	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
370	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
371
372	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
373	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
374	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
375	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
376	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
377	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
378	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
379	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
380	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
381	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
382	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
383	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
384	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
385	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
386	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
387	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
388	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
389	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
390	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
391	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
392	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
393	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
394	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
395	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
396	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
397	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
398	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
399	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
400	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
401	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
402	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
403	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
404	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
405	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
406	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
407	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
408	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
409	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
410	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
411	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
412	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
413
414	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
415	{
416	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
417	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
418	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
419	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
420	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
421	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
422	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
423	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
424	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
425	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
426
427	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
428	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
429	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
430	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
431	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
432	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
433	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
434	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
435	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
436	}
437
438	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
439	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
440	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
441	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
442	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
443	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
444	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
445	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
446	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
447	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
448	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
449	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
450	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
451	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
452	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
453	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
454	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
455	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
456	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
457	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
458	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
459	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
460	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
461	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
462	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
463	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
464	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
465	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
466	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
467	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
468	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
469
470	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
471	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
472	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
473	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
474	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
475	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
476	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
477	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
478	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
479	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
480	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
481	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
482	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
483	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
484	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
485	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
486	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
487	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
488	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
489	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
490	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
491	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
492	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
493	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
494	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
495	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
496	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
497	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
498	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
499	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
500	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
501	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
502	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
503	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
504	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
505
506	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
507	{
508	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
509
510	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
511	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
512	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
513	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
514	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
515	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
516	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
517	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
518	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
519	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
520	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
521	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
522	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
523	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
524	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
525	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
526	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
527	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
528	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
529	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
530	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
531	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
532	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
533	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
534	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
535	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
536	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
537	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
538	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
539	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
540	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
541	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
542	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
543	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
544	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
545	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
546	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
548	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
549	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
550	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
551	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
552	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
553	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
554	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
555	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
556	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
557	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
558	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
559	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
560	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
561	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
562	}
563
564	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
565	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
566	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
567	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
568	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
569
570	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
571	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
572	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
573	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
574	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
575
576	LogRel(("HWACCM: VMCS physaddr = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
577	LogRel(("HWACCM: TPR shadow physaddr = %VHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
578	LogRel(("HWACCM: MSR bitmap physaddr = %VHp\n", pVM->hwaccm.s.vmx.pMSRBitmapPhys));
579
580	#ifdef HWACCM_VTX_WITH_EPT
581	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
582	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
583	#endif /* HWACCM_VTX_WITH_EPT */
584	#ifdef HWACCM_VTX_WITH_VPID
585	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
586	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
587	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.fAllowVPID;
588	#endif /* HWACCM_VTX_WITH_VPID */
589
590	/* Only try once. */
591	pVM->hwaccm.s.fInitialized = true;
592
593	/* Allocate three pages for the TSS we need for real mode emulation. (2 page for the IO bitmap) */
594	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
595	AssertRC(rc);
596	if (RT_FAILURE(rc))
597	return rc;
598
599	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
600	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
601	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
602	/* Bit set to 0 means redirection enabled. */
603	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
604	/* Allow all port IO, so the VT-x IO intercepts do their job. */
605	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
606	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
607
608	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
609	* real and protected mode without paging with EPT.
610	*/
611	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
612	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
613	{
614	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
615	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
616	}
617
618	/* We convert it here every time as pci regions could be reconfigured. */
619	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
620	AssertRC(rc);
621	LogRel(("HWACCM: Real Mode TSS guest physaddr = %VGp\n", GCPhys));
622
623	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
624	AssertRC(rc);
625	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %VGp\n", GCPhys));
626
627	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
628	AssertRC(rc);
629	if (rc == VINF_SUCCESS)
630	{
631	pVM->fHWACCMEnabled = true;
632	pVM->hwaccm.s.vmx.fEnabled = true;
633	hwaccmR3DisableRawMode(pVM);
634
635	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
636	#ifdef VBOX_ENABLE_64_BITS_GUESTS
637	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
638	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
639	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
640	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
641	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
642	#endif
643	LogRel(("HWACCM: VMX enabled!\n"));
644	if (pVM->hwaccm.s.fNestedPaging)
645	{
646	LogRel(("HWACCM: Enabled nested paging\n"));
647	LogRel(("HWACCM: EPT root page = %VHp\n", PGMGetEPTCR3(pVM)));
648	}
649	if (pVM->hwaccm.s.vmx.fVPID)
650	LogRel(("HWACCM: Enabled VPID\n"));
651
652	if ( pVM->hwaccm.s.fNestedPaging
653	\|\| pVM->hwaccm.s.vmx.fVPID)
654	{
655	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
656	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
657	}
658	}
659	else
660	{
661	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
662	LogRel(("HWACCM: Last instruction error %x\n", pVM->hwaccm.s.vmx.ulLastInstrError));
663	pVM->fHWACCMEnabled = false;
664	}
665	}
666	}
667	else
668	if (pVM->hwaccm.s.svm.fSupported)
669	{
670	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
671
672	if (pVM->hwaccm.s.fInitialized == false)
673	{
674	/* Erratum 170 which requires a forced TLB flush for each world switch:
675	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
676	*
677	* All BH-G1/2 and DH-G1/2 models include a fix:
678	* Athlon X2: 0x6b 1/2
679	* 0x68 1/2
680	* Athlon 64: 0x7f 1
681	* 0x6f 2
682	* Sempron: 0x7f 1/2
683	* 0x6f 2
684	* 0x6c 2
685	* 0x7c 2
686	* Turion 64: 0x68 2
687	*
688	*/
689	uint32_t u32Dummy;
690	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
691	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
692	u32BaseFamily= (u32Version >> 8) & 0xf;
693	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
694	u32Model = ((u32Version >> 4) & 0xf);
695	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
696	u32Stepping = u32Version & 0xf;
697	if ( u32Family == 0xf
698	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
699	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
700	{
701	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
702	}
703
704	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
705	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
706	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
707	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
708	LogRel(("HWACCM: SVM features = %X\n", pVM->hwaccm.s.svm.u32Features));
709
710	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
711	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
712	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
713	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
714	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
715	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
716	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
717	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
718	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
719	LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
720
721	/* Only try once. */
722	pVM->hwaccm.s.fInitialized = true;
723
724	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
725	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
726
727	rc = SUPCallVMMR0Ex(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
728	AssertRC(rc);
729	if (rc == VINF_SUCCESS)
730	{
731	pVM->fHWACCMEnabled = true;
732	pVM->hwaccm.s.svm.fEnabled = true;
733
734	if (pVM->hwaccm.s.fNestedPaging)
735	LogRel(("HWACCM: Enabled nested paging\n"));
736
737	hwaccmR3DisableRawMode(pVM);
738	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
739	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
740	#ifdef VBOX_ENABLE_64_BITS_GUESTS
741	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
742	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
743	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
744	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
745	#endif
746	}
747	else
748	{
749	pVM->fHWACCMEnabled = false;
750	}
751	}
752	}
753	return VINF_SUCCESS;
754	}
755
756	/**
757	* Applies relocations to data and code managed by this
758	* component. This function will be called at init and
759	* whenever the VMM need to relocate it self inside the GC.
760	*
761	* @param pVM The VM.
762	*/
763	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
764	{
765	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
766	return;
767	}
768
769	/**
770	* Checks hardware accelerated raw mode is allowed.
771	*
772	* @returns boolean
773	* @param pVM The VM to operate on.
774	*/
775	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
776	{
777	return pVM->hwaccm.s.fAllowed;
778	}
779
780	/**
781	* Notification callback which is called whenever there is a chance that a CR3
782	* value might have changed.
783	*
784	* This is called by PGM.
785	*
786	* @param pVM The VM to operate on.
787	* @param enmShadowMode New shadow paging mode.
788	* @param enmGuestMode New guest paging mode.
789	*/
790	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
791	{
792	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
793	if ( pVM->hwaccm.s.vmx.fEnabled
794	&& pVM->fHWACCMEnabled)
795	{
796	if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
797	&& enmGuestMode >= PGMMODE_PROTECTED)
798	{
799	PCPUMCTX pCtx;
800
801	pCtx = CPUMQueryGuestCtxPtr(pVM);
802
803	/* After a real mode switch to protected mode we must force
804	* CPL to 0. Our real mode emulation had to set it to 3.
805	*/
806	pCtx->ssHid.Attr.n.u2Dpl = 0;
807	}
808	}
809	}
810
811	/**
812	* Terminates the HWACCM.
813	*
814	* Termination means cleaning up and freeing all resources,
815	* the VM it self is at this point powered off or suspended.
816	*
817	* @returns VBox status code.
818	* @param pVM The VM to operate on.
819	*/
820	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
821	{
822	if (pVM->hwaccm.s.vmx.pRealModeTSS)
823	{
824	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
825	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
826	}
827
828	if (pVM->hwaccm.s.paStatExitReason)
829	{
830	MMHyperFree(pVM, pVM->hwaccm.s.paStatExitReason);
831	pVM->hwaccm.s.paStatExitReason = NULL;
832	}
833	return 0;
834	}
835
836	/**
837	* The VM is being reset.
838	*
839	* For the HWACCM component this means that any GDT/LDT/TSS monitors
840	* needs to be removed.
841	*
842	* @param pVM VM handle.
843	*/
844	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
845	{
846	LogFlow(("HWACCMR3Reset:\n"));
847
848	if (pVM->fHWACCMEnabled)
849	hwaccmR3DisableRawMode(pVM);
850
851	/* On first entry we'll sync everything. */
852	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
853
854	pVM->hwaccm.s.vmx.cr0_mask = 0;
855	pVM->hwaccm.s.vmx.cr4_mask = 0;
856
857	pVM->hwaccm.s.Event.fPending = false;
858
859	/* Reset state information for real-mode emulation in VT-x. */
860	pVM->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
861	}
862
863	/**
864	* Checks if we can currently use hardware accelerated raw mode.
865	*
866	* @returns boolean
867	* @param pVM The VM to operate on.
868	* @param pCtx Partial VM execution context
869	*/
870	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
871	{
872	Assert(pVM->fHWACCMEnabled);
873
874	/* AMD SVM supports real & protected mode with or without paging. */
875	if (pVM->hwaccm.s.svm.fEnabled)
876	{
877	pVM->hwaccm.s.fActive = true;
878	return true;
879	}
880
881	pVM->hwaccm.s.fActive = false;
882
883	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
884	#ifdef HWACCM_VMX_EMULATE_REALMODE
885	if (CPUMIsGuestInRealModeEx(pCtx))
886	{
887	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
888	* The base must also be equal to (sel << 4).
889	*/
890	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
891	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
892	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
893	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
894	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
895	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
896	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
897	return false;
898	}
899	else
900	{
901	PGMMODE enmGuestMode = PGMGetGuestMode(pVM);
902	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
903	* from real to protected mode. (all sorts of RPL & DPL assumptions)
904	*/
905	if ( pVM->hwaccm.s.vmx.enmCurrGuestMode == PGMMODE_REAL
906	&& enmGuestMode >= PGMMODE_PROTECTED)
907	{
908	if ( (pCtx->cs & X86_SEL_RPL)
909	\|\| (pCtx->ds & X86_SEL_RPL)
910	\|\| (pCtx->es & X86_SEL_RPL)
911	\|\| (pCtx->fs & X86_SEL_RPL)
912	\|\| (pCtx->gs & X86_SEL_RPL)
913	\|\| (pCtx->ss & X86_SEL_RPL))
914	{
915	/* Flush the translation blocks as code pages may have been
916	* changed (Fedora4 boot image, reset, boot iso)
917	*/
918	REMFlushTBs(pVM);
919	return false;
920	}
921	}
922	}
923	#else
924	if (!CPUMIsGuestInLongModeEx(pCtx))
925	{
926	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
927	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
928	return false;
929
930	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
931	/* Windows XP; switch to protected mode; all selectors are marked not present in the
932	* hidden registers (possible recompiler bug; see load_seg_vm) */
933	if (pCtx->csHid.Attr.n.u1Present == 0)
934	return false;
935	if (pCtx->ssHid.Attr.n.u1Present == 0)
936	return false;
937	}
938	#endif
939
940	if (pVM->hwaccm.s.vmx.fEnabled)
941	{
942	uint32_t mask;
943
944	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
945	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
946	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
947	mask &= ~X86_CR0_NE;
948
949	#ifdef HWACCM_VMX_EMULATE_REALMODE
950	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
951	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
952	#else
953	/* We support protected mode without paging using identity mapping. */
954	mask &= ~X86_CR0_PG;
955	#endif
956	if ((pCtx->cr0 & mask) != mask)
957	return false;
958
959	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
960	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
961	if ((pCtx->cr0 & mask) != 0)
962	return false;
963
964	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
965	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
966	mask &= ~X86_CR4_VMXE;
967	if ((pCtx->cr4 & mask) != mask)
968	return false;
969
970	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
971	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
972	if ((pCtx->cr4 & mask) != 0)
973	return false;
974
975	pVM->hwaccm.s.fActive = true;
976	return true;
977	}
978
979	return false;
980	}
981
982	/**
983	* Checks if we are currently using hardware accelerated raw mode.
984	*
985	* @returns boolean
986	* @param pVM The VM to operate on.
987	*/
988	VMMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
989	{
990	return pVM->hwaccm.s.fActive;
991	}
992
993	/**
994	* Checks if we are currently using nested paging.
995	*
996	* @returns boolean
997	* @param pVM The VM to operate on.
998	*/
999	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
1000	{
1001	return pVM->hwaccm.s.fNestedPaging;
1002	}
1003
1004	/**
1005	* Checks if we are currently using VPID in VT-x mode.
1006	*
1007	* @returns boolean
1008	* @param pVM The VM to operate on.
1009	*/
1010	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
1011	{
1012	return pVM->hwaccm.s.vmx.fVPID;
1013	}
1014
1015
1016	/**
1017	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
1018	*
1019	* @returns boolean
1020	* @param pVM The VM to operate on.
1021	*/
1022	VMMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
1023	{
1024	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
1025	}
1026
1027	/**
1028	* Check fatal VT-x/AMD-V error and produce some meaningful
1029	* log release message.
1030	*
1031	* @param pVM The VM to operate on.
1032	* @param iStatusCode VBox status code
1033	*/
1034	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
1035	{
1036	switch(iStatusCode)
1037	{
1038	case VERR_VMX_INVALID_VMCS_FIELD:
1039	break;
1040
1041	case VERR_VMX_INVALID_VMCS_PTR:
1042	LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current pointer %VGp vs %VGp\n", pVM->hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->hwaccm.s.vmx.pVMCSPhys));
1043	LogRel(("VERR_VMX_INVALID_VMCS_PTR: Current VMCS version %x\n", pVM->hwaccm.s.vmx.lasterror.ulVMCSRevision));
1044	break;
1045
1046	case VERR_VMX_UNABLE_TO_START_VM:
1047	LogRel(("VERR_VMX_UNABLE_TO_START_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError));
1048	LogRel(("VERR_VMX_UNABLE_TO_START_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason));
1049	break;
1050
1051	case VERR_VMX_UNABLE_TO_RESUME_VM:
1052	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: instruction error %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastInstrError));
1053	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: exit reason %x\n", pVM->hwaccm.s.vmx.lasterror.ulLastExitReason));
1054	break;
1055
1056	case VERR_VMX_INVALID_VMXON_PTR:
1057	break;
1058	}
1059	}
1060
1061	/**
1062	* Execute state save operation.
1063	*
1064	* @returns VBox status code.
1065	* @param pVM VM Handle.
1066	* @param pSSM SSM operation handle.
1067	*/
1068	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
1069	{
1070	int rc;
1071
1072	Log(("hwaccmR3Save:\n"));
1073
1074	/*
1075	* Save the basic bits - fortunately all the other things can be resynced on load.
1076	*/
1077	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
1078	AssertRCReturn(rc, rc);
1079	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
1080	AssertRCReturn(rc, rc);
1081	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
1082	AssertRCReturn(rc, rc);
1083
1084	return VINF_SUCCESS;
1085	}
1086
1087	/**
1088	* Execute state load operation.
1089	*
1090	* @returns VBox status code.
1091	* @param pVM VM Handle.
1092	* @param pSSM SSM operation handle.
1093	* @param u32Version Data layout version.
1094	*/
1095	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1096	{
1097	int rc;
1098
1099	Log(("hwaccmR3Load:\n"));
1100
1101	/*
1102	* Validate version.
1103	*/
1104	if (u32Version != HWACCM_SSM_VERSION)
1105	{
1106	AssertMsgFailed(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
1107	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1108	}
1109	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
1110	AssertRCReturn(rc, rc);
1111	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
1112	AssertRCReturn(rc, rc);
1113	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
1114	AssertRCReturn(rc, rc);
1115
1116	return VINF_SUCCESS;
1117	}
1118
1119
1120
1121

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 13755

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