HWACCM.cpp@ 1210

Last change on this file since 1210 was 1210, checked in by vboxsync, 18 years ago
Added PGMR3ChangeShwPDMappings. Added VMX/SVM test case.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 23.3 KB

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1	/* $Id: HWACCM.cpp 1210 2007-03-05 12:36:53Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48	#include "x86context.h"
49
50
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58	/**
59	* Initializes the HWACCM.
60	*
61	* @returns VBox status code.
62	* @param pVM The VM to operate on.
63	*/
64	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65	{
66	LogFlow(("HWACCMR3Init\n"));
67
68	/*
69	* Assert alignment and sizes.
70	*/
71	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74	/* Some structure checks. */
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89	/*
90	* Register the saved state data unit.
91	*/
92	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93	NULL, hwaccmR3Save, NULL,
94	NULL, hwaccmR3Load, NULL);
95	if (VBOX_FAILURE(rc))
96	return rc;
97
98	/** @todo Make sure both pages are either not accessible or readonly! */
99	/* Allocate one page for VMXON. */
100	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMXONPhys);
101	if (pVM->hwaccm.s.vmx.pVMXON == 0)
102	{
103	AssertMsgFailed(("SUPContAlloc failed!!\n"));
104	return VERR_NO_MEMORY;
105	}
106	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108	/* Allocate one page for the VM control structure (VMCS). */
109	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMCSPhys);
110	if (pVM->hwaccm.s.vmx.pVMCS == 0)
111	{
112	AssertMsgFailed(("SUPContAlloc failed!!\n"));
113	return VERR_NO_MEMORY;
114	}
115	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117	/* Reuse those two pages for AMD SVM. (one is active; never both) */
118	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123	/* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124	pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125	if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126	{
127	AssertMsgFailed(("SUPContAlloc failed!!\n"));
128	return VERR_NO_MEMORY;
129	}
130	memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(PAGE_SIZE*3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135	{
136	AssertMsgFailed(("SUPContAlloc failed!!\n"));
137	return VERR_NO_MEMORY;
138	}
139	/* Set all bits to intercept all IO accesses. */
140	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(PAGE_SIZE*2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145	{
146	AssertMsgFailed(("SUPContAlloc failed!!\n"));
147	return VERR_NO_MEMORY;
148	}
149	/* Set all bits to intercept all MSR accesses. */
150	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152	/* Misc initialisation. */
153	pVM->hwaccm.s.vmx.fSupported = false;
154	pVM->hwaccm.s.svm.fSupported = false;
155	pVM->hwaccm.s.vmx.fEnabled = false;
156	pVM->hwaccm.s.svm.fEnabled = false;
157
158	pVM->hwaccm.s.fActive = false;
159
160	/* On first entry we'll sync everything. */
161	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163	pVM->hwaccm.s.vmx.cr0_mask = 0;
164	pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166	/*
167	* Statistics.
168	*/
169	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
195
196	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
198
199	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
200	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
201	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
202
203	pVM->hwaccm.s.pStatExitReason = 0;
204
205	#ifdef VBOX_WITH_STATISTICS
206	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
207	AssertRC(rc);
208	if (VBOX_SUCCESS(rc))
209	{
210	for (int i=0;i<MAX_EXITREASON_STAT;i++)
211	{
212	char szName[64];
213	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
214	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
215	AssertRC(rc);
216	}
217	}
218	#endif
219
220	/* Disabled by default. */
221	pVM->fHWACCMEnabled = false;
222
223	/* HWACCM support must be explicitely enabled in the configuration file. */
224	pVM->hwaccm.s.fAllowed = false;
225	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
226
227	return VINF_SUCCESS;
228	}
229
230
231	/**
232	* Turns off normal raw mode features
233	*
234	* @param pVM The VM to operate on.
235	*/
236	static void hwaccmr3DisableRawMode(PVM pVM)
237	{
238	/* Disable PATM & CSAM. */
239	PATMR3AllowPatching(pVM, false);
240	CSAMDisableScanning(pVM);
241
242	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
243	SELMR3DisableMonitoring(pVM);
244	TRPMR3DisableMonitoring(pVM);
245
246	/* The hidden selector registers are now valid. */
247	CPUMSetHiddenSelRegsValid(pVM, true);
248
249	/* Disable the switcher code (safety precaution). */
250	VMMR3DisableSwitcher(pVM);
251
252	/* Disable mapping of the hypervisor into the shadow page table. */
253	PGMR3ChangeShwPDMappings(pVM, false);
254
255	/* Disable the switcher */
256	VMMR3DisableSwitcher(pVM);
257	}
258
259	/**
260	* Applies relocations to data and code managed by this
261	* component. This function will be called at init and
262	* whenever the VMM need to relocate it self inside the GC.
263	*
264	* @param pVM The VM.
265	*/
266	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
267	{
268	#ifdef LOG_ENABLED
269	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
270	#endif
271
272	if (pVM->hwaccm.s.fAllowed == false)
273	return ;
274
275	if (pVM->hwaccm.s.vmx.fSupported)
276	{
277	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
278	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
279	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
280	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
281	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
282	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
283	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
284	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
285	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
286	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
287	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
288	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
289	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
290	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
291
292	if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
293	{
294	/* Only try once. */
295	pVM->hwaccm.s.fInitialized = true;
296
297	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
298	AssertRC(rc);
299	if (rc == VINF_SUCCESS)
300	{
301	hwaccmr3DisableRawMode(pVM);
302
303	pVM->fHWACCMEnabled = true;
304	pVM->hwaccm.s.vmx.fEnabled = true;
305	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
306	LogRel(("HWACCM: VMX enabled!\n"));
307	}
308	else
309	{
310	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
311	pVM->fHWACCMEnabled = false;
312	}
313	}
314	}
315	else
316	if (pVM->hwaccm.s.svm.fSupported)
317	{
318	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
319	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
320	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
321	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
322	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
323
324	if (pVM->hwaccm.s.fInitialized == false)
325	{
326	/* Only try once. */
327	pVM->hwaccm.s.fInitialized = true;
328
329	int rc = SUPCallVMMR0(pVM->pVMR0, VMMR0_DO_HWACC_SETUP_VM, NULL);
330	AssertRC(rc);
331	if (rc == VINF_SUCCESS)
332	{
333	hwaccmr3DisableRawMode(pVM);
334	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
335
336	pVM->fHWACCMEnabled = true;
337	pVM->hwaccm.s.svm.fEnabled = true;
338	}
339	else
340	{
341	pVM->fHWACCMEnabled = false;
342	}
343	}
344	}
345
346	}
347
348
349	/**
350	* Checks hardware accelerated raw mode is allowed.
351	*
352	* @returns boolean
353	* @param pVM The VM to operate on.
354	*/
355	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
356	{
357	return pVM->hwaccm.s.fAllowed;
358	}
359
360
361	/**
362	* Notification callback which is called whenever there is a chance that a CR3
363	* value might have changed.
364	* This is called by PGM.
365	*
366	* @param pVM The VM to operate on.
367	* @param enmShadowMode New paging mode.
368	*/
369	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
370	{
371	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
372	}
373
374	/**
375	* Terminates the HWACCM.
376	*
377	* Termination means cleaning up and freeing all resources,
378	* the VM it self is at this point powered off or suspended.
379	*
380	* @returns VBox status code.
381	* @param pVM The VM to operate on.
382	*/
383	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
384	{
385	if (pVM->hwaccm.s.pStatExitReason)
386	{
387	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
388	pVM->hwaccm.s.pStatExitReason = 0;
389	}
390
391	if (pVM->hwaccm.s.vmx.pVMXON)
392	{
393	SUPContFree(pVM->hwaccm.s.vmx.pVMXON);
394	pVM->hwaccm.s.vmx.pVMXON = 0;
395	}
396	if (pVM->hwaccm.s.vmx.pVMCS)
397	{
398	SUPContFree(pVM->hwaccm.s.vmx.pVMCS);
399	pVM->hwaccm.s.vmx.pVMCS = 0;
400	}
401	if (pVM->hwaccm.s.svm.pVMCBHost)
402	{
403	SUPContFree(pVM->hwaccm.s.svm.pVMCBHost);
404	pVM->hwaccm.s.svm.pVMCBHost = 0;
405	}
406	if (pVM->hwaccm.s.svm.pIOBitmap)
407	{
408	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap);
409	pVM->hwaccm.s.svm.pIOBitmap = 0;
410	}
411	if (pVM->hwaccm.s.svm.pMSRBitmap)
412	{
413	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap);
414	pVM->hwaccm.s.svm.pMSRBitmap = 0;
415	}
416	return 0;
417	}
418
419
420	/**
421	* The VM is being reset.
422	*
423	* For the HWACCM component this means that any GDT/LDT/TSS monitors
424	* needs to be removed.
425	*
426	* @param pVM VM handle.
427	*/
428	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
429	{
430	LogFlow(("HWACCMR3Reset:\n"));
431
432	if (pVM->fHWACCMEnabled)
433	hwaccmr3DisableRawMode(pVM);
434
435	/* On first entry we'll sync everything. */
436	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
437
438	pVM->hwaccm.s.vmx.cr0_mask = 0;
439	pVM->hwaccm.s.vmx.cr4_mask = 0;
440	}
441
442	/**
443	* Checks if we can currently use hardware accelerated raw mode.
444	*
445	* @returns boolean
446	* @param pVM The VM to operate on.
447	* @param pCtx Partial VM execution context
448	*/
449	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
450	{
451	uint32_t mask;
452
453	Assert(pVM->fHWACCMEnabled);
454
455	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
456	* (but do we really care?)
457	*/
458
459	pVM->hwaccm.s.fActive = false;
460
461	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
462
463	/* Too early for VMX and SVN (?). */
464	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
465	return false;
466
467	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
468	if (pCtx->csHid.Attr.n.u1Present == 0)
469	return false;
470	if (pCtx->ssHid.Attr.n.u1Present == 0)
471	return false;
472
473	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
474	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
475	return false;
476
477	if (pVM->hwaccm.s.vmx.fEnabled)
478	{
479	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
480	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
481	/** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
482	mask &= ~X86_CR0_NE;
483
484	if ((pCtx->cr0 & mask) != mask)
485	return false;
486
487	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
488	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
489	if ((pCtx->cr0 & mask) != 0)
490	return false;
491
492	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
493	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
494	mask &= ~X86_CR4_VMXE;
495	if ((pCtx->cr4 & mask) != mask)
496	return false;
497
498	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
499	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
500	if ((pCtx->cr4 & mask) != 0)
501	return false;
502
503	pVM->hwaccm.s.fActive = true;
504	return true;
505	}
506	else
507	{
508	Assert(pVM->hwaccm.s.svm.fEnabled);
509
510	/* Let's start with protected mode with paging enabled first. */
511	if ((pCtx->cr0 & (X86_CR0_PE\|X86_CR0_PG)) == (X86_CR0_PE\|X86_CR0_PG))
512	{
513	pVM->hwaccm.s.fActive = true;
514	return true;
515	}
516	}
517
518	return false;
519	}
520
521	/**
522	* Checks if we are currently using hardware accelerated raw mode.
523	*
524	* @returns boolean
525	* @param pVM The VM to operate on.
526	*/
527	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
528	{
529	return pVM->hwaccm.s.fActive;
530	}
531
532	/**
533	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
534	*
535	* @returns boolean
536	* @param pVM The VM to operate on.
537	*/
538	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
539	{
540	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
541	}
542
543	/**
544	* Execute state save operation.
545	*
546	* @returns VBox status code.
547	* @param pVM VM Handle.
548	* @param pSSM SSM operation handle.
549	*/
550	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
551	{
552	int rc;
553
554	Log(("hwaccmR3Save:\n"));
555
556	/*
557	* Save the basic bits - fortunately all the other things can be resynced on load.
558	*/
559	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
560	AssertRCReturn(rc, rc);
561	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
562	AssertRCReturn(rc, rc);
563	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
564	AssertRCReturn(rc, rc);
565
566	return VINF_SUCCESS;
567	}
568
569
570	/**
571	* Execute state load operation.
572	*
573	* @returns VBox status code.
574	* @param pVM VM Handle.
575	* @param pSSM SSM operation handle.
576	* @param u32Version Data layout version.
577	*/
578	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
579	{
580	int rc;
581
582	Log(("hwaccmR3Load:\n"));
583
584	/*
585	* Validate version.
586	*/
587	if (u32Version != HWACCM_SSM_VERSION)
588	{
589	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
590	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
591	}
592
593	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
594	AssertRCReturn(rc, rc);
595	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
596	AssertRCReturn(rc, rc);
597	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
598	AssertRCReturn(rc, rc);
599
600	return VINF_SUCCESS;
601	}
602
603
604
605

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 1210

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