VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 1

Last change on this file since 1 was 1, checked in by vboxsync, 55 years ago

import
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 23.2 KB
Line 
1/** @file
2 *
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdm.h>
30#include <VBox/pgm.h>
31#include <VBox/trpm.h>
32#include <VBox/dbgf.h>
33#include <VBox/hwacc_vmx.h>
34#include <VBox/hwacc_svm.h>
35#include "HWACCMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/patm.h>
40#include <VBox/csam.h>
41#include <VBox/selm.h>
42
43#include <iprt/assert.h>
44#include <VBox/log.h>
45#include <iprt/asm.h>
46#include <iprt/string.h>
47#include <iprt/thread.h>
48#include "x86context.h"
49
50#include <string.h>
51
52
53/*******************************************************************************
54* Internal Functions *
55*******************************************************************************/
56static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
57static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
58
59
60/**
61 * Initializes the HWACCM.
62 *
63 * @returns VBox status code.
64 * @param pVM The VM to operate on.
65 */
66HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
67{
68 LogFlow(("HWACCMR3Init\n"));
69
70 /*
71 * Assert alignment and sizes.
72 */
73 AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
74 AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
75
76 /* Some structure checks. */
77 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
78 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
79 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
80 AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
81
82 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
83 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
84 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
85 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
86 AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
87 AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
88 AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
89
90
91 /*
92 * Register the saved state data unit.
93 */
94 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
95 NULL, hwaccmR3Save, NULL,
96 NULL, hwaccmR3Load, NULL);
97 if (VBOX_FAILURE(rc))
98 return rc;
99
100 /** @todo Make sure both pages are either not accessible or readonly! */
101 /* Allocate one page for VMXON. */
102 pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMXONPhys);
103 if (pVM->hwaccm.s.vmx.pVMXON == 0)
104 {
105 AssertMsgFailed(("SUPContAlloc failed!!\n"));
106 return VERR_NO_MEMORY;
107 }
108 memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
109
110 /* Allocate one page for the VM control structure (VMCS). */
111 pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMCSPhys);
112 if (pVM->hwaccm.s.vmx.pVMCS == 0)
113 {
114 AssertMsgFailed(("SUPContAlloc failed!!\n"));
115 return VERR_NO_MEMORY;
116 }
117 memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
118
119 /* Reuse those two pages for AMD SVM. (one is active; never both) */
120 pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
121 pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
122 pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
123 pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
124
125 /* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
126 pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.svm.pVMCBHostPhys);
127 if (pVM->hwaccm.s.svm.pVMCBHost == 0)
128 {
129 AssertMsgFailed(("SUPContAlloc failed!!\n"));
130 return VERR_NO_MEMORY;
131 }
132 memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
133
134 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
135 pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(PAGE_SIZE*3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
136 if (pVM->hwaccm.s.svm.pIOBitmap == 0)
137 {
138 AssertMsgFailed(("SUPContAlloc failed!!\n"));
139 return VERR_NO_MEMORY;
140 }
141 /* Set all bits to intercept all IO accesses. */
142 memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
143
144 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
145 pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(PAGE_SIZE*2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
146 if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
147 {
148 AssertMsgFailed(("SUPContAlloc failed!!\n"));
149 return VERR_NO_MEMORY;
150 }
151 /* Set all bits to intercept all MSR accesses. */
152 memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
153
154 /* Misc initialisation. */
155 pVM->hwaccm.s.vmx.fSupported = false;
156 pVM->hwaccm.s.svm.fSupported = false;
157 pVM->hwaccm.s.vmx.fEnabled = false;
158 pVM->hwaccm.s.svm.fEnabled = false;
159
160 pVM->hwaccm.s.fActive = false;
161
162 /* On first entry we'll sync everything. */
163 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
164
165 pVM->hwaccm.s.vmx.cr0_mask = 0;
166 pVM->hwaccm.s.vmx.cr4_mask = 0;
167
168 /*
169 * Statistics.
170 */
171 STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
172 STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
173 STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
174
175 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
176 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
177 STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
178 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
179 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
180 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
181 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
182 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
183 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
184 STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
185 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
186 STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
187 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
188 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
189 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
190 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
191 STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
192 STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
193 STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
194 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
195 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
196 STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
197
198 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
199 STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
200
201 STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
202 STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
203 STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
204
205 pVM->hwaccm.s.pStatExitReason = 0;
206
207#ifdef VBOX_WITH_STATISTICS
208 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
209 AssertRC(rc);
210 if (VBOX_SUCCESS(rc))
211 {
212 for (int i=0;i<MAX_EXITREASON_STAT;i++)
213 {
214 char szName[64];
215 RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
216 int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
217 AssertRC(rc);
218 }
219 }
220#endif
221
222 /* Disabled by default. */
223 pVM->fHWACCMEnabled = false;
224
225 /* HWACCM support must be explicitely enabled in the configuration file. */
226 pVM->hwaccm.s.fAllowed = false;
227 CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
228
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * Turns off normal raw mode features
235 *
236 * @param pVM The VM to operate on.
237 */
238static void hwaccmr3DisableRawMode(PVM pVM)
239{
240 /* Disable PATM & CSAM. */
241 PATMR3AllowPatching(pVM, false);
242 CSAMDisableScanning(pVM);
243
244 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
245 SELMR3DisableMonitoring(pVM);
246 TRPMR3DisableMonitoring(pVM);
247
248 /* The hidden selector registers are now valid. */
249 CPUMSetHiddenSelRegsValid(pVM, true);
250
251 /* Disable the switcher code (safety precaution). */
252 VMMR3DisableSwitcher(pVM);
253
254 /* Disable mapping of the hypervisor into the shadow page table. */
255 PGMR3RemoveMappingsFromShwPD(pVM);
256}
257
258/**
259 * Applies relocations to data and code managed by this
260 * component. This function will be called at init and
261 * whenever the VMM need to relocate it self inside the GC.
262 *
263 * @param pVM The VM.
264 */
265HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
266{
267#ifdef LOG_ENABLED
268 Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
269#endif
270
271 if (pVM->hwaccm.s.fAllowed == false)
272 return ;
273
274 if (pVM->hwaccm.s.vmx.fSupported)
275 {
276 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
277 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
278 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
279 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
280 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
281 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
282 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
283 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
284 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
285 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
286 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
287 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
288 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
289 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
290
291 if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
292 {
293 /* Only try once. */
294 pVM->hwaccm.s.fInitialized = true;
295
296 int rc = SUPCallVMMR0(pVM, VMMR0_HWACC_SETUP_VM, NULL);
297 AssertRC(rc);
298 if (rc == VINF_SUCCESS)
299 {
300 hwaccmr3DisableRawMode(pVM);
301
302 pVM->fHWACCMEnabled = true;
303 pVM->hwaccm.s.vmx.fEnabled = true;
304 LogRel(("HWACCM: VMX enabled!\n"));
305 }
306 else
307 {
308 LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
309 pVM->fHWACCMEnabled = false;
310 }
311 }
312 }
313 else
314 if (pVM->hwaccm.s.svm.fSupported)
315 {
316 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
317 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
318 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
319 LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
320 LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
321
322 if (pVM->hwaccm.s.fInitialized == false)
323 {
324 /* Only try once. */
325 pVM->hwaccm.s.fInitialized = true;
326
327 int rc = SUPCallVMMR0(pVM, VMMR0_HWACC_SETUP_VM, NULL);
328 AssertRC(rc);
329 if (rc == VINF_SUCCESS)
330 {
331#if 1
332 LogRel(("HWACCM: SVM supported; disabled currently\n"));
333#else
334 hwaccmr3DisableRawMode(pVM);
335
336 pVM->fHWACCMEnabled = true;
337 pVM->hwaccm.s.svm.fEnabled = true;
338#endif
339 }
340 else
341 {
342 pVM->fHWACCMEnabled = false;
343 }
344 }
345 }
346
347}
348
349
350/**
351 * Checks hardware accelerated raw mode is allowed.
352 *
353 * @returns boolean
354 * @param pVM The VM to operate on.
355 */
356HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
357{
358 return pVM->hwaccm.s.fAllowed;
359}
360
361
362/**
363 * Notification callback which is called whenever there is a chance that a CR3
364 * value might have changed.
365 * This is called by PGM.
366 *
367 * @param pVM The VM to operate on.
368 * @param enmShadowMode New paging mode.
369 */
370HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
371{
372 pVM->hwaccm.s.enmShadowMode = enmShadowMode;
373}
374
375/**
376 * Terminates the HWACCM.
377 *
378 * Termination means cleaning up and freeing all resources,
379 * the VM it self is at this point powered off or suspended.
380 *
381 * @returns VBox status code.
382 * @param pVM The VM to operate on.
383 */
384HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
385{
386 if (pVM->hwaccm.s.pStatExitReason)
387 {
388 MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
389 pVM->hwaccm.s.pStatExitReason = 0;
390 }
391
392 if (pVM->hwaccm.s.vmx.pVMXON)
393 {
394 SUPContFree(pVM->hwaccm.s.vmx.pVMXON);
395 pVM->hwaccm.s.vmx.pVMXON = 0;
396 }
397 if (pVM->hwaccm.s.vmx.pVMCS)
398 {
399 SUPContFree(pVM->hwaccm.s.vmx.pVMCS);
400 pVM->hwaccm.s.vmx.pVMCS = 0;
401 }
402 if (pVM->hwaccm.s.svm.pVMCBHost)
403 {
404 SUPContFree(pVM->hwaccm.s.svm.pVMCBHost);
405 pVM->hwaccm.s.svm.pVMCBHost = 0;
406 }
407 if (pVM->hwaccm.s.svm.pIOBitmap)
408 {
409 SUPContFree(pVM->hwaccm.s.svm.pIOBitmap);
410 pVM->hwaccm.s.svm.pIOBitmap = 0;
411 }
412 if (pVM->hwaccm.s.svm.pMSRBitmap)
413 {
414 SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap);
415 pVM->hwaccm.s.svm.pMSRBitmap = 0;
416 }
417 return 0;
418}
419
420
421/**
422 * The VM is being reset.
423 *
424 * For the HWACCM component this means that any GDT/LDT/TSS monitors
425 * needs to be removed.
426 *
427 * @param pVM VM handle.
428 */
429HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
430{
431 LogFlow(("HWACCMR3Reset:\n"));
432
433 if (pVM->fHWACCMEnabled)
434 hwaccmr3DisableRawMode(pVM);
435
436 /* On first entry we'll sync everything. */
437 pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
438
439 pVM->hwaccm.s.vmx.cr0_mask = 0;
440 pVM->hwaccm.s.vmx.cr4_mask = 0;
441}
442
443/**
444 * Checks if we can currently use hardware accelerated raw mode.
445 *
446 * @returns boolean
447 * @param pVM The VM to operate on.
448 * @param pCtx Partial VM execution context
449 */
450HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
451{
452 uint32_t mask;
453
454 Assert(pVM->fHWACCMEnabled);
455
456 /* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
457 * (but do we really care?)
458 */
459
460 pVM->hwaccm.s.fActive = false;
461
462 /** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
463
464 /* Too early for VMX and SVN (?). */
465 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
466 return false;
467
468 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
469 if (pCtx->csHid.Attr.n.u1Present == 0)
470 return false;
471 if (pCtx->ssHid.Attr.n.u1Present == 0)
472 return false;
473
474 /** @todo if we remove this check, then Windows XP install fails during the textmode phase */
475 if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
476 return false;
477
478 if (pVM->hwaccm.s.vmx.fEnabled)
479 {
480 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
481 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
482 /** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
483 mask &= ~X86_CR0_NE;
484
485 if ((pCtx->cr0 & mask) != mask)
486 return false;
487
488 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
489 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
490 if ((pCtx->cr0 & mask) != 0)
491 return false;
492
493 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
494 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
495 mask &= ~X86_CR4_VMXE;
496 if ((pCtx->cr4 & mask) != mask)
497 return false;
498
499 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
500 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
501 if ((pCtx->cr4 & mask) != 0)
502 return false;
503
504 pVM->hwaccm.s.fActive = true;
505 return true;
506 }
507 else
508 {
509 Assert(pVM->hwaccm.s.svm.fEnabled);
510
511 /* Let's start with protected mode with paging enabled first. */
512 if ((pCtx->cr0 & (X86_CR0_PE|X86_CR0_PG)) == (X86_CR0_PE|X86_CR0_PG))
513 {
514 pVM->hwaccm.s.fActive = true;
515 return true;
516 }
517 }
518
519 return false;
520}
521
522/**
523 * Checks if we are currently using hardware accelerated raw mode.
524 *
525 * @returns boolean
526 * @param pVM The VM to operate on.
527 */
528HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
529{
530 return pVM->hwaccm.s.fActive;
531}
532
533/**
534 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
535 *
536 * @returns boolean
537 * @param pVM The VM to operate on.
538 */
539HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
540{
541 return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
542}
543
544/**
545 * Execute state save operation.
546 *
547 * @returns VBox status code.
548 * @param pVM VM Handle.
549 * @param pSSM SSM operation handle.
550 */
551static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
552{
553 int rc;
554
555 Log(("hwaccmR3Save:\n"));
556
557 /*
558 * Save the basic bits - fortunately all the other things can be resynced on load.
559 */
560 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
561 AssertRCReturn(rc, rc);
562 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
563 AssertRCReturn(rc, rc);
564 rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
565 AssertRCReturn(rc, rc);
566
567 return VINF_SUCCESS;
568}
569
570
571/**
572 * Execute state load operation.
573 *
574 * @returns VBox status code.
575 * @param pVM VM Handle.
576 * @param pSSM SSM operation handle.
577 * @param u32Version Data layout version.
578 */
579static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
580{
581 int rc;
582
583 Log(("hwaccmR3Load:\n"));
584
585 /*
586 * Validate version.
587 */
588 if (u32Version != HWACCM_SSM_VERSION)
589 {
590 Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
591 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
592 }
593
594 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
595 AssertRCReturn(rc, rc);
596 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
597 AssertRCReturn(rc, rc);
598 rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
599 AssertRCReturn(rc, rc);
600
601 return VINF_SUCCESS;
602}
603
604
605
606
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette