HWACCM.cpp@ 400

Last change on this file since 400 was 397, checked in by vboxsync, 18 years ago
Completed most of VBOX_WITHOUT_IDT_PATCHING. (hope I didn't break anything...) TODO: IST support on AMD64.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 23.2 KB

Line
1	/* $Id: HWACCM.cpp 397 2007-01-28 02:34:06Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_HWACCM
26	#include <VBox/cpum.h>
27	#include <VBox/stam.h>
28	#include <VBox/mm.h>
29	#include <VBox/pdm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/trpm.h>
32	#include <VBox/dbgf.h>
33	#include <VBox/hwacc_vmx.h>
34	#include <VBox/hwacc_svm.h>
35	#include "HWACCMInternal.h"
36	#include <VBox/vm.h>
37	#include <VBox/err.h>
38	#include <VBox/param.h>
39	#include <VBox/patm.h>
40	#include <VBox/csam.h>
41	#include <VBox/selm.h>
42
43	#include <iprt/assert.h>
44	#include <VBox/log.h>
45	#include <iprt/asm.h>
46	#include <iprt/string.h>
47	#include <iprt/thread.h>
48	#include "x86context.h"
49
50
51	/*******************************************************************************
52	* Internal Functions *
53	*******************************************************************************/
54	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
55	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
56
57
58	/**
59	* Initializes the HWACCM.
60	*
61	* @returns VBox status code.
62	* @param pVM The VM to operate on.
63	*/
64	HWACCMR3DECL(int) HWACCMR3Init(PVM pVM)
65	{
66	LogFlow(("HWACCMR3Init\n"));
67
68	/*
69	* Assert alignment and sizes.
70	*/
71	AssertRelease(!(RT_OFFSETOF(VM, hwaccm.s) & 31));
72	AssertRelease(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
73
74	/* Some structure checks. */
75	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
76	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
77	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
78	AssertMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
79
80	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
81	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
82	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
83	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
84	AssertMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
85	AssertMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
86	AssertMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
87
88
89	/*
90	* Register the saved state data unit.
91	*/
92	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
93	NULL, hwaccmR3Save, NULL,
94	NULL, hwaccmR3Load, NULL);
95	if (VBOX_FAILURE(rc))
96	return rc;
97
98	/** @todo Make sure both pages are either not accessible or readonly! */
99	/* Allocate one page for VMXON. */
100	pVM->hwaccm.s.vmx.pVMXON = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMXONPhys);
101	if (pVM->hwaccm.s.vmx.pVMXON == 0)
102	{
103	AssertMsgFailed(("SUPContAlloc failed!!\n"));
104	return VERR_NO_MEMORY;
105	}
106	memset(pVM->hwaccm.s.vmx.pVMXON, 0, PAGE_SIZE);
107
108	/* Allocate one page for the VM control structure (VMCS). */
109	pVM->hwaccm.s.vmx.pVMCS = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.vmx.pVMCSPhys);
110	if (pVM->hwaccm.s.vmx.pVMCS == 0)
111	{
112	AssertMsgFailed(("SUPContAlloc failed!!\n"));
113	return VERR_NO_MEMORY;
114	}
115	memset(pVM->hwaccm.s.vmx.pVMCS, 0, PAGE_SIZE);
116
117	/* Reuse those two pages for AMD SVM. (one is active; never both) */
118	pVM->hwaccm.s.svm.pHState = pVM->hwaccm.s.vmx.pVMXON;
119	pVM->hwaccm.s.svm.pHStatePhys = pVM->hwaccm.s.vmx.pVMXONPhys;
120	pVM->hwaccm.s.svm.pVMCB = pVM->hwaccm.s.vmx.pVMCS;
121	pVM->hwaccm.s.svm.pVMCBPhys = pVM->hwaccm.s.vmx.pVMCSPhys;
122
123	/* Allocate one page for the SVM host control structure (used for vmsave/vmload). */
124	pVM->hwaccm.s.svm.pVMCBHost = SUPContAlloc(PAGE_SIZE, &pVM->hwaccm.s.svm.pVMCBHostPhys);
125	if (pVM->hwaccm.s.svm.pVMCBHost == 0)
126	{
127	AssertMsgFailed(("SUPContAlloc failed!!\n"));
128	return VERR_NO_MEMORY;
129	}
130	memset(pVM->hwaccm.s.svm.pVMCBHost, 0, PAGE_SIZE);
131
132	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
133	pVM->hwaccm.s.svm.pIOBitmap = SUPContAlloc(PAGE_SIZE*3, &pVM->hwaccm.s.svm.pIOBitmapPhys);
134	if (pVM->hwaccm.s.svm.pIOBitmap == 0)
135	{
136	AssertMsgFailed(("SUPContAlloc failed!!\n"));
137	return VERR_NO_MEMORY;
138	}
139	/* Set all bits to intercept all IO accesses. */
140	memset(pVM->hwaccm.s.svm.pIOBitmap, 0xff, PAGE_SIZE*3);
141
142	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
143	pVM->hwaccm.s.svm.pMSRBitmap = SUPContAlloc(PAGE_SIZE*2, &pVM->hwaccm.s.svm.pMSRBitmapPhys);
144	if (pVM->hwaccm.s.svm.pMSRBitmap == 0)
145	{
146	AssertMsgFailed(("SUPContAlloc failed!!\n"));
147	return VERR_NO_MEMORY;
148	}
149	/* Set all bits to intercept all MSR accesses. */
150	memset(pVM->hwaccm.s.svm.pMSRBitmap, 0xff, PAGE_SIZE*2);
151
152	/* Misc initialisation. */
153	pVM->hwaccm.s.vmx.fSupported = false;
154	pVM->hwaccm.s.svm.fSupported = false;
155	pVM->hwaccm.s.vmx.fEnabled = false;
156	pVM->hwaccm.s.svm.fEnabled = false;
157
158	pVM->hwaccm.s.fActive = false;
159
160	/* On first entry we'll sync everything. */
161	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
162
163	pVM->hwaccm.s.vmx.cr0_mask = 0;
164	pVM->hwaccm.s.vmx.cr4_mask = 0;
165
166	/*
167	* Statistics.
168	*/
169	STAM_REG(pVM, &pVM->hwaccm.s.StatEntry, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchToGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry");
170	STAM_REG(pVM, &pVM->hwaccm.s.StatExit, STAMTYPE_PROFILE, "/PROF/HWACCM/SwitchFromGC", STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit");
171	STAM_REG(pVM, &pVM->hwaccm.s.StatInGC, STAMTYPE_PROFILE, "/PROF/HWACCM/InGC", STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch");
172
173	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
174	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNM, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NM", STAMUNIT_OCCURENCES, "Nr of occurances");
175	STAM_REG(pVM, &pVM->hwaccm.s.StatExitShadowPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Shadow/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
176	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestPF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#PF", STAMUNIT_OCCURENCES, "Nr of occurances");
177	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestUD, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#UD", STAMUNIT_OCCURENCES, "Nr of occurances");
178	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestSS, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#SS", STAMUNIT_OCCURENCES, "Nr of occurances");
179	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestNP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#NP", STAMUNIT_OCCURENCES, "Nr of occurances");
180	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestGP, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#GP", STAMUNIT_OCCURENCES, "Nr of occurances");
181	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestMF, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#MF", STAMUNIT_OCCURENCES, "Nr of occurances");
182	STAM_REG(pVM, &pVM->hwaccm.s.StatExitGuestDE, STAMTYPE_COUNTER, "/HWACCM/Exit/Trap/Guest/#DE", STAMUNIT_OCCURENCES, "Nr of occurances");
183	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvpg, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invlpg", STAMUNIT_OCCURENCES, "Nr of occurances");
184	STAM_REG(pVM, &pVM->hwaccm.s.StatExitInvd, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Invd", STAMUNIT_OCCURENCES, "Nr of occurances");
185	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCpuid, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/Cpuid", STAMUNIT_OCCURENCES, "Nr of occurances");
186	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
187	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
188	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
189	STAM_REG(pVM, &pVM->hwaccm.s.StatExitDRxRead, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/DRx/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
190	STAM_REG(pVM, &pVM->hwaccm.s.StatExitCLTS, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/CLTS", STAMUNIT_OCCURENCES, "Nr of occurances");
191	STAM_REG(pVM, &pVM->hwaccm.s.StatExitLMSW, STAMTYPE_COUNTER, "/HWACCM/Exit/Instr/LMSW", STAMUNIT_OCCURENCES, "Nr of occurances");
192	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIOWrite, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Write", STAMUNIT_OCCURENCES, "Nr of occurances");
193	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIORead, STAMTYPE_COUNTER, "/HWACCM/Exit/IO/Read", STAMUNIT_OCCURENCES, "Nr of occurances");
194	STAM_REG(pVM, &pVM->hwaccm.s.StatExitIrqWindow, STAMTYPE_COUNTER, "/HWACCM/Exit/GuestIrq/Pending", STAMUNIT_OCCURENCES, "Nr of occurances");
195
196	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchGuestIrq,STAMTYPE_COUNTER, "/HWACCM/Switch/IrqPending", STAMUNIT_OCCURENCES, "Nr of occurances");
197	STAM_REG(pVM, &pVM->hwaccm.s.StatSwitchToR3, STAMTYPE_COUNTER, "/HWACCM/Switch/ToR3", STAMUNIT_OCCURENCES, "Nr of occurances");
198
199	STAM_REG(pVM, &pVM->hwaccm.s.StatIntInject, STAMTYPE_COUNTER, "/HWACCM/Irq/Inject", STAMUNIT_OCCURENCES, "Nr of occurances");
200	STAM_REG(pVM, &pVM->hwaccm.s.StatIntReinject, STAMTYPE_COUNTER, "/HWACCM/Irq/Reinject", STAMUNIT_OCCURENCES, "Nr of occurances");
201	STAM_REG(pVM, &pVM->hwaccm.s.StatPendingHostIrq,STAMTYPE_COUNTER, "/HWACCM/Irq/PendingOnHost", STAMUNIT_OCCURENCES, "Nr of occurances");
202
203	pVM->hwaccm.s.pStatExitReason = 0;
204
205	#ifdef VBOX_WITH_STATISTICS
206	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVM->hwaccm.s.pStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVM->hwaccm.s.pStatExitReason);
207	AssertRC(rc);
208	if (VBOX_SUCCESS(rc))
209	{
210	for (int i=0;i<MAX_EXITREASON_STAT;i++)
211	{
212	char szName[64];
213	RTStrPrintf(szName, sizeof(szName), "/HWACCM/Exit/Reason/%02x", i);
214	int rc = STAMR3Register(pVM, &pVM->hwaccm.s.pStatExitReason[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "Exit reason");
215	AssertRC(rc);
216	}
217	}
218	#endif
219
220	/* Disabled by default. */
221	pVM->fHWACCMEnabled = false;
222
223	/* HWACCM support must be explicitely enabled in the configuration file. */
224	pVM->hwaccm.s.fAllowed = false;
225	CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWVirtExt/"), "Enabled", &pVM->hwaccm.s.fAllowed);
226
227	return VINF_SUCCESS;
228	}
229
230
231	/**
232	* Turns off normal raw mode features
233	*
234	* @param pVM The VM to operate on.
235	*/
236	static void hwaccmr3DisableRawMode(PVM pVM)
237	{
238	/* Disable PATM & CSAM. */
239	PATMR3AllowPatching(pVM, false);
240	CSAMDisableScanning(pVM);
241
242	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
243	SELMR3DisableMonitoring(pVM);
244	TRPMR3DisableMonitoring(pVM);
245
246	/* The hidden selector registers are now valid. */
247	CPUMSetHiddenSelRegsValid(pVM, true);
248
249	/* Disable the switcher code (safety precaution). */
250	VMMR3DisableSwitcher(pVM);
251
252	/* Disable mapping of the hypervisor into the shadow page table. */
253	PGMR3RemoveMappingsFromShwPD(pVM);
254	}
255
256	/**
257	* Applies relocations to data and code managed by this
258	* component. This function will be called at init and
259	* whenever the VMM need to relocate it self inside the GC.
260	*
261	* @param pVM The VM.
262	*/
263	HWACCMR3DECL(void) HWACCMR3Relocate(PVM pVM)
264	{
265	#ifdef LOG_ENABLED
266	Log(("HWACCMR3Relocate to %VGv\n", MMHyperGetArea(pVM, 0)));
267	#endif
268
269	if (pVM->hwaccm.s.fAllowed == false)
270	return ;
271
272	if (pVM->hwaccm.s.vmx.fSupported)
273	{
274	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
275	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
276	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %VX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
277	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
278	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls));
279	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls));
280	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit));
281	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry));
282	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
283	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
284	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
285	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
286	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
287	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %VX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
288
289	if (pVM->hwaccm.s.fInitialized == false && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
290	{
291	/* Only try once. */
292	pVM->hwaccm.s.fInitialized = true;
293
294	int rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_SETUP_VM, NULL);
295	AssertRC(rc);
296	if (rc == VINF_SUCCESS)
297	{
298	hwaccmr3DisableRawMode(pVM);
299
300	pVM->fHWACCMEnabled = true;
301	pVM->hwaccm.s.vmx.fEnabled = true;
302	LogRel(("HWACCM: VMX enabled!\n"));
303	}
304	else
305	{
306	LogRel(("HWACCM: VMX setup failed with rc=%Vrc!\n", rc));
307	pVM->fHWACCMEnabled = false;
308	}
309	}
310	}
311	else
312	if (pVM->hwaccm.s.svm.fSupported)
313	{
314	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
315	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
316	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %VX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
317	LogRel(("HWACCM: SVM revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
318	LogRel(("HWACCM: SVM max ASID = %d\n", pVM->hwaccm.s.svm.u32MaxASID));
319
320	if (pVM->hwaccm.s.fInitialized == false)
321	{
322	/* Only try once. */
323	pVM->hwaccm.s.fInitialized = true;
324
325	int rc = SUPCallVMMR0(pVM, VMMR0_DO_HWACC_SETUP_VM, NULL);
326	AssertRC(rc);
327	if (rc == VINF_SUCCESS)
328	{
329	#if 1
330	LogRel(("HWACCM: SVM supported; disabled currently\n"));
331	#else
332	hwaccmr3DisableRawMode(pVM);
333
334	pVM->fHWACCMEnabled = true;
335	pVM->hwaccm.s.svm.fEnabled = true;
336	#endif
337	}
338	else
339	{
340	pVM->fHWACCMEnabled = false;
341	}
342	}
343	}
344
345	}
346
347
348	/**
349	* Checks hardware accelerated raw mode is allowed.
350	*
351	* @returns boolean
352	* @param pVM The VM to operate on.
353	*/
354	HWACCMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
355	{
356	return pVM->hwaccm.s.fAllowed;
357	}
358
359
360	/**
361	* Notification callback which is called whenever there is a chance that a CR3
362	* value might have changed.
363	* This is called by PGM.
364	*
365	* @param pVM The VM to operate on.
366	* @param enmShadowMode New paging mode.
367	*/
368	HWACCMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PGMMODE enmShadowMode)
369	{
370	pVM->hwaccm.s.enmShadowMode = enmShadowMode;
371	}
372
373	/**
374	* Terminates the HWACCM.
375	*
376	* Termination means cleaning up and freeing all resources,
377	* the VM it self is at this point powered off or suspended.
378	*
379	* @returns VBox status code.
380	* @param pVM The VM to operate on.
381	*/
382	HWACCMR3DECL(int) HWACCMR3Term(PVM pVM)
383	{
384	if (pVM->hwaccm.s.pStatExitReason)
385	{
386	MMHyperFree(pVM, pVM->hwaccm.s.pStatExitReason);
387	pVM->hwaccm.s.pStatExitReason = 0;
388	}
389
390	if (pVM->hwaccm.s.vmx.pVMXON)
391	{
392	SUPContFree(pVM->hwaccm.s.vmx.pVMXON);
393	pVM->hwaccm.s.vmx.pVMXON = 0;
394	}
395	if (pVM->hwaccm.s.vmx.pVMCS)
396	{
397	SUPContFree(pVM->hwaccm.s.vmx.pVMCS);
398	pVM->hwaccm.s.vmx.pVMCS = 0;
399	}
400	if (pVM->hwaccm.s.svm.pVMCBHost)
401	{
402	SUPContFree(pVM->hwaccm.s.svm.pVMCBHost);
403	pVM->hwaccm.s.svm.pVMCBHost = 0;
404	}
405	if (pVM->hwaccm.s.svm.pIOBitmap)
406	{
407	SUPContFree(pVM->hwaccm.s.svm.pIOBitmap);
408	pVM->hwaccm.s.svm.pIOBitmap = 0;
409	}
410	if (pVM->hwaccm.s.svm.pMSRBitmap)
411	{
412	SUPContFree(pVM->hwaccm.s.svm.pMSRBitmap);
413	pVM->hwaccm.s.svm.pMSRBitmap = 0;
414	}
415	return 0;
416	}
417
418
419	/**
420	* The VM is being reset.
421	*
422	* For the HWACCM component this means that any GDT/LDT/TSS monitors
423	* needs to be removed.
424	*
425	* @param pVM VM handle.
426	*/
427	HWACCMR3DECL(void) HWACCMR3Reset(PVM pVM)
428	{
429	LogFlow(("HWACCMR3Reset:\n"));
430
431	if (pVM->fHWACCMEnabled)
432	hwaccmr3DisableRawMode(pVM);
433
434	/* On first entry we'll sync everything. */
435	pVM->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
436
437	pVM->hwaccm.s.vmx.cr0_mask = 0;
438	pVM->hwaccm.s.vmx.cr4_mask = 0;
439	}
440
441	/**
442	* Checks if we can currently use hardware accelerated raw mode.
443	*
444	* @returns boolean
445	* @param pVM The VM to operate on.
446	* @param pCtx Partial VM execution context
447	*/
448	HWACCMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
449	{
450	uint32_t mask;
451
452	Assert(pVM->fHWACCMEnabled);
453
454	/* @todo we can support real-mode by using v86 and protected mode without paging with identity mapped pages.
455	* (but do we really care?)
456	*/
457
458	pVM->hwaccm.s.fActive = false;
459
460	/** @note The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
461
462	/* Too early for VMX and SVN (?). */
463	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
464	return false;
465
466	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
467	if (pCtx->csHid.Attr.n.u1Present == 0)
468	return false;
469	if (pCtx->ssHid.Attr.n.u1Present == 0)
470	return false;
471
472	/** @todo if we remove this check, then Windows XP install fails during the textmode phase */
473	if (!(pCtx->cr0 & X86_CR0_WRITE_PROTECT))
474	return false;
475
476	if (pVM->hwaccm.s.vmx.fEnabled)
477	{
478	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
479	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
480	/** @note We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
481	mask &= ~X86_CR0_NE;
482
483	if ((pCtx->cr0 & mask) != mask)
484	return false;
485
486	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
487	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
488	if ((pCtx->cr0 & mask) != 0)
489	return false;
490
491	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
492	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
493	mask &= ~X86_CR4_VMXE;
494	if ((pCtx->cr4 & mask) != mask)
495	return false;
496
497	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
498	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
499	if ((pCtx->cr4 & mask) != 0)
500	return false;
501
502	pVM->hwaccm.s.fActive = true;
503	return true;
504	}
505	else
506	{
507	Assert(pVM->hwaccm.s.svm.fEnabled);
508
509	/* Let's start with protected mode with paging enabled first. */
510	if ((pCtx->cr0 & (X86_CR0_PE\|X86_CR0_PG)) == (X86_CR0_PE\|X86_CR0_PG))
511	{
512	pVM->hwaccm.s.fActive = true;
513	return true;
514	}
515	}
516
517	return false;
518	}
519
520	/**
521	* Checks if we are currently using hardware accelerated raw mode.
522	*
523	* @returns boolean
524	* @param pVM The VM to operate on.
525	*/
526	HWACCMR3DECL(bool) HWACCMR3IsActive(PVM pVM)
527	{
528	return pVM->hwaccm.s.fActive;
529	}
530
531	/**
532	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
533	*
534	* @returns boolean
535	* @param pVM The VM to operate on.
536	*/
537	HWACCMR3DECL(bool) HWACCMR3IsEventPending(PVM pVM)
538	{
539	return HWACCMIsEnabled(pVM) && pVM->hwaccm.s.Event.fPending;
540	}
541
542	/**
543	* Execute state save operation.
544	*
545	* @returns VBox status code.
546	* @param pVM VM Handle.
547	* @param pSSM SSM operation handle.
548	*/
549	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
550	{
551	int rc;
552
553	Log(("hwaccmR3Save:\n"));
554
555	/*
556	* Save the basic bits - fortunately all the other things can be resynced on load.
557	*/
558	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.fPending);
559	AssertRCReturn(rc, rc);
560	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.Event.errCode);
561	AssertRCReturn(rc, rc);
562	rc = SSMR3PutU64(pSSM, pVM->hwaccm.s.Event.intInfo);
563	AssertRCReturn(rc, rc);
564
565	return VINF_SUCCESS;
566	}
567
568
569	/**
570	* Execute state load operation.
571	*
572	* @returns VBox status code.
573	* @param pVM VM Handle.
574	* @param pSSM SSM operation handle.
575	* @param u32Version Data layout version.
576	*/
577	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
578	{
579	int rc;
580
581	Log(("hwaccmR3Load:\n"));
582
583	/*
584	* Validate version.
585	*/
586	if (u32Version != HWACCM_SSM_VERSION)
587	{
588	Log(("hwaccmR3Load: Invalid version u32Version=%d!\n", u32Version));
589	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
590	}
591
592	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.fPending);
593	AssertRCReturn(rc, rc);
594	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.Event.errCode);
595	AssertRCReturn(rc, rc);
596	rc = SSMR3GetU64(pSSM, &pVM->hwaccm.s.Event.intInfo);
597	AssertRCReturn(rc, rc);
598
599	return VINF_SUCCESS;
600	}
601
602
603
604

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source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 400

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