VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCM.cpp@ 26550

Last change on this file since 26550 was 26176, checked in by vboxsync, 15 years ago

VBox/err.h,*: Use RT_SUCCESS/FAILURE instead of the VBOX variants, removing the latter.
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File size: 129.3 KB
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1/* $Id: HWACCM.cpp 26176 2010-02-02 22:20:13Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_HWACCM
26#include <VBox/cpum.h>
27#include <VBox/stam.h>
28#include <VBox/mm.h>
29#include <VBox/pdmapi.h>
30#include <VBox/pgm.h>
31#include <VBox/ssm.h>
32#include <VBox/trpm.h>
33#include <VBox/dbgf.h>
34#include <VBox/iom.h>
35#include <VBox/patm.h>
36#include <VBox/csam.h>
37#include <VBox/selm.h>
38#include <VBox/rem.h>
39#include <VBox/hwacc_vmx.h>
40#include <VBox/hwacc_svm.h>
41#include "HWACCMInternal.h"
42#include <VBox/vm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON_NIL(),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL()
119};
120/** Exit reason descriptions for AMD-V, used to describe statistics. */
121static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
122{
123 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
124 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
125 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
126 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
127 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
128 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
129 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
130 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
131 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
132 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
133 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
134 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
135 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
136 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
137 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
138 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
155 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
156 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
157 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
158 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
159 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
160 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
161 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
162 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
163 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
164 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
165 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
166 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
167 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
168 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
169 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
170 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_INTR , 96, "Physical maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_NMI , 97, "Physical non-maskable interrupt."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_SMI , 98, "System management interrupt."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_INIT , 99, "Physical INIT signal."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_VINTR ,100, "Visual interrupt."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_IDTR_READ ,102, "Read IDTR"),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_GDTR_READ ,103, "Read GDTR"),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_LDTR_READ ,104, "Read LDTR."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,105, "Read TR."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,106, "Write IDTR."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,107, "Write GDTR."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,108, "Write LDTR."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_TR_READ ,109, "Write TR."),
233 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
234 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
235 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
236 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
237 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
238 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
239 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
240 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
241 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
242 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
243 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
245 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
246 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
247 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
248 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
249 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
250 EXIT_REASON(SVM_EXIT_TASK_SHUTDOWN ,127, "Shutdown."),
251 EXIT_REASON(SVM_EXIT_TASK_VMRUN ,128, "VMRUN instruction."),
252 EXIT_REASON(SVM_EXIT_TASK_VMCALL ,129, "VMCALL instruction."),
253 EXIT_REASON(SVM_EXIT_TASK_VMLOAD ,130, "VMLOAD instruction."),
254 EXIT_REASON(SVM_EXIT_TASK_VMSAVE ,131, "VMSAVE instruction."),
255 EXIT_REASON(SVM_EXIT_TASK_STGI ,132, "STGI instruction."),
256 EXIT_REASON(SVM_EXIT_TASK_CLGI ,133, "CLGI instruction."),
257 EXIT_REASON(SVM_EXIT_TASK_SKINIT ,134, "SKINIT instruction."),
258 EXIT_REASON(SVM_EXIT_TASK_RDTSCP ,135, "RDTSCP instruction."),
259 EXIT_REASON(SVM_EXIT_TASK_ICEBP ,136, "ICEBP instruction."),
260 EXIT_REASON(SVM_EXIT_TASK_WBINVD ,137, "WBINVD instruction."),
261 EXIT_REASON(SVM_EXIT_TASK_MONITOR ,138, "MONITOR instruction."),
262 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
263 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
264 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
265 EXIT_REASON_NIL()
266};
267# undef EXIT_REASON
268# undef EXIT_REASON_NIL
269#endif /* VBOX_WITH_STATISTICS */
270
271/*******************************************************************************
272* Internal Functions *
273*******************************************************************************/
274static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
275static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
276
277
278/**
279 * Initializes the HWACCM.
280 *
281 * @returns VBox status code.
282 * @param pVM The VM to operate on.
283 */
284VMMR3DECL(int) HWACCMR3Init(PVM pVM)
285{
286 LogFlow(("HWACCMR3Init\n"));
287
288 /*
289 * Assert alignment and sizes.
290 */
291 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
292 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
293
294 /* Some structure checks. */
295 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved3) == 0xC0, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved3)));
296 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
299
300 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4) == 0x4A0, ("guest.u8Reserved4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved4)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6) == 0x4D8, ("guest.u8Reserved6 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved6)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7) == 0x580, ("guest.u8Reserved7 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved7)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9) == 0x648, ("guest.u8Reserved9 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8Reserved9)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, u8Reserved10) == 0x698, ("u8Reserved3 offset = %x\n", RT_OFFSETOF(SVM_VMCB, u8Reserved10)));
306 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
307
308
309 /*
310 * Register the saved state data unit.
311 */
312 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
313 NULL, NULL, NULL,
314 NULL, hwaccmR3Save, NULL,
315 NULL, hwaccmR3Load, NULL);
316 if (RT_FAILURE(rc))
317 return rc;
318
319 /* Misc initialisation. */
320 pVM->hwaccm.s.vmx.fSupported = false;
321 pVM->hwaccm.s.svm.fSupported = false;
322 pVM->hwaccm.s.vmx.fEnabled = false;
323 pVM->hwaccm.s.svm.fEnabled = false;
324
325 pVM->hwaccm.s.fNestedPaging = false;
326
327 /* Disabled by default. */
328 pVM->fHWACCMEnabled = false;
329
330 /*
331 * Check CFGM options.
332 */
333 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
334 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
335 /* Nested paging: disabled by default. */
336 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
337 AssertRC(rc);
338
339 /* VT-x VPID: disabled by default. */
340 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
341 AssertRC(rc);
342
343 /* HWACCM support must be explicitely enabled in the configuration file. */
344 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
345 AssertRC(rc);
346
347 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
348 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
349 AssertRC(rc);
350
351#ifdef RT_OS_DARWIN
352 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
353#else
354 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
355#endif
356 {
357 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
358 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
359 return VERR_HWACCM_CONFIG_MISMATCH;
360 }
361
362 if (VMMIsHwVirtExtForced(pVM))
363 pVM->fHWACCMEnabled = true;
364
365#if HC_ARCH_BITS == 32
366 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
367 * (To use the default, don't set 64bitEnabled in CFGM.) */
368 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
369 AssertLogRelRCReturn(rc, rc);
370 if (pVM->hwaccm.s.fAllow64BitGuests)
371 {
372# ifdef RT_OS_DARWIN
373 if (!VMMIsHwVirtExtForced(pVM))
374# else
375 if (!pVM->hwaccm.s.fAllowed)
376# endif
377 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
378 }
379#else
380 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
381 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
382 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
383 AssertLogRelRCReturn(rc, rc);
384#endif
385
386
387 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
388 * or local init each time we wish to execute guest code.
389 *
390 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
391 */
392 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
393#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
394 false
395#else
396 true
397#endif
398 );
399
400 /* Max number of resume loops. */
401 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
402 AssertRC(rc);
403
404 return VINF_SUCCESS;
405}
406
407/**
408 * Initializes the per-VCPU HWACCM.
409 *
410 * @returns VBox status code.
411 * @param pVM The VM to operate on.
412 */
413VMMR3DECL(int) HWACCMR3InitCPU(PVM pVM)
414{
415 LogFlow(("HWACCMR3InitCPU\n"));
416
417 for (VMCPUID i = 0; i < pVM->cCpus; i++)
418 {
419 PVMCPU pVCpu = &pVM->aCpus[i];
420
421 pVCpu->hwaccm.s.fActive = false;
422 }
423
424#ifdef VBOX_WITH_STATISTICS
425 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
426 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
427 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
428 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
429
430 /*
431 * Statistics.
432 */
433 for (VMCPUID i = 0; i < pVM->cCpus; i++)
434 {
435 PVMCPU pVCpu = &pVM->aCpus[i];
436 int rc;
437
438 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
439 "/PROF/HWACCM/CPU%d/Poke", i);
440 AssertRC(rc);
441 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
442 "/PROF/HWACCM/CPU%d/PokeWait", i);
443 AssertRC(rc);
444 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
445 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
446 AssertRC(rc);
447 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
448 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
449 AssertRC(rc);
450 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
451 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
452 AssertRC(rc);
453 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
454 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
455 AssertRC(rc);
456# if 1 /* temporary for tracking down darwin holdup. */
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
458 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
461 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
464 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
465 AssertRC(rc);
466# endif
467 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
468 "/PROF/HWACCM/CPU%d/InGC", i);
469 AssertRC(rc);
470
471# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
472 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
473 "/PROF/HWACCM/CPU%d/Switcher3264", i);
474 AssertRC(rc);
475# endif
476
477# define HWACCM_REG_COUNTER(a, b) \
478 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
479 AssertRC(rc);
480
481 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
482 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
483 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
484 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
485 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
486 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
487 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
488 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
489 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
490 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
518
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
521
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
525
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
529 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
532 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
536 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
539
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
543
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
547
548 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
549 {
550 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
551 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
552 AssertRC(rc);
553 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
554 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
555 AssertRC(rc);
556 }
557
558#undef HWACCM_REG_COUNTER
559
560 pVCpu->hwaccm.s.paStatExitReason = NULL;
561
562 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
563 AssertRC(rc);
564 if (RT_SUCCESS(rc))
565 {
566 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
567 for (int j=0;j<MAX_EXITREASON_STAT;j++)
568 {
569 if (papszDesc[j])
570 {
571 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
572 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
573 AssertRC(rc);
574 }
575 }
576 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
577 AssertRC(rc);
578 }
579 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
580# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
581 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
582# else
583 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
584# endif
585
586 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
587 AssertRCReturn(rc, rc);
588 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
589# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
590 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
591# else
592 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
593# endif
594 for (unsigned j = 0; j < 255; j++)
595 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
596 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
597
598 }
599#endif /* VBOX_WITH_STATISTICS */
600
601#ifdef VBOX_WITH_CRASHDUMP_MAGIC
602 /* Magic marker for searching in crash dumps. */
603 for (VMCPUID i = 0; i < pVM->cCpus; i++)
604 {
605 PVMCPU pVCpu = &pVM->aCpus[i];
606
607 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
608 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
609 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
610 }
611#endif
612 return VINF_SUCCESS;
613}
614
615/**
616 * Turns off normal raw mode features
617 *
618 * @param pVM The VM to operate on.
619 */
620static void hwaccmR3DisableRawMode(PVM pVM)
621{
622 /* Disable PATM & CSAM. */
623 PATMR3AllowPatching(pVM, false);
624 CSAMDisableScanning(pVM);
625
626 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
627 SELMR3DisableMonitoring(pVM);
628 TRPMR3DisableMonitoring(pVM);
629
630 /* Disable the switcher code (safety precaution). */
631 VMMR3DisableSwitcher(pVM);
632
633 /* Disable mapping of the hypervisor into the shadow page table. */
634 PGMR3MappingsDisable(pVM);
635
636 /* Disable the switcher */
637 VMMR3DisableSwitcher(pVM);
638
639 /* Reinit the paging mode to force the new shadow mode. */
640 for (VMCPUID i = 0; i < pVM->cCpus; i++)
641 {
642 PVMCPU pVCpu = &pVM->aCpus[i];
643
644 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
645 }
646}
647
648/**
649 * Initialize VT-x or AMD-V.
650 *
651 * @returns VBox status code.
652 * @param pVM The VM handle.
653 */
654VMMR3DECL(int) HWACCMR3InitFinalizeR0(PVM pVM)
655{
656 int rc;
657
658 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
659 * is already using AMD-V.
660 */
661 if ( !pVM->hwaccm.s.vmx.fSupported
662 && !pVM->hwaccm.s.svm.fSupported
663 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
664 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
665 {
666 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
667 pVM->hwaccm.s.svm.fSupported = true;
668 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
669 }
670 else
671 if ( !pVM->hwaccm.s.vmx.fSupported
672 && !pVM->hwaccm.s.svm.fSupported)
673 {
674 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
675 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
676
677 if (VMMIsHwVirtExtForced(pVM))
678 {
679 switch (pVM->hwaccm.s.lLastError)
680 {
681 case VERR_VMX_NO_VMX:
682 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
683 case VERR_VMX_IN_VMX_ROOT_MODE:
684 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
685 case VERR_SVM_IN_USE:
686 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
687 case VERR_SVM_NO_SVM:
688 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
689 case VERR_SVM_DISABLED:
690 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
691 default:
692 return pVM->hwaccm.s.lLastError;
693 }
694 }
695 return VINF_SUCCESS;
696 }
697
698 if (pVM->hwaccm.s.vmx.fSupported)
699 {
700 rc = SUPR3QueryVTxSupported();
701 if (RT_FAILURE(rc))
702 {
703#ifdef RT_OS_LINUX
704 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
705#else
706 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
707#endif
708 if ( pVM->cCpus > 1
709 || VMMIsHwVirtExtForced(pVM))
710 return rc;
711
712 /* silently fall back to raw mode */
713 return VINF_SUCCESS;
714 }
715 }
716
717 if (!pVM->hwaccm.s.fAllowed)
718 return VINF_SUCCESS; /* nothing to do */
719
720 /* Enable VT-x or AMD-V on all host CPUs. */
721 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
722 if (RT_FAILURE(rc))
723 {
724 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
725 return rc;
726 }
727 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
728
729 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
730 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
731 if (!pVM->hwaccm.s.fHasIoApic)
732 {
733 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
734 pVM->hwaccm.s.fTRPPatchingAllowed = false;
735 }
736
737 if (pVM->hwaccm.s.vmx.fSupported)
738 {
739 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
740
741 if ( pVM->hwaccm.s.fInitialized == false
742 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
743 {
744 uint64_t val;
745 RTGCPHYS GCPhys = 0;
746
747 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
748 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
749 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
750 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
751 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
752 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
753 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
754 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
755
756 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
757 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
758 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
759 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
760 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
761 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
762 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
763 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
764 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
765 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
766 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
767 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
768 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
769 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
770 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
771 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
772 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
773 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
774 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
775
776 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
777 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
778 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
779 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
780 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
781 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
782 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
783 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
784 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
785 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
786 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
787 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
788 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
789 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
790 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
791 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
792 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
793 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
794 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
795 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
796 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
797 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
798 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
800 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
802 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
804 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
806 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
807 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
808 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
809 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
810 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
811 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
812 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
813 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
814 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
815 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
816 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
817 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
818 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
820
821 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
822 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
826 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
832 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
861 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
864
865 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
866 {
867 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
868 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
869 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
870 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
872 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
874 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
876 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
877 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
878 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
879 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
880 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
882 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
884 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
886 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
887
888 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
889 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
890 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
892 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
894 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
896 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
898 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
900 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
902 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
904 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
906 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
907 }
908
909 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
910 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
911 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
913 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
915 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
917 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
919 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
920 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
921 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
922 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
923 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
924 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
925 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
926 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
927 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
928 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
929 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
930 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
931 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
932 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
933 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
935 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
937 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
938 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
939 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
940
941 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
942 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
943 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
945 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
947 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
948 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
949 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
950 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
951 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
953 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
955 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
957 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
959 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
960 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
961 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
962 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
963 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
964 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
965 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
966 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
968 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
970 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
972 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
976
977 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
978 {
979 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
980
981 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
982 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
983 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
984 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
985 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
986 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
987 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
988 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
989 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
990 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
991 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
992 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
993 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
994 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
995 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
996 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
997 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
998 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
999 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1000 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1001 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1002 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1003 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1004 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1005 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1006 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1007 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1008 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1009 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1010 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1011 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1012 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1013 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1014 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1015 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1016 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1018 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1019 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1020 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1031 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1032 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1033 }
1034
1035 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1036 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1037 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1038 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1039 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1040 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1041
1042 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1043 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1044 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1045 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1046 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1047
1048 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1049
1050 /* Paranoia */
1051 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1052
1053 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1054 {
1055 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1056 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
1057 }
1058
1059#ifdef HWACCM_VTX_WITH_EPT
1060 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1061 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1062#endif /* HWACCM_VTX_WITH_EPT */
1063#ifdef HWACCM_VTX_WITH_VPID
1064 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1065 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1066 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1067#endif /* HWACCM_VTX_WITH_VPID */
1068
1069 /* Unrestricted guest execution relies on EPT. */
1070 if ( pVM->hwaccm.s.fNestedPaging
1071 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1072 {
1073 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1074 }
1075
1076 /* Only try once. */
1077 pVM->hwaccm.s.fInitialized = true;
1078
1079 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1080 {
1081 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1082 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1083 if (RT_SUCCESS(rc))
1084 {
1085 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1086 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1087 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1088 /* Bit set to 0 means redirection enabled. */
1089 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1090 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1091 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1092 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1093
1094 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1095 * real and protected mode without paging with EPT.
1096 */
1097 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1098 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1099 {
1100 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1101 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1102 }
1103
1104 /* We convert it here every time as pci regions could be reconfigured. */
1105 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1106 AssertRC(rc);
1107 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1108
1109 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1110 AssertRC(rc);
1111 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1112 }
1113 else
1114 {
1115 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1116 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1117 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1118 }
1119 }
1120
1121 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1122 AssertRC(rc);
1123 if (rc == VINF_SUCCESS)
1124 {
1125 pVM->fHWACCMEnabled = true;
1126 pVM->hwaccm.s.vmx.fEnabled = true;
1127 hwaccmR3DisableRawMode(pVM);
1128
1129 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1130#ifdef VBOX_ENABLE_64_BITS_GUESTS
1131 if (pVM->hwaccm.s.fAllow64BitGuests)
1132 {
1133 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1134 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1135 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1136 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1137 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1138 }
1139 else
1140 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1141 /* Todo: this needs to be fixed properly!! */
1142 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1143 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1144 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1145
1146 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1147 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1148 : "HWACCM: 32-bit guests supported.\n"));
1149#else
1150 LogRel(("HWACCM: 32-bit guests supported.\n"));
1151#endif
1152 LogRel(("HWACCM: VMX enabled!\n"));
1153 if (pVM->hwaccm.s.fNestedPaging)
1154 {
1155 LogRel(("HWACCM: Enabled nested paging\n"));
1156 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1157 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1158 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1159 }
1160 else
1161 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1162
1163 if (pVM->hwaccm.s.vmx.fVPID)
1164 LogRel(("HWACCM: Enabled VPID\n"));
1165
1166 if ( pVM->hwaccm.s.fNestedPaging
1167 || pVM->hwaccm.s.vmx.fVPID)
1168 {
1169 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1170 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1171 }
1172
1173 /* TPR patching status logging. */
1174 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1175 {
1176 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1177 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1178 {
1179 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1180 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1181 }
1182 else
1183 {
1184 uint32_t u32Eax, u32Dummy;
1185
1186 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1187 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1188 if ( u32Eax < 0x80000001
1189 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1190 {
1191 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1192 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1193 }
1194 }
1195 }
1196 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1197 }
1198 else
1199 {
1200 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1201 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1202 pVM->fHWACCMEnabled = false;
1203 }
1204 }
1205 }
1206 else
1207 if (pVM->hwaccm.s.svm.fSupported)
1208 {
1209 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1210
1211 if (pVM->hwaccm.s.fInitialized == false)
1212 {
1213 /* Erratum 170 which requires a forced TLB flush for each world switch:
1214 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1215 *
1216 * All BH-G1/2 and DH-G1/2 models include a fix:
1217 * Athlon X2: 0x6b 1/2
1218 * 0x68 1/2
1219 * Athlon 64: 0x7f 1
1220 * 0x6f 2
1221 * Sempron: 0x7f 1/2
1222 * 0x6f 2
1223 * 0x6c 2
1224 * 0x7c 2
1225 * Turion 64: 0x68 2
1226 *
1227 */
1228 uint32_t u32Dummy;
1229 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1230 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1231 u32BaseFamily= (u32Version >> 8) & 0xf;
1232 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1233 u32Model = ((u32Version >> 4) & 0xf);
1234 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1235 u32Stepping = u32Version & 0xf;
1236 if ( u32Family == 0xf
1237 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1238 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1239 {
1240 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1241 }
1242
1243 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1244 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1245 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1246 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1247 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1248 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1249
1250 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1251 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING\n"));
1252 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT)
1253 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT\n"));
1254 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK)
1255 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK\n"));
1256 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
1257 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE\n"));
1258 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE)
1259 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE\n"));
1260 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER)
1261 LogRel(("HWACCM: AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER\n"));
1262
1263 /* Only try once. */
1264 pVM->hwaccm.s.fInitialized = true;
1265
1266 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1267 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1268
1269 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1270 AssertRC(rc);
1271 if (rc == VINF_SUCCESS)
1272 {
1273 pVM->fHWACCMEnabled = true;
1274 pVM->hwaccm.s.svm.fEnabled = true;
1275
1276 if (pVM->hwaccm.s.fNestedPaging)
1277 LogRel(("HWACCM: Enabled nested paging\n"));
1278
1279 hwaccmR3DisableRawMode(pVM);
1280 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1281 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1282 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1283#ifdef VBOX_ENABLE_64_BITS_GUESTS
1284 if (pVM->hwaccm.s.fAllow64BitGuests)
1285 {
1286 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1287 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1288 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1289 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1290 }
1291 else
1292 /* Turn on NXE if PAE has been enabled. */
1293 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1294 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1295#endif
1296
1297 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1298 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1299 : "HWACCM: 32-bit guest supported.\n"));
1300
1301 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1302 }
1303 else
1304 {
1305 pVM->fHWACCMEnabled = false;
1306 }
1307 }
1308 }
1309 if (pVM->fHWACCMEnabled)
1310 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1311 return VINF_SUCCESS;
1312}
1313
1314/**
1315 * Applies relocations to data and code managed by this
1316 * component. This function will be called at init and
1317 * whenever the VMM need to relocate it self inside the GC.
1318 *
1319 * @param pVM The VM.
1320 */
1321VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1322{
1323 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1324
1325 /* Fetch the current paging mode during the relocate callback during state loading. */
1326 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1327 {
1328 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1329 {
1330 PVMCPU pVCpu = &pVM->aCpus[i];
1331
1332 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1333 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1334 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1335 }
1336 }
1337#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1338 if (pVM->fHWACCMEnabled)
1339 {
1340 int rc;
1341
1342 switch(PGMGetHostMode(pVM))
1343 {
1344 case PGMMODE_32_BIT:
1345 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1346 break;
1347
1348 case PGMMODE_PAE:
1349 case PGMMODE_PAE_NX:
1350 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1351 break;
1352
1353 default:
1354 AssertFailed();
1355 break;
1356 }
1357 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1358 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1359
1360 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1361 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1362
1363 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1364 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1365
1366 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1367 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1368
1369# ifdef DEBUG
1370 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1371 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1372# endif
1373 }
1374#endif
1375 return;
1376}
1377
1378/**
1379 * Checks hardware accelerated raw mode is allowed.
1380 *
1381 * @returns boolean
1382 * @param pVM The VM to operate on.
1383 */
1384VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1385{
1386 return pVM->hwaccm.s.fAllowed;
1387}
1388
1389/**
1390 * Notification callback which is called whenever there is a chance that a CR3
1391 * value might have changed.
1392 *
1393 * This is called by PGM.
1394 *
1395 * @param pVM The VM to operate on.
1396 * @param pVCpu The VMCPU to operate on.
1397 * @param enmShadowMode New shadow paging mode.
1398 * @param enmGuestMode New guest paging mode.
1399 */
1400VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1401{
1402 /* Ignore page mode changes during state loading. */
1403 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1404 return;
1405
1406 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1407
1408 if ( pVM->hwaccm.s.vmx.fEnabled
1409 && pVM->fHWACCMEnabled)
1410 {
1411 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1412 && enmGuestMode >= PGMMODE_PROTECTED)
1413 {
1414 PCPUMCTX pCtx;
1415
1416 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1417
1418 /* After a real mode switch to protected mode we must force
1419 * CPL to 0. Our real mode emulation had to set it to 3.
1420 */
1421 pCtx->ssHid.Attr.n.u2Dpl = 0;
1422 }
1423 }
1424
1425 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1426 {
1427 /* Keep track of paging mode changes. */
1428 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1429 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1430
1431 /* Did we miss a change, because all code was executed in the recompiler? */
1432 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1433 {
1434 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1435 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1436 }
1437 }
1438
1439 /* Reset the contents of the read cache. */
1440 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1441 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1442 pCache->Read.aFieldVal[j] = 0;
1443}
1444
1445/**
1446 * Terminates the HWACCM.
1447 *
1448 * Termination means cleaning up and freeing all resources,
1449 * the VM it self is at this point powered off or suspended.
1450 *
1451 * @returns VBox status code.
1452 * @param pVM The VM to operate on.
1453 */
1454VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1455{
1456 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1457 {
1458 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1459 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1460 }
1461 HWACCMR3TermCPU(pVM);
1462 return 0;
1463}
1464
1465/**
1466 * Terminates the per-VCPU HWACCM.
1467 *
1468 * Termination means cleaning up and freeing all resources,
1469 * the VM it self is at this point powered off or suspended.
1470 *
1471 * @returns VBox status code.
1472 * @param pVM The VM to operate on.
1473 */
1474VMMR3DECL(int) HWACCMR3TermCPU(PVM pVM)
1475{
1476 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1477 {
1478 PVMCPU pVCpu = &pVM->aCpus[i];
1479
1480#ifdef VBOX_WITH_STATISTICS
1481 if (pVCpu->hwaccm.s.paStatExitReason)
1482 {
1483 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1484 pVCpu->hwaccm.s.paStatExitReason = NULL;
1485 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1486 }
1487 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1488 {
1489 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1490 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1491 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1492 }
1493#endif
1494
1495#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1496 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1497 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1498 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1499#endif
1500 }
1501 return 0;
1502}
1503
1504/**
1505 * Resets a virtual CPU.
1506 *
1507 * Used by HWACCMR3Reset and CPU hot plugging.
1508 *
1509 * @param pVCpu The CPU to reset.
1510 */
1511VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1512{
1513 /* On first entry we'll sync everything. */
1514 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1515
1516 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1517 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1518
1519 pVCpu->hwaccm.s.fActive = false;
1520 pVCpu->hwaccm.s.Event.fPending = false;
1521
1522 /* Reset state information for real-mode emulation in VT-x. */
1523 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1524 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1525 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1526
1527 /* Reset the contents of the read cache. */
1528 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1529 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1530 pCache->Read.aFieldVal[j] = 0;
1531
1532#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1533 /* Magic marker for searching in crash dumps. */
1534 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1535 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1536#endif
1537}
1538
1539/**
1540 * The VM is being reset.
1541 *
1542 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1543 * needs to be removed.
1544 *
1545 * @param pVM VM handle.
1546 */
1547VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1548{
1549 LogFlow(("HWACCMR3Reset:\n"));
1550
1551 if (pVM->fHWACCMEnabled)
1552 hwaccmR3DisableRawMode(pVM);
1553
1554 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1555 {
1556 PVMCPU pVCpu = &pVM->aCpus[i];
1557
1558 HWACCMR3ResetCpu(pVCpu);
1559 }
1560
1561 /* Clear all patch information. */
1562 pVM->hwaccm.s.pGuestPatchMem = 0;
1563 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1564 pVM->hwaccm.s.cbGuestPatchMem = 0;
1565 pVM->hwaccm.s.cPatches = 0;
1566 pVM->hwaccm.s.PatchTree = 0;
1567 pVM->hwaccm.s.fTPRPatchingActive = false;
1568 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1569}
1570
1571/**
1572 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1573 *
1574 * @returns VBox strict status code.
1575 * @param pVM The VM handle.
1576 * @param pVCpu The VMCPU for the EMT we're being called on.
1577 * @param pvUser Unused
1578 *
1579 */
1580DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1581{
1582 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1583
1584 /* Only execute the handler on the VCPU the original patch request was issued. */
1585 if (pVCpu->idCpu != idCpu)
1586 return VINF_SUCCESS;
1587
1588 Log(("hwaccmR3RemovePatches\n"));
1589 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1590 {
1591 uint8_t szInstr[15];
1592 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1593 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1594 int rc;
1595
1596#ifdef LOG_ENABLED
1597 char szOutput[256];
1598
1599 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1600 if (RT_SUCCESS(rc))
1601 Log(("Patched instr: %s\n", szOutput));
1602#endif
1603
1604 /* Check if the instruction is still the same. */
1605 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1606 if (rc != VINF_SUCCESS)
1607 {
1608 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1609 continue; /* swapped out or otherwise removed; skip it. */
1610 }
1611
1612 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1613 {
1614 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1615 continue; /* skip it. */
1616 }
1617
1618 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1619 AssertRC(rc);
1620
1621#ifdef LOG_ENABLED
1622 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, 0, szOutput, sizeof(szOutput), 0);
1623 if (RT_SUCCESS(rc))
1624 Log(("Original instr: %s\n", szOutput));
1625#endif
1626 }
1627 pVM->hwaccm.s.cPatches = 0;
1628 pVM->hwaccm.s.PatchTree = 0;
1629 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1630 pVM->hwaccm.s.fTPRPatchingActive = false;
1631 return VINF_SUCCESS;
1632}
1633
1634/**
1635 * Enable patching in a VT-x/AMD-V guest
1636 *
1637 * @returns VBox status code.
1638 * @param pVM The VM to operate on.
1639 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1640 * @param pPatchMem Patch memory range
1641 * @param cbPatchMem Size of the memory range
1642 */
1643int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1644{
1645 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)idCpu);
1646 AssertRC(rc);
1647
1648 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1649 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1650 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1651 return VINF_SUCCESS;
1652}
1653
1654/**
1655 * Enable patching in a VT-x/AMD-V guest
1656 *
1657 * @returns VBox status code.
1658 * @param pVM The VM to operate on.
1659 * @param pPatchMem Patch memory range
1660 * @param cbPatchMem Size of the memory range
1661 */
1662VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1663{
1664 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1665 if (pVM->cCpus > 1)
1666 {
1667 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1668 int rc = VMR3ReqCallNoWaitU(pVM->pUVM, VMCPUID_ANY_QUEUE,
1669 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1670 AssertRC(rc);
1671 return rc;
1672 }
1673 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1674}
1675
1676/**
1677 * Disable patching in a VT-x/AMD-V guest
1678 *
1679 * @returns VBox status code.
1680 * @param pVM The VM to operate on.
1681 * @param pPatchMem Patch memory range
1682 * @param cbPatchMem Size of the memory range
1683 */
1684VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1685{
1686 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1687
1688 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1689 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1690
1691 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1692 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)VMMGetCpuId(pVM));
1693 AssertRC(rc);
1694
1695 pVM->hwaccm.s.pGuestPatchMem = 0;
1696 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1697 pVM->hwaccm.s.cbGuestPatchMem = 0;
1698 pVM->hwaccm.s.fTPRPatchingActive = false;
1699 return VINF_SUCCESS;
1700}
1701
1702
1703/**
1704 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1705 *
1706 * @returns VBox strict status code.
1707 * @param pVM The VM handle.
1708 * @param pVCpu The VMCPU for the EMT we're being called on.
1709 * @param pvUser User specified CPU context
1710 *
1711 */
1712DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1713{
1714 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1715 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1716 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1717 unsigned cbOp;
1718
1719 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1720 if (pVCpu->idCpu != idCpu)
1721 return VINF_SUCCESS;
1722
1723 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1724
1725 /* Two or more VCPUs were racing to patch this instruction. */
1726 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1727 if (pPatch)
1728 return VINF_SUCCESS;
1729
1730 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1731
1732 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1733 AssertRC(rc);
1734 if ( rc == VINF_SUCCESS
1735 && pDis->pCurInstr->opcode == OP_MOV
1736 && cbOp >= 3)
1737 {
1738 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1739 uint32_t idx = pVM->hwaccm.s.cPatches;
1740
1741 pPatch = &pVM->hwaccm.s.aPatches[idx];
1742
1743 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1744 AssertRC(rc);
1745
1746 pPatch->cbOp = cbOp;
1747
1748 if (pDis->param1.flags == USE_DISPLACEMENT32)
1749 {
1750 /* write. */
1751 if (pDis->param2.flags == USE_REG_GEN32)
1752 {
1753 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1754 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1755 }
1756 else
1757 {
1758 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1759 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1760 pPatch->uSrcOperand = pDis->param2.parval;
1761 }
1762 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1763 AssertRC(rc);
1764
1765 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1766 pPatch->cbNewOp = sizeof(aVMMCall);
1767 }
1768 else
1769 {
1770 RTGCPTR oldrip = pCtx->rip;
1771 uint32_t oldcbOp = cbOp;
1772 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1773
1774 /* read */
1775 Assert(pDis->param1.flags == USE_REG_GEN32);
1776
1777 /* Found:
1778 * mov eax, dword [fffe0080] (5 bytes)
1779 * Check if next instruction is:
1780 * shr eax, 4
1781 */
1782 pCtx->rip += cbOp;
1783 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1784 pCtx->rip = oldrip;
1785 if ( rc == VINF_SUCCESS
1786 && pDis->pCurInstr->opcode == OP_SHR
1787 && pDis->param1.flags == USE_REG_GEN32
1788 && pDis->param1.base.reg_gen == uMmioReg
1789 && pDis->param2.flags == USE_IMMEDIATE8
1790 && pDis->param2.parval == 4
1791 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1792 {
1793 uint8_t szInstr[15];
1794
1795 /* Replacing two instructions now. */
1796 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1797 AssertRC(rc);
1798
1799 pPatch->cbOp = oldcbOp + cbOp;
1800
1801 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1802 szInstr[0] = 0xF0;
1803 szInstr[1] = 0x0F;
1804 szInstr[2] = 0x20;
1805 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1806 for (unsigned i = 4; i < pPatch->cbOp; i++)
1807 szInstr[i] = 0x90; /* nop */
1808
1809 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1810 AssertRC(rc);
1811
1812 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1813 pPatch->cbNewOp = pPatch->cbOp;
1814
1815 Log(("Acceptable read/shr candidate!\n"));
1816 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1817 }
1818 else
1819 {
1820 pPatch->enmType = HWACCMTPRINSTR_READ;
1821 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1822
1823 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1824 AssertRC(rc);
1825
1826 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1827 pPatch->cbNewOp = sizeof(aVMMCall);
1828 }
1829 }
1830
1831 pPatch->Core.Key = pCtx->eip;
1832 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1833 AssertRC(rc);
1834
1835 pVM->hwaccm.s.cPatches++;
1836 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1837 return VINF_SUCCESS;
1838 }
1839
1840 /* Save invalid patch, so we will not try again. */
1841 uint32_t idx = pVM->hwaccm.s.cPatches;
1842
1843#ifdef LOG_ENABLED
1844 char szOutput[256];
1845 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1846 if (RT_SUCCESS(rc))
1847 Log(("Failed to patch instr: %s\n", szOutput));
1848#endif
1849
1850 pPatch = &pVM->hwaccm.s.aPatches[idx];
1851 pPatch->Core.Key = pCtx->eip;
1852 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1853 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1854 AssertRC(rc);
1855 pVM->hwaccm.s.cPatches++;
1856 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1857 return VINF_SUCCESS;
1858}
1859
1860/**
1861 * Callback to patch a TPR instruction (jump to generated code)
1862 *
1863 * @returns VBox strict status code.
1864 * @param pVM The VM handle.
1865 * @param pVCpu The VMCPU for the EMT we're being called on.
1866 * @param pvUser User specified CPU context
1867 *
1868 */
1869DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1870{
1871 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1872 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1873 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1874 unsigned cbOp;
1875 int rc;
1876#ifdef LOG_ENABLED
1877 RTGCPTR pInstr;
1878 char szOutput[256];
1879#endif
1880
1881 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1882 if (pVCpu->idCpu != idCpu)
1883 return VINF_SUCCESS;
1884
1885 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1886
1887 /* Two or more VCPUs were racing to patch this instruction. */
1888 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1889 if (pPatch)
1890 {
1891 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1892 return VINF_SUCCESS;
1893 }
1894
1895 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1896
1897 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1898 AssertRC(rc);
1899 if ( rc == VINF_SUCCESS
1900 && pDis->pCurInstr->opcode == OP_MOV
1901 && cbOp >= 5)
1902 {
1903 uint32_t idx = pVM->hwaccm.s.cPatches;
1904 uint8_t aPatch[64];
1905 uint32_t off = 0;
1906
1907 pPatch = &pVM->hwaccm.s.aPatches[idx];
1908
1909#ifdef LOG_ENABLED
1910 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
1911 if (RT_SUCCESS(rc))
1912 Log(("Original instr: %s\n", szOutput));
1913#endif
1914
1915 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1916 AssertRC(rc);
1917
1918 pPatch->cbOp = cbOp;
1919 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
1920
1921 if (pDis->param1.flags == USE_DISPLACEMENT32)
1922 {
1923 /*
1924 * TPR write:
1925 *
1926 * push ECX [51]
1927 * push EDX [52]
1928 * push EAX [50]
1929 * xor EDX,EDX [31 D2]
1930 * mov EAX,EAX [89 C0]
1931 * or
1932 * mov EAX,0000000CCh [B8 CC 00 00 00]
1933 * mov ECX,0C0000082h [B9 82 00 00 C0]
1934 * wrmsr [0F 30]
1935 * pop EAX [58]
1936 * pop EDX [5A]
1937 * pop ECX [59]
1938 * jmp return_address [E9 return_address]
1939 *
1940 */
1941 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
1942
1943 aPatch[off++] = 0x51; /* push ecx */
1944 aPatch[off++] = 0x52; /* push edx */
1945 if (!fUsesEax)
1946 aPatch[off++] = 0x50; /* push eax */
1947 aPatch[off++] = 0x31; /* xor edx, edx */
1948 aPatch[off++] = 0xD2;
1949 if (pDis->param2.flags == USE_REG_GEN32)
1950 {
1951 if (!fUsesEax)
1952 {
1953 aPatch[off++] = 0x89; /* mov eax, src_reg */
1954 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
1955 }
1956 }
1957 else
1958 {
1959 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1960 aPatch[off++] = 0xB8; /* mov eax, immediate */
1961 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
1962 off += sizeof(uint32_t);
1963 }
1964 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
1965 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
1966 off += sizeof(uint32_t);
1967
1968 aPatch[off++] = 0x0F; /* wrmsr */
1969 aPatch[off++] = 0x30;
1970 if (!fUsesEax)
1971 aPatch[off++] = 0x58; /* pop eax */
1972 aPatch[off++] = 0x5A; /* pop edx */
1973 aPatch[off++] = 0x59; /* pop ecx */
1974 }
1975 else
1976 {
1977 /*
1978 * TPR read:
1979 *
1980 * push ECX [51]
1981 * push EDX [52]
1982 * push EAX [50]
1983 * mov ECX,0C0000082h [B9 82 00 00 C0]
1984 * rdmsr [0F 32]
1985 * mov EAX,EAX [89 C0]
1986 * pop EAX [58]
1987 * pop EDX [5A]
1988 * pop ECX [59]
1989 * jmp return_address [E9 return_address]
1990 *
1991 */
1992 Assert(pDis->param1.flags == USE_REG_GEN32);
1993
1994 if (pDis->param1.base.reg_gen != USE_REG_ECX)
1995 aPatch[off++] = 0x51; /* push ecx */
1996 if (pDis->param1.base.reg_gen != USE_REG_EDX)
1997 aPatch[off++] = 0x52; /* push edx */
1998 if (pDis->param1.base.reg_gen != USE_REG_EAX)
1999 aPatch[off++] = 0x50; /* push eax */
2000
2001 aPatch[off++] = 0x31; /* xor edx, edx */
2002 aPatch[off++] = 0xD2;
2003
2004 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2005 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2006 off += sizeof(uint32_t);
2007
2008 aPatch[off++] = 0x0F; /* rdmsr */
2009 aPatch[off++] = 0x32;
2010
2011 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2012 {
2013 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2014 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2015 }
2016
2017 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2018 aPatch[off++] = 0x58; /* pop eax */
2019 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2020 aPatch[off++] = 0x5A; /* pop edx */
2021 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2022 aPatch[off++] = 0x59; /* pop ecx */
2023 }
2024 aPatch[off++] = 0xE9; /* jmp return_address */
2025 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2026 off += sizeof(RTRCUINTPTR);
2027
2028 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2029 {
2030 /* Write new code to the patch buffer. */
2031 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2032 AssertRC(rc);
2033
2034#ifdef LOG_ENABLED
2035 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2036 while (true)
2037 {
2038 uint32_t cb;
2039
2040 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, 0, szOutput, sizeof(szOutput), &cb);
2041 if (RT_SUCCESS(rc))
2042 Log(("Patch instr %s\n", szOutput));
2043
2044 pInstr += cb;
2045
2046 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2047 break;
2048 }
2049#endif
2050
2051 pPatch->aNewOpcode[0] = 0xE9;
2052 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2053
2054 /* Overwrite the TPR instruction with a jump. */
2055 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2056 AssertRC(rc);
2057
2058#ifdef LOG_ENABLED
2059 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2060 if (RT_SUCCESS(rc))
2061 Log(("Jump: %s\n", szOutput));
2062#endif
2063 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2064 pPatch->cbNewOp = 5;
2065
2066 pPatch->Core.Key = pCtx->eip;
2067 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2068 AssertRC(rc);
2069
2070 pVM->hwaccm.s.cPatches++;
2071 pVM->hwaccm.s.fTPRPatchingActive = true;
2072 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2073 return VINF_SUCCESS;
2074 }
2075 else
2076 Log(("Ran out of space in our patch buffer!\n"));
2077 }
2078
2079 /* Save invalid patch, so we will not try again. */
2080 uint32_t idx = pVM->hwaccm.s.cPatches;
2081
2082#ifdef LOG_ENABLED
2083 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, 0, szOutput, sizeof(szOutput), 0);
2084 if (RT_SUCCESS(rc))
2085 Log(("Failed to patch instr: %s\n", szOutput));
2086#endif
2087
2088 pPatch = &pVM->hwaccm.s.aPatches[idx];
2089 pPatch->Core.Key = pCtx->eip;
2090 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2091 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2092 AssertRC(rc);
2093 pVM->hwaccm.s.cPatches++;
2094 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2095 return VINF_SUCCESS;
2096}
2097
2098/**
2099 * Attempt to patch TPR mmio instructions
2100 *
2101 * @returns VBox status code.
2102 * @param pVM The VM to operate on.
2103 * @param pVCpu The VM CPU to operate on.
2104 * @param pCtx CPU context
2105 */
2106VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2107{
2108 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, (pVM->hwaccm.s.pGuestPatchMem) ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr, (void *)pVCpu->idCpu);
2109 AssertRC(rc);
2110 return rc;
2111}
2112
2113/**
2114 * Force execution of the current IO code in the recompiler
2115 *
2116 * @returns VBox status code.
2117 * @param pVM The VM to operate on.
2118 * @param pCtx Partial VM execution context
2119 */
2120VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2121{
2122 PVMCPU pVCpu = VMMGetCpu(pVM);
2123
2124 Assert(pVM->fHWACCMEnabled);
2125 Log(("HWACCMR3EmulateIoBlock\n"));
2126
2127 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2128 if (HWACCMCanEmulateIoBlockEx(pCtx))
2129 {
2130 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2131 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2132 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2133 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2134 return VINF_EM_RESCHEDULE_REM;
2135 }
2136 return VINF_SUCCESS;
2137}
2138
2139/**
2140 * Checks if we can currently use hardware accelerated raw mode.
2141 *
2142 * @returns boolean
2143 * @param pVM The VM to operate on.
2144 * @param pCtx Partial VM execution context
2145 */
2146VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2147{
2148 PVMCPU pVCpu = VMMGetCpu(pVM);
2149
2150 Assert(pVM->fHWACCMEnabled);
2151
2152 /* If we're still executing the IO code, then return false. */
2153 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2154 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2155 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2156 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2157 return false;
2158
2159 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2160
2161 /* AMD-V supports real & protected mode with or without paging. */
2162 if (pVM->hwaccm.s.svm.fEnabled)
2163 {
2164 pVCpu->hwaccm.s.fActive = true;
2165 return true;
2166 }
2167
2168 pVCpu->hwaccm.s.fActive = false;
2169
2170 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2171#ifdef HWACCM_VMX_EMULATE_REALMODE
2172 bool fVMMDeviceHeapEnabled = PDMVMMDevHeapIsEnabled(pVM);
2173
2174 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2175
2176 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2177 if (fVMMDeviceHeapEnabled)
2178 {
2179 if (CPUMIsGuestInRealModeEx(pCtx))
2180 {
2181 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2182 * The base must also be equal to (sel << 4).
2183 */
2184 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2185 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2186 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2187 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2188 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2189 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2190 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2191 {
2192 return false;
2193 }
2194 }
2195 else
2196 {
2197 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2198 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2199 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2200 */
2201 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2202 && enmGuestMode >= PGMMODE_PROTECTED)
2203 {
2204 if ( (pCtx->cs & X86_SEL_RPL)
2205 || (pCtx->ds & X86_SEL_RPL)
2206 || (pCtx->es & X86_SEL_RPL)
2207 || (pCtx->fs & X86_SEL_RPL)
2208 || (pCtx->gs & X86_SEL_RPL)
2209 || (pCtx->ss & X86_SEL_RPL))
2210 {
2211 return false;
2212 }
2213 }
2214 }
2215 }
2216 else
2217#endif /* HWACCM_VMX_EMULATE_REALMODE */
2218 {
2219 if ( !CPUMIsGuestInLongModeEx(pCtx)
2220 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2221 {
2222 /** @todo This should (probably) be set on every excursion to the REM,
2223 * however it's too risky right now. So, only apply it when we go
2224 * back to REM for real mode execution. (The XP hack below doesn't
2225 * work reliably without this.)
2226 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2227 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2228
2229 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2230 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2231 return false;
2232
2233 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2234 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2235 return false;
2236
2237 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2238 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2239 * hidden registers (possible recompiler bug; see load_seg_vm) */
2240 if (pCtx->csHid.Attr.n.u1Present == 0)
2241 return false;
2242 if (pCtx->ssHid.Attr.n.u1Present == 0)
2243 return false;
2244
2245 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2246 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2247 /** @todo This check is actually wrong, it doesn't take the direction of the
2248 * stack segment into account. But, it does the job for now. */
2249 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2250 return false;
2251#if 0
2252 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2253 || pCtx->ss >= pCtx->gdtr.cbGdt
2254 || pCtx->ds >= pCtx->gdtr.cbGdt
2255 || pCtx->es >= pCtx->gdtr.cbGdt
2256 || pCtx->fs >= pCtx->gdtr.cbGdt
2257 || pCtx->gs >= pCtx->gdtr.cbGdt)
2258 return false;
2259#endif
2260 }
2261 }
2262
2263 if (pVM->hwaccm.s.vmx.fEnabled)
2264 {
2265 uint32_t mask;
2266
2267 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2268 {
2269 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2270 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2271 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2272 mask &= ~X86_CR0_NE;
2273
2274#ifdef HWACCM_VMX_EMULATE_REALMODE
2275 if (fVMMDeviceHeapEnabled)
2276 {
2277 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2278 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2279 }
2280 else
2281#endif
2282 {
2283 /* We support protected mode without paging using identity mapping. */
2284 mask &= ~X86_CR0_PG;
2285 }
2286 if ((pCtx->cr0 & mask) != mask)
2287 return false;
2288
2289 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2290 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2291 if ((pCtx->cr0 & mask) != 0)
2292 return false;
2293 }
2294
2295 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2296 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2297 mask &= ~X86_CR4_VMXE;
2298 if ((pCtx->cr4 & mask) != mask)
2299 return false;
2300
2301 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2302 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2303 if ((pCtx->cr4 & mask) != 0)
2304 return false;
2305
2306 pVCpu->hwaccm.s.fActive = true;
2307 return true;
2308 }
2309
2310 return false;
2311}
2312
2313/**
2314 * Checks if we need to reschedule due to VMM device heap changes
2315 *
2316 * @returns boolean
2317 * @param pVM The VM to operate on.
2318 * @param pCtx VM execution context
2319 */
2320VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2321{
2322 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2323 if ( pVM->hwaccm.s.vmx.fEnabled
2324 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2325 && !PDMVMMDevHeapIsEnabled(pVM)
2326 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2327 return true;
2328
2329 return false;
2330}
2331
2332
2333/**
2334 * Notifcation from EM about a rescheduling into hardware assisted execution
2335 * mode.
2336 *
2337 * @param pVCpu Pointer to the current virtual cpu structure.
2338 */
2339VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2340{
2341 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2342}
2343
2344/**
2345 * Notifcation from EM about returning from instruction emulation (REM / EM).
2346 *
2347 * @param pVCpu Pointer to the current virtual cpu structure.
2348 */
2349VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2350{
2351 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2352}
2353
2354/**
2355 * Checks if we are currently using hardware accelerated raw mode.
2356 *
2357 * @returns boolean
2358 * @param pVCpu The VMCPU to operate on.
2359 */
2360VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2361{
2362 return pVCpu->hwaccm.s.fActive;
2363}
2364
2365/**
2366 * Checks if we are currently using nested paging.
2367 *
2368 * @returns boolean
2369 * @param pVM The VM to operate on.
2370 */
2371VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2372{
2373 return pVM->hwaccm.s.fNestedPaging;
2374}
2375
2376/**
2377 * Checks if we are currently using VPID in VT-x mode.
2378 *
2379 * @returns boolean
2380 * @param pVM The VM to operate on.
2381 */
2382VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2383{
2384 return pVM->hwaccm.s.vmx.fVPID;
2385}
2386
2387
2388/**
2389 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2390 *
2391 * @returns boolean
2392 * @param pVM The VM to operate on.
2393 */
2394VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2395{
2396 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2397}
2398
2399/**
2400 * Restart an I/O instruction that was refused in ring-0
2401 *
2402 * @returns Strict VBox status code. Informational status codes other than the one documented
2403 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2404 * @retval VINF_SUCCESS Success.
2405 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2406 * status code must be passed on to EM.
2407 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2408 *
2409 * @param pVM The VM to operate on.
2410 * @param pVCpu The VMCPU to operate on.
2411 * @param pCtx VCPU register context
2412 */
2413VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2414{
2415 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2416
2417 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2418
2419 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2420 || enmType == HWACCMPENDINGIO_INVALID)
2421 return VERR_NOT_FOUND;
2422
2423 VBOXSTRICTRC rcStrict;
2424 switch (enmType)
2425 {
2426 case HWACCMPENDINGIO_PORT_READ:
2427 {
2428 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2429 uint32_t u32Val = 0;
2430
2431 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2432 &u32Val,
2433 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2434 if (IOM_SUCCESS(rcStrict))
2435 {
2436 /* Write back to the EAX register. */
2437 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2438 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2439 }
2440 break;
2441 }
2442
2443 case HWACCMPENDINGIO_PORT_WRITE:
2444 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2445 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2446 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2447 if (IOM_SUCCESS(rcStrict))
2448 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2449 break;
2450
2451 default:
2452 AssertFailed();
2453 return VERR_INTERNAL_ERROR;
2454 }
2455
2456 return rcStrict;
2457}
2458
2459/**
2460 * Inject an NMI into a running VM (only VCPU 0!)
2461 *
2462 * @returns boolean
2463 * @param pVM The VM to operate on.
2464 */
2465VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2466{
2467 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2468 return VINF_SUCCESS;
2469}
2470
2471/**
2472 * Check fatal VT-x/AMD-V error and produce some meaningful
2473 * log release message.
2474 *
2475 * @param pVM The VM to operate on.
2476 * @param iStatusCode VBox status code
2477 */
2478VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2479{
2480 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2481 {
2482 switch(iStatusCode)
2483 {
2484 case VERR_VMX_INVALID_VMCS_FIELD:
2485 break;
2486
2487 case VERR_VMX_INVALID_VMCS_PTR:
2488 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys));
2489 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2490 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2491 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2492 break;
2493
2494 case VERR_VMX_UNABLE_TO_START_VM:
2495 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2496 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2497#if 0 /* @todo dump the current control fields to the release log */
2498 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2499 {
2500
2501 }
2502#endif
2503 break;
2504
2505 case VERR_VMX_UNABLE_TO_RESUME_VM:
2506 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2507 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2508 break;
2509
2510 case VERR_VMX_INVALID_VMXON_PTR:
2511 break;
2512 }
2513 }
2514}
2515
2516/**
2517 * Execute state save operation.
2518 *
2519 * @returns VBox status code.
2520 * @param pVM VM Handle.
2521 * @param pSSM SSM operation handle.
2522 */
2523static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2524{
2525 int rc;
2526
2527 Log(("hwaccmR3Save:\n"));
2528
2529 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2530 {
2531 /*
2532 * Save the basic bits - fortunately all the other things can be resynced on load.
2533 */
2534 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2535 AssertRCReturn(rc, rc);
2536 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2537 AssertRCReturn(rc, rc);
2538 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2539 AssertRCReturn(rc, rc);
2540
2541 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2542 AssertRCReturn(rc, rc);
2543 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2544 AssertRCReturn(rc, rc);
2545 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2546 AssertRCReturn(rc, rc);
2547 }
2548#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2549 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2550 AssertRCReturn(rc, rc);
2551 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2552 AssertRCReturn(rc, rc);
2553 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2554 AssertRCReturn(rc, rc);
2555
2556 /* Store all the guest patch records too. */
2557 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2558 AssertRCReturn(rc, rc);
2559
2560 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2561 {
2562 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2563
2564 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2565 AssertRCReturn(rc, rc);
2566
2567 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2568 AssertRCReturn(rc, rc);
2569
2570 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2571 AssertRCReturn(rc, rc);
2572
2573 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2574 AssertRCReturn(rc, rc);
2575
2576 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2577 AssertRCReturn(rc, rc);
2578
2579 AssertCompileSize(HWACCMTPRINSTR, 4);
2580 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2581 AssertRCReturn(rc, rc);
2582
2583 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2584 AssertRCReturn(rc, rc);
2585
2586 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2587 AssertRCReturn(rc, rc);
2588
2589 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2590 AssertRCReturn(rc, rc);
2591
2592 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2593 AssertRCReturn(rc, rc);
2594 }
2595#endif
2596 return VINF_SUCCESS;
2597}
2598
2599/**
2600 * Execute state load operation.
2601 *
2602 * @returns VBox status code.
2603 * @param pVM VM Handle.
2604 * @param pSSM SSM operation handle.
2605 * @param uVersion Data layout version.
2606 * @param uPass The data pass.
2607 */
2608static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2609{
2610 int rc;
2611
2612 Log(("hwaccmR3Load:\n"));
2613 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2614
2615 /*
2616 * Validate version.
2617 */
2618 if ( uVersion != HWACCM_SSM_VERSION
2619 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2620 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2621 {
2622 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2623 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2624 }
2625 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2626 {
2627 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2628 AssertRCReturn(rc, rc);
2629 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2630 AssertRCReturn(rc, rc);
2631 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2632 AssertRCReturn(rc, rc);
2633
2634 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2635 {
2636 uint32_t val;
2637
2638 rc = SSMR3GetU32(pSSM, &val);
2639 AssertRCReturn(rc, rc);
2640 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2641
2642 rc = SSMR3GetU32(pSSM, &val);
2643 AssertRCReturn(rc, rc);
2644 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2645
2646 rc = SSMR3GetU32(pSSM, &val);
2647 AssertRCReturn(rc, rc);
2648 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2649 }
2650 }
2651#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2652 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2653 {
2654 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2655 AssertRCReturn(rc, rc);
2656 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2657 AssertRCReturn(rc, rc);
2658 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2659 AssertRCReturn(rc, rc);
2660
2661 /* Fetch all TPR patch records. */
2662 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2663 AssertRCReturn(rc, rc);
2664
2665 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2666 {
2667 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2668
2669 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2670 AssertRCReturn(rc, rc);
2671
2672 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2673 AssertRCReturn(rc, rc);
2674
2675 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2676 AssertRCReturn(rc, rc);
2677
2678 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2679 AssertRCReturn(rc, rc);
2680
2681 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2682 AssertRCReturn(rc, rc);
2683
2684 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2685 AssertRCReturn(rc, rc);
2686
2687 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2688 pVM->hwaccm.s.fTPRPatchingActive = true;
2689
2690 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2691
2692 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2693 AssertRCReturn(rc, rc);
2694
2695 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2696 AssertRCReturn(rc, rc);
2697
2698 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2699 AssertRCReturn(rc, rc);
2700
2701 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2702 AssertRCReturn(rc, rc);
2703
2704 Log(("hwaccmR3Load: patch %d\n", i));
2705 Log(("Key = %x\n", pPatch->Core.Key));
2706 Log(("cbOp = %d\n", pPatch->cbOp));
2707 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2708 Log(("type = %d\n", pPatch->enmType));
2709 Log(("srcop = %d\n", pPatch->uSrcOperand));
2710 Log(("dstop = %d\n", pPatch->uDstOperand));
2711 Log(("cFaults = %d\n", pPatch->cFaults));
2712 Log(("target = %x\n", pPatch->pJumpTarget));
2713 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2714 AssertRC(rc);
2715 }
2716 }
2717#endif
2718
2719 /* Recheck all VCPUs if we can go staight into hwaccm execution mode. */
2720 if (HWACCMIsEnabled(pVM))
2721 {
2722 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2723 {
2724 PVMCPU pVCpu = &pVM->aCpus[i];
2725
2726 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2727 }
2728 }
2729 return VINF_SUCCESS;
2730}
2731
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