EMRaw.cpp@ 25046

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1	/* $Id: EMRaw.cpp 24999 2009-11-26 13:36:37Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_em EM - The Execution Monitor / Manager
23	*
24	* The Execution Monitor/Manager is responsible for running the VM, scheduling
25	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26	* Interpreted), and keeping the CPU states in sync. The function
27	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29	* emR3RemExecute).
30	*
31	* The interpreted execution is only used to avoid switching between
32	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33	* The interpretation is thus implemented as part of EM.
34	*
35	* @see grp_em
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_EM
42	#include <VBox/em.h>
43	#include <VBox/vmm.h>
44	#ifdef VBOX_WITH_VMI
45	# include <VBox/parav.h>
46	#endif
47	#include <VBox/patm.h>
48	#include <VBox/csam.h>
49	#include <VBox/selm.h>
50	#include <VBox/trpm.h>
51	#include <VBox/iom.h>
52	#include <VBox/dbgf.h>
53	#include <VBox/pgm.h>
54	#include <VBox/rem.h>
55	#include <VBox/tm.h>
56	#include <VBox/mm.h>
57	#include <VBox/ssm.h>
58	#include <VBox/pdmapi.h>
59	#include <VBox/pdmcritsect.h>
60	#include <VBox/pdmqueue.h>
61	#include <VBox/patm.h>
62	#include "EMInternal.h"
63	#include <VBox/vm.h>
64	#include <VBox/cpumdis.h>
65	#include <VBox/dis.h>
66	#include <VBox/disopcode.h>
67	#include <VBox/dbgf.h>
68
69	#include <VBox/log.h>
70	#include <iprt/string.h>
71	#include <iprt/stream.h>
72
73	/*******************************************************************************
74	* Defined Constants And Macros *
75	*******************************************************************************/
76
77
78	/*******************************************************************************
79	* Internal Functions *
80	*******************************************************************************/
81	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
82	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
83	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
84	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
85	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
86	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
87	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
88	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
89
90	#define EMHANDLERC_WITH_PATM
91	#include "EMHandleRCTmpl.h"
92
93	/**
94	* Enables or disables a set of raw-mode execution modes.
95	*
96	* @returns VINF_SUCCESS on success.
97	* @returns VINF_RESCHEDULE if a rescheduling might be required.
98	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
99	*
100	* @param pVM The VM to operate on.
101	* @param enmMode The execution mode change.
102	* @thread The emulation thread.
103	*/
104	VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
105	{
106	switch (enmMode)
107	{
108	case EMRAW_NONE:
109	pVM->fRawR3Enabled = false;
110	pVM->fRawR0Enabled = false;
111	break;
112	case EMRAW_RING3_ENABLE:
113	pVM->fRawR3Enabled = true;
114	break;
115	case EMRAW_RING3_DISABLE:
116	pVM->fRawR3Enabled = false;
117	break;
118	case EMRAW_RING0_ENABLE:
119	pVM->fRawR0Enabled = true;
120	break;
121	case EMRAW_RING0_DISABLE:
122	pVM->fRawR0Enabled = false;
123	break;
124	default:
125	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
126	return VERR_INVALID_PARAMETER;
127	}
128	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
129	pVM->fRawR3Enabled, pVM->fRawR0Enabled));
130	return pVM->aCpus[0].em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
131	}
132
133
134
135	#ifdef VBOX_WITH_STATISTICS
136	/**
137	* Just a braindead function to keep track of cli addresses.
138	* @param pVM VM handle.
139	* @param pVMCPU VMCPU handle.
140	* @param GCPtrInstr The EIP of the cli instruction.
141	*/
142	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
143	{
144	PCLISTAT pRec;
145
146	pRec = (PCLISTAT)RTAvlPVGet(&pVCpu->em.s.pCliStatTree, (AVLPVKEY)GCPtrInstr);
147	if (!pRec)
148	{
149	/* New cli instruction; insert into the tree. */
150	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
151	Assert(pRec);
152	if (!pRec)
153	return;
154	pRec->Core.Key = (AVLPVKEY)GCPtrInstr;
155
156	char szCliStatName[32];
157	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
158	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
159
160	bool fRc = RTAvlPVInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
161	Assert(fRc); NOREF(fRc);
162	}
163	STAM_COUNTER_INC(&pRec->Counter);
164	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
165	}
166	#endif /* VBOX_WITH_STATISTICS */
167
168
169
170	/**
171	* Resumes executing hypervisor after a debug event.
172	*
173	* This is kind of special since our current guest state is
174	* potentially out of sync.
175	*
176	* @returns VBox status code.
177	* @param pVM The VM handle.
178	* @param pVCpu The VMCPU handle.
179	*/
180	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
181	{
182	int rc;
183	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
184	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
185	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
186
187	/*
188	* Resume execution.
189	*/
190	CPUMRawEnter(pVCpu, NULL);
191	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
192	rc = VMMR3ResumeHyper(pVM, pVCpu);
193	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
194	rc = CPUMRawLeave(pVCpu, NULL, rc);
195	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
196
197	/*
198	* Deal with the return code.
199	*/
200	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
201	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
202	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
203	return rc;
204	}
205
206
207	/**
208	* Steps rawmode.
209	*
210	* @returns VBox status code.
211	* @param pVM The VM handle.
212	* @param pVCpu The VMCPU handle.
213	*/
214	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
215	{
216	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
217	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
218	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
219	int rc;
220	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
221	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
222	#ifndef DEBUG_sandervl
223	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
224	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
225	#endif
226	if (fGuest)
227	{
228	/*
229	* Check vital forced actions, but ignore pending interrupts and timers.
230	*/
231	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
232	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
233	{
234	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
235	if (rc != VINF_SUCCESS)
236	return rc;
237	}
238
239	/*
240	* Set flags for single stepping.
241	*/
242	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
243	}
244	else
245	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
246
247	/*
248	* Single step.
249	* We do not start time or anything, if anything we should just do a few nanoseconds.
250	*/
251	CPUMRawEnter(pVCpu, NULL);
252	do
253	{
254	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
255	rc = VMMR3ResumeHyper(pVM, pVCpu);
256	else
257	rc = VMMR3RawRunGC(pVM, pVCpu);
258	#ifndef DEBUG_sandervl
259	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
260	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
261	#endif
262	} while ( rc == VINF_SUCCESS
263	\|\| rc == VINF_EM_RAW_INTERRUPT);
264	rc = CPUMRawLeave(pVCpu, NULL, rc);
265	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
266
267	/*
268	* Make sure the trap flag is cleared.
269	* (Too bad if the guest is trying to single step too.)
270	*/
271	if (fGuest)
272	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
273	else
274	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
275
276	/*
277	* Deal with the return codes.
278	*/
279	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
280	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
281	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
282	return rc;
283	}
284
285
286	#ifdef DEBUG
287
288
289	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
290	{
291	int rc = VINF_SUCCESS;
292	EMSTATE enmOldState = pVCpu->em.s.enmState;
293	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
294
295	Log(("Single step BEGIN:\n"));
296	for (uint32_t i = 0; i < cIterations; i++)
297	{
298	DBGFR3PrgStep(pVCpu);
299	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
300	rc = emR3RawStep(pVM, pVCpu);
301	if (rc != VINF_SUCCESS)
302	break;
303	}
304	Log(("Single step END: rc=%Rrc\n", rc));
305	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
306	pVCpu->em.s.enmState = enmOldState;
307	return rc;
308	}
309
310	#endif /* DEBUG */
311
312
313	/**
314	* Executes one (or perhaps a few more) instruction(s).
315	*
316	* @returns VBox status code suitable for EM.
317	*
318	* @param pVM VM handle.
319	* @param pVCpu VMCPU handle
320	* @param rcGC GC return code
321	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
322	* instruction and prefix the log output with this text.
323	*/
324	#ifdef LOG_ENABLED
325	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
326	#else
327	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
328	#endif
329	{
330	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
331	int rc;
332
333	/*
334	*
335	* The simple solution is to use the recompiler.
336	* The better solution is to disassemble the current instruction and
337	* try handle as many as possible without using REM.
338	*
339	*/
340
341	#ifdef LOG_ENABLED
342	/*
343	* Disassemble the instruction if requested.
344	*/
345	if (pszPrefix)
346	{
347	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
348	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
349	}
350	#endif /* LOG_ENABLED */
351
352	/*
353	* PATM is making life more interesting.
354	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
355	* tell PATM there is a trap in this code and have it take the appropriate actions
356	* to allow us execute the code in REM.
357	*/
358	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
359	{
360	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
361
362	RTGCPTR pNewEip;
363	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
364	switch (rc)
365	{
366	/*
367	* It's not very useful to emulate a single instruction and then go back to raw
368	* mode; just execute the whole block until IF is set again.
369	*/
370	case VINF_SUCCESS:
371	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
372	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
373	pCtx->eip = pNewEip;
374	Assert(pCtx->eip);
375
376	if (pCtx->eflags.Bits.u1IF)
377	{
378	/*
379	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
380	*/
381	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
382	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
383	}
384	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
385	{
386	/* special case: iret, that sets IF, detected a pending irq/event */
387	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
388	}
389	return VINF_EM_RESCHEDULE_REM;
390
391	/*
392	* One instruction.
393	*/
394	case VINF_PATCH_EMULATE_INSTR:
395	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
396	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
397	pCtx->eip = pNewEip;
398	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
399
400	/*
401	* The patch was disabled, hand it to the REM.
402	*/
403	case VERR_PATCH_DISABLED:
404	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
405	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
406	pCtx->eip = pNewEip;
407	if (pCtx->eflags.Bits.u1IF)
408	{
409	/*
410	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
411	*/
412	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
413	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
414	}
415	return VINF_EM_RESCHEDULE_REM;
416
417	/* Force continued patch exection; usually due to write monitored stack. */
418	case VINF_PATCH_CONTINUE:
419	return VINF_SUCCESS;
420
421	default:
422	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
423	return VERR_IPE_UNEXPECTED_STATUS;
424	}
425	}
426
427	#if 0
428	/* Try our own instruction emulator before falling back to the recompiler. */
429	DISCPUSTATE Cpu;
430	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
431	if (RT_SUCCESS(rc))
432	{
433	uint32_t size;
434
435	switch (Cpu.pCurInstr->opcode)
436	{
437	/* @todo we can do more now */
438	case OP_MOV:
439	case OP_AND:
440	case OP_OR:
441	case OP_XOR:
442	case OP_POP:
443	case OP_INC:
444	case OP_DEC:
445	case OP_XCHG:
446	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
447	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
448	if (RT_SUCCESS(rc))
449	{
450	pCtx->rip += Cpu.opsize;
451	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
452	return rc;
453	}
454	if (rc != VERR_EM_INTERPRETER)
455	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
456	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
457	break;
458	}
459	}
460	#endif /* 0 */
461	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
462	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
463	EMRemLock(pVM);
464	/* Flush the recompiler TLB if the VCPU has changed. */
465	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
466	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
467	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
468
469	rc = REMR3EmulateInstruction(pVM, pVCpu);
470	EMRemUnlock(pVM);
471	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
472
473	return rc;
474	}
475
476
477	/**
478	* Executes one (or perhaps a few more) instruction(s).
479	* This is just a wrapper for discarding pszPrefix in non-logging builds.
480	*
481	* @returns VBox status code suitable for EM.
482	* @param pVM VM handle.
483	* @param pVCpu VMCPU handle.
484	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
485	* instruction and prefix the log output with this text.
486	* @param rcGC GC return code
487	*/
488	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
489	{
490	#ifdef LOG_ENABLED
491	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
492	#else
493	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
494	#endif
495	}
496
497	/**
498	* Executes one (or perhaps a few more) IO instruction(s).
499	*
500	* @returns VBox status code suitable for EM.
501	* @param pVM VM handle.
502	* @param pVCpu VMCPU handle.
503	*/
504	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
505	{
506	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
507
508	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
509
510	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
511	* as io instructions tend to come in packages of more than one
512	*/
513	DISCPUSTATE Cpu;
514	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
515	if (RT_SUCCESS(rc))
516	{
517	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
518
519	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
520	{
521	switch (Cpu.pCurInstr->opcode)
522	{
523	case OP_IN:
524	{
525	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
526	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
527	break;
528	}
529
530	case OP_OUT:
531	{
532	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
533	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
534	break;
535	}
536	}
537	}
538	else if (Cpu.prefix & PREFIX_REP)
539	{
540	switch (Cpu.pCurInstr->opcode)
541	{
542	case OP_INSB:
543	case OP_INSWD:
544	{
545	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
546	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
547	break;
548	}
549
550	case OP_OUTSB:
551	case OP_OUTSWD:
552	{
553	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
554	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
555	break;
556	}
557	}
558	}
559
560	/*
561	* Handled the I/O return codes.
562	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
563	*/
564	if (IOM_SUCCESS(rcStrict))
565	{
566	pCtx->rip += Cpu.opsize;
567	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
568	return VBOXSTRICTRC_TODO(rcStrict);
569	}
570
571	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
572	{
573	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
574	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
575	return VBOXSTRICTRC_TODO(rcStrict);
576	}
577	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
578
579	if (RT_FAILURE(rcStrict))
580	{
581	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
582	return VBOXSTRICTRC_TODO(rcStrict);
583	}
584	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
585	}
586	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
587	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
588	}
589
590
591	/**
592	* Handle a guest context trap.
593	*
594	* @returns VBox status code suitable for EM.
595	* @param pVM VM handle.
596	* @param pVCpu VMCPU handle.
597	*/
598	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
599	{
600	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
601
602	/*
603	* Get the trap info.
604	*/
605	uint8_t u8TrapNo;
606	TRPMEVENT enmType;
607	RTGCUINT uErrorCode;
608	RTGCUINTPTR uCR2;
609	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
610	if (RT_FAILURE(rc))
611	{
612	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
613	return rc;
614	}
615
616
617	#if 1 /* Experimental: Review, disable if it causes trouble. */
618	/*
619	* Handle traps in patch code first.
620	*
621	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
622	* but several traps isn't handled specially by TRPM in RC and we end up here
623	* instead. One example is #DE.
624	*/
625	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
626	if ( uCpl == 0
627	&& PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
628	{
629	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
630	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
631	}
632	#endif
633
634	/*
635	* If the guest gate is marked unpatched, then we will check again if we can patch it.
636	* (This assumes that we've already tried and failed to dispatch the trap in
637	* RC for the gates that already has been patched. Which is true for most high
638	* volume traps, because these are handled specially, but not for odd ones like #DE.)
639	*/
640	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
641	{
642	CSAMR3CheckGates(pVM, u8TrapNo, 1);
643	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
644
645	/* If it was successful, then we could go back to raw mode. */
646	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
647	{
648	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
649	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
650	AssertRCReturn(rc, rc);
651
652	TRPMERRORCODE enmError = uErrorCode != ~0U
653	? TRPM_TRAP_HAS_ERRORCODE
654	: TRPM_TRAP_NO_ERRORCODE;
655	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
656	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
657	{
658	TRPMResetTrap(pVCpu);
659	return VINF_EM_RESCHEDULE_RAW;
660	}
661	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
662	}
663	}
664
665	/*
666	* Scan kernel code that traps; we might not get another chance.
667	*/
668	/** @todo move this up before the dispatching? */
669	if ( (pCtx->ss & X86_SEL_RPL) <= 1
670	&& !pCtx->eflags.Bits.u1VM)
671	{
672	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
673	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
674	}
675
676	/*
677	* Trap specific handling.
678	*/
679	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
680	{
681	/*
682	* If MONITOR & MWAIT are supported, then interpret them here.
683	*/
684	DISCPUSTATE cpu;
685	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
686	if ( RT_SUCCESS(rc)
687	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
688	{
689	uint32_t u32Dummy, u32Features, u32ExtFeatures;
690	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
691	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
692	{
693	rc = TRPMResetTrap(pVCpu);
694	AssertRC(rc);
695
696	uint32_t opsize;
697	rc = EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, &opsize);
698	if (RT_SUCCESS(rc))
699	{
700	pCtx->rip += cpu.opsize;
701	return rc;
702	}
703	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
704	}
705	}
706	}
707	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
708	{
709	/*
710	* Handle I/O bitmap?
711	*/
712	/** @todo We're not supposed to be here with a false guest trap concerning
713	* I/O access. We can easily handle those in RC. */
714	DISCPUSTATE cpu;
715	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
716	if ( RT_SUCCESS(rc)
717	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
718	{
719	/*
720	* We should really check the TSS for the IO bitmap, but it's not like this
721	* lazy approach really makes things worse.
722	*/
723	rc = TRPMResetTrap(pVCpu);
724	AssertRC(rc);
725	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
726	}
727	}
728
729	#ifdef LOG_ENABLED
730	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
731	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
732
733	/* Get guest page information. */
734	uint64_t fFlags = 0;
735	RTGCPHYS GCPhys = 0;
736	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
737	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
738	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
739	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
740	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
741	#endif
742
743	/*
744	* #PG has CR2.
745	* (Because of stuff like above we must set CR2 in a delayed fashion.)
746	*/
747	if (u8TrapNo == 14 /* #PG */)
748	pCtx->cr2 = uCR2;
749
750	return VINF_EM_RESCHEDULE_REM;
751	}
752
753
754	/**
755	* Handle a ring switch trap.
756	* Need to do statistics and to install patches. The result is going to REM.
757	*
758	* @returns VBox status code suitable for EM.
759	* @param pVM VM handle.
760	* @param pVCpu VMCPU handle.
761	*/
762	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
763	{
764	int rc;
765	DISCPUSTATE Cpu;
766	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
767
768	/*
769	* sysenter, syscall & callgate
770	*/
771	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
772	if (RT_SUCCESS(rc))
773	{
774	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
775	{
776	if (pCtx->SysEnter.cs != 0)
777	{
778	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
779	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
780	if (RT_SUCCESS(rc))
781	{
782	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
783	return VINF_EM_RESCHEDULE_RAW;
784	}
785	}
786	}
787
788	#ifdef VBOX_WITH_STATISTICS
789	switch (Cpu.pCurInstr->opcode)
790	{
791	case OP_SYSENTER:
792	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
793	break;
794	case OP_SYSEXIT:
795	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
796	break;
797	case OP_SYSCALL:
798	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
799	break;
800	case OP_SYSRET:
801	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
802	break;
803	}
804	#endif
805	}
806	else
807	AssertRC(rc);
808
809	/* go to the REM to emulate a single instruction */
810	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
811	}
812
813
814	/**
815	* Handle a trap (\#PF or \#GP) in patch code
816	*
817	* @returns VBox status code suitable for EM.
818	* @param pVM VM handle.
819	* @param pVCpu VMCPU handle.
820	* @param pCtx CPU context
821	* @param gcret GC return code
822	*/
823	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
824	{
825	uint8_t u8TrapNo;
826	int rc;
827	TRPMEVENT enmType;
828	RTGCUINT uErrorCode;
829	RTGCUINTPTR uCR2;
830
831	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
832
833	if (gcret == VINF_PATM_PATCH_INT3)
834	{
835	u8TrapNo = 3;
836	uCR2 = 0;
837	uErrorCode = 0;
838	}
839	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
840	{
841	/* No active trap in this case. Kind of ugly. */
842	u8TrapNo = X86_XCPT_GP;
843	uCR2 = 0;
844	uErrorCode = 0;
845	}
846	else
847	{
848	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
849	if (RT_FAILURE(rc))
850	{
851	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
852	return rc;
853	}
854	/* Reset the trap as we'll execute the original instruction again. */
855	TRPMResetTrap(pVCpu);
856	}
857
858	/*
859	* Deal with traps inside patch code.
860	* (This code won't run outside GC.)
861	*/
862	if (u8TrapNo != 1)
863	{
864	#ifdef LOG_ENABLED
865	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
866	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
867
868	DISCPUSTATE Cpu;
869	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
870	if ( RT_SUCCESS(rc)
871	&& Cpu.pCurInstr->opcode == OP_IRET)
872	{
873	uint32_t eip, selCS, uEFlags;
874
875	/* Iret crashes are bad as we have already changed the flags on the stack */
876	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
877	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
878	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
879	if (rc == VINF_SUCCESS)
880	{
881	if ( (uEFlags & X86_EFL_VM)
882	\|\| (selCS & X86_SEL_RPL) == 3)
883	{
884	uint32_t selSS, esp;
885
886	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
887	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
888
889	if (uEFlags & X86_EFL_VM)
890	{
891	uint32_t selDS, selES, selFS, selGS;
892	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
893	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
894	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
895	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
896	if (rc == VINF_SUCCESS)
897	{
898	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
899	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
900	}
901	}
902	else
903	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
904	}
905	else
906	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
907	}
908	}
909	#endif /* LOG_ENABLED */
910	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
911	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
912
913	RTGCPTR pNewEip;
914	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
915	switch (rc)
916	{
917	/*
918	* Execute the faulting instruction.
919	*/
920	case VINF_SUCCESS:
921	{
922	/** @todo execute a whole block */
923	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
924	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
925	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
926
927	pCtx->eip = pNewEip;
928	AssertRelease(pCtx->eip);
929
930	if (pCtx->eflags.Bits.u1IF)
931	{
932	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
933	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
934	*/
935	if ( u8TrapNo == X86_XCPT_GP
936	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
937	{
938	/** @todo move to PATMR3HandleTrap */
939	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
940	PATMR3RemovePatch(pVM, pCtx->eip);
941	}
942
943	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
944	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
945
946	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
947	/* Interrupts are enabled; just go back to the original instruction.
948	return VINF_SUCCESS; */
949	}
950	return VINF_EM_RESCHEDULE_REM;
951	}
952
953	/*
954	* One instruction.
955	*/
956	case VINF_PATCH_EMULATE_INSTR:
957	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
958	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
959	pCtx->eip = pNewEip;
960	AssertRelease(pCtx->eip);
961	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
962
963	/*
964	* The patch was disabled, hand it to the REM.
965	*/
966	case VERR_PATCH_DISABLED:
967	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
968	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
969	pCtx->eip = pNewEip;
970	AssertRelease(pCtx->eip);
971
972	if (pCtx->eflags.Bits.u1IF)
973	{
974	/*
975	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
976	*/
977	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
978	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
979	}
980	return VINF_EM_RESCHEDULE_REM;
981
982	/* Force continued patch exection; usually due to write monitored stack. */
983	case VINF_PATCH_CONTINUE:
984	return VINF_SUCCESS;
985
986	/*
987	* Anything else is fatal.
988	*/
989	default:
990	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
991	return VERR_IPE_UNEXPECTED_STATUS;
992	}
993	}
994	return VINF_SUCCESS;
995	}
996
997
998	/**
999	* Handle a privileged instruction.
1000	*
1001	* @returns VBox status code suitable for EM.
1002	* @param pVM VM handle.
1003	* @param pVCpu VMCPU handle;
1004	*/
1005	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
1006	{
1007	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1008
1009	Assert(!pCtx->eflags.Bits.u1VM);
1010
1011	if (PATMIsEnabled(pVM))
1012	{
1013	/*
1014	* Check if in patch code.
1015	*/
1016	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1017	{
1018	#ifdef LOG_ENABLED
1019	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1020	#endif
1021	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1022	return VERR_EM_RAW_PATCH_CONFLICT;
1023	}
1024	if ( (pCtx->ss & X86_SEL_RPL) == 0
1025	&& !pCtx->eflags.Bits.u1VM
1026	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1027	{
1028	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1029	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1030	if (RT_SUCCESS(rc))
1031	{
1032	#ifdef LOG_ENABLED
1033	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1034	#endif
1035	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
1036	return VINF_SUCCESS;
1037	}
1038	}
1039	}
1040
1041	#ifdef LOG_ENABLED
1042	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1043	{
1044	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1045	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1046	}
1047	#endif
1048
1049	/*
1050	* Instruction statistics and logging.
1051	*/
1052	DISCPUSTATE Cpu;
1053	int rc;
1054
1055	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1056	if (RT_SUCCESS(rc))
1057	{
1058	#ifdef VBOX_WITH_STATISTICS
1059	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
1060	switch (Cpu.pCurInstr->opcode)
1061	{
1062	case OP_INVLPG:
1063	STAM_COUNTER_INC(&pStats->StatInvlpg);
1064	break;
1065	case OP_IRET:
1066	STAM_COUNTER_INC(&pStats->StatIret);
1067	break;
1068	case OP_CLI:
1069	STAM_COUNTER_INC(&pStats->StatCli);
1070	emR3RecordCli(pVM, pVCpu, pCtx->rip);
1071	break;
1072	case OP_STI:
1073	STAM_COUNTER_INC(&pStats->StatSti);
1074	break;
1075	case OP_INSB:
1076	case OP_INSWD:
1077	case OP_IN:
1078	case OP_OUTSB:
1079	case OP_OUTSWD:
1080	case OP_OUT:
1081	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1082	break;
1083
1084	case OP_MOV_CR:
1085	if (Cpu.param1.flags & USE_REG_GEN32)
1086	{
1087	//read
1088	Assert(Cpu.param2.flags & USE_REG_CR);
1089	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1090	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1091	}
1092	else
1093	{
1094	//write
1095	Assert(Cpu.param1.flags & USE_REG_CR);
1096	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1097	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1098	}
1099	break;
1100
1101	case OP_MOV_DR:
1102	STAM_COUNTER_INC(&pStats->StatMovDRx);
1103	break;
1104	case OP_LLDT:
1105	STAM_COUNTER_INC(&pStats->StatMovLldt);
1106	break;
1107	case OP_LIDT:
1108	STAM_COUNTER_INC(&pStats->StatMovLidt);
1109	break;
1110	case OP_LGDT:
1111	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1112	break;
1113	case OP_SYSENTER:
1114	STAM_COUNTER_INC(&pStats->StatSysEnter);
1115	break;
1116	case OP_SYSEXIT:
1117	STAM_COUNTER_INC(&pStats->StatSysExit);
1118	break;
1119	case OP_SYSCALL:
1120	STAM_COUNTER_INC(&pStats->StatSysCall);
1121	break;
1122	case OP_SYSRET:
1123	STAM_COUNTER_INC(&pStats->StatSysRet);
1124	break;
1125	case OP_HLT:
1126	STAM_COUNTER_INC(&pStats->StatHlt);
1127	break;
1128	default:
1129	STAM_COUNTER_INC(&pStats->StatMisc);
1130	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1131	break;
1132	}
1133	#endif /* VBOX_WITH_STATISTICS */
1134	if ( (pCtx->ss & X86_SEL_RPL) == 0
1135	&& !pCtx->eflags.Bits.u1VM
1136	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1137	{
1138	uint32_t size;
1139
1140	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1141	switch (Cpu.pCurInstr->opcode)
1142	{
1143	case OP_CLI:
1144	pCtx->eflags.u32 &= ~X86_EFL_IF;
1145	Assert(Cpu.opsize == 1);
1146	pCtx->rip += Cpu.opsize;
1147	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1148	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1149
1150	case OP_STI:
1151	pCtx->eflags.u32 \|= X86_EFL_IF;
1152	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1153	Assert(Cpu.opsize == 1);
1154	pCtx->rip += Cpu.opsize;
1155	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1156	return VINF_SUCCESS;
1157
1158	case OP_HLT:
1159	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1160	{
1161	PATMTRANSSTATE enmState;
1162	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1163
1164	if (enmState == PATMTRANS_OVERWRITTEN)
1165	{
1166	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1167	Assert(rc == VERR_PATCH_DISABLED);
1168	/* Conflict detected, patch disabled */
1169	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1170
1171	enmState = PATMTRANS_SAFE;
1172	}
1173
1174	/* The translation had better be successful. Otherwise we can't recover. */
1175	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1176	if (enmState != PATMTRANS_OVERWRITTEN)
1177	pCtx->eip = pOrgInstrGC;
1178	}
1179	/* no break; we could just return VINF_EM_HALT here */
1180
1181	case OP_MOV_CR:
1182	case OP_MOV_DR:
1183	#ifdef LOG_ENABLED
1184	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1185	{
1186	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1187	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1188	}
1189	#endif
1190
1191	rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1192	if (RT_SUCCESS(rc))
1193	{
1194	pCtx->rip += Cpu.opsize;
1195	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1196
1197	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1198	&& Cpu.param1.flags == USE_REG_CR /* write */
1199	)
1200	{
1201	/* Deal with CR0 updates inside patch code that force
1202	* us to go to the recompiler.
1203	*/
1204	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1205	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1206	{
1207	PATMTRANSSTATE enmState;
1208	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1209
1210	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1211	if (enmState == PATMTRANS_OVERWRITTEN)
1212	{
1213	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1214	Assert(rc == VERR_PATCH_DISABLED);
1215	/* Conflict detected, patch disabled */
1216	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1217	enmState = PATMTRANS_SAFE;
1218	}
1219	/* The translation had better be successful. Otherwise we can't recover. */
1220	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1221	if (enmState != PATMTRANS_OVERWRITTEN)
1222	pCtx->rip = pOrgInstrGC;
1223	}
1224
1225	/* Reschedule is necessary as the execution/paging mode might have changed. */
1226	return VINF_EM_RESCHEDULE;
1227	}
1228	return rc; /* can return VINF_EM_HALT as well. */
1229	}
1230	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1231	break; /* fall back to the recompiler */
1232	}
1233	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1234	}
1235	}
1236
1237	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1238	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1239
1240	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1241	}
1242
1243
1244	/**
1245	* Update the forced rawmode execution modifier.
1246	*
1247	* This function is called when we're returning from the raw-mode loop(s). If we're
1248	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1249	* if not in patch code, the flag will be cleared.
1250	*
1251	* We should never interrupt patch code while it's being executed. Cli patches can
1252	* contain big code blocks, but they are always executed with IF=0. Other patches
1253	* replace single instructions and should be atomic.
1254	*
1255	* @returns Updated rc.
1256	*
1257	* @param pVM The VM handle.
1258	* @param pVCpu The VMCPU handle.
1259	* @param pCtx The guest CPU context.
1260	* @param rc The result code.
1261	*/
1262	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1263	{
1264	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1265	{
1266	/* ignore reschedule attempts. */
1267	switch (rc)
1268	{
1269	case VINF_EM_RESCHEDULE:
1270	case VINF_EM_RESCHEDULE_REM:
1271	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1272	rc = VINF_SUCCESS;
1273	break;
1274	}
1275	pVCpu->em.s.fForceRAW = true;
1276	}
1277	else
1278	pVCpu->em.s.fForceRAW = false;
1279	return rc;
1280	}
1281
1282
1283	/**
1284	* Check for pending raw actions
1285	*
1286	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1287	* EM statuses.
1288	* @param pVM The VM to operate on.
1289	* @param pVCpu The VMCPU handle.
1290	*/
1291	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1292	{
1293	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1294	}
1295
1296
1297	/**
1298	* Process raw-mode specific forced actions.
1299	*
1300	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1301	*
1302	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1303	* EM statuses.
1304	* @param pVM The VM handle.
1305	* @param pVCpu The VMCPU handle.
1306	* @param pCtx The guest CPUM register context.
1307	*/
1308	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1309	{
1310	/*
1311	* Note that the order is vitally important!
1312	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1313	*/
1314
1315
1316	/*
1317	* Sync selector tables.
1318	*/
1319	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1320	{
1321	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1322	if (RT_FAILURE(rc))
1323	return rc;
1324	}
1325
1326	/*
1327	* Sync IDT.
1328	*
1329	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1330	* and PGMShwModifyPage, so we're in for trouble if for instance a
1331	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1332	*/
1333	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1334	{
1335	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1336	&& EMIsRawRing0Enabled(pVM)
1337	&& CSAMIsEnabled(pVM))
1338	{
1339	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1340	if (RT_FAILURE(rc))
1341	return rc;
1342	}
1343
1344	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1345	if (RT_FAILURE(rc))
1346	return rc;
1347	}
1348
1349	/*
1350	* Sync TSS.
1351	*/
1352	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1353	{
1354	int rc = SELMR3SyncTSS(pVM, pVCpu);
1355	if (RT_FAILURE(rc))
1356	return rc;
1357	}
1358
1359	/*
1360	* Sync page directory.
1361	*/
1362	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1363	{
1364	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1365	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1366	if (RT_FAILURE(rc))
1367	return rc;
1368
1369	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1370
1371	/* Prefetch pages for EIP and ESP. */
1372	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1373	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1374	if (rc == VINF_SUCCESS)
1375	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1376	if (rc != VINF_SUCCESS)
1377	{
1378	if (rc != VINF_PGM_SYNC_CR3)
1379	{
1380	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1381	return rc;
1382	}
1383	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1384	if (RT_FAILURE(rc))
1385	return rc;
1386	}
1387	/** @todo maybe prefetch the supervisor stack page as well */
1388	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1389	}
1390
1391	/*
1392	* Allocate handy pages (just in case the above actions have consumed some pages).
1393	*/
1394	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1395	{
1396	int rc = PGMR3PhysAllocateHandyPages(pVM);
1397	if (RT_FAILURE(rc))
1398	return rc;
1399	}
1400
1401	/*
1402	* Check whether we're out of memory now.
1403	*
1404	* This may stem from some of the above actions or operations that has been executed
1405	* since we ran FFs. The allocate handy pages must for instance always be followed by
1406	* this check.
1407	*/
1408	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1409	return VINF_EM_NO_MEMORY;
1410
1411	return VINF_SUCCESS;
1412	}
1413
1414
1415	/**
1416	* Executes raw code.
1417	*
1418	* This function contains the raw-mode version of the inner
1419	* execution loop (the outer loop being in EMR3ExecuteVM()).
1420	*
1421	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1422	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1423	*
1424	* @param pVM VM handle.
1425	* @param pVCpu VMCPU handle.
1426	* @param pfFFDone Where to store an indicator telling whether or not
1427	* FFs were done before returning.
1428	*/
1429	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1430	{
1431	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1432
1433	int rc = VERR_INTERNAL_ERROR;
1434	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1435	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1436	pVCpu->em.s.fForceRAW = false;
1437	*pfFFDone = false;
1438
1439
1440	/*
1441	*
1442	* Spin till we get a forced action or raw mode status code resulting in
1443	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1444	*
1445	*/
1446	for (;;)
1447	{
1448	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1449
1450	/*
1451	* Check various preconditions.
1452	*/
1453	#ifdef VBOX_STRICT
1454	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1455	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
1456	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1457	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1458	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1459	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1460	&& PGMMapHasConflicts(pVM))
1461	{
1462	PGMMapCheck(pVM);
1463	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1464	return VERR_INTERNAL_ERROR;
1465	}
1466	#endif /* VBOX_STRICT */
1467
1468	/*
1469	* Process high priority pre-execution raw-mode FFs.
1470	*/
1471	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1472	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1473	{
1474	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1475	if (rc != VINF_SUCCESS)
1476	break;
1477	}
1478
1479	/*
1480	* If we're going to execute ring-0 code, the guest state needs to
1481	* be modified a bit and some of the state components (IF, SS/CS RPL,
1482	* and perhaps EIP) needs to be stored with PATM.
1483	*/
1484	rc = CPUMRawEnter(pVCpu, NULL);
1485	if (rc != VINF_SUCCESS)
1486	{
1487	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1488	break;
1489	}
1490
1491	/*
1492	* Scan code before executing it. Don't bother with user mode or V86 code
1493	*/
1494	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1495	&& !pCtx->eflags.Bits.u1VM
1496	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1497	{
1498	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1499	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1500	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1501	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1502	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1503	{
1504	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1505	if (rc != VINF_SUCCESS)
1506	{
1507	rc = CPUMRawLeave(pVCpu, NULL, rc);
1508	break;
1509	}
1510	}
1511	}
1512
1513	#ifdef LOG_ENABLED
1514	/*
1515	* Log important stuff before entering GC.
1516	*/
1517	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1518	if (pCtx->eflags.Bits.u1VM)
1519	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1520	else if ((pCtx->ss & X86_SEL_RPL) == 1)
1521	{
1522	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1523	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1524	}
1525	else if ((pCtx->ss & X86_SEL_RPL) == 3)
1526	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1527	#endif /* LOG_ENABLED */
1528
1529
1530
1531	/*
1532	* Execute the code.
1533	*/
1534	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1535	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1536	rc = VMMR3RawRunGC(pVM, pVCpu);
1537	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1538	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1539
1540	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1541	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1542
1543
1544
1545	/*
1546	* Restore the real CPU state and deal with high priority post
1547	* execution FFs before doing anything else.
1548	*/
1549	rc = CPUMRawLeave(pVCpu, NULL, rc);
1550	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1551	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1552	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1553	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1554
1555	#ifdef VBOX_STRICT
1556	/*
1557	* Assert TSS consistency & rc vs patch code.
1558	*/
1559	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1560	&& EMIsRawRing0Enabled(pVM))
1561	SELMR3CheckTSS(pVM);
1562	switch (rc)
1563	{
1564	case VINF_SUCCESS:
1565	case VINF_EM_RAW_INTERRUPT:
1566	case VINF_PATM_PATCH_TRAP_PF:
1567	case VINF_PATM_PATCH_TRAP_GP:
1568	case VINF_PATM_PATCH_INT3:
1569	case VINF_PATM_CHECK_PATCH_PAGE:
1570	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1571	case VINF_EM_RAW_GUEST_TRAP:
1572	case VINF_EM_RESCHEDULE_RAW:
1573	break;
1574
1575	default:
1576	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1577	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1578	break;
1579	}
1580	/*
1581	* Let's go paranoid!
1582	*/
1583	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1584	&& PGMMapHasConflicts(pVM))
1585	{
1586	PGMMapCheck(pVM);
1587	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1588	return VERR_INTERNAL_ERROR;
1589	}
1590	#endif /* VBOX_STRICT */
1591
1592	/*
1593	* Process the returned status code.
1594	*/
1595	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1596	{
1597	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1598	break;
1599	}
1600	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1601	if (rc != VINF_SUCCESS)
1602	{
1603	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1604	if (rc != VINF_SUCCESS)
1605	{
1606	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1607	break;
1608	}
1609	}
1610
1611	/*
1612	* Check and execute forced actions.
1613	*/
1614	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1615	TMTimerPollVoid(pVM, pVCpu);
1616	#endif
1617	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1618	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1619	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1620	{
1621	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1622
1623	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1624	rc = emR3ForcedActions(pVM, pVCpu, rc);
1625	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1626	if ( rc != VINF_SUCCESS
1627	&& rc != VINF_EM_RESCHEDULE_RAW)
1628	{
1629	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1630	if (rc != VINF_SUCCESS)
1631	{
1632	*pfFFDone = true;
1633	break;
1634	}
1635	}
1636	}
1637	}
1638
1639	/*
1640	* Return to outer loop.
1641	*/
1642	#if defined(LOG_ENABLED) && defined(DEBUG)
1643	RTLogFlush(NULL);
1644	#endif
1645	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1646	return rc;
1647	}
1648

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source: vbox/trunk/src/VBox/VMM/EMRaw.cpp@ 25046

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