EMHandleRCTmpl.h@ 29532

Last change on this file since 29532 was 29329, checked in by vboxsync, 15 years ago
removed VBOX_WITH_VMI
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 11.8 KB

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1	/* $Id: EMHandleRCTmpl.h 29329 2010-05-11 10:18:30Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hwaccm]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___EMHandleRCTmpl_h
19	#define ___EMHandleRCTmpl_h
20
21	/**
22	* Process a subset of the raw-mode return code.
23	*
24	* Since we have to share this with raw-mode single stepping, this inline
25	* function has been created to avoid code duplication.
26	*
27	* @returns VINF_SUCCESS if it's ok to continue raw mode.
28	* @returns VBox status code to return to the EM main loop.
29	*
30	* @param pVM The VM handle
31	* @param pVCpu The VMCPU handle
32	* @param rc The return code.
33	* @param pCtx The guest cpu context.
34	*/
35	#ifdef EMHANDLERC_WITH_PATM
36	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
37	#elif defined(EMHANDLERC_WITH_HWACCM)
38	int emR3HwaccmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
39	#endif
40	{
41	switch (rc)
42	{
43	/*
44	* Common & simple ones.
45	*/
46	case VINF_SUCCESS:
47	break;
48	case VINF_EM_RESCHEDULE_RAW:
49	case VINF_EM_RESCHEDULE_HWACC:
50	case VINF_EM_RAW_INTERRUPT:
51	case VINF_EM_RAW_TO_R3:
52	case VINF_EM_RAW_TIMER_PENDING:
53	case VINF_EM_PENDING_REQUEST:
54	rc = VINF_SUCCESS;
55	break;
56
57	#ifdef EMHANDLERC_WITH_PATM
58	/*
59	* Privileged instruction.
60	*/
61	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
62	case VINF_PATM_PATCH_TRAP_GP:
63	rc = emR3RawPrivileged(pVM, pVCpu);
64	break;
65
66	case VINF_EM_RAW_GUEST_TRAP:
67	/*
68	* Got a trap which needs dispatching.
69	*/
70	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
71	{
72	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
73	rc = VERR_EM_RAW_PATCH_CONFLICT;
74	break;
75	}
76	rc = emR3RawGuestTrap(pVM, pVCpu);
77	break;
78
79	/*
80	* Trap in patch code.
81	*/
82	case VINF_PATM_PATCH_TRAP_PF:
83	case VINF_PATM_PATCH_INT3:
84	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
85	break;
86
87	case VINF_PATM_DUPLICATE_FUNCTION:
88	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
89	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
90	AssertRC(rc);
91	rc = VINF_SUCCESS;
92	break;
93
94	case VINF_PATM_CHECK_PATCH_PAGE:
95	rc = PATMR3HandleMonitoredPage(pVM);
96	AssertRC(rc);
97	rc = VINF_SUCCESS;
98	break;
99
100	/*
101	* Patch manager.
102	*/
103	case VERR_EM_RAW_PATCH_CONFLICT:
104	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
105	break;
106	#endif /* EMHANDLERC_WITH_PATM */
107
108	#ifdef EMHANDLERC_WITH_PATM
109	/*
110	* Memory mapped I/O access - attempt to patch the instruction
111	*/
112	case VINF_PATM_HC_MMIO_PATCH_READ:
113	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
114	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
115	if (RT_FAILURE(rc))
116	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
117	break;
118
119	case VINF_PATM_HC_MMIO_PATCH_WRITE:
120	AssertFailed(); /* not yet implemented. */
121	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
122	break;
123	#endif /* EMHANDLERC_WITH_PATM */
124
125	/*
126	* Conflict or out of page tables.
127	*
128	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
129	* do here is to execute the pending forced actions.
130	*/
131	case VINF_PGM_SYNC_CR3:
132	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
133	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
134	rc = VINF_SUCCESS;
135	break;
136
137	/*
138	* PGM pool flush pending (guest SMP only).
139	*/
140	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
141	* if the EMT thread that's supposed to handle the flush is currently not active
142	* (e.g. waiting to be scheduled) -> fix this properly!
143	*
144	* bird: Since the clearing is global and done via a rendezvous any CPU can do
145	* it. They would have to choose who to call VMMR3EmtRendezvous and send
146	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
147	* all that well since the the latter will race the setup done by the
148	* first. Guess that means we need some new magic in that area for
149	* handling this case. :/
150	*/
151	case VINF_PGM_POOL_FLUSH_PENDING:
152	rc = VINF_SUCCESS;
153	break;
154
155	/*
156	* Paging mode change.
157	*/
158	case VINF_PGM_CHANGE_MODE:
159	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
160	if (rc == VINF_SUCCESS)
161	rc = VINF_EM_RESCHEDULE;
162	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
163	break;
164
165	#ifdef EMHANDLERC_WITH_PATM
166	/*
167	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
168	*/
169	case VINF_CSAM_PENDING_ACTION:
170	rc = VINF_SUCCESS;
171	break;
172
173	/*
174	* Invoked Interrupt gate - must directly (!) go to the recompiler.
175	*/
176	case VINF_EM_RAW_INTERRUPT_PENDING:
177	case VINF_EM_RAW_RING_SWITCH_INT:
178	Assert(TRPMHasTrap(pVCpu));
179	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
180
181	if (TRPMHasTrap(pVCpu))
182	{
183	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
184	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
185	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
186	{
187	CSAMR3CheckGates(pVM, u8Interrupt, 1);
188	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
189	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
190	}
191	}
192	rc = VINF_EM_RESCHEDULE_REM;
193	break;
194
195	/*
196	* Other ring switch types.
197	*/
198	case VINF_EM_RAW_RING_SWITCH:
199	rc = emR3RawRingSwitch(pVM, pVCpu);
200	break;
201	#endif /* EMHANDLERC_WITH_PATM */
202
203	/*
204	* I/O Port access - emulate the instruction.
205	*/
206	case VINF_IOM_HC_IOPORT_READ:
207	case VINF_IOM_HC_IOPORT_WRITE:
208	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
209	break;
210
211	/*
212	* Memory mapped I/O access - emulate the instruction.
213	*/
214	case VINF_IOM_HC_MMIO_READ:
215	case VINF_IOM_HC_MMIO_WRITE:
216	case VINF_IOM_HC_MMIO_READ_WRITE:
217	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
218	break;
219
220	#ifdef EMHANDLERC_WITH_HWACCM
221	/*
222	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
223	*/
224	case VINF_EM_RAW_EMULATE_IO_BLOCK:
225	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
226	break;
227
228	case VINF_EM_HWACCM_PATCH_TPR_INSTR:
229	rc = HWACCMR3PatchTprInstr(pVM, pVCpu, pCtx);
230	break;
231	#endif
232
233	#ifdef EMHANDLERC_WITH_PATM
234	/*
235	* Execute instruction.
236	*/
237	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
238	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
239	break;
240	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
241	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
242	break;
243	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
244	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
245	break;
246	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
247	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
248	break;
249	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
250	rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
251	break;
252	case VINF_EM_RAW_EMULATE_INSTR_HLT:
253	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
254	rc = emR3RawPrivileged(pVM, pVCpu);
255	break;
256	#endif
257
258	#ifdef EMHANDLERC_WITH_PATM
259	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
260	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
261	break;
262
263	case VINF_PATCH_EMULATE_INSTR:
264	#else
265	case VINF_EM_RAW_GUEST_TRAP:
266	#endif
267	case VINF_EM_RAW_EMULATE_INSTR:
268	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
269	break;
270
271	#ifdef EMHANDLERC_WITH_PATM
272	/*
273	* Stale selector and iret traps => REM.
274	*/
275	case VINF_EM_RAW_STALE_SELECTOR:
276	case VINF_EM_RAW_IRET_TRAP:
277	/* We will not go to the recompiler if EIP points to patch code. */
278	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
279	{
280	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
281	}
282	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
283	rc = VINF_EM_RESCHEDULE_REM;
284	break;
285	#endif
286
287	/*
288	* Up a level.
289	*/
290	case VINF_EM_TERMINATE:
291	case VINF_EM_OFF:
292	case VINF_EM_RESET:
293	case VINF_EM_SUSPEND:
294	case VINF_EM_HALT:
295	case VINF_EM_RESUME:
296	case VINF_EM_NO_MEMORY:
297	case VINF_EM_RESCHEDULE:
298	case VINF_EM_RESCHEDULE_REM:
299	case VINF_EM_WAIT_SIPI:
300	break;
301
302	/*
303	* Up a level and invoke the debugger.
304	*/
305	case VINF_EM_DBG_STEPPED:
306	case VINF_EM_DBG_BREAKPOINT:
307	case VINF_EM_DBG_STEP:
308	case VINF_EM_DBG_HYPER_BREAKPOINT:
309	case VINF_EM_DBG_HYPER_STEPPED:
310	case VINF_EM_DBG_HYPER_ASSERTION:
311	case VINF_EM_DBG_STOP:
312	break;
313
314	/*
315	* Up a level, dump and debug.
316	*/
317	case VERR_TRPM_DONT_PANIC:
318	case VERR_TRPM_PANIC:
319	case VERR_VMM_RING0_ASSERTION:
320	case VERR_VMM_HYPER_CR3_MISMATCH:
321	case VERR_VMM_RING3_CALL_DISABLED:
322	break;
323
324	#ifdef EMHANDLERC_WITH_HWACCM
325	/*
326	* Up a level, after HwAccM have done some release logging.
327	*/
328	case VERR_VMX_INVALID_VMCS_FIELD:
329	case VERR_VMX_INVALID_VMCS_PTR:
330	case VERR_VMX_INVALID_VMXON_PTR:
331	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
332	case VERR_VMX_UNEXPECTED_EXCEPTION:
333	case VERR_VMX_UNEXPECTED_EXIT_CODE:
334	case VERR_VMX_INVALID_GUEST_STATE:
335	case VERR_VMX_UNABLE_TO_START_VM:
336	case VERR_VMX_UNABLE_TO_RESUME_VM:
337	HWACCMR3CheckError(pVM, rc);
338	break;
339
340	/* Up a level; fatal */
341	case VERR_VMX_IN_VMX_ROOT_MODE:
342	case VERR_SVM_IN_USE:
343	break;
344	#endif
345
346	/*
347	* Anything which is not known to us means an internal error
348	* and the termination of the VM!
349	*/
350	default:
351	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
352	break;
353	}
354	return rc;
355	}
356
357	#endif
358

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source: vbox/trunk/src/VBox/VMM/EMHandleRCTmpl.h@ 29532

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