EMHandleRCTmpl.h@ 28425

Last change on this file since 28425 was 26271, checked in by vboxsync, 15 years ago
VMM: warnings. Changed PATMIsPatchGCAddr and CSAMIsKnownDangerousInstr to take RTRCUINTPTR instead of RTRCPTR so we can mostly avoid having to cast the parameter.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 12.2 KB

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1	/* $Id: EMHandleRCTmpl.h 26271 2010-02-05 04:04:36Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hwaccm]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___EMHandleRCTmpl_h
23	#define ___EMHandleRCTmpl_h
24
25	/**
26	* Process a subset of the raw-mode return code.
27	*
28	* Since we have to share this with raw-mode single stepping, this inline
29	* function has been created to avoid code duplication.
30	*
31	* @returns VINF_SUCCESS if it's ok to continue raw mode.
32	* @returns VBox status code to return to the EM main loop.
33	*
34	* @param pVM The VM handle
35	* @param pVCpu The VMCPU handle
36	* @param rc The return code.
37	* @param pCtx The guest cpu context.
38	*/
39	#ifdef EMHANDLERC_WITH_PATM
40	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
41	#elif defined(EMHANDLERC_WITH_HWACCM)
42	int emR3HwaccmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
43	#endif
44	{
45	switch (rc)
46	{
47	/*
48	* Common & simple ones.
49	*/
50	case VINF_SUCCESS:
51	break;
52	case VINF_EM_RESCHEDULE_RAW:
53	case VINF_EM_RESCHEDULE_HWACC:
54	case VINF_EM_RAW_INTERRUPT:
55	case VINF_EM_RAW_TO_R3:
56	case VINF_EM_RAW_TIMER_PENDING:
57	case VINF_EM_PENDING_REQUEST:
58	rc = VINF_SUCCESS;
59	break;
60
61	#ifdef EMHANDLERC_WITH_PATM
62	/*
63	* Privileged instruction.
64	*/
65	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
66	case VINF_PATM_PATCH_TRAP_GP:
67	rc = emR3RawPrivileged(pVM, pVCpu);
68	break;
69
70	case VINF_EM_RAW_GUEST_TRAP:
71	/*
72	* Got a trap which needs dispatching.
73	*/
74	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
75	{
76	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
77	rc = VERR_EM_RAW_PATCH_CONFLICT;
78	break;
79	}
80	rc = emR3RawGuestTrap(pVM, pVCpu);
81	break;
82
83	/*
84	* Trap in patch code.
85	*/
86	case VINF_PATM_PATCH_TRAP_PF:
87	case VINF_PATM_PATCH_INT3:
88	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
89	break;
90
91	case VINF_PATM_DUPLICATE_FUNCTION:
92	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
93	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
94	AssertRC(rc);
95	rc = VINF_SUCCESS;
96	break;
97
98	case VINF_PATM_CHECK_PATCH_PAGE:
99	rc = PATMR3HandleMonitoredPage(pVM);
100	AssertRC(rc);
101	rc = VINF_SUCCESS;
102	break;
103
104	/*
105	* Patch manager.
106	*/
107	case VERR_EM_RAW_PATCH_CONFLICT:
108	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
109	break;
110	#endif /* EMHANDLERC_WITH_PATM */
111
112	#ifdef VBOX_WITH_VMI
113	/*
114	* PARAV function.
115	*/
116	case VINF_EM_RESCHEDULE_PARAV:
117	rc = PARAVCallFunction(pVM);
118	break;
119	#endif
120
121	#ifdef EMHANDLERC_WITH_PATM
122	/*
123	* Memory mapped I/O access - attempt to patch the instruction
124	*/
125	case VINF_PATM_HC_MMIO_PATCH_READ:
126	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
127	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
128	if (RT_FAILURE(rc))
129	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
130	break;
131
132	case VINF_PATM_HC_MMIO_PATCH_WRITE:
133	AssertFailed(); /* not yet implemented. */
134	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
135	break;
136	#endif /* EMHANDLERC_WITH_PATM */
137
138	/*
139	* Conflict or out of page tables.
140	*
141	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
142	* do here is to execute the pending forced actions.
143	*/
144	case VINF_PGM_SYNC_CR3:
145	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
146	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
147	rc = VINF_SUCCESS;
148	break;
149
150	/*
151	* PGM pool flush pending (guest SMP only).
152	*/
153	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
154	* if the EMT thread that's supposed to handle the flush is currently not active
155	* (e.g. waiting to be scheduled) -> fix this properly!
156	*
157	* bird: Since the clearing is global and done via a rendezvous any CPU can do
158	* it. They would have to choose who to call VMMR3EmtRendezvous and send
159	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
160	* all that well since the the latter will race the setup done by the
161	* first. Guess that means we need some new magic in that area for
162	* handling this case. :/
163	*/
164	case VINF_PGM_POOL_FLUSH_PENDING:
165	rc = VINF_SUCCESS;
166	break;
167
168	/*
169	* Paging mode change.
170	*/
171	case VINF_PGM_CHANGE_MODE:
172	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
173	if (rc == VINF_SUCCESS)
174	rc = VINF_EM_RESCHEDULE;
175	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
176	break;
177
178	#ifdef EMHANDLERC_WITH_PATM
179	/*
180	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
181	*/
182	case VINF_CSAM_PENDING_ACTION:
183	rc = VINF_SUCCESS;
184	break;
185
186	/*
187	* Invoked Interrupt gate - must directly (!) go to the recompiler.
188	*/
189	case VINF_EM_RAW_INTERRUPT_PENDING:
190	case VINF_EM_RAW_RING_SWITCH_INT:
191	Assert(TRPMHasTrap(pVCpu));
192	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
193
194	if (TRPMHasTrap(pVCpu))
195	{
196	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
197	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
198	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
199	{
200	CSAMR3CheckGates(pVM, u8Interrupt, 1);
201	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
202	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
203	}
204	}
205	rc = VINF_EM_RESCHEDULE_REM;
206	break;
207
208	/*
209	* Other ring switch types.
210	*/
211	case VINF_EM_RAW_RING_SWITCH:
212	rc = emR3RawRingSwitch(pVM, pVCpu);
213	break;
214	#endif /* EMHANDLERC_WITH_PATM */
215
216	/*
217	* I/O Port access - emulate the instruction.
218	*/
219	case VINF_IOM_HC_IOPORT_READ:
220	case VINF_IOM_HC_IOPORT_WRITE:
221	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
222	break;
223
224	/*
225	* Memory mapped I/O access - emulate the instruction.
226	*/
227	case VINF_IOM_HC_MMIO_READ:
228	case VINF_IOM_HC_MMIO_WRITE:
229	case VINF_IOM_HC_MMIO_READ_WRITE:
230	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
231	break;
232
233	#ifdef EMHANDLERC_WITH_HWACCM
234	/*
235	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
236	*/
237	case VINF_EM_RAW_EMULATE_IO_BLOCK:
238	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
239	break;
240
241	case VINF_EM_HWACCM_PATCH_TPR_INSTR:
242	rc = HWACCMR3PatchTprInstr(pVM, pVCpu, pCtx);
243	break;
244	#endif
245
246	#ifdef EMHANDLERC_WITH_PATM
247	/*
248	* Execute instruction.
249	*/
250	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
251	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
252	break;
253	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
254	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
255	break;
256	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
257	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
258	break;
259	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
260	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
261	break;
262	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
263	rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
264	break;
265	case VINF_EM_RAW_EMULATE_INSTR_HLT:
266	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
267	rc = emR3RawPrivileged(pVM, pVCpu);
268	break;
269	#endif
270
271	#ifdef EMHANDLERC_WITH_PATM
272	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
273	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
274	break;
275
276	case VINF_PATCH_EMULATE_INSTR:
277	#else
278	case VINF_EM_RAW_GUEST_TRAP:
279	#endif
280	case VINF_EM_RAW_EMULATE_INSTR:
281	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
282	break;
283
284	#ifdef EMHANDLERC_WITH_PATM
285	/*
286	* Stale selector and iret traps => REM.
287	*/
288	case VINF_EM_RAW_STALE_SELECTOR:
289	case VINF_EM_RAW_IRET_TRAP:
290	/* We will not go to the recompiler if EIP points to patch code. */
291	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
292	{
293	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
294	}
295	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
296	rc = VINF_EM_RESCHEDULE_REM;
297	break;
298	#endif
299
300	/*
301	* Up a level.
302	*/
303	case VINF_EM_TERMINATE:
304	case VINF_EM_OFF:
305	case VINF_EM_RESET:
306	case VINF_EM_SUSPEND:
307	case VINF_EM_HALT:
308	case VINF_EM_RESUME:
309	case VINF_EM_NO_MEMORY:
310	case VINF_EM_RESCHEDULE:
311	case VINF_EM_RESCHEDULE_REM:
312	case VINF_EM_WAIT_SIPI:
313	break;
314
315	/*
316	* Up a level and invoke the debugger.
317	*/
318	case VINF_EM_DBG_STEPPED:
319	case VINF_EM_DBG_BREAKPOINT:
320	case VINF_EM_DBG_STEP:
321	case VINF_EM_DBG_HYPER_BREAKPOINT:
322	case VINF_EM_DBG_HYPER_STEPPED:
323	case VINF_EM_DBG_HYPER_ASSERTION:
324	case VINF_EM_DBG_STOP:
325	break;
326
327	/*
328	* Up a level, dump and debug.
329	*/
330	case VERR_TRPM_DONT_PANIC:
331	case VERR_TRPM_PANIC:
332	case VERR_VMM_RING0_ASSERTION:
333	case VERR_VMM_HYPER_CR3_MISMATCH:
334	case VERR_VMM_RING3_CALL_DISABLED:
335	break;
336
337	#ifdef EMHANDLERC_WITH_HWACCM
338	/*
339	* Up a level, after HwAccM have done some release logging.
340	*/
341	case VERR_VMX_INVALID_VMCS_FIELD:
342	case VERR_VMX_INVALID_VMCS_PTR:
343	case VERR_VMX_INVALID_VMXON_PTR:
344	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
345	case VERR_VMX_UNEXPECTED_EXCEPTION:
346	case VERR_VMX_UNEXPECTED_EXIT_CODE:
347	case VERR_VMX_INVALID_GUEST_STATE:
348	case VERR_VMX_UNABLE_TO_START_VM:
349	case VERR_VMX_UNABLE_TO_RESUME_VM:
350	HWACCMR3CheckError(pVM, rc);
351	break;
352
353	/* Up a level; fatal */
354	case VERR_VMX_IN_VMX_ROOT_MODE:
355	case VERR_SVM_IN_USE:
356	break;
357	#endif
358
359	/*
360	* Anything which is not known to us means an internal error
361	* and the termination of the VM!
362	*/
363	default:
364	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
365	break;
366	}
367	return rc;
368	}
369
370	#endif
371

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source: vbox/trunk/src/VBox/VMM/EMHandleRCTmpl.h@ 28425

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