VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 878

Last change on this file since 878 was 748, checked in by vboxsync, 18 years ago

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1/* $Id: EM.cpp 748 2007-02-07 14:09:17Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor/Manager.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/** @page pg_em EM - The Execution Monitor/Manager
24 *
25 * The Execution Monitor/Manager is responsible for running the VM, scheduling
26 * the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27 * the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28 * the VM.
29 *
30 */
31
32/*******************************************************************************
33* Header Files *
34*******************************************************************************/
35#define LOG_GROUP LOG_GROUP_EM
36#include <VBox/em.h>
37#include <VBox/vmm.h>
38#include <VBox/patm.h>
39#include <VBox/csam.h>
40#include <VBox/selm.h>
41#include <VBox/trpm.h>
42#include <VBox/iom.h>
43#include <VBox/dbgf.h>
44#include <VBox/pgm.h>
45#include <VBox/rem.h>
46#include <VBox/tm.h>
47#include <VBox/mm.h>
48#include <VBox/pdm.h>
49#include <VBox/hwaccm.h>
50#include <VBox/patm.h>
51#include "EMInternal.h"
52#include <VBox/vm.h>
53#include <VBox/cpumdis.h>
54#include <VBox/dis.h>
55#include <VBox/disopcode.h>
56#include <VBox/dbgf.h>
57
58#include <VBox/log.h>
59#include <iprt/thread.h>
60#include <iprt/assert.h>
61#include <iprt/asm.h>
62#include <iprt/semaphore.h>
63#include <iprt/string.h>
64#include <iprt/avl.h>
65#include <iprt/stream.h>
66#include <VBox/param.h>
67#include <VBox/err.h>
68
69
70/*******************************************************************************
71* Internal Functions *
72*******************************************************************************/
73static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75static int emR3Debug(PVM pVM, int rc);
76static int emR3RemStep(PVM pVM);
77static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78static int emR3RawResumeHyper(PVM pVM);
79static int emR3RawStep(PVM pVM);
80DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86static int emR3ForcedActions(PVM pVM, int rc);
87static int emR3RawGuestTrap(PVM pVM);
88
89
90/**
91 * Initializes the EM.
92 *
93 * @returns VBox status code.
94 * @param pVM The VM to operate on.
95 */
96EMR3DECL(int) EMR3Init(PVM pVM)
97{
98 LogFlow(("EMR3Init\n"));
99 /*
100 * Assert alignment and sizes.
101 */
102 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107 /*
108 * Init the structure.
109 */
110 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112 if (VBOX_FAILURE(rc))
113 pVM->fRawR3Enabled = true;
114 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115 if (VBOX_FAILURE(rc))
116 pVM->fRawR0Enabled = true;
117 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118 pVM->em.s.enmState = EMSTATE_NONE;
119 pVM->em.s.fForceRAW = false;
120
121 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122 AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126 /*
127 * Saved state.
128 */
129 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130 NULL, emR3Save, NULL,
131 NULL, emR3Load, NULL);
132 if (VBOX_FAILURE(rc))
133 return rc;
134
135 /*
136 * Statistics.
137 */
138#ifdef VBOX_WITH_STATISTICS
139 PEMSTATS pStats;
140 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
141 if (VBOX_FAILURE(rc))
142 return rc;
143 pVM->em.s.pStatsHC = pStats;
144 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146 STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147 STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149 STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150 STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152 STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153 STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154 STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155 STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156 STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157 STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158 STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159 STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160 STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161 STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162 STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163 STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164 STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165 STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194
195 STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
196 STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
197
198 STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
203 STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
204 STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
205 STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
206 STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
207 STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
234
235 STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
236 STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
237 STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
238 STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
239 STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
245 STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
246 STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
247 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
248 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
257
258 STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
259 STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
260 STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
261 STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
262
263 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
264 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
265 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
266 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
267 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
268 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
269 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
270 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
271 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
272 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
273 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
274 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
275 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
276 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
277 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
278 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
279 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
280 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
281 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
282 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
283 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
284 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
285 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
286 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
287 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
288 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
289
290 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
291 pVM->em.s.pCliStatTree = 0;
292#endif /* VBOX_WITH_STATISTICS */
293
294/* these should be considered for release statistics. */
295 STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
296 STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
297 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
298 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
299 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
300 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
301 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
302 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
303 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
304 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
305 STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
306 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
307 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
308 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
309 STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
310 STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
311
312
313 return VINF_SUCCESS;
314}
315
316
317
318/**
319 * Applies relocations to data and code managed by this
320 * component. This function will be called at init and
321 * whenever the VMM need to relocate it self inside the GC.
322 *
323 * @param pVM The VM.
324 */
325EMR3DECL(void) EMR3Relocate(PVM pVM)
326{
327 LogFlow(("EMR3Relocate\n"));
328 if (pVM->em.s.pStatsHC)
329 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
330}
331
332
333/**
334 * Reset notification.
335 *
336 * @param pVM
337 */
338EMR3DECL(void) EMR3Reset(PVM pVM)
339{
340 LogFlow(("EMR3Reset: \n"));
341 pVM->em.s.fForceRAW = false;
342}
343
344
345/**
346 * Terminates the EM.
347 *
348 * Termination means cleaning up and freeing all resources,
349 * the VM it self is at this point powered off or suspended.
350 *
351 * @returns VBox status code.
352 * @param pVM The VM to operate on.
353 */
354EMR3DECL(int) EMR3Term(PVM pVM)
355{
356 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
357
358 return VINF_SUCCESS;
359}
360
361
362/**
363 * Execute state save operation.
364 *
365 * @returns VBox status code.
366 * @param pVM VM Handle.
367 * @param pSSM SSM operation handle.
368 */
369static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
370{
371 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
372}
373
374
375/**
376 * Execute state load operation.
377 *
378 * @returns VBox status code.
379 * @param pVM VM Handle.
380 * @param pSSM SSM operation handle.
381 * @param u32Version Data layout version.
382 */
383static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
384{
385 /*
386 * Validate version.
387 */
388 if (u32Version != EM_SAVED_STATE_VERSION)
389 {
390 Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
391 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
392 }
393
394 /*
395 * Load the saved state.
396 */
397 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
398 if (VBOX_FAILURE(rc))
399 pVM->em.s.fForceRAW = false;
400
401 Assert(pVM->em.s.pCliStatTree == 0);
402 return rc;
403}
404
405
406/**
407 * Enables or disables a set of raw-mode execution modes.
408 *
409 * @returns VINF_SUCCESS on success.
410 * @returns VINF_RESCHEDULE if a rescheduling might be required.
411 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
412 *
413 * @param pVM The VM to operate on.
414 * @param enmMode The execution mode change.
415 * @thread The emulation thread.
416 */
417EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
418{
419 switch (enmMode)
420 {
421 case EMRAW_NONE:
422 pVM->fRawR3Enabled = false;
423 pVM->fRawR0Enabled = false;
424 break;
425 case EMRAW_RING3_ENABLE:
426 pVM->fRawR3Enabled = true;
427 break;
428 case EMRAW_RING3_DISABLE:
429 pVM->fRawR3Enabled = false;
430 break;
431 case EMRAW_RING0_ENABLE:
432 pVM->fRawR0Enabled = true;
433 break;
434 case EMRAW_RING0_DISABLE:
435 pVM->fRawR0Enabled = false;
436 break;
437 default:
438 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
439 return VERR_INVALID_PARAMETER;
440 }
441 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
442 pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
443 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
444}
445
446
447/**
448 * Raise a fatal error.
449 *
450 * Safely terminate the VM with full state report and stuff. This function
451 * will naturally never return.
452 *
453 * @param pVM VM handle.
454 * @param rc VBox status code.
455 */
456EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
457{
458 longjmp(pVM->em.s.u.FatalLongJump, rc);
459 AssertReleaseMsgFailed(("longjmp returned!\n"));
460}
461
462
463/**
464 * Gets the EM state name.
465 *
466 * @returns pointer to read only state name,
467 * @param enmState The state.
468 */
469EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
470{
471 switch (enmState)
472 {
473 case EMSTATE_RAW: return "EMSTATE_RAW";
474 case EMSTATE_HWACC: return "EMSTATE_HWACC";
475 case EMSTATE_REM: return "EMSTATE_REM";
476 case EMSTATE_HALTED: return "EMSTATE_HALTED";
477 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
478 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
479 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
480 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
481 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
482 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
483 default: return "Unknown!";
484 }
485}
486
487
488#ifdef VBOX_WITH_STATISTICS
489/**
490 * Just a braindead function to keep track of cli addresses.
491 * @param pVM VM handle.
492 * @param pInstrGC The EIP of the cli instruction.
493 */
494static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
495{
496 PCLISTAT pRec;
497
498 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
499 if (!pRec)
500 {
501 /* New cli instruction; insert into the tree. */
502 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
503 Assert(pRec);
504 if (!pRec)
505 return;
506 pRec->Core.Key = (AVLPVKEY)pInstrGC;
507
508 char szCliStatName[32];
509 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
510 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
511
512 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
513 Assert(fRc); NOREF(fRc);
514 }
515 STAM_COUNTER_INC(&pRec->Counter);
516 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
517}
518#endif /* VBOX_WITH_STATISTICS */
519
520
521/**
522 * Debug loop.
523 *
524 * @returns VBox status code for EM.
525 * @param pVM VM handle.
526 * @param rc Current EM VBox status code..
527 */
528static int emR3Debug(PVM pVM, int rc)
529{
530 for (;;)
531 {
532 Log(("emR3Debug: rc=%Vrc\n", rc));
533 const int rcLast = rc;
534
535 /*
536 * Debug related RC.
537 */
538 switch (rc)
539 {
540 /*
541 * Single step an instruction.
542 */
543 case VINF_EM_DBG_STEP:
544 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
545 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
546 || pVM->em.s.fForceRAW /* paranoia */)
547 rc = emR3RawStep(pVM);
548 else
549 {
550 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
551 rc = emR3RemStep(pVM);
552 }
553 break;
554
555 /*
556 * Simple events: stepped, breakpoint, stop/assertion.
557 */
558 case VINF_EM_DBG_STEPPED:
559 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
560 break;
561
562 case VINF_EM_DBG_BREAKPOINT:
563 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
564 break;
565
566 case VINF_EM_DBG_STOP:
567 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
568 break;
569
570 case VINF_EM_DBG_HYPER_STEPPED:
571 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
572 break;
573
574 case VINF_EM_DBG_HYPER_BREAKPOINT:
575 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
576 break;
577
578 case VINF_EM_DBG_HYPER_ASSERTION:
579 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
580 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
581 break;
582
583 /*
584 * Guru meditation.
585 */
586 default: /** @todo don't use default for guru, but make special errors code! */
587 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
588 break;
589 }
590
591 /*
592 * Process the result.
593 */
594 do
595 {
596 switch (rc)
597 {
598 /*
599 * Continue the debugging loop.
600 */
601 case VINF_EM_DBG_STEP:
602 case VINF_EM_DBG_STOP:
603 case VINF_EM_DBG_STEPPED:
604 case VINF_EM_DBG_BREAKPOINT:
605 case VINF_EM_DBG_HYPER_STEPPED:
606 case VINF_EM_DBG_HYPER_BREAKPOINT:
607 case VINF_EM_DBG_HYPER_ASSERTION:
608 break;
609
610 /*
611 * Resuming execution (in some form) has to be done here if we got
612 * a hypervisor debug event.
613 */
614 case VINF_SUCCESS:
615 case VINF_EM_RESUME:
616 case VINF_EM_SUSPEND:
617 case VINF_EM_RESCHEDULE:
618 case VINF_EM_RESCHEDULE_RAW:
619 case VINF_EM_RESCHEDULE_REM:
620 case VINF_EM_HALT:
621 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
622 {
623 rc = emR3RawResumeHyper(pVM);
624 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
625 continue;
626 }
627 if (rc == VINF_SUCCESS)
628 rc = VINF_EM_RESCHEDULE;
629 return rc;
630
631 /*
632 * The debugger isn't attached.
633 * We'll simply turn the thing off since that's the easiest thing to do.
634 */
635 case VERR_DBGF_NOT_ATTACHED:
636 switch (rcLast)
637 {
638 case VINF_EM_DBG_HYPER_ASSERTION:
639 case VINF_EM_DBG_HYPER_STEPPED:
640 case VINF_EM_DBG_HYPER_BREAKPOINT:
641 return rcLast;
642 }
643 return VINF_EM_OFF;
644
645 /*
646 * Status codes terminating the VM in one or another sense.
647 */
648 case VINF_EM_TERMINATE:
649 case VINF_EM_OFF:
650 case VINF_EM_RESET:
651 case VINF_EM_RAW_STALE_SELECTOR:
652 case VINF_EM_RAW_IRET_TRAP:
653 case VERR_TRPM_PANIC:
654 case VERR_TRPM_DONT_PANIC:
655 case VERR_INTERNAL_ERROR:
656 return rc;
657
658 /*
659 * The rest is unexpected, and will keep us here.
660 */
661 default:
662 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
663 break;
664 }
665 } while (false);
666 } /* debug for ever */
667}
668
669
670/**
671 * Steps recompiled code.
672 *
673 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
674 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
675 *
676 * @param pVM VM handle.
677 */
678static int emR3RemStep(PVM pVM)
679{
680 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
681
682 /*
683 * Switch to REM, step instruction, switch back.
684 */
685 int rc = REMR3State(pVM);
686 if (VBOX_SUCCESS(rc))
687 {
688 rc = REMR3Step(pVM);
689 REMR3StateBack(pVM);
690 }
691 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
692 return rc;
693}
694
695/**
696 * Executes recompiled code.
697 *
698 * This function contains the recompiler version of the inner
699 * execution loop (the outer loop being in EMR3ExecuteVM()).
700 *
701 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
702 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
703 *
704 * @param pVM VM handle.
705 * @param pfFFDone Where to store an indicator telling wheter or not
706 * FFs were done before returning.
707 *
708 */
709static int emR3RemExecute(PVM pVM, bool *pfFFDone)
710{
711#ifdef LOG_ENABLED
712 PCPUMCTX pCtx = pVM->em.s.pCtx;
713 if ((pCtx->ss & X86_SEL_RPL) == 0)
714 Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
715#endif
716 STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
717
718#if defined(VBOX_STRICT) && defined(DEBUG_bird)
719 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
720 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
721 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
722#endif
723
724 /*
725 * Spin till we get a forced action which returns anything but VINF_SUCCESS
726 * or the REM suggests raw-mode execution.
727 */
728 *pfFFDone = false;
729 bool fInREMState = false;
730 int rc = VINF_SUCCESS;
731 for (;;)
732 {
733 /*
734 * Update REM state if not already in sync.
735 */
736 if (!fInREMState)
737 {
738 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
739 rc = REMR3State(pVM);
740 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
741 if (VBOX_FAILURE(rc))
742 break;
743 fInREMState = true;
744
745 /*
746 * We might have missed the raising of VMREQ, TIMER and some other
747 * imporant FFs while we were busy switching the state. So, check again.
748 */
749 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
750 {
751 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
752 goto l_REMDoForcedActions;
753 }
754 }
755
756
757 /*
758 * Execute REM.
759 */
760 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
761 rc = REMR3Run(pVM);
762 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
763
764
765 /*
766 * Deal with high priority post execution FFs before doing anything else.
767 */
768 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
769 rc = emR3HighPriorityPostForcedActions(pVM, rc);
770
771 /*
772 * Process the returned status code.
773 * (Try keep this short! Call functions!)
774 */
775 if (rc != VINF_SUCCESS)
776 {
777 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
778 break;
779 if (rc != VINF_REM_INTERRUPED_FF)
780 {
781 /*
782 * Anything which is not known to us means an internal error
783 * and the termination of the VM!
784 */
785 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
786 break;
787 }
788 }
789
790
791 /*
792 * Check and execute forced actions.
793 * Sync back the VM state before calling any of these.
794 */
795#ifdef VBOX_HIGH_RES_TIMERS_HACK
796 TMTimerPoll(pVM);
797#endif
798 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_FLUSH_DIRTY_PAGE | VM_FF_CSAM_SCAN_PAGE)))
799 {
800l_REMDoForcedActions:
801 if (fInREMState)
802 {
803 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
804 REMR3StateBack(pVM);
805 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
806 fInREMState = false;
807 }
808 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
809 rc = emR3ForcedActions(pVM, rc);
810 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
811 if ( rc != VINF_SUCCESS
812 && rc != VINF_EM_RESCHEDULE_REM)
813 {
814 *pfFFDone = true;
815 break;
816 }
817 }
818
819 } /* The Inner Loop, recompiled execution mode version. */
820
821
822 /*
823 * Returning. Sync back the VM state if required.
824 */
825 if (fInREMState)
826 {
827 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
828 REMR3StateBack(pVM);
829 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
830 }
831
832 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
833 return rc;
834}
835
836
837/**
838 * Resumes executing hypervisor after a debug event.
839 *
840 * This is kind of special since our current guest state is
841 * potentially out of sync.
842 *
843 * @returns VBox status code.
844 * @param pVM The VM handle.
845 */
846static int emR3RawResumeHyper(PVM pVM)
847{
848 int rc;
849 PCPUMCTX pCtx = pVM->em.s.pCtx;
850 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
851 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
852
853 /*
854 * Resume execution.
855 */
856 CPUMRawEnter(pVM, NULL);
857 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
858 rc = VMMR3ResumeHyper(pVM);
859 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
860 rc = CPUMRawLeave(pVM, NULL, rc);
861 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
862
863 /*
864 * Deal with the return code.
865 */
866 rc = emR3HighPriorityPostForcedActions(pVM, rc);
867 rc = emR3RawHandleRC(pVM, pCtx, rc);
868 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
869 return rc;
870}
871
872
873/**
874 * Steps rawmode.
875 *
876 * @returns VBox status code.
877 * @param pVM The VM handle.
878 */
879static int emR3RawStep(PVM pVM)
880{
881 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
882 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
883 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
884 int rc;
885 PCPUMCTX pCtx = pVM->em.s.pCtx;
886 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
887#ifndef DEBUG_sandervl
888 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
889 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
890#endif
891 if (fGuest)
892 {
893 /*
894 * Check vital forced actions, but ignore pending interrupts and timers.
895 */
896 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
897 {
898 rc = emR3RawForcedActions(pVM, pCtx);
899 if (VBOX_FAILURE(rc))
900 return rc;
901 }
902
903 /*
904 * Set flags for single stepping.
905 */
906 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
907 }
908 else
909 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
910
911 /*
912 * Single step.
913 * We do not start time or anything, if anything we should just do a few nanoseconds.
914 */
915 CPUMRawEnter(pVM, NULL);
916 do
917 {
918 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
919 rc = VMMR3ResumeHyper(pVM);
920 else
921 rc = VMMR3RawRunGC(pVM);
922#ifndef DEBUG_sandervl
923 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
924 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
925#endif
926 } while ( rc == VINF_SUCCESS
927 || rc == VINF_EM_RAW_INTERRUPT);
928 rc = CPUMRawLeave(pVM, NULL, rc);
929 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
930
931 /*
932 * Make sure the trap flag is cleared.
933 * (Too bad if the guest is trying to single step too.)
934 */
935 if (fGuest)
936 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
937 else
938 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
939
940 /*
941 * Deal with the return codes.
942 */
943 rc = emR3HighPriorityPostForcedActions(pVM, rc);
944 rc = emR3RawHandleRC(pVM, pCtx, rc);
945 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
946 return rc;
947}
948
949#ifdef DEBUG_sandervl
950void emR3SingleStepExec(PVM pVM, uint32_t cIterations)
951{
952 EMSTATE enmOldState = pVM->em.s.enmState;
953 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
954
955 Log(("Single step BEGIN:\n"));
956 for(uint32_t i=0;i<cIterations;i++)
957 {
958 DBGFR3PrgStep(pVM);
959 emR3RawStep(pVM);
960 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
961 }
962 Log(("Single step END:\n"));
963 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
964 pVM->em.s.enmState = enmOldState;
965}
966#endif
967
968/**
969 * Executes one (or perhaps a few more) instruction(s).
970 *
971 * @returns VBox status code suitable for EM.
972 *
973 * @param pVM VM handle.
974 * @param rcGC GC return code
975 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
976 * instruction and prefix the log output with this text.
977 */
978#ifdef LOG_ENABLED
979static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
980#else
981static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
982#endif
983{
984 PCPUMCTX pCtx = pVM->em.s.pCtx;
985 int rc;
986
987 /*
988 *
989 * The simple solution is to use the recompiler.
990 * The better solution is to disassemble the current instruction and
991 * try handle as many as possible without using REM.
992 *
993 */
994
995#ifdef LOG_ENABLED
996 /*
997 * Disassemble the instruction if requested.
998 */
999 if (pszPrefix)
1000 {
1001 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1002 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1003 }
1004#endif /* LOG_ENABLED */
1005
1006
1007 Assert((pCtx->ss & X86_SEL_RPL) != 1);
1008
1009 /*
1010 * PATM is making life more interesting.
1011 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1012 * tell PATM there is a trap in this code and have it take the appropriate actions
1013 * to allow us execute the code in REM.
1014 */
1015 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1016 {
1017 Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1018
1019 RTGCPTR pNewEip;
1020 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1021 switch (rc)
1022 {
1023 /*
1024 * It's not very useful to emulate a single instruction and then go back to raw
1025 * mode; just execute the whole block until IF is set again.
1026 */
1027 case VINF_SUCCESS:
1028 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1029 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1030 pCtx->eip = pNewEip;
1031 Assert(pCtx->eip);
1032
1033 if (pCtx->eflags.Bits.u1IF)
1034 {
1035 /*
1036 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1037 */
1038 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1039 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1040 }
1041#if 0 /** @note no noticable change; revisit later when we can emulate iret ourselves. */
1042 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1043 {
1044 /* special case: iret, that sets IF, detected a pending irq/event */
1045 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1046 }
1047#endif
1048 return VINF_EM_RESCHEDULE_REM;
1049
1050 /*
1051 * One instruction.
1052 */
1053 case VINF_PATCH_EMULATE_INSTR:
1054 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1055 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1056 pCtx->eip = pNewEip;
1057 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1058
1059 /*
1060 * The patch was disabled, hand it to the REM.
1061 */
1062 case VERR_PATCH_DISABLED:
1063 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1064 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1065 pCtx->eip = pNewEip;
1066 if (pCtx->eflags.Bits.u1IF)
1067 {
1068 /*
1069 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1070 */
1071 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1072 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1073 }
1074 return VINF_EM_RESCHEDULE_REM;
1075
1076 /* Force continued patch exection; usually due to write monitored stack. */
1077 case VINF_PATCH_CONTINUE:
1078 return VINF_SUCCESS;
1079
1080 default:
1081 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1082 return VERR_INTERNAL_ERROR;
1083 }
1084 }
1085
1086#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1087 DISCPUSTATE Cpu;
1088 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1089 if (VBOX_SUCCESS(rc))
1090 {
1091 uint32_t size;
1092
1093 switch (Cpu.pCurInstr->opcode)
1094 {
1095 case OP_MOV:
1096 case OP_AND:
1097 case OP_OR:
1098 case OP_XOR:
1099 case OP_POP:
1100 case OP_INC:
1101 case OP_DEC:
1102 case OP_XCHG:
1103 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1104 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1105 if (VBOX_SUCCESS(rc))
1106 {
1107 pCtx->eip += Cpu.opsize;
1108 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1109 return rc;
1110 }
1111 if (rc != VERR_EM_INTERPRETER)
1112 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1113 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1114 break;
1115 }
1116 }
1117#endif
1118 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1119 rc = REMR3EmulateInstruction(pVM);
1120 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1121
1122 return rc;
1123}
1124
1125
1126/**
1127 * Executes one (or perhaps a few more) instruction(s).
1128 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1129 *
1130 * @returns VBox status code suitable for EM.
1131 * @param pVM VM handle.
1132 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1133 * instruction and prefix the log output with this text.
1134 * @param rcGC GC return code
1135 */
1136DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1137{
1138#ifdef LOG_ENABLED
1139 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1140#else
1141 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1142#endif
1143}
1144
1145/**
1146 * Executes one (or perhaps a few more) IO instruction(s).
1147 *
1148 * @returns VBox status code suitable for EM.
1149 * @param pVM VM handle.
1150 */
1151int emR3RawExecuteIOInstruction(PVM pVM)
1152{
1153 int rc;
1154 PCPUMCTX pCtx = pVM->em.s.pCtx;
1155
1156 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1157
1158 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1159 * as io instructions tend to come in packages of more than one
1160 */
1161 DISCPUSTATE Cpu;
1162 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1163 if (VBOX_SUCCESS(rc))
1164 {
1165#ifdef VBOX_WITH_STATISTICS
1166 switch (Cpu.pCurInstr->opcode)
1167 {
1168 case OP_INSB:
1169 case OP_INSWD:
1170 case OP_IN:
1171 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1172 break;
1173
1174 case OP_OUTSB:
1175 case OP_OUTSWD:
1176 case OP_OUT:
1177 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1178 break;
1179 }
1180#endif
1181
1182 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1183 {
1184 OP_PARAMVAL ParmVal;
1185 int rc;
1186 switch (Cpu.pCurInstr->opcode)
1187 {
1188 case OP_IN:
1189 {
1190 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1191 if ( VBOX_FAILURE(rc)
1192 || ParmVal.type != PARMTYPE_IMMEDIATE)
1193 break;
1194
1195 if (!(Cpu.param1.flags & (USE_REG_GEN8 | USE_REG_GEN16 | USE_REG_GEN32)))
1196 break;
1197
1198 /* Make sure port access is allowed */
1199 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1200 if (rc != VINF_SUCCESS)
1201 {
1202 if (rc == VINF_EM_RAW_GUEST_TRAP)
1203 rc = emR3RawGuestTrap(pVM);
1204
1205 return rc;
1206 }
1207
1208 uint32_t u32Value = 0;
1209 switch (Cpu.param1.size)
1210 {
1211 case 1:
1212 Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1213 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1214 if (VBOX_SUCCESS(rc))
1215 {
1216 pCtx->eax = (pCtx->eax & ~0xFF) | (uint8_t)u32Value;
1217 Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1218 pCtx->eip += Cpu.opsize;
1219 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1220 return rc;
1221 }
1222 AssertRC(rc);
1223 break;
1224
1225 case 2:
1226 Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1227 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1228 if (VBOX_SUCCESS(rc))
1229 {
1230 pCtx->eax = (pCtx->eax & ~0xFFFF) | (uint16_t)u32Value;
1231 Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1232 pCtx->eip += Cpu.opsize;
1233 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1234 return rc;
1235 }
1236 AssertRC(rc);
1237 break;
1238
1239 case 4:
1240 Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1241 rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1242 if (VBOX_SUCCESS(rc))
1243 {
1244 pCtx->eax = u32Value;
1245 Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1246 pCtx->eip += Cpu.opsize;
1247 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1248 return rc;
1249 }
1250 AssertRC(rc);
1251 break;
1252
1253 default:
1254 AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1255 break;
1256 }
1257 break;
1258 }
1259
1260 case OP_OUT:
1261 {
1262 // it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1263 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1264 if ( VBOX_FAILURE(rc)
1265 || ParmVal.type != PARMTYPE_IMMEDIATE)
1266 break;
1267 OP_PARAMVAL ParmVal2;
1268 rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1269 if ( VBOX_FAILURE(rc)
1270 || ParmVal2.type != PARMTYPE_IMMEDIATE)
1271 break;
1272
1273 /* Make sure port access is allowed */
1274 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1275 if (rc != VINF_SUCCESS)
1276 {
1277 if (rc == VINF_EM_RAW_GUEST_TRAP)
1278 rc = emR3RawGuestTrap(pVM);
1279
1280 return rc;
1281 }
1282
1283 AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1284 switch (ParmVal2.size)
1285 {
1286 case 1:
1287 Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1288 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1289 if (VBOX_SUCCESS(rc))
1290 {
1291 pCtx->eip += Cpu.opsize;
1292 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1293 return rc;
1294 }
1295 AssertRC(rc);
1296 break;
1297
1298 case 2:
1299 Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1300 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1301 if (VBOX_SUCCESS(rc))
1302 {
1303 pCtx->eip += Cpu.opsize;
1304 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1305 return rc;
1306 }
1307 AssertRC(rc);
1308 break;
1309
1310 case 4:
1311 Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1312 rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1313 if (VBOX_SUCCESS(rc))
1314 {
1315 pCtx->eip += Cpu.opsize;
1316 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1317 return rc;
1318 }
1319 AssertRC(rc);
1320 break;
1321
1322 default:
1323 AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1324 break;
1325 }
1326 break;
1327 }
1328
1329 default:
1330 break;
1331 }
1332 }//if(!(Cpu.prefix & (PREFIX_REP|PREFIX_REPNE))
1333 else if (Cpu.prefix & PREFIX_REP)
1334 {
1335 switch (Cpu.pCurInstr->opcode)
1336 {
1337 case OP_INSB:
1338 case OP_INSWD:
1339 {
1340 /*
1341 * Do not optimize the destination address decrement case (not worth the effort)
1342 * and likewise for 16 bit address size (would need to use and update only cx/di).
1343 */
1344 if (pCtx->eflags.Bits.u1DF || Cpu.addrmode != CPUMODE_32BIT)
1345 break;
1346 /*
1347 * Get port number and transfer count directly from the registers (no need to bother the
1348 * disassembler). And get the I/O register size from the opcode / prefix.
1349 */
1350 uint32_t uPort = pCtx->edx & 0xffff;
1351 RTGCUINTREG cTransfers = pCtx->ecx;
1352 unsigned cbUnit;
1353 if (Cpu.pCurInstr->opcode == OP_INSB)
1354 cbUnit = 1;
1355 else
1356 cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1357
1358 RTGCPTR GCPtrDst = pCtx->edi;
1359 /* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1360 rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1361 X86_PTE_RW | (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1362 if (rc != VINF_SUCCESS)
1363 {
1364 Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1365 break;
1366 }
1367
1368 Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1369
1370 /* Make sure port access is allowed */
1371 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1372 if (rc != VINF_SUCCESS)
1373 {
1374 if (rc == VINF_EM_RAW_GUEST_TRAP)
1375 rc = emR3RawGuestTrap(pVM);
1376
1377 return rc;
1378 }
1379
1380 /*
1381 * If the device supports string transfers, ask it to do as
1382 * much as it wants. The rest is done with single-word transfers.
1383 */
1384 rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1385 AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1386
1387 while (cTransfers && rc == VINF_SUCCESS)
1388 {
1389 uint32_t u32Value;
1390 rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1391 AssertRC(rc);
1392 int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1393 AssertRC(rc2);
1394 GCPtrDst += cbUnit;
1395 cTransfers--;
1396 }
1397 pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1398 pCtx->ecx = cTransfers;
1399 if (!cTransfers && VBOX_SUCCESS(rc))
1400 pCtx->eip += Cpu.opsize;
1401 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1402 return rc;
1403 }
1404 case OP_OUTSB:
1405 case OP_OUTSWD:
1406 {
1407 /*
1408 * Do not optimize the source address decrement case (not worth the effort)
1409 * and likewise for 16 bit address size (would need to use and update only cx/si).
1410 */
1411 if (pCtx->eflags.Bits.u1DF || Cpu.addrmode != CPUMODE_32BIT)
1412 break;
1413 /*
1414 * Get port number and transfer count directly from the registers (no need to bother the
1415 * disassembler). And get the I/O register size from the opcode / prefix.
1416 */
1417 uint32_t uPort = pCtx->edx & 0xffff;
1418 RTGCUINTREG cTransfers = pCtx->ecx;
1419 unsigned cbUnit;
1420 if (Cpu.pCurInstr->opcode == OP_OUTSB)
1421 cbUnit = 1;
1422 else
1423 cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1424
1425 RTGCPTR GCPtrSrc = pCtx->esi;
1426 /* Access verification first; we currently can't recover properly from traps inside this instruction */
1427 rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1428 if (rc != VINF_SUCCESS)
1429 {
1430 Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1431 break;
1432 }
1433
1434 Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1435
1436 /* Make sure port access is allowed */
1437 rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1438 if (rc != VINF_SUCCESS)
1439 {
1440 if (rc == VINF_EM_RAW_GUEST_TRAP)
1441 rc = emR3RawGuestTrap(pVM);
1442
1443 return rc;
1444 }
1445
1446 /*
1447 * If the device supports string transfers, ask it to do as
1448 * much as it wants. The rest is done with single-word transfers.
1449 */
1450 rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1451 AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1452
1453 while (cTransfers && rc == VINF_SUCCESS)
1454 {
1455 uint32_t u32Value;
1456 rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1457 Assert(rc == VINF_SUCCESS);
1458 rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1459 AssertRC(rc);
1460 GCPtrSrc += cbUnit;
1461 cTransfers--;
1462 }
1463 pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1464 pCtx->ecx = cTransfers;
1465 if (!cTransfers && VBOX_SUCCESS(rc))
1466 pCtx->eip += Cpu.opsize;
1467 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1468 return rc;
1469 }
1470 }
1471 }//if(Cpu.prefix & PREFIX_REP)
1472 }
1473
1474 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1475 return emR3RawExecuteInstruction(pVM, "IO: ");
1476}
1477
1478
1479/**
1480 * Handle a guest context trap.
1481 *
1482 * @returns VBox status code suitable for EM.
1483 * @param pVM VM handle.
1484 */
1485static int emR3RawGuestTrap(PVM pVM)
1486{
1487 PCPUMCTX pCtx = pVM->em.s.pCtx;
1488
1489 /*
1490 * Get the trap info.
1491 */
1492 uint8_t u8TrapNo;
1493 bool fSoftwareInterrupt;
1494 RTGCUINT uErrorCode;
1495 RTGCUINTPTR uCR2;
1496 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1497 if (VBOX_FAILURE(rc))
1498 {
1499 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1500 return rc;
1501 }
1502
1503 /* Traps can be directly forwarded in hardware accelerated mode. */
1504 if (HWACCMR3IsActive(pVM))
1505 {
1506#ifdef LOGGING_ENABLED
1507 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1508 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1509#endif
1510 return VINF_EM_RESCHEDULE_HWACC;
1511 }
1512
1513 /** Scan kernel code that traps; we might not get another chance. */
1514 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1515 && pCtx->eflags.Bits.u1VM == 0)
1516 {
1517 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1518 CSAMR3CheckEIP(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid));
1519 }
1520
1521 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1522 {
1523 DISCPUSTATE cpu;
1524
1525 /* If MONITOR & MWAIT are supported, then interpret them here. */
1526 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1527 if ( VBOX_SUCCESS(rc)
1528 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1529 {
1530 uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1531
1532 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1533
1534 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1535 {
1536 rc = TRPMResetTrap(pVM);
1537 AssertRC(rc);
1538
1539 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1540 if (VBOX_SUCCESS(rc))
1541 {
1542 pCtx->eip += cpu.opsize;
1543 return rc;
1544 }
1545 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1546 }
1547 }
1548 }
1549 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1550 {
1551 DISCPUSTATE cpu;
1552
1553 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1554 if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1555 {
1556 /*
1557 * We should really check the TSS for the IO bitmap, but it's not like this
1558 * lazy approach really makes things worse.
1559 */
1560 rc = TRPMResetTrap(pVM);
1561 AssertRC(rc);
1562 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1563 }
1564 }
1565
1566#ifdef LOG_ENABLED
1567 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1568 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1569
1570 /* Get guest page information. */
1571 uint64_t fFlags = 0;
1572 RTGCPHYS GCPhys = 0;
1573 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1574 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1575 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1576 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1577 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1578#endif
1579
1580 /*
1581 * #PG has CR2.
1582 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1583 */
1584 if (u8TrapNo == 14 /* #PG */)
1585 pCtx->cr2 = uCR2;
1586
1587 return VINF_EM_RESCHEDULE_REM;
1588}
1589
1590
1591/**
1592 * Handle a ring switch trap.
1593 * Need to do statistics and to install patches. The result is going to REM.
1594 *
1595 * @returns VBox status code suitable for EM.
1596 * @param pVM VM handle.
1597 */
1598int emR3RawRingSwitch(PVM pVM)
1599{
1600 int rc;
1601 DISCPUSTATE Cpu;
1602 PCPUMCTX pCtx = pVM->em.s.pCtx;
1603
1604 /*
1605 * sysenter, syscall & callgate
1606 */
1607 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1608 if (VBOX_SUCCESS(rc))
1609 {
1610 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1611 {
1612 if (pCtx->SysEnter.cs != 0)
1613 {
1614 rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1615 if (VBOX_SUCCESS(rc))
1616 {
1617 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1618 return VINF_EM_RESCHEDULE_RAW;
1619 }
1620 }
1621 }
1622
1623#ifdef VBOX_WITH_STATISTICS
1624 switch (Cpu.pCurInstr->opcode)
1625 {
1626 case OP_SYSENTER:
1627 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1628 break;
1629 case OP_SYSEXIT:
1630 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1631 break;
1632 case OP_SYSCALL:
1633 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1634 break;
1635 case OP_SYSRET:
1636 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1637 break;
1638 }
1639#endif
1640 }
1641 else
1642 AssertRC(rc);
1643
1644 /* go to the REM to emulate a single instruction */
1645 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1646}
1647
1648/**
1649 * Handle a trap (#PF or #GP) in patch code
1650 *
1651 * @returns VBox status code suitable for EM.
1652 * @param pVM VM handle.
1653 * @param pCtx CPU context
1654 * @param gcret GC return code
1655 */
1656int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1657{
1658 uint8_t u8TrapNo;
1659 int rc;
1660 bool fSoftwareInterrupt;
1661 RTGCUINT uErrorCode;
1662 RTGCUINTPTR uCR2;
1663
1664 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1665
1666 if (gcret == VINF_PATM_PATCH_INT3)
1667 {
1668 u8TrapNo = 3;
1669 uCR2 = 0;
1670 uErrorCode = 0;
1671 }
1672 else
1673 if (gcret == VINF_PATM_PATCH_TRAP_GP)
1674 {
1675 /* No active trap in this case. Kind of ugly. */
1676 u8TrapNo = X86_XCPT_GP;
1677 uCR2 = 0;
1678 uErrorCode = 0;
1679 }
1680 else
1681 {
1682 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1683 if (VBOX_FAILURE(rc))
1684 {
1685 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1686 return rc;
1687 }
1688 /* Reset the trap as we'll execute the original instruction again. */
1689 TRPMResetTrap(pVM);
1690 }
1691
1692 /*
1693 * Deal with traps inside patch code.
1694 * (This code won't run outside GC.)
1695 */
1696 if (u8TrapNo != 1)
1697 {
1698#ifdef LOG_ENABLED
1699 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1700 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1701#endif
1702 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1703 pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1704
1705 RTGCPTR pNewEip;
1706 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1707 switch (rc)
1708 {
1709 /*
1710 * Execute the faulting instruction.
1711 */
1712 case VINF_SUCCESS:
1713 {
1714 /** @todo execute a whole block */
1715 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1716 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1717 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1718
1719 pCtx->eip = pNewEip;
1720 AssertRelease(pCtx->eip);
1721
1722 if (pCtx->eflags.Bits.u1IF)
1723 {
1724 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1725 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1726 */
1727 if ( u8TrapNo == X86_XCPT_GP
1728 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1729 {
1730 /** @todo move to PATMR3HandleTrap */
1731 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1732 PATMR3RemovePatch(pVM, pCtx->eip);
1733 }
1734
1735 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1736 /** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1737
1738 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1739 /* Interrupts are enabled; just go back to the original instruction.
1740 return VINF_SUCCESS; */
1741 }
1742 return VINF_EM_RESCHEDULE_REM;
1743 }
1744
1745 /*
1746 * One instruction.
1747 */
1748 case VINF_PATCH_EMULATE_INSTR:
1749 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1750 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1751 pCtx->eip = pNewEip;
1752 AssertRelease(pCtx->eip);
1753 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1754
1755 /*
1756 * The patch was disabled, hand it to the REM.
1757 */
1758 case VERR_PATCH_DISABLED:
1759 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1760 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1761 pCtx->eip = pNewEip;
1762 AssertRelease(pCtx->eip);
1763
1764 if (pCtx->eflags.Bits.u1IF)
1765 {
1766 /*
1767 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1768 */
1769 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1770 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1771 }
1772 return VINF_EM_RESCHEDULE_REM;
1773
1774 /* Force continued patch exection; usually due to write monitored stack. */
1775 case VINF_PATCH_CONTINUE:
1776 return VINF_SUCCESS;
1777
1778 /*
1779 * Anything else is *fatal*.
1780 */
1781 default:
1782 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1783 return VERR_INTERNAL_ERROR;
1784 }
1785 }
1786 return VINF_SUCCESS;
1787}
1788
1789
1790/**
1791 * Handle a privileged instruction.
1792 *
1793 * @returns VBox status code suitable for EM.
1794 * @param pVM VM handle.
1795 */
1796int emR3RawPrivileged(PVM pVM)
1797{
1798 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1799 PCPUMCTX pCtx = pVM->em.s.pCtx;
1800
1801 if (PATMIsEnabled(pVM))
1802 {
1803 /*
1804 * Check if in patch code.
1805 */
1806 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1807 {
1808#ifdef LOG_ENABLED
1809 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1810#endif
1811 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1812 return VERR_EM_RAW_PATCH_CONFLICT;
1813 }
1814 if ( (pCtx->ss & X86_SEL_RPL) == 0
1815 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1816 {
1817 int rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1818 if (VBOX_SUCCESS(rc))
1819 {
1820#ifdef LOG_ENABLED
1821 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1822#endif
1823 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1824 return VINF_SUCCESS;
1825 }
1826 }
1827 }
1828
1829#ifdef LOG_ENABLED
1830 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1831 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1832#endif
1833
1834 /*
1835 * Instruction statistics and logging.
1836 */
1837 DISCPUSTATE Cpu;
1838 int rc;
1839
1840 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1841 if (VBOX_SUCCESS(rc))
1842 {
1843#ifdef VBOX_WITH_STATISTICS
1844 PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1845 switch (Cpu.pCurInstr->opcode)
1846 {
1847 case OP_INVLPG:
1848 STAM_COUNTER_INC(&pStats->StatInvlpg);
1849 break;
1850 case OP_IRET:
1851 STAM_COUNTER_INC(&pStats->StatIret);
1852 break;
1853 case OP_CLI:
1854 STAM_COUNTER_INC(&pStats->StatCli);
1855 emR3RecordCli(pVM, pCtx->eip);
1856 break;
1857 case OP_STI:
1858 STAM_COUNTER_INC(&pStats->StatSti);
1859 break;
1860 case OP_INSB:
1861 case OP_INSWD:
1862 case OP_IN:
1863 case OP_OUTSB:
1864 case OP_OUTSWD:
1865 case OP_OUT:
1866 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1867 break;
1868
1869 case OP_MOV_CR:
1870 if (Cpu.param1.flags & USE_REG_GEN32)
1871 {
1872 //read
1873 Assert(Cpu.param2.flags & USE_REG_CR);
1874 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1875 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1876 }
1877 else
1878 {
1879 //write
1880 Assert(Cpu.param1.flags & USE_REG_CR);
1881 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1882 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1883 }
1884 break;
1885
1886 case OP_MOV_DR:
1887 STAM_COUNTER_INC(&pStats->StatMovDRx);
1888 break;
1889 case OP_LLDT:
1890 STAM_COUNTER_INC(&pStats->StatMovLldt);
1891 break;
1892 case OP_LIDT:
1893 STAM_COUNTER_INC(&pStats->StatMovLidt);
1894 break;
1895 case OP_LGDT:
1896 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1897 break;
1898 case OP_SYSENTER:
1899 STAM_COUNTER_INC(&pStats->StatSysEnter);
1900 break;
1901 case OP_SYSEXIT:
1902 STAM_COUNTER_INC(&pStats->StatSysExit);
1903 break;
1904 case OP_SYSCALL:
1905 STAM_COUNTER_INC(&pStats->StatSysCall);
1906 break;
1907 case OP_SYSRET:
1908 STAM_COUNTER_INC(&pStats->StatSysRet);
1909 break;
1910 case OP_HLT:
1911 STAM_COUNTER_INC(&pStats->StatHlt);
1912 break;
1913 default:
1914 STAM_COUNTER_INC(&pStats->StatMisc);
1915 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1916 break;
1917 }
1918#endif
1919 if ( (pCtx->ss & X86_SEL_RPL) == 0
1920 && SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid))
1921 {
1922 uint32_t size;
1923
1924 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1925 switch (Cpu.pCurInstr->opcode)
1926 {
1927 case OP_CLI:
1928 pCtx->eflags.u32 &= ~X86_EFL_IF;
1929 Assert(Cpu.opsize == 1);
1930 pCtx->eip += Cpu.opsize;
1931 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1932 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1933
1934 case OP_STI:
1935 pCtx->eflags.u32 |= X86_EFL_IF;
1936 EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1937 Assert(Cpu.opsize == 1);
1938 pCtx->eip += Cpu.opsize;
1939 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1940 return VINF_SUCCESS;
1941
1942 case OP_HLT:
1943 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1944 {
1945 PATMTRANSSTATE enmState;
1946 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1947
1948 if (enmState == PATMTRANS_OVERWRITTEN)
1949 {
1950 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1951 Assert(rc == VERR_PATCH_DISABLED);
1952 /* Conflict detected, patch disabled */
1953 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1954
1955 enmState = PATMTRANS_SAFE;
1956 }
1957
1958 /* The translation had better be successful. Otherwise we can't recover. */
1959 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1960 if (enmState != PATMTRANS_OVERWRITTEN)
1961 pCtx->eip = pOrgInstrGC;
1962 }
1963 /* no break; we could just return VINF_EM_HALT here */
1964
1965 case OP_MOV_CR:
1966 case OP_MOV_DR:
1967 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1968 if (VBOX_SUCCESS(rc))
1969 {
1970 pCtx->eip += Cpu.opsize;
1971 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1972
1973 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1974 && Cpu.param1.flags == USE_REG_CR /* write */
1975 )
1976 {
1977 /* Reschedule is necessary as the execution/paging mode might have changed. */
1978 return VINF_EM_RESCHEDULE;
1979 }
1980 return rc; /* can return VINF_EM_HALT as well. */
1981 }
1982 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1983 break; /* fall back to the recompiler */
1984 }
1985 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1986 }
1987 }
1988
1989 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1990 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1991
1992 return emR3RawExecuteInstruction(pVM, "PRIV");
1993}
1994
1995
1996/**
1997 * Update the forced rawmode execution modifier.
1998 *
1999 * This function is called when we're returning from the raw-mode loop(s). If we're
2000 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
2001 * if not in patch code, the flag will be cleared.
2002 *
2003 * We should never interrupt patch code while it's being executed. Cli patches can
2004 * contain big code blocks, but they are always executed with IF=0. Other patches
2005 * replace single instructions and should be atomic.
2006 *
2007 * @returns Updated rc.
2008 *
2009 * @param pVM The VM handle.
2010 * @param pCtx The guest CPU context.
2011 * @param rc The result code.
2012 */
2013DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
2014{
2015 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
2016 {
2017 /* ignore reschedule attempts. */
2018 switch (rc)
2019 {
2020 case VINF_EM_RESCHEDULE:
2021 case VINF_EM_RESCHEDULE_REM:
2022 rc = VINF_SUCCESS;
2023 break;
2024 }
2025 pVM->em.s.fForceRAW = true;
2026 }
2027 else
2028 pVM->em.s.fForceRAW = false;
2029 return rc;
2030}
2031
2032
2033/**
2034 * Process a subset of the raw-mode return code.
2035 *
2036 * Since we have to share this with raw-mode single stepping, this inline
2037 * function has been created to avoid code duplication.
2038 *
2039 * @returns VINF_SUCCESS if it's ok to continue raw mode.
2040 * @returns VBox status code to return to the EM main loop.
2041 *
2042 * @param pVM The VM handle
2043 * @param rc The return code.
2044 * @param pCtx The guest cpu context.
2045 */
2046DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2047{
2048 switch (rc)
2049 {
2050 /*
2051 * Common & simple ones.
2052 */
2053 case VINF_SUCCESS:
2054 break;
2055 case VINF_EM_RESCHEDULE_RAW:
2056 case VINF_EM_RESCHEDULE_HWACC:
2057 case VINF_EM_RAW_INTERRUPT:
2058 case VINF_EM_RAW_TO_R3:
2059 case VINF_EM_RAW_TIMER_PENDING:
2060 case VINF_EM_PENDING_REQUEST:
2061 rc = VINF_SUCCESS;
2062 break;
2063
2064 /*
2065 * Privileged instruction.
2066 */
2067 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2068 case VINF_PATM_PATCH_TRAP_GP:
2069 rc = emR3RawPrivileged(pVM);
2070 break;
2071
2072 /*
2073 * Got a trap which needs dispatching.
2074 */
2075 case VINF_EM_RAW_GUEST_TRAP:
2076 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2077 {
2078 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2079 rc = VERR_EM_RAW_PATCH_CONFLICT;
2080 break;
2081 }
2082 uint8_t u8Interrupt;
2083
2084 Assert(TRPMHasTrap(pVM));
2085 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2086
2087 if (TRPMHasTrap(pVM))
2088 {
2089 u8Interrupt = TRPMGetTrapNo(pVM);
2090
2091 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2092 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2093 {
2094 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2095 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2096 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2097 }
2098 }
2099 rc = emR3RawGuestTrap(pVM);
2100 break;
2101
2102 /*
2103 * Trap in patch code.
2104 */
2105 case VINF_PATM_PATCH_TRAP_PF:
2106 case VINF_PATM_PATCH_INT3:
2107 rc = emR3PatchTrap(pVM, pCtx, rc);
2108 break;
2109
2110 case VINF_PATM_DUPLICATE_FUNCTION:
2111 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2112 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2113 AssertRC(rc);
2114 rc = VINF_SUCCESS;
2115 break;
2116
2117 case VINF_PATM_CHECK_PATCH_PAGE:
2118 rc = PATMR3HandleMonitoredPage(pVM);
2119 AssertRC(rc);
2120 rc = VINF_SUCCESS;
2121 break;
2122
2123 /*
2124 * Patch manager.
2125 */
2126 case VERR_EM_RAW_PATCH_CONFLICT:
2127 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2128 break;
2129
2130 /*
2131 * Memory mapped I/O access - attempt to patch the instruction
2132 */
2133 case VINF_PATM_HC_MMIO_PATCH_READ:
2134 rc = PATMR3InstallPatch(pVM, pCtx->eip, PATMFL_MMIO_ACCESS | (SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2135 if (VBOX_FAILURE(rc))
2136 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2137 break;
2138
2139 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2140 AssertFailed(); /* not yet implemented. */
2141 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2142 break;
2143
2144 /*
2145 * Conflict or out of page tables.
2146 *
2147 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2148 * do here is to execute the pending forced actions.
2149 */
2150 case VINF_PGM_SYNC_CR3:
2151 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2152 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2153 rc = VINF_SUCCESS;
2154 break;
2155
2156 /*
2157 * Paging mode change.
2158 */
2159 case VINF_PGM_CHANGE_MODE:
2160 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2161 if (VBOX_SUCCESS(rc))
2162 rc = VINF_EM_RESCHEDULE;
2163 break;
2164
2165 /*
2166 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2167 */
2168 case VINF_CSAM_PENDING_ACTION:
2169 rc = VINF_SUCCESS;
2170 break;
2171
2172 /*
2173 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2174 */
2175 case VINF_EM_RAW_INTERRUPT_PENDING:
2176 case VINF_EM_RAW_RING_SWITCH_INT:
2177 {
2178 uint8_t u8Interrupt;
2179
2180 Assert(TRPMHasTrap(pVM));
2181 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2182
2183 if (TRPMHasTrap(pVM))
2184 {
2185 u8Interrupt = TRPMGetTrapNo(pVM);
2186
2187 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2188 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2189 {
2190 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2191 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2192 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2193 }
2194 }
2195 rc = VINF_EM_RESCHEDULE_REM;
2196 break;
2197 }
2198
2199 /*
2200 * Other ring switch types.
2201 */
2202 case VINF_EM_RAW_RING_SWITCH:
2203 rc = emR3RawRingSwitch(pVM);
2204 break;
2205
2206 /*
2207 * REMGCNotifyInvalidatePage() failed because of overflow.
2208 */
2209 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2210 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2211 REMR3ReplayInvalidatedPages(pVM);
2212 break;
2213
2214 /*
2215 * I/O Port access - emulate the instruction.
2216 */
2217 case VINF_IOM_HC_IOPORT_READ:
2218 case VINF_IOM_HC_IOPORT_WRITE:
2219 case VINF_IOM_HC_IOPORT_READWRITE:
2220 rc = emR3RawExecuteIOInstruction(pVM);
2221 break;
2222
2223 /*
2224 * Memory mapped I/O access - emulate the instruction.
2225 */
2226 case VINF_IOM_HC_MMIO_READ:
2227 case VINF_IOM_HC_MMIO_WRITE:
2228 case VINF_IOM_HC_MMIO_READ_WRITE:
2229 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2230 break;
2231
2232 /*
2233 * Execute instruction.
2234 */
2235 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2236 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2237 break;
2238 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2239 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2240 break;
2241 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2242 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2243 break;
2244 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2245 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2246 break;
2247 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2248 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2249 break;
2250
2251 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2252 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2253 rc = emR3RawPrivileged(pVM);
2254 break;
2255
2256 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2257 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2258 break;
2259
2260 case VINF_EM_RAW_EMULATE_INSTR:
2261 case VINF_PATCH_EMULATE_INSTR:
2262 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2263 break;
2264
2265 /*
2266 * Stale selector and iret traps => REM.
2267 */
2268 case VINF_EM_RAW_STALE_SELECTOR:
2269 case VINF_EM_RAW_IRET_TRAP:
2270 /* We will not go to the recompiler if EIP points to patch code. */
2271 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2272 {
2273 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2274 }
2275 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2276 rc = VINF_EM_RESCHEDULE_REM;
2277 break;
2278
2279 /*
2280 * Up a level.
2281 */
2282 case VINF_EM_TERMINATE:
2283 case VINF_EM_OFF:
2284 case VINF_EM_RESET:
2285 case VINF_EM_SUSPEND:
2286 case VINF_EM_HALT:
2287 case VINF_EM_RESUME:
2288 case VINF_EM_RESCHEDULE:
2289 case VINF_EM_RESCHEDULE_REM:
2290 break;
2291
2292 /*
2293 * Up a level and invoke the debugger.
2294 */
2295 case VINF_EM_DBG_STEPPED:
2296 case VINF_EM_DBG_BREAKPOINT:
2297 case VINF_EM_DBG_STEP:
2298 case VINF_EM_DBG_HYPER_ASSERTION:
2299 case VINF_EM_DBG_HYPER_BREAKPOINT:
2300 case VINF_EM_DBG_HYPER_STEPPED:
2301 case VINF_EM_DBG_STOP:
2302 break;
2303
2304 /*
2305 * Up a level, dump and debug.
2306 */
2307 case VERR_TRPM_DONT_PANIC:
2308 case VERR_TRPM_PANIC:
2309 break;
2310
2311 /*
2312 * Anything which is not known to us means an internal error
2313 * and the termination of the VM!
2314 */
2315 default:
2316 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2317 break;
2318 }
2319 return rc;
2320}
2321
2322
2323/**
2324 * Process raw-mode specific forced actions.
2325 *
2326 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2327 *
2328 * @returns VBox status code.
2329 * Only the normal success/failure stuff, no VINF_EM_*.
2330 * @param pVM The VM handle.
2331 * @param pCtx The guest CPUM register context.
2332 */
2333static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2334{
2335 /*
2336 * Note that the order is *vitally* important!
2337 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2338 */
2339
2340
2341 /*
2342 * Sync selector tables.
2343 */
2344 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2345 {
2346 int rc = SELMR3UpdateFromCPUM(pVM);
2347 if (VBOX_FAILURE(rc))
2348 return rc;
2349 }
2350
2351 /*
2352 * Sync IDT.
2353 */
2354 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2355 {
2356 int rc = TRPMR3SyncIDT(pVM);
2357 if (VBOX_FAILURE(rc))
2358 return rc;
2359 }
2360
2361 /*
2362 * Sync TSS.
2363 */
2364 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2365 {
2366 int rc = SELMR3SyncTSS(pVM);
2367 if (VBOX_FAILURE(rc))
2368 return rc;
2369 }
2370
2371 /*
2372 * Sync page directory.
2373 */
2374 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2375 {
2376 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2377 if (VBOX_FAILURE(rc))
2378 return rc;
2379
2380 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2381
2382 /* Prefetch pages for EIP and ESP */
2383 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2384 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2385 if (rc == VINF_SUCCESS)
2386 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2387 if (rc != VINF_SUCCESS)
2388 {
2389 if (rc != VINF_PGM_SYNC_CR3)
2390 return rc;
2391 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2392 if (VBOX_FAILURE(rc))
2393 return rc;
2394 }
2395 /** @todo maybe prefetch the supervisor stack page as well */
2396 }
2397
2398 return VINF_SUCCESS;
2399}
2400
2401
2402/**
2403 * Executes raw code.
2404 *
2405 * This function contains the raw-mode version of the inner
2406 * execution loop (the outer loop being in EMR3ExecuteVM()).
2407 *
2408 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2409 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2410 *
2411 * @param pVM VM handle.
2412 * @param pfFFDone Where to store an indicator telling whether or not
2413 * FFs were done before returning.
2414 */
2415static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2416{
2417 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2418
2419 int rc = VERR_INTERNAL_ERROR;
2420 PCPUMCTX pCtx = pVM->em.s.pCtx;
2421 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2422 pVM->em.s.fForceRAW = false;
2423 *pfFFDone = false;
2424
2425
2426 /*
2427 *
2428 * Spin till we get a forced action or raw mode status code resulting in
2429 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2430 *
2431 */
2432 for (;;)
2433 {
2434 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2435
2436 /*
2437 * Check various preconditions.
2438 */
2439#ifdef VBOX_STRICT
2440 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2441 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2442 Assert((pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2443 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2444 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2445 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2446 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2447 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2448 {
2449 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2450 return VERR_INTERNAL_ERROR;
2451 }
2452#endif /* VBOX_STRICT */
2453
2454 /*
2455 * Process high priority pre-execution raw-mode FFs.
2456 */
2457 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2458 {
2459 rc = emR3RawForcedActions(pVM, pCtx);
2460 if (VBOX_FAILURE(rc))
2461 break;
2462 }
2463
2464 /*
2465 * If we're going to execute ring-0 code, the guest state needs to
2466 * be modified a bit and some of the state components (IF, SS/CS RPL,
2467 * and perhaps EIP) needs to be stored with PATM.
2468 */
2469 rc = CPUMRawEnter(pVM, NULL);
2470 if (rc != VINF_SUCCESS)
2471 {
2472 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2473 break;
2474 }
2475
2476 /*
2477 * Scan code before executing it. Don't bother with user mode or V86 code
2478 */
2479 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2480 && pCtx->eflags.Bits.u1VM == 0
2481 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2482 {
2483 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2484 CSAMR3CheckEIP(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid));
2485 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2486 }
2487
2488#ifdef LOG_ENABLED
2489 /*
2490 * Log important stuff before entering GC.
2491 */
2492 bool fSingleStep = false;
2493 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2494 if ((pCtx->ss & X86_SEL_RPL) == 1 && !fSingleStep)
2495 {
2496 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2497 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2498 }
2499 else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2500 Log(("RV86: %08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2501 else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2502 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2503#endif /* LOG_ENABLED */
2504
2505
2506
2507 /*
2508 * Execute the code.
2509 */
2510 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2511 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2512 VMMR3Unlock(pVM);
2513 rc = VMMR3RawRunGC(pVM);
2514 VMMR3Lock(pVM);
2515 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2516 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2517
2518 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2519 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2520
2521
2522 /*
2523 * Restore the real CPU state and deal with high priority post
2524 * execution FFs before doing anything else.
2525 */
2526 rc = CPUMRawLeave(pVM, NULL, rc);
2527 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2528 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2529 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2530
2531#ifdef PGM_CACHE_VERY_STRICT
2532 /*
2533 * Page manager cache checks.
2534 */
2535 if ( rc == VINF_EM_RAW_INTERRUPT
2536 || rc == VINF_EM_RAW_GUEST_TRAP
2537 || rc == VINF_IOM_HC_IOPORT_READ
2538 || rc == VINF_IOM_HC_IOPORT_WRITE
2539 || rc == VINF_IOM_HC_IOPORT_READWRITE
2540 //|| rc == VINF_PATM_PATCH_INT3
2541 )
2542 pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2543#endif
2544
2545#ifdef VBOX_STRICT
2546 /*
2547 * Assert TSS consistency & rc vs patch code.
2548 */
2549 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2550 && EMIsRawRing0Enabled(pVM))
2551 SELMR3CheckTSS(pVM);
2552 switch (rc)
2553 {
2554 case VINF_SUCCESS:
2555 case VINF_EM_RAW_INTERRUPT:
2556 case VINF_PATM_PATCH_TRAP_PF:
2557 case VINF_PATM_PATCH_TRAP_GP:
2558 case VINF_PATM_PATCH_INT3:
2559 case VINF_PATM_CHECK_PATCH_PAGE:
2560 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2561 case VINF_EM_RAW_GUEST_TRAP:
2562 case VINF_EM_RESCHEDULE_RAW:
2563 break;
2564
2565 default:
2566 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2567 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2568 break;
2569 }
2570 /*
2571 * Let's go paranoid!
2572 */
2573 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2574 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2575 {
2576 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2577 return VERR_INTERNAL_ERROR;
2578 }
2579#endif /* VBOX_STRICT */
2580
2581 /*
2582 * Process the returned status code.
2583 */
2584 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2585 {
2586 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2587 break;
2588 }
2589 rc = emR3RawHandleRC(pVM, pCtx, rc);
2590 if (rc != VINF_SUCCESS)
2591 {
2592 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2593 if (rc != VINF_SUCCESS)
2594 {
2595 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2596 break;
2597 }
2598 }
2599
2600 /*
2601 * Check and execute forced actions.
2602 */
2603#ifdef VBOX_HIGH_RES_TIMERS_HACK
2604 TMTimerPoll(pVM);
2605#endif
2606 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2607 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2608 {
2609 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2610
2611 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2612 rc = emR3ForcedActions(pVM, rc);
2613 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2614 if ( rc != VINF_SUCCESS
2615 && rc != VINF_EM_RESCHEDULE_RAW)
2616 {
2617 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2618 if (rc != VINF_SUCCESS)
2619 {
2620 *pfFFDone = true;
2621 break;
2622 }
2623 }
2624 }
2625 }
2626
2627 /*
2628 * Return to outer loop.
2629 */
2630#if defined(LOG_ENABLED) && defined(DEBUG)
2631 RTLogFlush(NULL);
2632#endif
2633 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2634 return rc;
2635}
2636
2637
2638/**
2639 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2640 *
2641 * This function contains the raw-mode version of the inner
2642 * execution loop (the outer loop being in EMR3ExecuteVM()).
2643 *
2644 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2645 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2646 *
2647 * @param pVM VM handle.
2648 * @param pfFFDone Where to store an indicator telling whether or not
2649 * FFs were done before returning.
2650 */
2651static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2652{
2653 int rc = VERR_INTERNAL_ERROR;
2654 PCPUMCTX pCtx = pVM->em.s.pCtx;
2655
2656 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2657 *pfFFDone = false;
2658
2659 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2660
2661 /*
2662 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2663 */
2664 for (;;)
2665 {
2666 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2667
2668 /*
2669 * Check various preconditions.
2670 */
2671 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2672
2673 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2674
2675 /*
2676 * Sync page directory.
2677 */
2678 if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2679 {
2680 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2681 if (VBOX_FAILURE(rc))
2682 return rc;
2683
2684 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2685
2686 /* Prefetch pages for EIP and ESP */
2687 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2688 if (rc == VINF_SUCCESS)
2689 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2690 if (rc != VINF_SUCCESS)
2691 {
2692 if (rc != VINF_PGM_SYNC_CR3)
2693 return rc;
2694 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2695 if (VBOX_FAILURE(rc))
2696 return rc;
2697 }
2698
2699 /** @todo maybe prefetch the supervisor stack page as well */
2700 }
2701
2702#ifdef LOG_ENABLED
2703 uint8_t u8Vector;
2704
2705 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2706 if (rc == VINF_SUCCESS)
2707 {
2708 Log(("Pending hardware interrupt %d\n", u8Vector));
2709 }
2710 /*
2711 * Log important stuff before entering GC.
2712 */
2713 bool fSingleStep = false;
2714 if ((pCtx->ss & X86_SEL_RPL) == 0 && !fSingleStep)
2715 Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2716 else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2717 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2718 else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2719 Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2720#endif
2721
2722
2723 /*
2724 * Execute the code.
2725 */
2726 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2727 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2728 VMMR3Unlock(pVM);
2729 rc = VMMR3HwAccRunGC(pVM);
2730 VMMR3Lock(pVM);
2731 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2732
2733
2734 /*
2735 * Deal with high priority post execution FFs before doing anything else.
2736 */
2737 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2738 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2739 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2740
2741 /*
2742 * Process the returned status code.
2743 */
2744 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2745 break;
2746
2747 rc = emR3RawHandleRC(pVM, pCtx, rc);
2748 if (rc != VINF_SUCCESS)
2749 break;
2750
2751 /*
2752 * Check and execute forced actions.
2753 */
2754#ifdef VBOX_HIGH_RES_TIMERS_HACK
2755 TMTimerPoll(pVM);
2756#endif
2757 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2758 {
2759 rc = emR3ForcedActions(pVM, rc);
2760 if ( rc != VINF_SUCCESS
2761 && rc != VINF_EM_RESCHEDULE_HWACC)
2762 {
2763 *pfFFDone = true;
2764 break;
2765 }
2766 }
2767 }
2768 /*
2769 * Return to outer loop.
2770 */
2771#if defined(LOG_ENABLED) && defined(DEBUG)
2772 RTLogFlush(NULL);
2773#endif
2774 return rc;
2775}
2776
2777
2778/**
2779 * Decides whether to execute RAW, HWACC or REM.
2780 *
2781 * @returns new EM state
2782 * @param pVM The VM.
2783 * @param pCtx The CPU context.
2784 */
2785inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2786{
2787 /*
2788 * When forcing raw-mode execution, things are simple.
2789 */
2790 if (pVM->em.s.fForceRAW)
2791 return EMSTATE_RAW;
2792
2793 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2794 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2795 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2796
2797 X86EFLAGS EFlags = pCtx->eflags;
2798 if (HWACCMIsEnabled(pVM))
2799 {
2800 /* Hardware accelerated raw-mode:
2801 *
2802 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2803 */
2804 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2805 return EMSTATE_HWACC;
2806
2807 /** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2808 return EMSTATE_REM;
2809 }
2810
2811 /* Standard raw-mode:
2812 *
2813 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2814 * or 32 bits protected mode ring 0 code
2815 *
2816 * The tests are ordered by the likelyhood of being true during normal execution.
2817 */
2818 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2819 {
2820 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2821 return EMSTATE_REM;
2822 }
2823
2824#ifndef VBOX_RAW_V86
2825 if (EFlags.u32 & X86_EFL_VM) {
2826 Log2(("raw mode refused: VM_MASK\n"));
2827 return EMSTATE_REM;
2828 }
2829#endif
2830
2831 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2832 uint32_t u32CR0 = pCtx->cr0;
2833 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2834 {
2835 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2836 return EMSTATE_REM;
2837 }
2838
2839 if (pCtx->cr4 & X86_CR4_PAE)
2840 {
2841 //Log2(("raw mode refused: PAE\n"));
2842 return EMSTATE_REM;
2843 }
2844
2845 unsigned uSS = pCtx->ss;
2846 if ((uSS & X86_SEL_RPL) == 3)
2847 {
2848 if (!EMIsRawRing3Enabled(pVM))
2849 return EMSTATE_REM;
2850
2851 if (!(EFlags.u32 & X86_EFL_IF))
2852 {
2853#ifdef VBOX_RAW_V86
2854 if(!(EFlags.u32 & X86_EFL_VM))
2855 return EMSTATE_REM;
2856#else
2857 Log2(("raw mode refused: IF (RawR3)\n"));
2858 return EMSTATE_REM;
2859#endif
2860 }
2861
2862 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2863 {
2864 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2865 return EMSTATE_REM;
2866 }
2867 }
2868 else
2869 {
2870 if (!EMIsRawRing0Enabled(pVM))
2871 return EMSTATE_REM;
2872
2873 /* Only ring 0 supervisor code. */
2874 if ((uSS & X86_SEL_RPL) != 0)
2875 {
2876 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2877 return EMSTATE_REM;
2878 }
2879
2880 // Let's start with pure 32 bits ring 0 code first
2881 /** @todo What's pure 32-bit mode? flat? */
2882 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2883 || !(pCtx->csHid.Attr.n.u1DefBig))
2884 {
2885 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2886 return EMSTATE_REM;
2887 }
2888
2889 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2890 if (!(u32CR0 & X86_CR0_WP))
2891 {
2892 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2893 return EMSTATE_REM;
2894 }
2895
2896 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2897 {
2898 Log2(("raw r0 mode forced: patch code\n"));
2899 return EMSTATE_RAW;
2900 }
2901
2902#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2903 if (!(EFlags.u32 & X86_EFL_IF))
2904 {
2905 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2906 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2907 return EMSTATE_REM;
2908 }
2909#endif
2910
2911 /** @todo still necessary??? */
2912 if (EFlags.Bits.u2IOPL != 0)
2913 {
2914 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2915 return EMSTATE_REM;
2916 }
2917 }
2918
2919 Assert(PGMPhysIsA20Enabled(pVM));
2920 return EMSTATE_RAW;
2921}
2922
2923
2924/**
2925 * Executes all high priority post execution force actions.
2926 *
2927 * @returns rc or a fatal status code.
2928 *
2929 * @param pVM VM handle.
2930 * @param rc The current rc.
2931 */
2932static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2933{
2934 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2935 PDMR3CritSectFF(pVM);
2936
2937 if (VM_FF_ISSET(pVM, VM_FF_CSAM_FLUSH_DIRTY_PAGE))
2938 CSAMR3FlushDirtyPages(pVM);
2939
2940 return rc;
2941}
2942
2943
2944/**
2945 * Executes all pending forced actions.
2946 *
2947 * Forced actions can cause execution delays and execution
2948 * rescheduling. The first we deal with using action priority, so
2949 * that for instance pending timers aren't scheduled and ran until
2950 * right before execution. The rescheduling we deal with using
2951 * return codes. The same goes for VM termination, only in that case
2952 * we exit everything.
2953 *
2954 * @returns VBox status code of equal or greater importance/severity than rc.
2955 * The most important ones are: VINF_EM_RESCHEDULE,
2956 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2957 *
2958 * @param pVM VM handle.
2959 * @param rc The current rc.
2960 *
2961 */
2962static int emR3ForcedActions(PVM pVM, int rc)
2963{
2964#ifdef VBOX_STRICT
2965 int rcIrq = VINF_SUCCESS;
2966#endif
2967 STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2968
2969#define UPDATE_RC() \
2970 do { \
2971 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2972 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
2973 break; \
2974 if (!rc || rc2 < rc) \
2975 rc = rc2; \
2976 } while (0)
2977
2978 int rc2;
2979
2980 /*
2981 * Post execution chunk first.
2982 */
2983 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2984 {
2985 /*
2986 * Termination request.
2987 */
2988 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2989 {
2990 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2991 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2992 return VINF_EM_TERMINATE;
2993 }
2994
2995 /*
2996 * Debugger Facility polling.
2997 */
2998 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2999 {
3000 rc2 = DBGFR3VMMForcedAction(pVM);
3001 UPDATE_RC();
3002 }
3003
3004 /*
3005 * Postponed reset request.
3006 */
3007 if (VM_FF_ISSET(pVM, VM_FF_RESET))
3008 {
3009 rc2 = VMR3Reset(pVM);
3010 UPDATE_RC();
3011 VM_FF_CLEAR(pVM, VM_FF_RESET);
3012 }
3013
3014 /*
3015 * CSAM page scanning.
3016 */
3017 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
3018 {
3019 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
3020 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
3021 CSAMR3CheckEIP(pVM, CPUMGetGuestEIP(pVM), true);
3022 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3023 }
3024
3025 /* check that we got them all */
3026 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
3027 }
3028
3029 /*
3030 * Normal priority then.
3031 * (Executed in no particular order.)
3032 */
3033 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3034 {
3035 /*
3036 * PDM Queues are pending.
3037 */
3038 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3039 PDMR3QueueFlushAll(pVM);
3040
3041 /*
3042 * PDM DMA transfers are pending.
3043 */
3044 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3045 PDMR3DmaRun(pVM);
3046
3047 /*
3048 * Requests from other threads.
3049 */
3050 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3051 {
3052 rc2 = VMR3ReqProcess(pVM);
3053 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
3054 {
3055 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3056 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3057 return rc2;
3058 }
3059 UPDATE_RC();
3060 }
3061
3062 /* check that we got them all */
3063 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA)));
3064 }
3065
3066 /*
3067 * Execute polling function ever so often.
3068 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING SOON!
3069 */
3070 static unsigned cLast = 0;
3071 if (!((++cLast) % 4))
3072 PDMR3Poll(pVM);
3073
3074 /*
3075 * High priority pre execution chunk last.
3076 * (Executed in ascending priority order.)
3077 */
3078 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3079 {
3080 /*
3081 * Timers before interrupts.
3082 */
3083 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3084 TMR3TimerQueuesDo(pVM);
3085
3086 /*
3087 * The instruction following an emulated STI should *always* be executed!
3088 */
3089 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3090 {
3091 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3092 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3093 {
3094 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3095 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3096 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3097 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3098 */
3099 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3100 }
3101 if (HWACCMR3IsActive(pVM))
3102 rc2 = VINF_EM_RESCHEDULE_HWACC;
3103 else
3104 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3105
3106 UPDATE_RC();
3107 }
3108
3109 /*
3110 * Interrupts.
3111 */
3112 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3113 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3114 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3115 && PATMAreInterruptsEnabled(pVM)
3116 && !HWACCMR3IsEventPending(pVM))
3117 {
3118 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3119 {
3120 /** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3121 /** @todo this really isn't nice, should properly handle this */
3122 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3123#ifdef VBOX_STRICT
3124 rcIrq = rc2;
3125#endif
3126 UPDATE_RC();
3127 }
3128 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3129 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3130 {
3131 rc2 = VINF_EM_RESCHEDULE_REM;
3132 UPDATE_RC();
3133 }
3134 }
3135
3136 /*
3137 * Debugger Facility request.
3138 */
3139 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3140 {
3141 rc2 = DBGFR3VMMForcedAction(pVM);
3142 UPDATE_RC();
3143 }
3144
3145 /*
3146 * Termination request.
3147 */
3148 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3149 {
3150 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3151 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3152 return VINF_EM_TERMINATE;
3153 }
3154
3155#ifdef DEBUG
3156 /*
3157 * Debug, pause the VM.
3158 */
3159 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3160 {
3161 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3162 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3163 return VINF_EM_SUSPEND;
3164 }
3165
3166#endif
3167 /* check that we got them all */
3168 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS)));
3169 }
3170
3171#undef UPDATE_RC
3172 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3173 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3174 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3175 return rc;
3176}
3177
3178
3179/**
3180 * Execute VM.
3181 *
3182 * This function is the main loop of the VM. The emulation thread
3183 * calls this function when the VM has been successfully constructed
3184 * and we're ready for executing the VM.
3185 *
3186 * Returning from this function means that the VM is turned off or
3187 * suspended (state already saved) and deconstruction in next in line.
3188 *
3189 * All interaction from other thread are done using forced actions
3190 * and signaling of the wait object.
3191 *
3192 * @returns VBox status code.
3193 * @param pVM The VM to operate on.
3194 */
3195EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3196{
3197 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3198 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3199 VM_ASSERT_EMT(pVM);
3200 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3201
3202 VMMR3Lock(pVM);
3203
3204 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3205 if (rc == 0)
3206 {
3207 /*
3208 * Start the virtual time.
3209 */
3210 rc = TMVirtualResume(pVM);
3211 Assert(rc == VINF_SUCCESS);
3212
3213 /*
3214 * The Outer Main Loop.
3215 */
3216 bool fFFDone = false;
3217 rc = VINF_EM_RESCHEDULE;
3218 pVM->em.s.enmState = EMSTATE_REM;
3219 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3220 for (;;)
3221 {
3222 /*
3223 * Before we can schedule anything (we're here because
3224 * scheduling is required) we must service any pending
3225 * forced actions to avoid any pending action causing
3226 * immidate rescheduling upon entering an inner loop
3227 *
3228 * Do forced actions.
3229 */
3230 if ( !fFFDone
3231 && rc != VINF_EM_TERMINATE
3232 && rc != VINF_EM_OFF
3233 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3234 {
3235 rc = emR3ForcedActions(pVM, rc);
3236 if ( ( rc == VINF_EM_RESCHEDULE_REM
3237 || rc == VINF_EM_RESCHEDULE_HWACC)
3238 && pVM->em.s.fForceRAW)
3239 rc = VINF_EM_RESCHEDULE_RAW;
3240 }
3241 else if (fFFDone)
3242 fFFDone = false;
3243
3244 /*
3245 * Now what to do?
3246 */
3247 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3248 switch (rc)
3249 {
3250 /*
3251 * Keep doing what we're currently doing.
3252 */
3253 case VINF_SUCCESS:
3254 break;
3255
3256 /*
3257 * Reschedule - to raw-mode execution.
3258 */
3259 case VINF_EM_RESCHEDULE_RAW:
3260 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3261 pVM->em.s.enmState = EMSTATE_RAW;
3262 break;
3263
3264 /*
3265 * Reschedule - to hardware accelerated raw-mode execution.
3266 */
3267 case VINF_EM_RESCHEDULE_HWACC:
3268 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3269 Assert(!pVM->em.s.fForceRAW);
3270 pVM->em.s.enmState = EMSTATE_HWACC;
3271 break;
3272
3273 /*
3274 * Reschedule - to recompiled execution.
3275 */
3276 case VINF_EM_RESCHEDULE_REM:
3277 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3278 pVM->em.s.enmState = EMSTATE_REM;
3279 break;
3280
3281 /*
3282 * Resume.
3283 */
3284 case VINF_EM_RESUME:
3285 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3286 /* fall through and get scheduled. */
3287
3288 /*
3289 * Reschedule.
3290 */
3291 case VINF_EM_RESCHEDULE:
3292 {
3293 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3294 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3295 pVM->em.s.enmState = enmState;
3296 break;
3297 }
3298
3299 /*
3300 * Halted.
3301 */
3302 case VINF_EM_HALT:
3303 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3304 pVM->em.s.enmState = EMSTATE_HALTED;
3305 break;
3306
3307 /*
3308 * Suspend.
3309 */
3310 case VINF_EM_SUSPEND:
3311 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3312 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3313 break;
3314
3315 /*
3316 * Reset.
3317 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3318 */
3319 case VINF_EM_RESET:
3320 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3321 pVM->em.s.enmState = EMSTATE_REM;
3322 break;
3323
3324 /*
3325 * Power Off.
3326 */
3327 case VINF_EM_OFF:
3328 pVM->em.s.enmState = EMSTATE_TERMINATING;
3329 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3330 TMVirtualPause(pVM);
3331 VMMR3Unlock(pVM);
3332 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3333 return rc;
3334
3335 /*
3336 * Terminate the VM.
3337 */
3338 case VINF_EM_TERMINATE:
3339 pVM->em.s.enmState = EMSTATE_TERMINATING;
3340 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3341 TMVirtualPause(pVM);
3342 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3343 return rc;
3344
3345 /*
3346 * Guest debug events.
3347 */
3348 case VINF_EM_DBG_STEPPED:
3349 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3350 case VINF_EM_DBG_STOP:
3351 case VINF_EM_DBG_BREAKPOINT:
3352 case VINF_EM_DBG_STEP:
3353 if (pVM->em.s.enmState == EMSTATE_RAW)
3354 {
3355 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3356 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3357 }
3358 else
3359 {
3360 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3361 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3362 }
3363 break;
3364
3365 /*
3366 * Hypervisor debug events.
3367 */
3368 case VINF_EM_DBG_HYPER_STEPPED:
3369 case VINF_EM_DBG_HYPER_BREAKPOINT:
3370 case VINF_EM_DBG_HYPER_ASSERTION:
3371 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3372 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3373 break;
3374
3375 /*
3376 * Any error code showing up here other than the ones we
3377 * know and process above are considered to be FATAL.
3378 *
3379 * Unknown warnings and informational status codes are also
3380 * included in this.
3381 */
3382 default:
3383 if (VBOX_SUCCESS(rc))
3384 {
3385 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3386 rc = VERR_EM_INTERNAL_ERROR;
3387 }
3388 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3389 Log(("EMR3ExecuteVM returns %d\n", rc));
3390 break;
3391 }
3392
3393
3394 /*
3395 * Any waiters can now be woken up
3396 */
3397 VMMR3Unlock(pVM);
3398 VMMR3Lock(pVM);
3399
3400 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3401 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3402
3403 /*
3404 * Act on the state.
3405 */
3406 switch (pVM->em.s.enmState)
3407 {
3408 /*
3409 * Execute raw.
3410 */
3411 case EMSTATE_RAW:
3412 rc = emR3RawExecute(pVM, &fFFDone);
3413 break;
3414
3415 /*
3416 * Execute hardware accelerated raw.
3417 */
3418 case EMSTATE_HWACC:
3419 rc = emR3HwAccExecute(pVM, &fFFDone);
3420 break;
3421
3422 /*
3423 * Execute recompiled.
3424 */
3425 case EMSTATE_REM:
3426#if 0
3427 /* simulate a runtime error */
3428 VMSetRuntimeError (pVM, true, "simulatedError", "pVM=%p", pVM);
3429#endif
3430 rc = emR3RemExecute(pVM, &fFFDone);
3431 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3432 break;
3433
3434 /*
3435 * hlt - execution halted until interrupt.
3436 */
3437 case EMSTATE_HALTED:
3438 {
3439 STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3440 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3441 STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3442 break;
3443 }
3444
3445 /*
3446 * Suspended - return to VM.cpp.
3447 */
3448 case EMSTATE_SUSPENDED:
3449 TMVirtualPause(pVM);
3450 VMMR3Unlock(pVM);
3451 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3452 return VINF_EM_SUSPEND;
3453
3454 /*
3455 * Debugging in the guest.
3456 */
3457 case EMSTATE_DEBUG_GUEST_REM:
3458 case EMSTATE_DEBUG_GUEST_RAW:
3459 TMVirtualPause(pVM);
3460 rc = emR3Debug(pVM, rc);
3461 TMVirtualResume(pVM);
3462 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3463 break;
3464
3465 /*
3466 * Debugging in the hypervisor.
3467 */
3468 case EMSTATE_DEBUG_HYPER:
3469 {
3470 TMVirtualPause(pVM);
3471 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3472
3473 rc = emR3Debug(pVM, rc);
3474 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3475 if (rc != VINF_SUCCESS)
3476 {
3477 /* switch to guru meditation mode */
3478 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3479 VMMR3FatalDump(pVM, rc);
3480 return rc;
3481 }
3482
3483 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3484 TMVirtualResume(pVM);
3485 break;
3486 }
3487
3488 /*
3489 * Guru meditation takes place in the debugger.
3490 */
3491 case EMSTATE_GURU_MEDITATION:
3492 {
3493 /** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3494 TMVirtualPause(pVM);
3495 VMMR3FatalDump(pVM, rc);
3496 int rc2 = emR3Debug(pVM, rc);
3497 if (rc2 == VERR_DBGF_NOT_ATTACHED)
3498 {
3499 VMMR3Unlock(pVM);
3500 /** @todo change the VM state! */
3501 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3502 return rc;
3503 }
3504 TMVirtualResume(pVM);
3505 rc = rc2;
3506 /** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3507 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3508 break;
3509 }
3510
3511 /*
3512 * The states we don't expect here.
3513 */
3514 case EMSTATE_NONE:
3515 case EMSTATE_TERMINATING:
3516 default:
3517 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3518 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3519 TMVirtualPause(pVM);
3520 VMMR3Unlock(pVM);
3521 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3522 return VERR_EM_INTERNAL_ERROR;
3523 }
3524 } /* The Outer Main Loop */
3525 }
3526 else
3527 {
3528 /*
3529 * Fatal error.
3530 */
3531 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3532 TMVirtualPause(pVM);
3533 VMMR3FatalDump(pVM, rc);
3534 emR3Debug(pVM, rc);
3535 VMMR3Unlock(pVM);
3536 /** @todo change the VM state! */
3537 return rc;
3538 }
3539
3540 /* (won't ever get here). */
3541 AssertFailed();
3542}
3543
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