VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 4394

Last change on this file since 4394 was 4295, checked in by vboxsync, 17 years ago

VMSTATE_GURU_MEDITATION when EMR3Execute returns with the EM state EMSTATE_GURU_MEDITATION.
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1/* $Id: EM.cpp 4295 2007-08-22 20:17:19Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor/Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_em EM - The Execution Monitor/Manager
20 *
21 * The Execution Monitor/Manager is responsible for running the VM, scheduling
22 * the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
23 * the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
24 * the VM.
25 *
26 */
27
28/*******************************************************************************
29* Header Files *
30*******************************************************************************/
31#define LOG_GROUP LOG_GROUP_EM
32#include <VBox/em.h>
33#include <VBox/vmm.h>
34#include <VBox/patm.h>
35#include <VBox/csam.h>
36#include <VBox/selm.h>
37#include <VBox/trpm.h>
38#include <VBox/iom.h>
39#include <VBox/dbgf.h>
40#include <VBox/pgm.h>
41#include <VBox/rem.h>
42#include <VBox/tm.h>
43#include <VBox/mm.h>
44#include <VBox/ssm.h>
45#include <VBox/pdmapi.h>
46#include <VBox/pdmcritsect.h>
47#include <VBox/pdmqueue.h>
48#include <VBox/hwaccm.h>
49#include <VBox/patm.h>
50#include "EMInternal.h"
51#include <VBox/vm.h>
52#include <VBox/cpumdis.h>
53#include <VBox/dis.h>
54#include <VBox/disopcode.h>
55#include <VBox/dbgf.h>
56
57#include <VBox/log.h>
58#include <iprt/thread.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/semaphore.h>
62#include <iprt/string.h>
63#include <iprt/avl.h>
64#include <iprt/stream.h>
65#include <VBox/param.h>
66#include <VBox/err.h>
67
68
69/*******************************************************************************
70* Internal Functions *
71*******************************************************************************/
72static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
73static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
74static int emR3Debug(PVM pVM, int rc);
75static int emR3RemStep(PVM pVM);
76static int emR3RemExecute(PVM pVM, bool *pfFFDone);
77static int emR3RawResumeHyper(PVM pVM);
78static int emR3RawStep(PVM pVM);
79DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
80DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
81static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
82static int emR3RawExecute(PVM pVM, bool *pfFFDone);
83DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
84static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
85static int emR3ForcedActions(PVM pVM, int rc);
86static int emR3RawGuestTrap(PVM pVM);
87
88
89/**
90 * Initializes the EM.
91 *
92 * @returns VBox status code.
93 * @param pVM The VM to operate on.
94 */
95EMR3DECL(int) EMR3Init(PVM pVM)
96{
97 LogFlow(("EMR3Init\n"));
98 /*
99 * Assert alignment and sizes.
100 */
101 AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
102 AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
103 AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
104 ("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
105
106 /*
107 * Init the structure.
108 */
109 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
110 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
111 if (VBOX_FAILURE(rc))
112 pVM->fRawR3Enabled = true;
113 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
114 if (VBOX_FAILURE(rc))
115 pVM->fRawR0Enabled = true;
116 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
117 pVM->em.s.enmState = EMSTATE_NONE;
118 pVM->em.s.fForceRAW = false;
119
120 rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
121 AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
122 pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
123 AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
124
125 /*
126 * Saved state.
127 */
128 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
129 NULL, emR3Save, NULL,
130 NULL, emR3Load, NULL);
131 if (VBOX_FAILURE(rc))
132 return rc;
133
134 /*
135 * Statistics.
136 */
137#ifdef VBOX_WITH_STATISTICS
138 PEMSTATS pStats;
139 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
140 if (VBOX_FAILURE(rc))
141 return rc;
142 pVM->em.s.pStatsHC = pStats;
143 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
144
145 STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
146 STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147
148 STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
149 STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150
151 STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
152 STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153 STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
154 STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155 STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
156 STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157 STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
158 STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159 STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
160 STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161 STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
162 STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163 STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
164 STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165 STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
166 STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167 STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
168 STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169 STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
170 STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171 STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
172 STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173 STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
174 STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175 STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
176 STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177 STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
178 STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179 STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
180 STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181 STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
182 STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183 STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
184 STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185 STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
186 STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187 STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
188 STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189 STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
190 STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191 STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
192 STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193 STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
194 STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195 STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
196 STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197 STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
198 STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199 STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
200 STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201 STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
202 STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203
204 STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
205 STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206
207 STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
208 STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209 STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
210 STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211 STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
212 STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213 STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
214 STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215 STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
216 STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217 STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
218 STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219 STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
220 STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221 STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
222 STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223 STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
224 STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225 STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
226 STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227 STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
228 STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229 STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
230 STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231 STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
232 STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233 STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
234 STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235 STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
236 STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237 STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
238 STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239 STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
240 STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241 STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242 STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243 STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
244 STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245
246 STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
247 STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248 STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
249 STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250 STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
251 STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252 STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
253 STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254 STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
255 STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256 STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
257 STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258 STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
259 STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260 STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
261 STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262 STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
263 STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264 STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
265 STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266 STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
267 STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268 STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
269 STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270
271 STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
272 STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273 STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
274 STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275
276 STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
277 STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
278 STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
279 STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
280 STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
281 STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
282 STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
283 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
284 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
285 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
286 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
287 STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
288 STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
289 STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
290 STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
291 STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
292 STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
293 STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
294 STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
295 STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
296 STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
297 STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
298 STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
299 STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
300 STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
301 STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
302
303 STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
304 pVM->em.s.pCliStatTree = 0;
305#endif /* VBOX_WITH_STATISTICS */
306
307/* these should be considered for release statistics. */
308 STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
309 STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
310 STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
311 STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
312 STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
313 STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
314 STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
315 STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
316 STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
317 STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
318 STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
319 STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
320 STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
321 STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
322 STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
323 STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
324
325
326 return VINF_SUCCESS;
327}
328
329
330
331/**
332 * Applies relocations to data and code managed by this
333 * component. This function will be called at init and
334 * whenever the VMM need to relocate it self inside the GC.
335 *
336 * @param pVM The VM.
337 */
338EMR3DECL(void) EMR3Relocate(PVM pVM)
339{
340 LogFlow(("EMR3Relocate\n"));
341 if (pVM->em.s.pStatsHC)
342 pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
343}
344
345
346/**
347 * Reset notification.
348 *
349 * @param pVM
350 */
351EMR3DECL(void) EMR3Reset(PVM pVM)
352{
353 LogFlow(("EMR3Reset: \n"));
354 pVM->em.s.fForceRAW = false;
355}
356
357
358/**
359 * Terminates the EM.
360 *
361 * Termination means cleaning up and freeing all resources,
362 * the VM it self is at this point powered off or suspended.
363 *
364 * @returns VBox status code.
365 * @param pVM The VM to operate on.
366 */
367EMR3DECL(int) EMR3Term(PVM pVM)
368{
369 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
370
371 return VINF_SUCCESS;
372}
373
374
375/**
376 * Execute state save operation.
377 *
378 * @returns VBox status code.
379 * @param pVM VM Handle.
380 * @param pSSM SSM operation handle.
381 */
382static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
383{
384 return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
385}
386
387
388/**
389 * Execute state load operation.
390 *
391 * @returns VBox status code.
392 * @param pVM VM Handle.
393 * @param pSSM SSM operation handle.
394 * @param u32Version Data layout version.
395 */
396static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
397{
398 /*
399 * Validate version.
400 */
401 if (u32Version != EM_SAVED_STATE_VERSION)
402 {
403 Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
404 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
405 }
406
407 /*
408 * Load the saved state.
409 */
410 int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
411 if (VBOX_FAILURE(rc))
412 pVM->em.s.fForceRAW = false;
413
414 Assert(pVM->em.s.pCliStatTree == 0);
415 return rc;
416}
417
418
419/**
420 * Enables or disables a set of raw-mode execution modes.
421 *
422 * @returns VINF_SUCCESS on success.
423 * @returns VINF_RESCHEDULE if a rescheduling might be required.
424 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
425 *
426 * @param pVM The VM to operate on.
427 * @param enmMode The execution mode change.
428 * @thread The emulation thread.
429 */
430EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
431{
432 switch (enmMode)
433 {
434 case EMRAW_NONE:
435 pVM->fRawR3Enabled = false;
436 pVM->fRawR0Enabled = false;
437 break;
438 case EMRAW_RING3_ENABLE:
439 pVM->fRawR3Enabled = true;
440 break;
441 case EMRAW_RING3_DISABLE:
442 pVM->fRawR3Enabled = false;
443 break;
444 case EMRAW_RING0_ENABLE:
445 pVM->fRawR0Enabled = true;
446 break;
447 case EMRAW_RING0_DISABLE:
448 pVM->fRawR0Enabled = false;
449 break;
450 default:
451 AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
452 return VERR_INVALID_PARAMETER;
453 }
454 Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
455 pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
456 return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
457}
458
459
460/**
461 * Raise a fatal error.
462 *
463 * Safely terminate the VM with full state report and stuff. This function
464 * will naturally never return.
465 *
466 * @param pVM VM handle.
467 * @param rc VBox status code.
468 */
469EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
470{
471 longjmp(pVM->em.s.u.FatalLongJump, rc);
472 AssertReleaseMsgFailed(("longjmp returned!\n"));
473}
474
475
476/**
477 * Gets the EM state name.
478 *
479 * @returns pointer to read only state name,
480 * @param enmState The state.
481 */
482EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
483{
484 switch (enmState)
485 {
486 case EMSTATE_RAW: return "EMSTATE_RAW";
487 case EMSTATE_HWACC: return "EMSTATE_HWACC";
488 case EMSTATE_REM: return "EMSTATE_REM";
489 case EMSTATE_HALTED: return "EMSTATE_HALTED";
490 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
491 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
492 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
493 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
494 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
495 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
496 default: return "Unknown!";
497 }
498}
499
500
501#ifdef VBOX_WITH_STATISTICS
502/**
503 * Just a braindead function to keep track of cli addresses.
504 * @param pVM VM handle.
505 * @param pInstrGC The EIP of the cli instruction.
506 */
507static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
508{
509 PCLISTAT pRec;
510
511 pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
512 if (!pRec)
513 {
514 /* New cli instruction; insert into the tree. */
515 pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
516 Assert(pRec);
517 if (!pRec)
518 return;
519 pRec->Core.Key = (AVLPVKEY)pInstrGC;
520
521 char szCliStatName[32];
522 RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
523 STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
524
525 bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
526 Assert(fRc); NOREF(fRc);
527 }
528 STAM_COUNTER_INC(&pRec->Counter);
529 STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
530}
531#endif /* VBOX_WITH_STATISTICS */
532
533
534/**
535 * Debug loop.
536 *
537 * @returns VBox status code for EM.
538 * @param pVM VM handle.
539 * @param rc Current EM VBox status code..
540 */
541static int emR3Debug(PVM pVM, int rc)
542{
543 for (;;)
544 {
545 Log(("emR3Debug: rc=%Vrc\n", rc));
546 const int rcLast = rc;
547
548 /*
549 * Debug related RC.
550 */
551 switch (rc)
552 {
553 /*
554 * Single step an instruction.
555 */
556 case VINF_EM_DBG_STEP:
557 if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
558 || pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
559 || pVM->em.s.fForceRAW /* paranoia */)
560 rc = emR3RawStep(pVM);
561 else
562 {
563 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
564 rc = emR3RemStep(pVM);
565 }
566 break;
567
568 /*
569 * Simple events: stepped, breakpoint, stop/assertion.
570 */
571 case VINF_EM_DBG_STEPPED:
572 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
573 break;
574
575 case VINF_EM_DBG_BREAKPOINT:
576 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
577 break;
578
579 case VINF_EM_DBG_STOP:
580 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
581 break;
582
583 case VINF_EM_DBG_HYPER_STEPPED:
584 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
585 break;
586
587 case VINF_EM_DBG_HYPER_BREAKPOINT:
588 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
589 break;
590
591 case VINF_EM_DBG_HYPER_ASSERTION:
592 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
593 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594 break;
595
596 /*
597 * Guru meditation.
598 */
599 default: /** @todo don't use default for guru, but make special errors code! */
600 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
601 break;
602 }
603
604 /*
605 * Process the result.
606 */
607 do
608 {
609 switch (rc)
610 {
611 /*
612 * Continue the debugging loop.
613 */
614 case VINF_EM_DBG_STEP:
615 case VINF_EM_DBG_STOP:
616 case VINF_EM_DBG_STEPPED:
617 case VINF_EM_DBG_BREAKPOINT:
618 case VINF_EM_DBG_HYPER_STEPPED:
619 case VINF_EM_DBG_HYPER_BREAKPOINT:
620 case VINF_EM_DBG_HYPER_ASSERTION:
621 break;
622
623 /*
624 * Resuming execution (in some form) has to be done here if we got
625 * a hypervisor debug event.
626 */
627 case VINF_SUCCESS:
628 case VINF_EM_RESUME:
629 case VINF_EM_SUSPEND:
630 case VINF_EM_RESCHEDULE:
631 case VINF_EM_RESCHEDULE_RAW:
632 case VINF_EM_RESCHEDULE_REM:
633 case VINF_EM_HALT:
634 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
635 {
636 rc = emR3RawResumeHyper(pVM);
637 if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
638 continue;
639 }
640 if (rc == VINF_SUCCESS)
641 rc = VINF_EM_RESCHEDULE;
642 return rc;
643
644 /*
645 * The debugger isn't attached.
646 * We'll simply turn the thing off since that's the easiest thing to do.
647 */
648 case VERR_DBGF_NOT_ATTACHED:
649 switch (rcLast)
650 {
651 case VINF_EM_DBG_HYPER_ASSERTION:
652 case VINF_EM_DBG_HYPER_STEPPED:
653 case VINF_EM_DBG_HYPER_BREAKPOINT:
654 return rcLast;
655 }
656 return VINF_EM_OFF;
657
658 /*
659 * Status codes terminating the VM in one or another sense.
660 */
661 case VINF_EM_TERMINATE:
662 case VINF_EM_OFF:
663 case VINF_EM_RESET:
664 case VINF_EM_RAW_STALE_SELECTOR:
665 case VINF_EM_RAW_IRET_TRAP:
666 case VERR_TRPM_PANIC:
667 case VERR_TRPM_DONT_PANIC:
668 case VERR_INTERNAL_ERROR:
669 return rc;
670
671 /*
672 * The rest is unexpected, and will keep us here.
673 */
674 default:
675 AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
676 break;
677 }
678 } while (false);
679 } /* debug for ever */
680}
681
682
683/**
684 * Steps recompiled code.
685 *
686 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
687 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
688 *
689 * @param pVM VM handle.
690 */
691static int emR3RemStep(PVM pVM)
692{
693 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
694
695 /*
696 * Switch to REM, step instruction, switch back.
697 */
698 int rc = REMR3State(pVM);
699 if (VBOX_SUCCESS(rc))
700 {
701 rc = REMR3Step(pVM);
702 REMR3StateBack(pVM);
703 }
704 LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
705 return rc;
706}
707
708/**
709 * Executes recompiled code.
710 *
711 * This function contains the recompiler version of the inner
712 * execution loop (the outer loop being in EMR3ExecuteVM()).
713 *
714 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
715 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
716 *
717 * @param pVM VM handle.
718 * @param pfFFDone Where to store an indicator telling wheter or not
719 * FFs were done before returning.
720 *
721 */
722static int emR3RemExecute(PVM pVM, bool *pfFFDone)
723{
724#ifdef LOG_ENABLED
725 PCPUMCTX pCtx = pVM->em.s.pCtx;
726 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
727
728 if (pCtx->eflags.Bits.u1VM)
729 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
730 else
731 Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
732#endif
733 STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
734
735#if defined(VBOX_STRICT) && defined(DEBUG_bird)
736 AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
737 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
738 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
739#endif
740
741 /*
742 * Spin till we get a forced action which returns anything but VINF_SUCCESS
743 * or the REM suggests raw-mode execution.
744 */
745 *pfFFDone = false;
746 bool fInREMState = false;
747 int rc = VINF_SUCCESS;
748 for (;;)
749 {
750 /*
751 * Update REM state if not already in sync.
752 */
753 if (!fInREMState)
754 {
755 STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
756 rc = REMR3State(pVM);
757 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
758 if (VBOX_FAILURE(rc))
759 break;
760 fInREMState = true;
761
762 /*
763 * We might have missed the raising of VMREQ, TIMER and some other
764 * imporant FFs while we were busy switching the state. So, check again.
765 */
766 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_TIMER | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET))
767 {
768 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
769 goto l_REMDoForcedActions;
770 }
771 }
772
773
774 /*
775 * Execute REM.
776 */
777 STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
778 rc = REMR3Run(pVM);
779 STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
780
781
782 /*
783 * Deal with high priority post execution FFs before doing anything else.
784 */
785 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
786 rc = emR3HighPriorityPostForcedActions(pVM, rc);
787
788 /*
789 * Process the returned status code.
790 * (Try keep this short! Call functions!)
791 */
792 if (rc != VINF_SUCCESS)
793 {
794 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
795 break;
796 if (rc != VINF_REM_INTERRUPED_FF)
797 {
798 /*
799 * Anything which is not known to us means an internal error
800 * and the termination of the VM!
801 */
802 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
803 break;
804 }
805 }
806
807
808 /*
809 * Check and execute forced actions.
810 * Sync back the VM state before calling any of these.
811 */
812#ifdef VBOX_HIGH_RES_TIMERS_HACK
813 TMTimerPoll(pVM);
814#endif
815 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION | VM_FF_CSAM_SCAN_PAGE)))
816 {
817l_REMDoForcedActions:
818 if (fInREMState)
819 {
820 STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
821 REMR3StateBack(pVM);
822 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
823 fInREMState = false;
824 }
825 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
826 rc = emR3ForcedActions(pVM, rc);
827 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
828 if ( rc != VINF_SUCCESS
829 && rc != VINF_EM_RESCHEDULE_REM)
830 {
831 *pfFFDone = true;
832 break;
833 }
834 }
835
836 } /* The Inner Loop, recompiled execution mode version. */
837
838
839 /*
840 * Returning. Sync back the VM state if required.
841 */
842 if (fInREMState)
843 {
844 STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
845 REMR3StateBack(pVM);
846 STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
847 }
848
849 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
850 return rc;
851}
852
853
854/**
855 * Resumes executing hypervisor after a debug event.
856 *
857 * This is kind of special since our current guest state is
858 * potentially out of sync.
859 *
860 * @returns VBox status code.
861 * @param pVM The VM handle.
862 */
863static int emR3RawResumeHyper(PVM pVM)
864{
865 int rc;
866 PCPUMCTX pCtx = pVM->em.s.pCtx;
867 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
868 Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
869
870 /*
871 * Resume execution.
872 */
873 CPUMRawEnter(pVM, NULL);
874 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_RF);
875 rc = VMMR3ResumeHyper(pVM);
876 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
877 rc = CPUMRawLeave(pVM, NULL, rc);
878 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
879
880 /*
881 * Deal with the return code.
882 */
883 rc = emR3HighPriorityPostForcedActions(pVM, rc);
884 rc = emR3RawHandleRC(pVM, pCtx, rc);
885 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
886 return rc;
887}
888
889
890/**
891 * Steps rawmode.
892 *
893 * @returns VBox status code.
894 * @param pVM The VM handle.
895 */
896static int emR3RawStep(PVM pVM)
897{
898 Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
899 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
900 || pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
901 int rc;
902 PCPUMCTX pCtx = pVM->em.s.pCtx;
903 bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
904#ifndef DEBUG_sandervl
905 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
906 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
907#endif
908 if (fGuest)
909 {
910 /*
911 * Check vital forced actions, but ignore pending interrupts and timers.
912 */
913 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
914 {
915 rc = emR3RawForcedActions(pVM, pCtx);
916 if (VBOX_FAILURE(rc))
917 return rc;
918 }
919
920 /*
921 * Set flags for single stepping.
922 */
923 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
924 }
925 else
926 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
927
928 /*
929 * Single step.
930 * We do not start time or anything, if anything we should just do a few nanoseconds.
931 */
932 CPUMRawEnter(pVM, NULL);
933 do
934 {
935 if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
936 rc = VMMR3ResumeHyper(pVM);
937 else
938 rc = VMMR3RawRunGC(pVM);
939#ifndef DEBUG_sandervl
940 Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
941 fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
942#endif
943 } while ( rc == VINF_SUCCESS
944 || rc == VINF_EM_RAW_INTERRUPT);
945 rc = CPUMRawLeave(pVM, NULL, rc);
946 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
947
948 /*
949 * Make sure the trap flag is cleared.
950 * (Too bad if the guest is trying to single step too.)
951 */
952 if (fGuest)
953 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
954 else
955 CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
956
957 /*
958 * Deal with the return codes.
959 */
960 rc = emR3HighPriorityPostForcedActions(pVM, rc);
961 rc = emR3RawHandleRC(pVM, pCtx, rc);
962 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
963 return rc;
964}
965
966
967#ifdef DEBUG
968
969/**
970 * Steps hardware accelerated mode.
971 *
972 * @returns VBox status code.
973 * @param pVM The VM handle.
974 */
975static int emR3HwAccStep(PVM pVM)
976{
977 Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
978
979 int rc;
980 PCPUMCTX pCtx = pVM->em.s.pCtx;
981 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
982
983 /*
984 * Check vital forced actions, but ignore pending interrupts and timers.
985 */
986 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
987 {
988 rc = emR3RawForcedActions(pVM, pCtx);
989 if (VBOX_FAILURE(rc))
990 return rc;
991 }
992 /*
993 * Set flags for single stepping.
994 */
995 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) | X86_EFL_TF | X86_EFL_RF);
996
997 /*
998 * Single step.
999 * We do not start time or anything, if anything we should just do a few nanoseconds.
1000 */
1001 do
1002 {
1003 rc = VMMR3HwAccRunGC(pVM);
1004 } while ( rc == VINF_SUCCESS
1005 || rc == VINF_EM_RAW_INTERRUPT);
1006 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1007
1008 /*
1009 * Make sure the trap flag is cleared.
1010 * (Too bad if the guest is trying to single step too.)
1011 */
1012 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1013
1014 /*
1015 * Deal with the return codes.
1016 */
1017 rc = emR3HighPriorityPostForcedActions(pVM, rc);
1018 rc = emR3RawHandleRC(pVM, pCtx, rc);
1019 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1020 return rc;
1021}
1022
1023
1024void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1025{
1026 EMSTATE enmOldState = pVM->em.s.enmState;
1027
1028 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1029
1030 Log(("Single step BEGIN:\n"));
1031 for(uint32_t i=0;i<cIterations;i++)
1032 {
1033 DBGFR3PrgStep(pVM);
1034 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1035 emR3RawStep(pVM);
1036 }
1037 Log(("Single step END:\n"));
1038 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1039 pVM->em.s.enmState = enmOldState;
1040}
1041
1042
1043void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1044{
1045 EMSTATE enmOldState = pVM->em.s.enmState;
1046
1047 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1048
1049 Log(("Single step BEGIN:\n"));
1050 for(uint32_t i=0;i<cIterations;i++)
1051 {
1052 DBGFR3PrgStep(pVM);
1053 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1054 emR3HwAccStep(pVM);
1055 }
1056 Log(("Single step END:\n"));
1057 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1058 pVM->em.s.enmState = enmOldState;
1059}
1060
1061
1062void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1063{
1064 EMSTATE enmOldState = pVM->em.s.enmState;
1065
1066 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1067
1068 Log(("Single step BEGIN:\n"));
1069 for(uint32_t i=0;i<cIterations;i++)
1070 {
1071 DBGFR3PrgStep(pVM);
1072 DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1073 emR3RemStep(pVM);
1074 }
1075 Log(("Single step END:\n"));
1076 CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1077 pVM->em.s.enmState = enmOldState;
1078}
1079
1080#endif /* DEBUG */
1081
1082
1083/**
1084 * Executes one (or perhaps a few more) instruction(s).
1085 *
1086 * @returns VBox status code suitable for EM.
1087 *
1088 * @param pVM VM handle.
1089 * @param rcGC GC return code
1090 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1091 * instruction and prefix the log output with this text.
1092 */
1093#ifdef LOG_ENABLED
1094static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1095#else
1096static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1097#endif
1098{
1099 PCPUMCTX pCtx = pVM->em.s.pCtx;
1100 int rc;
1101
1102 /*
1103 *
1104 * The simple solution is to use the recompiler.
1105 * The better solution is to disassemble the current instruction and
1106 * try handle as many as possible without using REM.
1107 *
1108 */
1109
1110#ifdef LOG_ENABLED
1111 /*
1112 * Disassemble the instruction if requested.
1113 */
1114 if (pszPrefix)
1115 {
1116 DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1117 DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1118 }
1119#endif /* LOG_ENABLED */
1120
1121 /*
1122 * PATM is making life more interesting.
1123 * We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1124 * tell PATM there is a trap in this code and have it take the appropriate actions
1125 * to allow us execute the code in REM.
1126 */
1127 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1128 {
1129 Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1130
1131 RTGCPTR pNewEip;
1132 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1133 switch (rc)
1134 {
1135 /*
1136 * It's not very useful to emulate a single instruction and then go back to raw
1137 * mode; just execute the whole block until IF is set again.
1138 */
1139 case VINF_SUCCESS:
1140 Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1141 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1142 pCtx->eip = pNewEip;
1143 Assert(pCtx->eip);
1144
1145 if (pCtx->eflags.Bits.u1IF)
1146 {
1147 /*
1148 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1149 */
1150 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1151 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1152 }
1153 else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1154 {
1155 /* special case: iret, that sets IF, detected a pending irq/event */
1156 return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1157 }
1158 return VINF_EM_RESCHEDULE_REM;
1159
1160 /*
1161 * One instruction.
1162 */
1163 case VINF_PATCH_EMULATE_INSTR:
1164 Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1165 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1166 pCtx->eip = pNewEip;
1167 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1168
1169 /*
1170 * The patch was disabled, hand it to the REM.
1171 */
1172 case VERR_PATCH_DISABLED:
1173 Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1174 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1175 pCtx->eip = pNewEip;
1176 if (pCtx->eflags.Bits.u1IF)
1177 {
1178 /*
1179 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1180 */
1181 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1182 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1183 }
1184 return VINF_EM_RESCHEDULE_REM;
1185
1186 /* Force continued patch exection; usually due to write monitored stack. */
1187 case VINF_PATCH_CONTINUE:
1188 return VINF_SUCCESS;
1189
1190 default:
1191 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1192 return VERR_INTERNAL_ERROR;
1193 }
1194 }
1195
1196#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1197 DISCPUSTATE Cpu;
1198 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1199 if (VBOX_SUCCESS(rc))
1200 {
1201 uint32_t size;
1202
1203 switch (Cpu.pCurInstr->opcode)
1204 {
1205 case OP_MOV:
1206 case OP_AND:
1207 case OP_OR:
1208 case OP_XOR:
1209 case OP_POP:
1210 case OP_INC:
1211 case OP_DEC:
1212 case OP_XCHG:
1213 STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1214 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1215 if (VBOX_SUCCESS(rc))
1216 {
1217 pCtx->eip += Cpu.opsize;
1218 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1219 return rc;
1220 }
1221 if (rc != VERR_EM_INTERPRETER)
1222 AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1223 STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1224 break;
1225 }
1226 }
1227#endif
1228 STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1229 rc = REMR3EmulateInstruction(pVM);
1230 STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1231
1232 return rc;
1233}
1234
1235
1236/**
1237 * Executes one (or perhaps a few more) instruction(s).
1238 * This is just a wrapper for discarding pszPrefix in non-logging builds.
1239 *
1240 * @returns VBox status code suitable for EM.
1241 * @param pVM VM handle.
1242 * @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1243 * instruction and prefix the log output with this text.
1244 * @param rcGC GC return code
1245 */
1246DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1247{
1248#ifdef LOG_ENABLED
1249 return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1250#else
1251 return emR3RawExecuteInstructionWorker(pVM, rcGC);
1252#endif
1253}
1254
1255/**
1256 * Executes one (or perhaps a few more) IO instruction(s).
1257 *
1258 * @returns VBox status code suitable for EM.
1259 * @param pVM VM handle.
1260 */
1261int emR3RawExecuteIOInstruction(PVM pVM)
1262{
1263 int rc;
1264 PCPUMCTX pCtx = pVM->em.s.pCtx;
1265
1266 STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1267
1268 /** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1269 * as io instructions tend to come in packages of more than one
1270 */
1271 DISCPUSTATE Cpu;
1272 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1273 if (VBOX_SUCCESS(rc))
1274 {
1275 rc = VINF_EM_RAW_EMULATE_INSTR;
1276
1277 if (!(Cpu.prefix & (PREFIX_REP | PREFIX_REPNE)))
1278 {
1279 switch (Cpu.pCurInstr->opcode)
1280 {
1281 case OP_IN:
1282 {
1283 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1284 rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1285 break;
1286 }
1287
1288 case OP_OUT:
1289 {
1290 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1291 rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1292 break;
1293 }
1294 }
1295 }
1296 else if (Cpu.prefix & PREFIX_REP)
1297 {
1298 switch (Cpu.pCurInstr->opcode)
1299 {
1300 case OP_INSB:
1301 case OP_INSWD:
1302 {
1303 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1304 rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1305 break;
1306 }
1307
1308 case OP_OUTSB:
1309 case OP_OUTSWD:
1310 {
1311 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1312 rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1313 break;
1314 }
1315 }
1316 }
1317
1318 /*
1319 * Handled the I/O return codes.
1320 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1321 */
1322 if (IOM_SUCCESS(rc))
1323 {
1324 pCtx->eip += Cpu.opsize;
1325 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1326 return rc;
1327 }
1328
1329 if (rc == VINF_EM_RAW_GUEST_TRAP)
1330 {
1331 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1332 rc = emR3RawGuestTrap(pVM);
1333 return rc;
1334 }
1335 AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1336
1337 if (VBOX_FAILURE(rc))
1338 {
1339 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1340 return rc;
1341 }
1342 AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1343 }
1344 STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1345 return emR3RawExecuteInstruction(pVM, "IO: ");
1346}
1347
1348
1349/**
1350 * Handle a guest context trap.
1351 *
1352 * @returns VBox status code suitable for EM.
1353 * @param pVM VM handle.
1354 */
1355static int emR3RawGuestTrap(PVM pVM)
1356{
1357 PCPUMCTX pCtx = pVM->em.s.pCtx;
1358
1359 /*
1360 * Get the trap info.
1361 */
1362 uint8_t u8TrapNo;
1363 TRPMEVENT enmType;;
1364 RTGCUINT uErrorCode;
1365 RTGCUINTPTR uCR2;
1366 int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1367 if (VBOX_FAILURE(rc))
1368 {
1369 AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1370 return rc;
1371 }
1372
1373 /* Traps can be directly forwarded in hardware accelerated mode. */
1374 if (HWACCMR3IsActive(pVM))
1375 {
1376#ifdef LOGGING_ENABLED
1377 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1378 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1379#endif
1380 return VINF_EM_RESCHEDULE_HWACC;
1381 }
1382
1383 /** Scan kernel code that traps; we might not get another chance. */
1384 if ( (pCtx->ss & X86_SEL_RPL) <= 1
1385 && !pCtx->eflags.Bits.u1VM)
1386 {
1387 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1388 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1389 }
1390
1391 if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1392 {
1393 DISCPUSTATE cpu;
1394
1395 /* If MONITOR & MWAIT are supported, then interpret them here. */
1396 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1397 if ( VBOX_SUCCESS(rc)
1398 && (cpu.pCurInstr->opcode == OP_MONITOR || cpu.pCurInstr->opcode == OP_MWAIT))
1399 {
1400 uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1401
1402 CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1403
1404 if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1405 {
1406 rc = TRPMResetTrap(pVM);
1407 AssertRC(rc);
1408
1409 rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1410 if (VBOX_SUCCESS(rc))
1411 {
1412 pCtx->eip += cpu.opsize;
1413 return rc;
1414 }
1415 return emR3RawExecuteInstruction(pVM, "Monitor: ");
1416 }
1417 }
1418 }
1419 else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1420 {
1421 DISCPUSTATE cpu;
1422
1423 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1424 if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1425 {
1426 /*
1427 * We should really check the TSS for the IO bitmap, but it's not like this
1428 * lazy approach really makes things worse.
1429 */
1430 rc = TRPMResetTrap(pVM);
1431 AssertRC(rc);
1432 return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1433 }
1434 }
1435
1436#ifdef LOG_ENABLED
1437 DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1438 DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1439
1440 /* Get guest page information. */
1441 uint64_t fFlags = 0;
1442 RTGCPHYS GCPhys = 0;
1443 int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1444 Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1445 pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1446 fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1447 fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1448#endif
1449
1450 /*
1451 * #PG has CR2.
1452 * (Because of stuff like above we must set CR2 in a delayed fashion.)
1453 */
1454 if (u8TrapNo == 14 /* #PG */)
1455 pCtx->cr2 = uCR2;
1456
1457 return VINF_EM_RESCHEDULE_REM;
1458}
1459
1460
1461/**
1462 * Handle a ring switch trap.
1463 * Need to do statistics and to install patches. The result is going to REM.
1464 *
1465 * @returns VBox status code suitable for EM.
1466 * @param pVM VM handle.
1467 */
1468int emR3RawRingSwitch(PVM pVM)
1469{
1470 int rc;
1471 DISCPUSTATE Cpu;
1472 PCPUMCTX pCtx = pVM->em.s.pCtx;
1473
1474 /*
1475 * sysenter, syscall & callgate
1476 */
1477 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1478 if (VBOX_SUCCESS(rc))
1479 {
1480 if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1481 {
1482 if (pCtx->SysEnter.cs != 0)
1483 {
1484 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1485 SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1486 if (VBOX_SUCCESS(rc))
1487 {
1488 DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1489 return VINF_EM_RESCHEDULE_RAW;
1490 }
1491 }
1492 }
1493
1494#ifdef VBOX_WITH_STATISTICS
1495 switch (Cpu.pCurInstr->opcode)
1496 {
1497 case OP_SYSENTER:
1498 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1499 break;
1500 case OP_SYSEXIT:
1501 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1502 break;
1503 case OP_SYSCALL:
1504 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1505 break;
1506 case OP_SYSRET:
1507 STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1508 break;
1509 }
1510#endif
1511 }
1512 else
1513 AssertRC(rc);
1514
1515 /* go to the REM to emulate a single instruction */
1516 return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1517}
1518
1519/**
1520 * Handle a trap (#PF or #GP) in patch code
1521 *
1522 * @returns VBox status code suitable for EM.
1523 * @param pVM VM handle.
1524 * @param pCtx CPU context
1525 * @param gcret GC return code
1526 */
1527int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1528{
1529 uint8_t u8TrapNo;
1530 int rc;
1531 TRPMEVENT enmType;
1532 RTGCUINT uErrorCode;
1533 RTGCUINTPTR uCR2;
1534
1535 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1536
1537 if (gcret == VINF_PATM_PATCH_INT3)
1538 {
1539 u8TrapNo = 3;
1540 uCR2 = 0;
1541 uErrorCode = 0;
1542 }
1543 else
1544 if (gcret == VINF_PATM_PATCH_TRAP_GP)
1545 {
1546 /* No active trap in this case. Kind of ugly. */
1547 u8TrapNo = X86_XCPT_GP;
1548 uCR2 = 0;
1549 uErrorCode = 0;
1550 }
1551 else
1552 {
1553 rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1554 if (VBOX_FAILURE(rc))
1555 {
1556 AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1557 return rc;
1558 }
1559 /* Reset the trap as we'll execute the original instruction again. */
1560 TRPMResetTrap(pVM);
1561 }
1562
1563 /*
1564 * Deal with traps inside patch code.
1565 * (This code won't run outside GC.)
1566 */
1567 if (u8TrapNo != 1)
1568 {
1569#ifdef LOG_ENABLED
1570 DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1571 DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1572
1573 DISCPUSTATE Cpu;
1574 int rc;
1575
1576 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1577 if ( VBOX_SUCCESS(rc)
1578 && Cpu.pCurInstr->opcode == OP_IRET)
1579 {
1580 uint32_t eip, selCS, uEFlags;
1581
1582 /* Iret crashes are bad as we have already changed the flags on the stack */
1583 rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1584 rc |= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1585 rc |= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1586 if (rc == VINF_SUCCESS)
1587 {
1588 if ( (uEFlags & X86_EFL_VM)
1589 || (selCS & X86_SEL_RPL) == 3)
1590 {
1591 uint32_t selSS, esp;
1592
1593 rc |= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1594 rc |= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1595
1596 if (uEFlags & X86_EFL_VM)
1597 {
1598 uint32_t selDS, selES, selFS, selGS;
1599 rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1600 rc |= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1601 rc |= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1602 rc |= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1603 if (rc == VINF_SUCCESS)
1604 {
1605 Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1606 Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1607 }
1608 }
1609 else
1610 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1611 }
1612 else
1613 Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1614 }
1615 }
1616#endif
1617 Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1618 pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1619
1620 RTGCPTR pNewEip;
1621 rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1622 switch (rc)
1623 {
1624 /*
1625 * Execute the faulting instruction.
1626 */
1627 case VINF_SUCCESS:
1628 {
1629 /** @todo execute a whole block */
1630 Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1631 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1632 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1633
1634 pCtx->eip = pNewEip;
1635 AssertRelease(pCtx->eip);
1636
1637 if (pCtx->eflags.Bits.u1IF)
1638 {
1639 /* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1640 * int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1641 */
1642 if ( u8TrapNo == X86_XCPT_GP
1643 && PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1644 {
1645 /** @todo move to PATMR3HandleTrap */
1646 Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1647 PATMR3RemovePatch(pVM, pCtx->eip);
1648 }
1649
1650 /** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1651 /** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1652
1653 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1654 /* Interrupts are enabled; just go back to the original instruction.
1655 return VINF_SUCCESS; */
1656 }
1657 return VINF_EM_RESCHEDULE_REM;
1658 }
1659
1660 /*
1661 * One instruction.
1662 */
1663 case VINF_PATCH_EMULATE_INSTR:
1664 Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1665 pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1666 pCtx->eip = pNewEip;
1667 AssertRelease(pCtx->eip);
1668 return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1669
1670 /*
1671 * The patch was disabled, hand it to the REM.
1672 */
1673 case VERR_PATCH_DISABLED:
1674 if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1675 Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1676 pCtx->eip = pNewEip;
1677 AssertRelease(pCtx->eip);
1678
1679 if (pCtx->eflags.Bits.u1IF)
1680 {
1681 /*
1682 * The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1683 */
1684 Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1685 return emR3RawExecuteInstruction(pVM, "PATCHIR");
1686 }
1687 return VINF_EM_RESCHEDULE_REM;
1688
1689 /* Force continued patch exection; usually due to write monitored stack. */
1690 case VINF_PATCH_CONTINUE:
1691 return VINF_SUCCESS;
1692
1693 /*
1694 * Anything else is *fatal*.
1695 */
1696 default:
1697 AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1698 return VERR_INTERNAL_ERROR;
1699 }
1700 }
1701 return VINF_SUCCESS;
1702}
1703
1704
1705/**
1706 * Handle a privileged instruction.
1707 *
1708 * @returns VBox status code suitable for EM.
1709 * @param pVM VM handle.
1710 */
1711int emR3RawPrivileged(PVM pVM)
1712{
1713 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1714 PCPUMCTX pCtx = pVM->em.s.pCtx;
1715
1716 Assert(!pCtx->eflags.Bits.u1VM);
1717
1718 if (PATMIsEnabled(pVM))
1719 {
1720 /*
1721 * Check if in patch code.
1722 */
1723 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1724 {
1725#ifdef LOG_ENABLED
1726 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1727#endif
1728 AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1729 return VERR_EM_RAW_PATCH_CONFLICT;
1730 }
1731 if ( (pCtx->ss & X86_SEL_RPL) == 0
1732 && !pCtx->eflags.Bits.u1VM
1733 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
1734 {
1735 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1736 SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1737 if (VBOX_SUCCESS(rc))
1738 {
1739#ifdef LOG_ENABLED
1740 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1741#endif
1742 DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1743 return VINF_SUCCESS;
1744 }
1745 }
1746 }
1747
1748#ifdef LOG_ENABLED
1749 if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1750 {
1751 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1752 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1753 }
1754#endif
1755
1756 /*
1757 * Instruction statistics and logging.
1758 */
1759 DISCPUSTATE Cpu;
1760 int rc;
1761
1762 rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1763 if (VBOX_SUCCESS(rc))
1764 {
1765#ifdef VBOX_WITH_STATISTICS
1766 PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1767 switch (Cpu.pCurInstr->opcode)
1768 {
1769 case OP_INVLPG:
1770 STAM_COUNTER_INC(&pStats->StatInvlpg);
1771 break;
1772 case OP_IRET:
1773 STAM_COUNTER_INC(&pStats->StatIret);
1774 break;
1775 case OP_CLI:
1776 STAM_COUNTER_INC(&pStats->StatCli);
1777 emR3RecordCli(pVM, pCtx->eip);
1778 break;
1779 case OP_STI:
1780 STAM_COUNTER_INC(&pStats->StatSti);
1781 break;
1782 case OP_INSB:
1783 case OP_INSWD:
1784 case OP_IN:
1785 case OP_OUTSB:
1786 case OP_OUTSWD:
1787 case OP_OUT:
1788 AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1789 break;
1790
1791 case OP_MOV_CR:
1792 if (Cpu.param1.flags & USE_REG_GEN32)
1793 {
1794 //read
1795 Assert(Cpu.param2.flags & USE_REG_CR);
1796 Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1797 STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1798 }
1799 else
1800 {
1801 //write
1802 Assert(Cpu.param1.flags & USE_REG_CR);
1803 Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1804 STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1805 }
1806 break;
1807
1808 case OP_MOV_DR:
1809 STAM_COUNTER_INC(&pStats->StatMovDRx);
1810 break;
1811 case OP_LLDT:
1812 STAM_COUNTER_INC(&pStats->StatMovLldt);
1813 break;
1814 case OP_LIDT:
1815 STAM_COUNTER_INC(&pStats->StatMovLidt);
1816 break;
1817 case OP_LGDT:
1818 STAM_COUNTER_INC(&pStats->StatMovLgdt);
1819 break;
1820 case OP_SYSENTER:
1821 STAM_COUNTER_INC(&pStats->StatSysEnter);
1822 break;
1823 case OP_SYSEXIT:
1824 STAM_COUNTER_INC(&pStats->StatSysExit);
1825 break;
1826 case OP_SYSCALL:
1827 STAM_COUNTER_INC(&pStats->StatSysCall);
1828 break;
1829 case OP_SYSRET:
1830 STAM_COUNTER_INC(&pStats->StatSysRet);
1831 break;
1832 case OP_HLT:
1833 STAM_COUNTER_INC(&pStats->StatHlt);
1834 break;
1835 default:
1836 STAM_COUNTER_INC(&pStats->StatMisc);
1837 Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1838 break;
1839 }
1840#endif
1841 if ( (pCtx->ss & X86_SEL_RPL) == 0
1842 && !pCtx->eflags.Bits.u1VM
1843 && SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1844 {
1845 uint32_t size;
1846
1847 STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1848 switch (Cpu.pCurInstr->opcode)
1849 {
1850 case OP_CLI:
1851 pCtx->eflags.u32 &= ~X86_EFL_IF;
1852 Assert(Cpu.opsize == 1);
1853 pCtx->eip += Cpu.opsize;
1854 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1855 return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1856
1857 case OP_STI:
1858 pCtx->eflags.u32 |= X86_EFL_IF;
1859 EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1860 Assert(Cpu.opsize == 1);
1861 pCtx->eip += Cpu.opsize;
1862 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1863 return VINF_SUCCESS;
1864
1865 case OP_HLT:
1866 if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1867 {
1868 PATMTRANSSTATE enmState;
1869 RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1870
1871 if (enmState == PATMTRANS_OVERWRITTEN)
1872 {
1873 rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1874 Assert(rc == VERR_PATCH_DISABLED);
1875 /* Conflict detected, patch disabled */
1876 Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1877
1878 enmState = PATMTRANS_SAFE;
1879 }
1880
1881 /* The translation had better be successful. Otherwise we can't recover. */
1882 AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1883 if (enmState != PATMTRANS_OVERWRITTEN)
1884 pCtx->eip = pOrgInstrGC;
1885 }
1886 /* no break; we could just return VINF_EM_HALT here */
1887
1888 case OP_MOV_CR:
1889 case OP_MOV_DR:
1890#ifdef LOG_ENABLED
1891 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1892 {
1893 DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1894 DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1895 }
1896#endif
1897
1898 rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1899 if (VBOX_SUCCESS(rc))
1900 {
1901 pCtx->eip += Cpu.opsize;
1902 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1903
1904 if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1905 && Cpu.param1.flags == USE_REG_CR /* write */
1906 )
1907 {
1908 /* Reschedule is necessary as the execution/paging mode might have changed. */
1909 return VINF_EM_RESCHEDULE;
1910 }
1911 return rc; /* can return VINF_EM_HALT as well. */
1912 }
1913 AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1914 break; /* fall back to the recompiler */
1915 }
1916 STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1917 }
1918 }
1919
1920 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1921 return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1922
1923 return emR3RawExecuteInstruction(pVM, "PRIV");
1924}
1925
1926
1927/**
1928 * Update the forced rawmode execution modifier.
1929 *
1930 * This function is called when we're returning from the raw-mode loop(s). If we're
1931 * in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1932 * if not in patch code, the flag will be cleared.
1933 *
1934 * We should never interrupt patch code while it's being executed. Cli patches can
1935 * contain big code blocks, but they are always executed with IF=0. Other patches
1936 * replace single instructions and should be atomic.
1937 *
1938 * @returns Updated rc.
1939 *
1940 * @param pVM The VM handle.
1941 * @param pCtx The guest CPU context.
1942 * @param rc The result code.
1943 */
1944DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1945{
1946 if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1947 {
1948 /* ignore reschedule attempts. */
1949 switch (rc)
1950 {
1951 case VINF_EM_RESCHEDULE:
1952 case VINF_EM_RESCHEDULE_REM:
1953 rc = VINF_SUCCESS;
1954 break;
1955 }
1956 pVM->em.s.fForceRAW = true;
1957 }
1958 else
1959 pVM->em.s.fForceRAW = false;
1960 return rc;
1961}
1962
1963
1964/**
1965 * Process a subset of the raw-mode return code.
1966 *
1967 * Since we have to share this with raw-mode single stepping, this inline
1968 * function has been created to avoid code duplication.
1969 *
1970 * @returns VINF_SUCCESS if it's ok to continue raw mode.
1971 * @returns VBox status code to return to the EM main loop.
1972 *
1973 * @param pVM The VM handle
1974 * @param rc The return code.
1975 * @param pCtx The guest cpu context.
1976 */
1977DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
1978{
1979 switch (rc)
1980 {
1981 /*
1982 * Common & simple ones.
1983 */
1984 case VINF_SUCCESS:
1985 break;
1986 case VINF_EM_RESCHEDULE_RAW:
1987 case VINF_EM_RESCHEDULE_HWACC:
1988 case VINF_EM_RAW_INTERRUPT:
1989 case VINF_EM_RAW_TO_R3:
1990 case VINF_EM_RAW_TIMER_PENDING:
1991 case VINF_EM_PENDING_REQUEST:
1992 rc = VINF_SUCCESS;
1993 break;
1994
1995 /*
1996 * Privileged instruction.
1997 */
1998 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1999 case VINF_PATM_PATCH_TRAP_GP:
2000 rc = emR3RawPrivileged(pVM);
2001 break;
2002
2003 /*
2004 * Got a trap which needs dispatching.
2005 */
2006 case VINF_EM_RAW_GUEST_TRAP:
2007 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2008 {
2009 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2010 rc = VERR_EM_RAW_PATCH_CONFLICT;
2011 break;
2012 }
2013
2014 Assert(TRPMHasTrap(pVM));
2015 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2016
2017 if (TRPMHasTrap(pVM))
2018 {
2019 uint8_t u8Interrupt;
2020 uint32_t uErrorCode;
2021 TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2022
2023 rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2024 AssertRC(rc);
2025
2026 if (uErrorCode != ~0U)
2027 enmError = TRPM_TRAP_HAS_ERRORCODE;
2028
2029 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2030 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2031 {
2032 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2033 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2034
2035 /** If it was successful, then we could go back to raw mode. */
2036 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2037 {
2038 /* Must check pending forced actions as our IDT or GDT might be out of sync */
2039 EMR3CheckRawForcedActions(pVM);
2040
2041 rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2042 if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2043 {
2044 TRPMResetTrap(pVM);
2045 return VINF_EM_RESCHEDULE_RAW;
2046 }
2047 }
2048 }
2049 }
2050 rc = emR3RawGuestTrap(pVM);
2051 break;
2052
2053 /*
2054 * Trap in patch code.
2055 */
2056 case VINF_PATM_PATCH_TRAP_PF:
2057 case VINF_PATM_PATCH_INT3:
2058 rc = emR3PatchTrap(pVM, pCtx, rc);
2059 break;
2060
2061 case VINF_PATM_DUPLICATE_FUNCTION:
2062 Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2063 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2064 AssertRC(rc);
2065 rc = VINF_SUCCESS;
2066 break;
2067
2068 case VINF_PATM_CHECK_PATCH_PAGE:
2069 rc = PATMR3HandleMonitoredPage(pVM);
2070 AssertRC(rc);
2071 rc = VINF_SUCCESS;
2072 break;
2073
2074 /*
2075 * Patch manager.
2076 */
2077 case VERR_EM_RAW_PATCH_CONFLICT:
2078 AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2079 break;
2080
2081 /*
2082 * Memory mapped I/O access - attempt to patch the instruction
2083 */
2084 case VINF_PATM_HC_MMIO_PATCH_READ:
2085 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2086 PATMFL_MMIO_ACCESS | (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2087 if (VBOX_FAILURE(rc))
2088 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2089 break;
2090
2091 case VINF_PATM_HC_MMIO_PATCH_WRITE:
2092 AssertFailed(); /* not yet implemented. */
2093 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2094 break;
2095
2096 /*
2097 * Conflict or out of page tables.
2098 *
2099 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2100 * do here is to execute the pending forced actions.
2101 */
2102 case VINF_PGM_SYNC_CR3:
2103 AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2104 ("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2105 rc = VINF_SUCCESS;
2106 break;
2107
2108 /*
2109 * Paging mode change.
2110 */
2111 case VINF_PGM_CHANGE_MODE:
2112 rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2113 if (VBOX_SUCCESS(rc))
2114 rc = VINF_EM_RESCHEDULE;
2115 break;
2116
2117 /*
2118 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
2119 */
2120 case VINF_CSAM_PENDING_ACTION:
2121 rc = VINF_SUCCESS;
2122 break;
2123
2124 /*
2125 * Invoked Interrupt gate - must directly (!) go to the recompiler.
2126 */
2127 case VINF_EM_RAW_INTERRUPT_PENDING:
2128 case VINF_EM_RAW_RING_SWITCH_INT:
2129 {
2130 uint8_t u8Interrupt;
2131
2132 Assert(TRPMHasTrap(pVM));
2133 Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2134
2135 if (TRPMHasTrap(pVM))
2136 {
2137 u8Interrupt = TRPMGetTrapNo(pVM);
2138
2139 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2140 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2141 {
2142 CSAMR3CheckGates(pVM, u8Interrupt, 1);
2143 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2144 /** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2145 }
2146 }
2147 rc = VINF_EM_RESCHEDULE_REM;
2148 break;
2149 }
2150
2151 /*
2152 * Other ring switch types.
2153 */
2154 case VINF_EM_RAW_RING_SWITCH:
2155 rc = emR3RawRingSwitch(pVM);
2156 break;
2157
2158 /*
2159 * REMGCNotifyInvalidatePage() failed because of overflow.
2160 */
2161 case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2162 Assert((pCtx->ss & X86_SEL_RPL) != 1);
2163 REMR3ReplayInvalidatedPages(pVM);
2164 break;
2165
2166 /*
2167 * I/O Port access - emulate the instruction.
2168 */
2169 case VINF_IOM_HC_IOPORT_READ:
2170 case VINF_IOM_HC_IOPORT_WRITE:
2171 rc = emR3RawExecuteIOInstruction(pVM);
2172 break;
2173
2174 /*
2175 * Memory mapped I/O access - emulate the instruction.
2176 */
2177 case VINF_IOM_HC_MMIO_READ:
2178 case VINF_IOM_HC_MMIO_WRITE:
2179 case VINF_IOM_HC_MMIO_READ_WRITE:
2180 rc = emR3RawExecuteInstruction(pVM, "MMIO");
2181 break;
2182
2183 /*
2184 * Execute instruction.
2185 */
2186 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2187 rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2188 break;
2189 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2190 rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2191 break;
2192 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2193 rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2194 break;
2195 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2196 rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2197 break;
2198 case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2199 rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2200 break;
2201
2202 case VINF_EM_RAW_EMULATE_INSTR_HLT:
2203 /** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2204 rc = emR3RawPrivileged(pVM);
2205 break;
2206
2207 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2208 rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2209 break;
2210
2211 case VINF_EM_RAW_EMULATE_INSTR:
2212 case VINF_PATCH_EMULATE_INSTR:
2213 rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2214 break;
2215
2216 /*
2217 * Stale selector and iret traps => REM.
2218 */
2219 case VINF_EM_RAW_STALE_SELECTOR:
2220 case VINF_EM_RAW_IRET_TRAP:
2221 /* We will not go to the recompiler if EIP points to patch code. */
2222 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2223 {
2224 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2225 }
2226 LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2227 rc = VINF_EM_RESCHEDULE_REM;
2228 break;
2229
2230 /*
2231 * Up a level.
2232 */
2233 case VINF_EM_TERMINATE:
2234 case VINF_EM_OFF:
2235 case VINF_EM_RESET:
2236 case VINF_EM_SUSPEND:
2237 case VINF_EM_HALT:
2238 case VINF_EM_RESUME:
2239 case VINF_EM_RESCHEDULE:
2240 case VINF_EM_RESCHEDULE_REM:
2241 break;
2242
2243 /*
2244 * Up a level and invoke the debugger.
2245 */
2246 case VINF_EM_DBG_STEPPED:
2247 case VINF_EM_DBG_BREAKPOINT:
2248 case VINF_EM_DBG_STEP:
2249 case VINF_EM_DBG_HYPER_ASSERTION:
2250 case VINF_EM_DBG_HYPER_BREAKPOINT:
2251 case VINF_EM_DBG_HYPER_STEPPED:
2252 case VINF_EM_DBG_STOP:
2253 break;
2254
2255 /*
2256 * Up a level, dump and debug.
2257 */
2258 case VERR_TRPM_DONT_PANIC:
2259 case VERR_TRPM_PANIC:
2260 break;
2261
2262 /*
2263 * Anything which is not known to us means an internal error
2264 * and the termination of the VM!
2265 */
2266 default:
2267 AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2268 break;
2269 }
2270 return rc;
2271}
2272
2273/**
2274 * Check for pending raw actions
2275 *
2276 * @returns VBox status code.
2277 * @param pVM The VM to operate on.
2278 */
2279EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2280{
2281 return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2282}
2283
2284
2285/**
2286 * Process raw-mode specific forced actions.
2287 *
2288 * This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2289 *
2290 * @returns VBox status code.
2291 * Only the normal success/failure stuff, no VINF_EM_*.
2292 * @param pVM The VM handle.
2293 * @param pCtx The guest CPUM register context.
2294 */
2295static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2296{
2297 /*
2298 * Note that the order is *vitally* important!
2299 * Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2300 */
2301
2302
2303 /*
2304 * Sync selector tables.
2305 */
2306 if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT))
2307 {
2308 int rc = SELMR3UpdateFromCPUM(pVM);
2309 if (VBOX_FAILURE(rc))
2310 return rc;
2311 }
2312
2313 /*
2314 * Sync IDT.
2315 */
2316 if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2317 {
2318 int rc = TRPMR3SyncIDT(pVM);
2319 if (VBOX_FAILURE(rc))
2320 return rc;
2321 }
2322
2323 /*
2324 * Sync TSS.
2325 */
2326 if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2327 {
2328 int rc = SELMR3SyncTSS(pVM);
2329 if (VBOX_FAILURE(rc))
2330 return rc;
2331 }
2332
2333 /*
2334 * Sync page directory.
2335 */
2336 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2337 {
2338 int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2339 if (VBOX_FAILURE(rc))
2340 return rc;
2341
2342 Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT));
2343
2344 /* Prefetch pages for EIP and ESP */
2345 /** @todo This is rather expensive. Should investigate if it really helps at all. */
2346 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2347 if (rc == VINF_SUCCESS)
2348 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2349 if (rc != VINF_SUCCESS)
2350 {
2351 if (rc != VINF_PGM_SYNC_CR3)
2352 return rc;
2353 rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2354 if (VBOX_FAILURE(rc))
2355 return rc;
2356 }
2357 /** @todo maybe prefetch the supervisor stack page as well */
2358 }
2359
2360 return VINF_SUCCESS;
2361}
2362
2363
2364/**
2365 * Executes raw code.
2366 *
2367 * This function contains the raw-mode version of the inner
2368 * execution loop (the outer loop being in EMR3ExecuteVM()).
2369 *
2370 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2371 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2372 *
2373 * @param pVM VM handle.
2374 * @param pfFFDone Where to store an indicator telling whether or not
2375 * FFs were done before returning.
2376 */
2377static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2378{
2379 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2380
2381 int rc = VERR_INTERNAL_ERROR;
2382 PCPUMCTX pCtx = pVM->em.s.pCtx;
2383 LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2384 pVM->em.s.fForceRAW = false;
2385 *pfFFDone = false;
2386
2387
2388 /*
2389 *
2390 * Spin till we get a forced action or raw mode status code resulting in
2391 * in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2392 *
2393 */
2394 for (;;)
2395 {
2396 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2397
2398 /*
2399 * Check various preconditions.
2400 */
2401#ifdef VBOX_STRICT
2402 Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2403 Assert(!(pCtx->cr4 & X86_CR4_PAE));
2404 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) == 3 || (pCtx->ss & X86_SEL_RPL) == 0);
2405 AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2406 || PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2407 ("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2408 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2409 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2410 {
2411 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2412 return VERR_INTERNAL_ERROR;
2413 }
2414#endif /* VBOX_STRICT */
2415
2416 /*
2417 * Process high priority pre-execution raw-mode FFs.
2418 */
2419 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2420 {
2421 rc = emR3RawForcedActions(pVM, pCtx);
2422 if (VBOX_FAILURE(rc))
2423 break;
2424 }
2425
2426 /*
2427 * If we're going to execute ring-0 code, the guest state needs to
2428 * be modified a bit and some of the state components (IF, SS/CS RPL,
2429 * and perhaps EIP) needs to be stored with PATM.
2430 */
2431 rc = CPUMRawEnter(pVM, NULL);
2432 if (rc != VINF_SUCCESS)
2433 {
2434 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2435 break;
2436 }
2437
2438 /*
2439 * Scan code before executing it. Don't bother with user mode or V86 code
2440 */
2441 if ( (pCtx->ss & X86_SEL_RPL) <= 1
2442 && !pCtx->eflags.Bits.u1VM
2443 && !PATMIsPatchGCAddr(pVM, pCtx->eip))
2444 {
2445 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2446 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2447 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2448 }
2449
2450#ifdef LOG_ENABLED
2451 /*
2452 * Log important stuff before entering GC.
2453 */
2454 PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2455 if (pCtx->eflags.Bits.u1VM)
2456 Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2457 else if ((pCtx->ss & X86_SEL_RPL) == 1)
2458 {
2459 bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2460 Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2461 }
2462 else if ((pCtx->ss & X86_SEL_RPL) == 3)
2463 Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2464#endif /* LOG_ENABLED */
2465
2466
2467
2468 /*
2469 * Execute the code.
2470 */
2471 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2472 STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2473 VMMR3Unlock(pVM);
2474 rc = VMMR3RawRunGC(pVM);
2475 VMMR3Lock(pVM);
2476 STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2477 STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2478
2479 LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2480 LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2481
2482 /*
2483 * Restore the real CPU state and deal with high priority post
2484 * execution FFs before doing anything else.
2485 */
2486 rc = CPUMRawLeave(pVM, NULL, rc);
2487 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2488 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2489 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2490
2491#ifdef PGM_CACHE_VERY_STRICT
2492 /*
2493 * Page manager cache checks.
2494 */
2495 if ( rc == VINF_EM_RAW_INTERRUPT
2496 || rc == VINF_EM_RAW_GUEST_TRAP
2497 || rc == VINF_IOM_HC_IOPORT_READ
2498 || rc == VINF_IOM_HC_IOPORT_WRITE
2499 //|| rc == VINF_PATM_PATCH_INT3
2500 )
2501 pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2502#endif
2503
2504#ifdef VBOX_STRICT
2505 /*
2506 * Assert TSS consistency & rc vs patch code.
2507 */
2508 if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS | VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2509 && EMIsRawRing0Enabled(pVM))
2510 SELMR3CheckTSS(pVM);
2511 switch (rc)
2512 {
2513 case VINF_SUCCESS:
2514 case VINF_EM_RAW_INTERRUPT:
2515 case VINF_PATM_PATCH_TRAP_PF:
2516 case VINF_PATM_PATCH_TRAP_GP:
2517 case VINF_PATM_PATCH_INT3:
2518 case VINF_PATM_CHECK_PATCH_PAGE:
2519 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2520 case VINF_EM_RAW_GUEST_TRAP:
2521 case VINF_EM_RESCHEDULE_RAW:
2522 break;
2523
2524 default:
2525 if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2526 LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2527 break;
2528 }
2529 /*
2530 * Let's go paranoid!
2531 */
2532 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2533 && PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2534 {
2535 AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2536 return VERR_INTERNAL_ERROR;
2537 }
2538#endif /* VBOX_STRICT */
2539
2540 /*
2541 * Process the returned status code.
2542 */
2543 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2544 {
2545 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2546 break;
2547 }
2548 rc = emR3RawHandleRC(pVM, pCtx, rc);
2549 if (rc != VINF_SUCCESS)
2550 {
2551 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2552 if (rc != VINF_SUCCESS)
2553 {
2554 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2555 break;
2556 }
2557 }
2558
2559 /*
2560 * Check and execute forced actions.
2561 */
2562#ifdef VBOX_HIGH_RES_TIMERS_HACK
2563 TMTimerPoll(pVM);
2564#endif
2565 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2566 if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2567 {
2568 Assert(pCtx->eflags.Bits.u1VM || (pCtx->ss & X86_SEL_RPL) != 1);
2569
2570 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2571 rc = emR3ForcedActions(pVM, rc);
2572 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2573 if ( rc != VINF_SUCCESS
2574 && rc != VINF_EM_RESCHEDULE_RAW)
2575 {
2576 rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2577 if (rc != VINF_SUCCESS)
2578 {
2579 *pfFFDone = true;
2580 break;
2581 }
2582 }
2583 }
2584 }
2585
2586 /*
2587 * Return to outer loop.
2588 */
2589#if defined(LOG_ENABLED) && defined(DEBUG)
2590 RTLogFlush(NULL);
2591#endif
2592 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2593 return rc;
2594}
2595
2596
2597/**
2598 * Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2599 *
2600 * This function contains the raw-mode version of the inner
2601 * execution loop (the outer loop being in EMR3ExecuteVM()).
2602 *
2603 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2604 * VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2605 *
2606 * @param pVM VM handle.
2607 * @param pfFFDone Where to store an indicator telling whether or not
2608 * FFs were done before returning.
2609 */
2610static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2611{
2612 int rc = VERR_INTERNAL_ERROR;
2613 PCPUMCTX pCtx = pVM->em.s.pCtx;
2614
2615 LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2616 *pfFFDone = false;
2617
2618 STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2619
2620 /*
2621 * Spin till we get a forced action which returns anything but VINF_SUCCESS.
2622 */
2623 for (;;)
2624 {
2625 STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2626
2627 /*
2628 * Check various preconditions.
2629 */
2630 VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_TSS));
2631
2632 /*
2633 * Process high priority pre-execution raw-mode FFs.
2634 */
2635 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2636 {
2637 rc = emR3RawForcedActions(pVM, pCtx);
2638 if (VBOX_FAILURE(rc))
2639 break;
2640 }
2641
2642#ifdef LOG_ENABLED
2643 uint8_t u8Vector;
2644
2645 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2646 if (rc == VINF_SUCCESS)
2647 {
2648 Log(("Pending hardware interrupt %d\n", u8Vector));
2649 }
2650 /*
2651 * Log important stuff before entering GC.
2652 */
2653 uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2654
2655 if (pCtx->eflags.Bits.u1VM)
2656 Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2657 else
2658 Log(("HWR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
2659#endif
2660
2661 /*
2662 * Execute the code.
2663 */
2664 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2665 STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2666 VMMR3Unlock(pVM);
2667 rc = VMMR3HwAccRunGC(pVM);
2668 VMMR3Lock(pVM);
2669 STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2670
2671 /*
2672 * Deal with high priority post execution FFs before doing anything else.
2673 */
2674 VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2675 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2676 rc = emR3HighPriorityPostForcedActions(pVM, rc);
2677
2678 /*
2679 * Process the returned status code.
2680 */
2681 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2682 break;
2683
2684 rc = emR3RawHandleRC(pVM, pCtx, rc);
2685 if (rc != VINF_SUCCESS)
2686 break;
2687
2688 /*
2689 * Check and execute forced actions.
2690 */
2691#ifdef VBOX_HIGH_RES_TIMERS_HACK
2692 TMTimerPoll(pVM);
2693#endif
2694 if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2695 {
2696 rc = emR3ForcedActions(pVM, rc);
2697 if ( rc != VINF_SUCCESS
2698 && rc != VINF_EM_RESCHEDULE_HWACC)
2699 {
2700 *pfFFDone = true;
2701 break;
2702 }
2703 }
2704 }
2705 /*
2706 * Return to outer loop.
2707 */
2708#if defined(LOG_ENABLED) && defined(DEBUG)
2709 RTLogFlush(NULL);
2710#endif
2711 return rc;
2712}
2713
2714
2715/**
2716 * Decides whether to execute RAW, HWACC or REM.
2717 *
2718 * @returns new EM state
2719 * @param pVM The VM.
2720 * @param pCtx The CPU context.
2721 */
2722inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2723{
2724 /*
2725 * When forcing raw-mode execution, things are simple.
2726 */
2727 if (pVM->em.s.fForceRAW)
2728 return EMSTATE_RAW;
2729
2730 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2731 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2732 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2733
2734 X86EFLAGS EFlags = pCtx->eflags;
2735 if (HWACCMIsEnabled(pVM))
2736 {
2737 /* Hardware accelerated raw-mode:
2738 *
2739 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2740 */
2741 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2742 return EMSTATE_HWACC;
2743
2744 /** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2745 return EMSTATE_REM;
2746 }
2747
2748 /* Standard raw-mode:
2749 *
2750 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2751 * or 32 bits protected mode ring 0 code
2752 *
2753 * The tests are ordered by the likelyhood of being true during normal execution.
2754 */
2755 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
2756 {
2757 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2758 return EMSTATE_REM;
2759 }
2760
2761#ifndef VBOX_RAW_V86
2762 if (EFlags.u32 & X86_EFL_VM) {
2763 Log2(("raw mode refused: VM_MASK\n"));
2764 return EMSTATE_REM;
2765 }
2766#endif
2767
2768 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2769 uint32_t u32CR0 = pCtx->cr0;
2770 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
2771 {
2772 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2773 return EMSTATE_REM;
2774 }
2775
2776 if (pCtx->cr4 & X86_CR4_PAE)
2777 {
2778 //Log2(("raw mode refused: PAE\n"));
2779 return EMSTATE_REM;
2780 }
2781
2782 unsigned uSS = pCtx->ss;
2783 if ( pCtx->eflags.Bits.u1VM
2784 || (uSS & X86_SEL_RPL) == 3)
2785 {
2786 if (!EMIsRawRing3Enabled(pVM))
2787 return EMSTATE_REM;
2788
2789 if (!(EFlags.u32 & X86_EFL_IF))
2790 {
2791 Log2(("raw mode refused: IF (RawR3)\n"));
2792 return EMSTATE_REM;
2793 }
2794
2795 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2796 {
2797 Log2(("raw mode refused: CR0.WP + RawR0\n"));
2798 return EMSTATE_REM;
2799 }
2800 }
2801 else
2802 {
2803 if (!EMIsRawRing0Enabled(pVM))
2804 return EMSTATE_REM;
2805
2806 /* Only ring 0 supervisor code. */
2807 if ((uSS & X86_SEL_RPL) != 0)
2808 {
2809 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2810 return EMSTATE_REM;
2811 }
2812
2813 // Let's start with pure 32 bits ring 0 code first
2814 /** @todo What's pure 32-bit mode? flat? */
2815 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2816 || !(pCtx->csHid.Attr.n.u1DefBig))
2817 {
2818 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2819 return EMSTATE_REM;
2820 }
2821
2822 /* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2823 if (!(u32CR0 & X86_CR0_WP))
2824 {
2825 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2826 return EMSTATE_REM;
2827 }
2828
2829 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2830 {
2831 Log2(("raw r0 mode forced: patch code\n"));
2832 return EMSTATE_RAW;
2833 }
2834
2835#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2836 if (!(EFlags.u32 & X86_EFL_IF))
2837 {
2838 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2839 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2840 return EMSTATE_REM;
2841 }
2842#endif
2843
2844 /** @todo still necessary??? */
2845 if (EFlags.Bits.u2IOPL != 0)
2846 {
2847 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2848 return EMSTATE_REM;
2849 }
2850 }
2851
2852 Assert(PGMPhysIsA20Enabled(pVM));
2853 return EMSTATE_RAW;
2854}
2855
2856
2857/**
2858 * Executes all high priority post execution force actions.
2859 *
2860 * @returns rc or a fatal status code.
2861 *
2862 * @param pVM VM handle.
2863 * @param rc The current rc.
2864 */
2865static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2866{
2867 if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2868 PDMR3CritSectFF(pVM);
2869
2870 if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2871 CSAMR3DoPendingAction(pVM);
2872
2873 return rc;
2874}
2875
2876
2877/**
2878 * Executes all pending forced actions.
2879 *
2880 * Forced actions can cause execution delays and execution
2881 * rescheduling. The first we deal with using action priority, so
2882 * that for instance pending timers aren't scheduled and ran until
2883 * right before execution. The rescheduling we deal with using
2884 * return codes. The same goes for VM termination, only in that case
2885 * we exit everything.
2886 *
2887 * @returns VBox status code of equal or greater importance/severity than rc.
2888 * The most important ones are: VINF_EM_RESCHEDULE,
2889 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2890 *
2891 * @param pVM VM handle.
2892 * @param rc The current rc.
2893 *
2894 */
2895static int emR3ForcedActions(PVM pVM, int rc)
2896{
2897#ifdef VBOX_STRICT
2898 int rcIrq = VINF_SUCCESS;
2899#endif
2900 STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2901
2902#define UPDATE_RC() \
2903 do { \
2904 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2905 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
2906 break; \
2907 if (!rc || rc2 < rc) \
2908 rc = rc2; \
2909 } while (0)
2910
2911 int rc2;
2912
2913 /*
2914 * Post execution chunk first.
2915 */
2916 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2917 {
2918 /*
2919 * Termination request.
2920 */
2921 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2922 {
2923 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2924 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2925 return VINF_EM_TERMINATE;
2926 }
2927
2928 /*
2929 * Debugger Facility polling.
2930 */
2931 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2932 {
2933 rc2 = DBGFR3VMMForcedAction(pVM);
2934 UPDATE_RC();
2935 }
2936
2937 /*
2938 * Postponed reset request.
2939 */
2940 if (VM_FF_ISSET(pVM, VM_FF_RESET))
2941 {
2942 rc2 = VMR3Reset(pVM);
2943 UPDATE_RC();
2944 VM_FF_CLEAR(pVM, VM_FF_RESET);
2945 }
2946
2947 /*
2948 * CSAM page scanning.
2949 */
2950 if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2951 {
2952 PCPUMCTX pCtx = pVM->em.s.pCtx;
2953
2954 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2955 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2956
2957 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2958 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2959 }
2960
2961 /* check that we got them all */
2962 Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_CSAM_SCAN_PAGE)));
2963 }
2964
2965 /*
2966 * Normal priority then.
2967 * (Executed in no particular order.)
2968 */
2969 if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2970 {
2971 /*
2972 * PDM Queues are pending.
2973 */
2974 if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
2975 PDMR3QueueFlushAll(pVM);
2976
2977 /*
2978 * PDM DMA transfers are pending.
2979 */
2980 if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
2981 PDMR3DmaRun(pVM);
2982
2983 /*
2984 * Requests from other threads.
2985 */
2986 if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
2987 {
2988 rc2 = VMR3ReqProcess(pVM);
2989 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE)
2990 {
2991 Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
2992 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2993 return rc2;
2994 }
2995 UPDATE_RC();
2996 }
2997
2998 /* check that we got them all */
2999 Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA)));
3000 }
3001
3002 /*
3003 * Execute polling function ever so often.
3004 * THIS IS A HACK, IT WILL BE *REPLACED* BY PROPER ASYNC NETWORKING SOON!
3005 */
3006 static unsigned cLast = 0;
3007 if (!((++cLast) % 4))
3008 PDMR3Poll(pVM);
3009
3010 /*
3011 * High priority pre execution chunk last.
3012 * (Executed in ascending priority order.)
3013 */
3014 if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3015 {
3016 /*
3017 * Timers before interrupts.
3018 */
3019 if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3020 TMR3TimerQueuesDo(pVM);
3021
3022 /*
3023 * The instruction following an emulated STI should *always* be executed!
3024 */
3025 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3026 {
3027 Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3028 if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3029 {
3030 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3031 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3032 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3033 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3034 */
3035 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3036 }
3037 if (HWACCMR3IsActive(pVM))
3038 rc2 = VINF_EM_RESCHEDULE_HWACC;
3039 else
3040 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3041
3042 UPDATE_RC();
3043 }
3044
3045 /*
3046 * Interrupts.
3047 */
3048 if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3049 && (!rc || rc >= VINF_EM_RESCHEDULE_RAW)
3050 && !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3051 && PATMAreInterruptsEnabled(pVM)
3052 && !HWACCMR3IsEventPending(pVM))
3053 {
3054 if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC))
3055 {
3056 /** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3057 /** @todo this really isn't nice, should properly handle this */
3058 rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3059#ifdef VBOX_STRICT
3060 rcIrq = rc2;
3061#endif
3062 UPDATE_RC();
3063 }
3064 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3065 else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3066 {
3067 rc2 = VINF_EM_RESCHEDULE_REM;
3068 UPDATE_RC();
3069 }
3070 }
3071
3072 /*
3073 * Debugger Facility request.
3074 */
3075 if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3076 {
3077 rc2 = DBGFR3VMMForcedAction(pVM);
3078 UPDATE_RC();
3079 }
3080
3081 /*
3082 * Termination request.
3083 */
3084 if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3085 {
3086 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3087 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3088 return VINF_EM_TERMINATE;
3089 }
3090
3091#ifdef DEBUG
3092 /*
3093 * Debug, pause the VM.
3094 */
3095 if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3096 {
3097 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3098 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3099 return VINF_EM_SUSPEND;
3100 }
3101
3102#endif
3103 /* check that we got them all */
3104 Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER | VM_FF_INTERRUPT_APIC | VM_FF_INTERRUPT_PIC | VM_FF_DBGF | VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL | VM_FF_SELM_SYNC_TSS | VM_FF_TRPM_SYNC_IDT | VM_FF_SELM_SYNC_GDT | VM_FF_SELM_SYNC_LDT | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_INHIBIT_INTERRUPTS)));
3105 }
3106
3107#undef UPDATE_RC
3108 Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3109 STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3110 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
3111 return rc;
3112}
3113
3114
3115/**
3116 * Execute VM.
3117 *
3118 * This function is the main loop of the VM. The emulation thread
3119 * calls this function when the VM has been successfully constructed
3120 * and we're ready for executing the VM.
3121 *
3122 * Returning from this function means that the VM is turned off or
3123 * suspended (state already saved) and deconstruction in next in line.
3124 *
3125 * All interaction from other thread are done using forced actions
3126 * and signaling of the wait object.
3127 *
3128 * @returns VBox status code.
3129 * @param pVM The VM to operate on.
3130 */
3131EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3132{
3133 LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3134 pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3135 VM_ASSERT_EMT(pVM);
3136 Assert(pVM->em.s.enmState == EMSTATE_NONE || pVM->em.s.enmState == EMSTATE_SUSPENDED);
3137
3138 VMMR3Lock(pVM);
3139
3140 int rc = setjmp(pVM->em.s.u.FatalLongJump);
3141 if (rc == 0)
3142 {
3143 /*
3144 * Start the virtual time.
3145 */
3146 rc = TMVirtualResume(pVM);
3147 Assert(rc == VINF_SUCCESS);
3148 rc = TMCpuTickResume(pVM);
3149 Assert(rc == VINF_SUCCESS);
3150
3151 /*
3152 * The Outer Main Loop.
3153 */
3154 bool fFFDone = false;
3155 rc = VINF_EM_RESCHEDULE;
3156 pVM->em.s.enmState = EMSTATE_REM;
3157 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3158 for (;;)
3159 {
3160 /*
3161 * Before we can schedule anything (we're here because
3162 * scheduling is required) we must service any pending
3163 * forced actions to avoid any pending action causing
3164 * immidate rescheduling upon entering an inner loop
3165 *
3166 * Do forced actions.
3167 */
3168 if ( !fFFDone
3169 && rc != VINF_EM_TERMINATE
3170 && rc != VINF_EM_OFF
3171 && VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3172 {
3173 rc = emR3ForcedActions(pVM, rc);
3174 if ( ( rc == VINF_EM_RESCHEDULE_REM
3175 || rc == VINF_EM_RESCHEDULE_HWACC)
3176 && pVM->em.s.fForceRAW)
3177 rc = VINF_EM_RESCHEDULE_RAW;
3178 }
3179 else if (fFFDone)
3180 fFFDone = false;
3181
3182 /*
3183 * Now what to do?
3184 */
3185 Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3186 switch (rc)
3187 {
3188 /*
3189 * Keep doing what we're currently doing.
3190 */
3191 case VINF_SUCCESS:
3192 break;
3193
3194 /*
3195 * Reschedule - to raw-mode execution.
3196 */
3197 case VINF_EM_RESCHEDULE_RAW:
3198 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3199 pVM->em.s.enmState = EMSTATE_RAW;
3200 break;
3201
3202 /*
3203 * Reschedule - to hardware accelerated raw-mode execution.
3204 */
3205 case VINF_EM_RESCHEDULE_HWACC:
3206 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3207 Assert(!pVM->em.s.fForceRAW);
3208 pVM->em.s.enmState = EMSTATE_HWACC;
3209 break;
3210
3211 /*
3212 * Reschedule - to recompiled execution.
3213 */
3214 case VINF_EM_RESCHEDULE_REM:
3215 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3216 pVM->em.s.enmState = EMSTATE_REM;
3217 break;
3218
3219 /*
3220 * Resume.
3221 */
3222 case VINF_EM_RESUME:
3223 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3224 /* fall through and get scheduled. */
3225
3226 /*
3227 * Reschedule.
3228 */
3229 case VINF_EM_RESCHEDULE:
3230 {
3231 EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3232 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3233 pVM->em.s.enmState = enmState;
3234 break;
3235 }
3236
3237 /*
3238 * Halted.
3239 */
3240 case VINF_EM_HALT:
3241 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3242 pVM->em.s.enmState = EMSTATE_HALTED;
3243 break;
3244
3245 /*
3246 * Suspend.
3247 */
3248 case VINF_EM_SUSPEND:
3249 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3250 pVM->em.s.enmState = EMSTATE_SUSPENDED;
3251 break;
3252
3253 /*
3254 * Reset.
3255 * We might end up doing a double reset for now, we'll have to clean up the mess later.
3256 */
3257 case VINF_EM_RESET:
3258 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3259 pVM->em.s.enmState = EMSTATE_REM;
3260 break;
3261
3262 /*
3263 * Power Off.
3264 */
3265 case VINF_EM_OFF:
3266 pVM->em.s.enmState = EMSTATE_TERMINATING;
3267 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3268 TMVirtualPause(pVM);
3269 TMCpuTickPause(pVM);
3270 VMMR3Unlock(pVM);
3271 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3272 return rc;
3273
3274 /*
3275 * Terminate the VM.
3276 */
3277 case VINF_EM_TERMINATE:
3278 pVM->em.s.enmState = EMSTATE_TERMINATING;
3279 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3280 TMVirtualPause(pVM);
3281 TMCpuTickPause(pVM);
3282 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3283 return rc;
3284
3285 /*
3286 * Guest debug events.
3287 */
3288 case VINF_EM_DBG_STEPPED:
3289 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3290 case VINF_EM_DBG_STOP:
3291 case VINF_EM_DBG_BREAKPOINT:
3292 case VINF_EM_DBG_STEP:
3293 if (pVM->em.s.enmState == EMSTATE_RAW)
3294 {
3295 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3296 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3297 }
3298 else
3299 {
3300 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3301 pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3302 }
3303 break;
3304
3305 /*
3306 * Hypervisor debug events.
3307 */
3308 case VINF_EM_DBG_HYPER_STEPPED:
3309 case VINF_EM_DBG_HYPER_BREAKPOINT:
3310 case VINF_EM_DBG_HYPER_ASSERTION:
3311 Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3312 pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3313 break;
3314
3315 /*
3316 * Any error code showing up here other than the ones we
3317 * know and process above are considered to be FATAL.
3318 *
3319 * Unknown warnings and informational status codes are also
3320 * included in this.
3321 */
3322 default:
3323 if (VBOX_SUCCESS(rc))
3324 {
3325 AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3326 rc = VERR_EM_INTERNAL_ERROR;
3327 }
3328 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3329 Log(("EMR3ExecuteVM returns %d\n", rc));
3330 break;
3331 }
3332
3333
3334 /*
3335 * Any waiters can now be woken up
3336 */
3337 VMMR3Unlock(pVM);
3338 VMMR3Lock(pVM);
3339
3340 STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3341 STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3342
3343 /*
3344 * Act on the state.
3345 */
3346 switch (pVM->em.s.enmState)
3347 {
3348 /*
3349 * Execute raw.
3350 */
3351 case EMSTATE_RAW:
3352 rc = emR3RawExecute(pVM, &fFFDone);
3353 break;
3354
3355 /*
3356 * Execute hardware accelerated raw.
3357 */
3358 case EMSTATE_HWACC:
3359 rc = emR3HwAccExecute(pVM, &fFFDone);
3360 break;
3361
3362 /*
3363 * Execute recompiled.
3364 */
3365 case EMSTATE_REM:
3366 rc = emR3RemExecute(pVM, &fFFDone);
3367 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3368 break;
3369
3370 /*
3371 * hlt - execution halted until interrupt.
3372 */
3373 case EMSTATE_HALTED:
3374 {
3375 STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3376 rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3377 STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3378 break;
3379 }
3380
3381 /*
3382 * Suspended - return to VM.cpp.
3383 */
3384 case EMSTATE_SUSPENDED:
3385 TMVirtualPause(pVM);
3386 TMCpuTickPause(pVM);
3387 VMMR3Unlock(pVM);
3388 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3389 return VINF_EM_SUSPEND;
3390
3391 /*
3392 * Debugging in the guest.
3393 */
3394 case EMSTATE_DEBUG_GUEST_REM:
3395 case EMSTATE_DEBUG_GUEST_RAW:
3396 TMVirtualPause(pVM);
3397 TMCpuTickPause(pVM);
3398 rc = emR3Debug(pVM, rc);
3399 TMVirtualResume(pVM);
3400 TMCpuTickResume(pVM);
3401 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3402 break;
3403
3404 /*
3405 * Debugging in the hypervisor.
3406 */
3407 case EMSTATE_DEBUG_HYPER:
3408 {
3409 TMVirtualPause(pVM);
3410 TMCpuTickPause(pVM);
3411 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3412
3413 rc = emR3Debug(pVM, rc);
3414 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3415 if (rc != VINF_SUCCESS)
3416 {
3417 /* switch to guru meditation mode */
3418 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3419 VMMR3FatalDump(pVM, rc);
3420 return rc;
3421 }
3422
3423 STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3424 TMVirtualResume(pVM);
3425 TMCpuTickResume(pVM);
3426 break;
3427 }
3428
3429 /*
3430 * Guru meditation takes place in the debugger.
3431 */
3432 case EMSTATE_GURU_MEDITATION:
3433 {
3434 /** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3435 TMVirtualPause(pVM);
3436 TMCpuTickPause(pVM);
3437 VMMR3FatalDump(pVM, rc);
3438 int rc2 = emR3Debug(pVM, rc);
3439 if (rc2 == VERR_DBGF_NOT_ATTACHED)
3440 {
3441 VMMR3Unlock(pVM);
3442 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3443 return rc;
3444 }
3445 TMVirtualResume(pVM);
3446 TMCpuTickResume(pVM);
3447 rc = rc2;
3448 /** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3449 Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3450 break;
3451 }
3452
3453 /*
3454 * The states we don't expect here.
3455 */
3456 case EMSTATE_NONE:
3457 case EMSTATE_TERMINATING:
3458 default:
3459 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3460 pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3461 TMVirtualPause(pVM);
3462 TMCpuTickPause(pVM);
3463 VMMR3Unlock(pVM);
3464 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3465 return VERR_EM_INTERNAL_ERROR;
3466 }
3467 } /* The Outer Main Loop */
3468 }
3469 else
3470 {
3471 /*
3472 * Fatal error.
3473 */
3474 LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3475 TMVirtualPause(pVM);
3476 TMCpuTickPause(pVM);
3477 VMMR3FatalDump(pVM, rc);
3478 emR3Debug(pVM, rc);
3479 VMMR3Unlock(pVM);
3480 STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3481 /** @todo change the VM state! */
3482 return rc;
3483 }
3484
3485 /* (won't ever get here). */
3486 AssertFailed();
3487}
3488
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