EM.cpp@ 2981

Last change on this file since 2981 was 2981, checked in by vboxsync, 17 years ago
InnoTek -> innotek: all the headers and comments.
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1	/* $Id: EM.cpp 2981 2007-06-01 16:01:28Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
204
205	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
207
208	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
246
247	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
271
272	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
274	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
276
277	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
278	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
279	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
280	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
281	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
282	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
285	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
289	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
290	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
291	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
292	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
293	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
294	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
295	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
296	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
297	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
298	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
299	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
300	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
301	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
302	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
303
304	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
305	pVM->em.s.pCliStatTree = 0;
306	#endif /* VBOX_WITH_STATISTICS */
307
308	/* these should be considered for release statistics. */
309	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
310	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
311	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
312	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
313	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
314	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
315	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
316	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
317	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
318	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
319	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
320	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
321	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
322	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
323	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
324	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
325
326
327	return VINF_SUCCESS;
328	}
329
330
331
332	/**
333	* Applies relocations to data and code managed by this
334	* component. This function will be called at init and
335	* whenever the VMM need to relocate it self inside the GC.
336	*
337	* @param pVM The VM.
338	*/
339	EMR3DECL(void) EMR3Relocate(PVM pVM)
340	{
341	LogFlow(("EMR3Relocate\n"));
342	if (pVM->em.s.pStatsHC)
343	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
344	}
345
346
347	/**
348	* Reset notification.
349	*
350	* @param pVM
351	*/
352	EMR3DECL(void) EMR3Reset(PVM pVM)
353	{
354	LogFlow(("EMR3Reset: \n"));
355	pVM->em.s.fForceRAW = false;
356	}
357
358
359	/**
360	* Terminates the EM.
361	*
362	* Termination means cleaning up and freeing all resources,
363	* the VM it self is at this point powered off or suspended.
364	*
365	* @returns VBox status code.
366	* @param pVM The VM to operate on.
367	*/
368	EMR3DECL(int) EMR3Term(PVM pVM)
369	{
370	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
371
372	return VINF_SUCCESS;
373	}
374
375
376	/**
377	* Execute state save operation.
378	*
379	* @returns VBox status code.
380	* @param pVM VM Handle.
381	* @param pSSM SSM operation handle.
382	*/
383	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
384	{
385	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
386	}
387
388
389	/**
390	* Execute state load operation.
391	*
392	* @returns VBox status code.
393	* @param pVM VM Handle.
394	* @param pSSM SSM operation handle.
395	* @param u32Version Data layout version.
396	*/
397	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
398	{
399	/*
400	* Validate version.
401	*/
402	if (u32Version != EM_SAVED_STATE_VERSION)
403	{
404	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
405	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
406	}
407
408	/*
409	* Load the saved state.
410	*/
411	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
412	if (VBOX_FAILURE(rc))
413	pVM->em.s.fForceRAW = false;
414
415	Assert(pVM->em.s.pCliStatTree == 0);
416	return rc;
417	}
418
419
420	/**
421	* Enables or disables a set of raw-mode execution modes.
422	*
423	* @returns VINF_SUCCESS on success.
424	* @returns VINF_RESCHEDULE if a rescheduling might be required.
425	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
426	*
427	* @param pVM The VM to operate on.
428	* @param enmMode The execution mode change.
429	* @thread The emulation thread.
430	*/
431	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
432	{
433	switch (enmMode)
434	{
435	case EMRAW_NONE:
436	pVM->fRawR3Enabled = false;
437	pVM->fRawR0Enabled = false;
438	break;
439	case EMRAW_RING3_ENABLE:
440	pVM->fRawR3Enabled = true;
441	break;
442	case EMRAW_RING3_DISABLE:
443	pVM->fRawR3Enabled = false;
444	break;
445	case EMRAW_RING0_ENABLE:
446	pVM->fRawR0Enabled = true;
447	break;
448	case EMRAW_RING0_DISABLE:
449	pVM->fRawR0Enabled = false;
450	break;
451	default:
452	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
453	return VERR_INVALID_PARAMETER;
454	}
455	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
456	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
457	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
458	}
459
460
461	/**
462	* Raise a fatal error.
463	*
464	* Safely terminate the VM with full state report and stuff. This function
465	* will naturally never return.
466	*
467	* @param pVM VM handle.
468	* @param rc VBox status code.
469	*/
470	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
471	{
472	longjmp(pVM->em.s.u.FatalLongJump, rc);
473	AssertReleaseMsgFailed(("longjmp returned!\n"));
474	}
475
476
477	/**
478	* Gets the EM state name.
479	*
480	* @returns pointer to read only state name,
481	* @param enmState The state.
482	*/
483	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
484	{
485	switch (enmState)
486	{
487	case EMSTATE_RAW: return "EMSTATE_RAW";
488	case EMSTATE_HWACC: return "EMSTATE_HWACC";
489	case EMSTATE_REM: return "EMSTATE_REM";
490	case EMSTATE_HALTED: return "EMSTATE_HALTED";
491	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
492	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
493	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
494	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
495	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
496	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
497	default: return "Unknown!";
498	}
499	}
500
501
502	#ifdef VBOX_WITH_STATISTICS
503	/**
504	* Just a braindead function to keep track of cli addresses.
505	* @param pVM VM handle.
506	* @param pInstrGC The EIP of the cli instruction.
507	*/
508	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
509	{
510	PCLISTAT pRec;
511
512	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
513	if (!pRec)
514	{
515	/* New cli instruction; insert into the tree. */
516	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
517	Assert(pRec);
518	if (!pRec)
519	return;
520	pRec->Core.Key = (AVLPVKEY)pInstrGC;
521
522	char szCliStatName[32];
523	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
524	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
525
526	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
527	Assert(fRc); NOREF(fRc);
528	}
529	STAM_COUNTER_INC(&pRec->Counter);
530	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
531	}
532	#endif /* VBOX_WITH_STATISTICS */
533
534
535	/**
536	* Debug loop.
537	*
538	* @returns VBox status code for EM.
539	* @param pVM VM handle.
540	* @param rc Current EM VBox status code..
541	*/
542	static int emR3Debug(PVM pVM, int rc)
543	{
544	for (;;)
545	{
546	Log(("emR3Debug: rc=%Vrc\n", rc));
547	const int rcLast = rc;
548
549	/*
550	* Debug related RC.
551	*/
552	switch (rc)
553	{
554	/*
555	* Single step an instruction.
556	*/
557	case VINF_EM_DBG_STEP:
558	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
559	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
560	\|\| pVM->em.s.fForceRAW /* paranoia */)
561	rc = emR3RawStep(pVM);
562	else
563	{
564	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
565	rc = emR3RemStep(pVM);
566	}
567	break;
568
569	/*
570	* Simple events: stepped, breakpoint, stop/assertion.
571	*/
572	case VINF_EM_DBG_STEPPED:
573	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
574	break;
575
576	case VINF_EM_DBG_BREAKPOINT:
577	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
578	break;
579
580	case VINF_EM_DBG_STOP:
581	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
582	break;
583
584	case VINF_EM_DBG_HYPER_STEPPED:
585	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
586	break;
587
588	case VINF_EM_DBG_HYPER_BREAKPOINT:
589	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
590	break;
591
592	case VINF_EM_DBG_HYPER_ASSERTION:
593	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
595	break;
596
597	/*
598	* Guru meditation.
599	*/
600	default: /** @todo don't use default for guru, but make special errors code! */
601	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
602	break;
603	}
604
605	/*
606	* Process the result.
607	*/
608	do
609	{
610	switch (rc)
611	{
612	/*
613	* Continue the debugging loop.
614	*/
615	case VINF_EM_DBG_STEP:
616	case VINF_EM_DBG_STOP:
617	case VINF_EM_DBG_STEPPED:
618	case VINF_EM_DBG_BREAKPOINT:
619	case VINF_EM_DBG_HYPER_STEPPED:
620	case VINF_EM_DBG_HYPER_BREAKPOINT:
621	case VINF_EM_DBG_HYPER_ASSERTION:
622	break;
623
624	/*
625	* Resuming execution (in some form) has to be done here if we got
626	* a hypervisor debug event.
627	*/
628	case VINF_SUCCESS:
629	case VINF_EM_RESUME:
630	case VINF_EM_SUSPEND:
631	case VINF_EM_RESCHEDULE:
632	case VINF_EM_RESCHEDULE_RAW:
633	case VINF_EM_RESCHEDULE_REM:
634	case VINF_EM_HALT:
635	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
636	{
637	rc = emR3RawResumeHyper(pVM);
638	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
639	continue;
640	}
641	if (rc == VINF_SUCCESS)
642	rc = VINF_EM_RESCHEDULE;
643	return rc;
644
645	/*
646	* The debugger isn't attached.
647	* We'll simply turn the thing off since that's the easiest thing to do.
648	*/
649	case VERR_DBGF_NOT_ATTACHED:
650	switch (rcLast)
651	{
652	case VINF_EM_DBG_HYPER_ASSERTION:
653	case VINF_EM_DBG_HYPER_STEPPED:
654	case VINF_EM_DBG_HYPER_BREAKPOINT:
655	return rcLast;
656	}
657	return VINF_EM_OFF;
658
659	/*
660	* Status codes terminating the VM in one or another sense.
661	*/
662	case VINF_EM_TERMINATE:
663	case VINF_EM_OFF:
664	case VINF_EM_RESET:
665	case VINF_EM_RAW_STALE_SELECTOR:
666	case VINF_EM_RAW_IRET_TRAP:
667	case VERR_TRPM_PANIC:
668	case VERR_TRPM_DONT_PANIC:
669	case VERR_INTERNAL_ERROR:
670	return rc;
671
672	/*
673	* The rest is unexpected, and will keep us here.
674	*/
675	default:
676	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
677	break;
678	}
679	} while (false);
680	} /* debug for ever */
681	}
682
683
684	/**
685	* Steps recompiled code.
686	*
687	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
688	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
689	*
690	* @param pVM VM handle.
691	*/
692	static int emR3RemStep(PVM pVM)
693	{
694	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
695
696	/*
697	* Switch to REM, step instruction, switch back.
698	*/
699	int rc = REMR3State(pVM);
700	if (VBOX_SUCCESS(rc))
701	{
702	rc = REMR3Step(pVM);
703	REMR3StateBack(pVM);
704	}
705	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
706	return rc;
707	}
708
709	/**
710	* Executes recompiled code.
711	*
712	* This function contains the recompiler version of the inner
713	* execution loop (the outer loop being in EMR3ExecuteVM()).
714	*
715	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
716	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
717	*
718	* @param pVM VM handle.
719	* @param pfFFDone Where to store an indicator telling wheter or not
720	* FFs were done before returning.
721	*
722	*/
723	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
724	{
725	#ifdef LOG_ENABLED
726	PCPUMCTX pCtx = pVM->em.s.pCtx;
727	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
728
729	if (pCtx->eflags.Bits.u1VM)
730	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
731	else
732	Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
733	#endif
734	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
735
736	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
737	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
738	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
739	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
740	#endif
741
742	/*
743	* Spin till we get a forced action which returns anything but VINF_SUCCESS
744	* or the REM suggests raw-mode execution.
745	*/
746	*pfFFDone = false;
747	bool fInREMState = false;
748	int rc = VINF_SUCCESS;
749	for (;;)
750	{
751	/*
752	* Update REM state if not already in sync.
753	*/
754	if (!fInREMState)
755	{
756	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
757	rc = REMR3State(pVM);
758	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
759	if (VBOX_FAILURE(rc))
760	break;
761	fInREMState = true;
762
763	/*
764	* We might have missed the raising of VMREQ, TIMER and some other
765	* imporant FFs while we were busy switching the state. So, check again.
766	*/
767	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
768	{
769	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
770	goto l_REMDoForcedActions;
771	}
772	}
773
774
775	/*
776	* Execute REM.
777	*/
778	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
779	rc = REMR3Run(pVM);
780	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
781
782
783	/*
784	* Deal with high priority post execution FFs before doing anything else.
785	*/
786	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
787	rc = emR3HighPriorityPostForcedActions(pVM, rc);
788
789	/*
790	* Process the returned status code.
791	* (Try keep this short! Call functions!)
792	*/
793	if (rc != VINF_SUCCESS)
794	{
795	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
796	break;
797	if (rc != VINF_REM_INTERRUPED_FF)
798	{
799	/*
800	* Anything which is not known to us means an internal error
801	* and the termination of the VM!
802	*/
803	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
804	break;
805	}
806	}
807
808
809	/*
810	* Check and execute forced actions.
811	* Sync back the VM state before calling any of these.
812	*/
813	#ifdef VBOX_HIGH_RES_TIMERS_HACK
814	TMTimerPoll(pVM);
815	#endif
816	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
817	{
818	l_REMDoForcedActions:
819	if (fInREMState)
820	{
821	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
822	REMR3StateBack(pVM);
823	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
824	fInREMState = false;
825	}
826	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
827	rc = emR3ForcedActions(pVM, rc);
828	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
829	if ( rc != VINF_SUCCESS
830	&& rc != VINF_EM_RESCHEDULE_REM)
831	{
832	*pfFFDone = true;
833	break;
834	}
835	}
836
837	} /* The Inner Loop, recompiled execution mode version. */
838
839
840	/*
841	* Returning. Sync back the VM state if required.
842	*/
843	if (fInREMState)
844	{
845	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
846	REMR3StateBack(pVM);
847	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
848	}
849
850	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
851	return rc;
852	}
853
854
855	/**
856	* Resumes executing hypervisor after a debug event.
857	*
858	* This is kind of special since our current guest state is
859	* potentially out of sync.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM handle.
863	*/
864	static int emR3RawResumeHyper(PVM pVM)
865	{
866	int rc;
867	PCPUMCTX pCtx = pVM->em.s.pCtx;
868	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
869	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
870
871	/*
872	* Resume execution.
873	*/
874	CPUMRawEnter(pVM, NULL);
875	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
876	rc = VMMR3ResumeHyper(pVM);
877	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
878	rc = CPUMRawLeave(pVM, NULL, rc);
879	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
880
881	/*
882	* Deal with the return code.
883	*/
884	rc = emR3HighPriorityPostForcedActions(pVM, rc);
885	rc = emR3RawHandleRC(pVM, pCtx, rc);
886	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
887	return rc;
888	}
889
890
891	/**
892	* Steps rawmode.
893	*
894	* @returns VBox status code.
895	* @param pVM The VM handle.
896	*/
897	static int emR3RawStep(PVM pVM)
898	{
899	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
900	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
901	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
902	int rc;
903	PCPUMCTX pCtx = pVM->em.s.pCtx;
904	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
905	#ifndef DEBUG_sandervl
906	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
907	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
908	#endif
909	if (fGuest)
910	{
911	/*
912	* Check vital forced actions, but ignore pending interrupts and timers.
913	*/
914	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
915	{
916	rc = emR3RawForcedActions(pVM, pCtx);
917	if (VBOX_FAILURE(rc))
918	return rc;
919	}
920
921	/*
922	* Set flags for single stepping.
923	*/
924	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
925	}
926	else
927	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
928
929	/*
930	* Single step.
931	* We do not start time or anything, if anything we should just do a few nanoseconds.
932	*/
933	CPUMRawEnter(pVM, NULL);
934	do
935	{
936	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
937	rc = VMMR3ResumeHyper(pVM);
938	else
939	rc = VMMR3RawRunGC(pVM);
940	#ifndef DEBUG_sandervl
941	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
942	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
943	#endif
944	} while ( rc == VINF_SUCCESS
945	\|\| rc == VINF_EM_RAW_INTERRUPT);
946	rc = CPUMRawLeave(pVM, NULL, rc);
947	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
948
949	/*
950	* Make sure the trap flag is cleared.
951	* (Too bad if the guest is trying to single step too.)
952	*/
953	if (fGuest)
954	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
955	else
956	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
957
958	/*
959	* Deal with the return codes.
960	*/
961	rc = emR3HighPriorityPostForcedActions(pVM, rc);
962	rc = emR3RawHandleRC(pVM, pCtx, rc);
963	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
964	return rc;
965	}
966
967
968	#ifdef DEBUG
969
970	/**
971	* Steps hardware accelerated mode.
972	*
973	* @returns VBox status code.
974	* @param pVM The VM handle.
975	*/
976	static int emR3HwAccStep(PVM pVM)
977	{
978	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
979
980	int rc;
981	PCPUMCTX pCtx = pVM->em.s.pCtx;
982	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
983
984	/*
985	* Check vital forced actions, but ignore pending interrupts and timers.
986	*/
987	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
988	{
989	rc = emR3RawForcedActions(pVM, pCtx);
990	if (VBOX_FAILURE(rc))
991	return rc;
992	}
993	/*
994	* Set flags for single stepping.
995	*/
996	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
997
998	/*
999	* Single step.
1000	* We do not start time or anything, if anything we should just do a few nanoseconds.
1001	*/
1002	do
1003	{
1004	rc = VMMR3HwAccRunGC(pVM);
1005	} while ( rc == VINF_SUCCESS
1006	\|\| rc == VINF_EM_RAW_INTERRUPT);
1007	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1008
1009	/*
1010	* Make sure the trap flag is cleared.
1011	* (Too bad if the guest is trying to single step too.)
1012	*/
1013	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1014
1015	/*
1016	* Deal with the return codes.
1017	*/
1018	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1019	rc = emR3RawHandleRC(pVM, pCtx, rc);
1020	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1021	return rc;
1022	}
1023
1024
1025	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1026	{
1027	EMSTATE enmOldState = pVM->em.s.enmState;
1028
1029	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1030
1031	Log(("Single step BEGIN:\n"));
1032	for(uint32_t i=0;i<cIterations;i++)
1033	{
1034	DBGFR3PrgStep(pVM);
1035	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1036	emR3RawStep(pVM);
1037	}
1038	Log(("Single step END:\n"));
1039	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1040	pVM->em.s.enmState = enmOldState;
1041	}
1042
1043
1044	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1045	{
1046	EMSTATE enmOldState = pVM->em.s.enmState;
1047
1048	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1049
1050	Log(("Single step BEGIN:\n"));
1051	for(uint32_t i=0;i<cIterations;i++)
1052	{
1053	DBGFR3PrgStep(pVM);
1054	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1055	emR3HwAccStep(pVM);
1056	}
1057	Log(("Single step END:\n"));
1058	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1059	pVM->em.s.enmState = enmOldState;
1060	}
1061
1062
1063	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1064	{
1065	EMSTATE enmOldState = pVM->em.s.enmState;
1066
1067	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1068
1069	Log(("Single step BEGIN:\n"));
1070	for(uint32_t i=0;i<cIterations;i++)
1071	{
1072	DBGFR3PrgStep(pVM);
1073	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1074	emR3RemStep(pVM);
1075	}
1076	Log(("Single step END:\n"));
1077	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1078	pVM->em.s.enmState = enmOldState;
1079	}
1080
1081	#endif /* DEBUG */
1082
1083
1084	/**
1085	* Executes one (or perhaps a few more) instruction(s).
1086	*
1087	* @returns VBox status code suitable for EM.
1088	*
1089	* @param pVM VM handle.
1090	* @param rcGC GC return code
1091	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1092	* instruction and prefix the log output with this text.
1093	*/
1094	#ifdef LOG_ENABLED
1095	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1096	#else
1097	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1098	#endif
1099	{
1100	PCPUMCTX pCtx = pVM->em.s.pCtx;
1101	int rc;
1102
1103	/*
1104	*
1105	* The simple solution is to use the recompiler.
1106	* The better solution is to disassemble the current instruction and
1107	* try handle as many as possible without using REM.
1108	*
1109	*/
1110
1111	#ifdef LOG_ENABLED
1112	/*
1113	* Disassemble the instruction if requested.
1114	*/
1115	if (pszPrefix)
1116	{
1117	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1118	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1119	}
1120	#endif /* LOG_ENABLED */
1121
1122	/*
1123	* PATM is making life more interesting.
1124	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1125	* tell PATM there is a trap in this code and have it take the appropriate actions
1126	* to allow us execute the code in REM.
1127	*/
1128	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1129	{
1130	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1131
1132	RTGCPTR pNewEip;
1133	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1134	switch (rc)
1135	{
1136	/*
1137	* It's not very useful to emulate a single instruction and then go back to raw
1138	* mode; just execute the whole block until IF is set again.
1139	*/
1140	case VINF_SUCCESS:
1141	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1142	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1143	pCtx->eip = pNewEip;
1144	Assert(pCtx->eip);
1145
1146	if (pCtx->eflags.Bits.u1IF)
1147	{
1148	/*
1149	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1150	*/
1151	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1152	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1153	}
1154	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1155	{
1156	/* special case: iret, that sets IF, detected a pending irq/event */
1157	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1158	}
1159	return VINF_EM_RESCHEDULE_REM;
1160
1161	/*
1162	* One instruction.
1163	*/
1164	case VINF_PATCH_EMULATE_INSTR:
1165	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1166	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1167	pCtx->eip = pNewEip;
1168	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1169
1170	/*
1171	* The patch was disabled, hand it to the REM.
1172	*/
1173	case VERR_PATCH_DISABLED:
1174	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1175	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1176	pCtx->eip = pNewEip;
1177	if (pCtx->eflags.Bits.u1IF)
1178	{
1179	/*
1180	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1181	*/
1182	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1183	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1184	}
1185	return VINF_EM_RESCHEDULE_REM;
1186
1187	/* Force continued patch exection; usually due to write monitored stack. */
1188	case VINF_PATCH_CONTINUE:
1189	return VINF_SUCCESS;
1190
1191	default:
1192	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1193	return VERR_INTERNAL_ERROR;
1194	}
1195	}
1196
1197	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1198	DISCPUSTATE Cpu;
1199	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1200	if (VBOX_SUCCESS(rc))
1201	{
1202	uint32_t size;
1203
1204	switch (Cpu.pCurInstr->opcode)
1205	{
1206	case OP_MOV:
1207	case OP_AND:
1208	case OP_OR:
1209	case OP_XOR:
1210	case OP_POP:
1211	case OP_INC:
1212	case OP_DEC:
1213	case OP_XCHG:
1214	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1215	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1216	if (VBOX_SUCCESS(rc))
1217	{
1218	pCtx->eip += Cpu.opsize;
1219	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1220	return rc;
1221	}
1222	if (rc != VERR_EM_INTERPRETER)
1223	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1224	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1225	break;
1226	}
1227	}
1228	#endif
1229	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1230	rc = REMR3EmulateInstruction(pVM);
1231	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1232
1233	return rc;
1234	}
1235
1236
1237	/**
1238	* Executes one (or perhaps a few more) instruction(s).
1239	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1240	*
1241	* @returns VBox status code suitable for EM.
1242	* @param pVM VM handle.
1243	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1244	* instruction and prefix the log output with this text.
1245	* @param rcGC GC return code
1246	*/
1247	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1248	{
1249	#ifdef LOG_ENABLED
1250	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1251	#else
1252	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1253	#endif
1254	}
1255
1256	/**
1257	* Executes one (or perhaps a few more) IO instruction(s).
1258	*
1259	* @returns VBox status code suitable for EM.
1260	* @param pVM VM handle.
1261	*/
1262	int emR3RawExecuteIOInstruction(PVM pVM)
1263	{
1264	int rc;
1265	PCPUMCTX pCtx = pVM->em.s.pCtx;
1266
1267	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1268
1269	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1270	* as io instructions tend to come in packages of more than one
1271	*/
1272	DISCPUSTATE Cpu;
1273	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1274	if (VBOX_SUCCESS(rc))
1275	{
1276	rc = VINF_EM_RESCHEDULE_REM;
1277
1278	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1279	{
1280	switch (Cpu.pCurInstr->opcode)
1281	{
1282	case OP_IN:
1283	{
1284	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1285	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1286	break;
1287	}
1288
1289	case OP_OUT:
1290	{
1291	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1292	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1293	break;
1294	}
1295	}
1296	}
1297	else if (Cpu.prefix & PREFIX_REP)
1298	{
1299	switch (Cpu.pCurInstr->opcode)
1300	{
1301	case OP_INSB:
1302	case OP_INSWD:
1303	{
1304	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1305	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1306	break;
1307	}
1308
1309	case OP_OUTSB:
1310	case OP_OUTSWD:
1311	{
1312	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1313	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1314	break;
1315	}
1316	}
1317	}
1318
1319	/*
1320	* Handled the I/O return codes.
1321	* (The unhandled cases end up with rc == VINF_EM_RESCHEDULE_REM.)
1322	*/
1323	if (rc == VINF_EM_RESCHEDULE_REM)
1324	{
1325	/* emulate this instruction only */
1326	goto emulate_instr;
1327	}
1328
1329	if ( rc == VINF_SUCCESS
1330	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1331	{
1332	pCtx->eip += Cpu.opsize;
1333	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1334	return rc;
1335	}
1336
1337	if (rc == VINF_EM_RAW_GUEST_TRAP)
1338	{
1339	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1340	rc = emR3RawGuestTrap(pVM);
1341	return rc;
1342	}
1343	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1344	if (VBOX_FAILURE(rc))
1345	{
1346	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1347	return rc;
1348	}
1349	AssertMsg(rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1350	}
1351	emulate_instr:
1352	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1353	return emR3RawExecuteInstruction(pVM, "IO: ");
1354	}
1355
1356
1357	/**
1358	* Handle a guest context trap.
1359	*
1360	* @returns VBox status code suitable for EM.
1361	* @param pVM VM handle.
1362	*/
1363	static int emR3RawGuestTrap(PVM pVM)
1364	{
1365	PCPUMCTX pCtx = pVM->em.s.pCtx;
1366
1367	/*
1368	* Get the trap info.
1369	*/
1370	uint8_t u8TrapNo;
1371	TRPMEVENT enmType;;
1372	RTGCUINT uErrorCode;
1373	RTGCUINTPTR uCR2;
1374	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1375	if (VBOX_FAILURE(rc))
1376	{
1377	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1378	return rc;
1379	}
1380
1381	/* Traps can be directly forwarded in hardware accelerated mode. */
1382	if (HWACCMR3IsActive(pVM))
1383	{
1384	#ifdef LOGGING_ENABLED
1385	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1386	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1387	#endif
1388	return VINF_EM_RESCHEDULE_HWACC;
1389	}
1390
1391	/** Scan kernel code that traps; we might not get another chance. */
1392	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1393	&& !pCtx->eflags.Bits.u1VM)
1394	{
1395	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1396	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1397	}
1398
1399	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1400	{
1401	DISCPUSTATE cpu;
1402
1403	/* If MONITOR & MWAIT are supported, then interpret them here. */
1404	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1405	if ( VBOX_SUCCESS(rc)
1406	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1407	{
1408	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1409
1410	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1411
1412	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1413	{
1414	rc = TRPMResetTrap(pVM);
1415	AssertRC(rc);
1416
1417	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1418	if (VBOX_SUCCESS(rc))
1419	{
1420	pCtx->eip += cpu.opsize;
1421	return rc;
1422	}
1423	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1424	}
1425	}
1426	}
1427	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1428	{
1429	DISCPUSTATE cpu;
1430
1431	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1432	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1433	{
1434	/*
1435	* We should really check the TSS for the IO bitmap, but it's not like this
1436	* lazy approach really makes things worse.
1437	*/
1438	rc = TRPMResetTrap(pVM);
1439	AssertRC(rc);
1440	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1441	}
1442	}
1443
1444	#ifdef LOG_ENABLED
1445	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1446	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1447
1448	/* Get guest page information. */
1449	uint64_t fFlags = 0;
1450	RTGCPHYS GCPhys = 0;
1451	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1452	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1453	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1454	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1455	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1456	#endif
1457
1458	/*
1459	* #PG has CR2.
1460	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1461	*/
1462	if (u8TrapNo == 14 /* #PG */)
1463	pCtx->cr2 = uCR2;
1464
1465	return VINF_EM_RESCHEDULE_REM;
1466	}
1467
1468
1469	/**
1470	* Handle a ring switch trap.
1471	* Need to do statistics and to install patches. The result is going to REM.
1472	*
1473	* @returns VBox status code suitable for EM.
1474	* @param pVM VM handle.
1475	*/
1476	int emR3RawRingSwitch(PVM pVM)
1477	{
1478	int rc;
1479	DISCPUSTATE Cpu;
1480	PCPUMCTX pCtx = pVM->em.s.pCtx;
1481
1482	/*
1483	* sysenter, syscall & callgate
1484	*/
1485	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1486	if (VBOX_SUCCESS(rc))
1487	{
1488	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1489	{
1490	if (pCtx->SysEnter.cs != 0)
1491	{
1492	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1493	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1494	if (VBOX_SUCCESS(rc))
1495	{
1496	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1497	return VINF_EM_RESCHEDULE_RAW;
1498	}
1499	}
1500	}
1501
1502	#ifdef VBOX_WITH_STATISTICS
1503	switch (Cpu.pCurInstr->opcode)
1504	{
1505	case OP_SYSENTER:
1506	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1507	break;
1508	case OP_SYSEXIT:
1509	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1510	break;
1511	case OP_SYSCALL:
1512	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1513	break;
1514	case OP_SYSRET:
1515	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1516	break;
1517	}
1518	#endif
1519	}
1520	else
1521	AssertRC(rc);
1522
1523	/* go to the REM to emulate a single instruction */
1524	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1525	}
1526
1527	/**
1528	* Handle a trap (#PF or #GP) in patch code
1529	*
1530	* @returns VBox status code suitable for EM.
1531	* @param pVM VM handle.
1532	* @param pCtx CPU context
1533	* @param gcret GC return code
1534	*/
1535	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1536	{
1537	uint8_t u8TrapNo;
1538	int rc;
1539	TRPMEVENT enmType;
1540	RTGCUINT uErrorCode;
1541	RTGCUINTPTR uCR2;
1542
1543	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1544
1545	if (gcret == VINF_PATM_PATCH_INT3)
1546	{
1547	u8TrapNo = 3;
1548	uCR2 = 0;
1549	uErrorCode = 0;
1550	}
1551	else
1552	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1553	{
1554	/* No active trap in this case. Kind of ugly. */
1555	u8TrapNo = X86_XCPT_GP;
1556	uCR2 = 0;
1557	uErrorCode = 0;
1558	}
1559	else
1560	{
1561	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1562	if (VBOX_FAILURE(rc))
1563	{
1564	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1565	return rc;
1566	}
1567	/* Reset the trap as we'll execute the original instruction again. */
1568	TRPMResetTrap(pVM);
1569	}
1570
1571	/*
1572	* Deal with traps inside patch code.
1573	* (This code won't run outside GC.)
1574	*/
1575	if (u8TrapNo != 1)
1576	{
1577	#ifdef LOG_ENABLED
1578	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1579	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1580
1581	DISCPUSTATE Cpu;
1582	int rc;
1583
1584	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1585	if ( VBOX_SUCCESS(rc)
1586	&& Cpu.pCurInstr->opcode == OP_IRET)
1587	{
1588	uint32_t eip, selCS, uEFlags;
1589
1590	/* Iret crashes are bad as we have already changed the flags on the stack */
1591	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1592	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1593	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1594	if (rc == VINF_SUCCESS)
1595	{
1596	if ( (uEFlags & X86_EFL_VM)
1597	\|\| (selCS & X86_SEL_RPL) == 3)
1598	{
1599	uint32_t selSS, esp;
1600
1601	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1602	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1603
1604	if (uEFlags & X86_EFL_VM)
1605	{
1606	uint32_t selDS, selES, selFS, selGS;
1607	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1608	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1609	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1610	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1611	if (rc == VINF_SUCCESS)
1612	{
1613	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1614	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1615	}
1616	}
1617	else
1618	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1619	}
1620	else
1621	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1622	}
1623	}
1624	#endif
1625	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1626	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1627
1628	RTGCPTR pNewEip;
1629	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1630	switch (rc)
1631	{
1632	/*
1633	* Execute the faulting instruction.
1634	*/
1635	case VINF_SUCCESS:
1636	{
1637	/** @todo execute a whole block */
1638	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1639	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1640	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1641
1642	pCtx->eip = pNewEip;
1643	AssertRelease(pCtx->eip);
1644
1645	if (pCtx->eflags.Bits.u1IF)
1646	{
1647	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1648	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1649	*/
1650	if ( u8TrapNo == X86_XCPT_GP
1651	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1652	{
1653	/** @todo move to PATMR3HandleTrap */
1654	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1655	PATMR3RemovePatch(pVM, pCtx->eip);
1656	}
1657
1658	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1659	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1660
1661	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1662	/* Interrupts are enabled; just go back to the original instruction.
1663	return VINF_SUCCESS; */
1664	}
1665	return VINF_EM_RESCHEDULE_REM;
1666	}
1667
1668	/*
1669	* One instruction.
1670	*/
1671	case VINF_PATCH_EMULATE_INSTR:
1672	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1673	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1674	pCtx->eip = pNewEip;
1675	AssertRelease(pCtx->eip);
1676	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1677
1678	/*
1679	* The patch was disabled, hand it to the REM.
1680	*/
1681	case VERR_PATCH_DISABLED:
1682	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1683	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1684	pCtx->eip = pNewEip;
1685	AssertRelease(pCtx->eip);
1686
1687	if (pCtx->eflags.Bits.u1IF)
1688	{
1689	/*
1690	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1691	*/
1692	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1693	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1694	}
1695	return VINF_EM_RESCHEDULE_REM;
1696
1697	/* Force continued patch exection; usually due to write monitored stack. */
1698	case VINF_PATCH_CONTINUE:
1699	return VINF_SUCCESS;
1700
1701	/*
1702	* Anything else is fatal.
1703	*/
1704	default:
1705	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1706	return VERR_INTERNAL_ERROR;
1707	}
1708	}
1709	return VINF_SUCCESS;
1710	}
1711
1712
1713	/**
1714	* Handle a privileged instruction.
1715	*
1716	* @returns VBox status code suitable for EM.
1717	* @param pVM VM handle.
1718	*/
1719	int emR3RawPrivileged(PVM pVM)
1720	{
1721	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1722	PCPUMCTX pCtx = pVM->em.s.pCtx;
1723
1724	Assert(!pCtx->eflags.Bits.u1VM);
1725
1726	if (PATMIsEnabled(pVM))
1727	{
1728	/*
1729	* Check if in patch code.
1730	*/
1731	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1732	{
1733	#ifdef LOG_ENABLED
1734	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1735	#endif
1736	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1737	return VERR_EM_RAW_PATCH_CONFLICT;
1738	}
1739	if ( (pCtx->ss & X86_SEL_RPL) == 0
1740	&& !pCtx->eflags.Bits.u1VM
1741	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1742	{
1743	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1744	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1745	if (VBOX_SUCCESS(rc))
1746	{
1747	#ifdef LOG_ENABLED
1748	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1749	#endif
1750	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1751	return VINF_SUCCESS;
1752	}
1753	}
1754	}
1755
1756	#ifdef LOG_ENABLED
1757	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1758	{
1759	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1760	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1761	}
1762	#endif
1763
1764	/*
1765	* Instruction statistics and logging.
1766	*/
1767	DISCPUSTATE Cpu;
1768	int rc;
1769
1770	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1771	if (VBOX_SUCCESS(rc))
1772	{
1773	#ifdef VBOX_WITH_STATISTICS
1774	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1775	switch (Cpu.pCurInstr->opcode)
1776	{
1777	case OP_INVLPG:
1778	STAM_COUNTER_INC(&pStats->StatInvlpg);
1779	break;
1780	case OP_IRET:
1781	STAM_COUNTER_INC(&pStats->StatIret);
1782	break;
1783	case OP_CLI:
1784	STAM_COUNTER_INC(&pStats->StatCli);
1785	emR3RecordCli(pVM, pCtx->eip);
1786	break;
1787	case OP_STI:
1788	STAM_COUNTER_INC(&pStats->StatSti);
1789	break;
1790	case OP_INSB:
1791	case OP_INSWD:
1792	case OP_IN:
1793	case OP_OUTSB:
1794	case OP_OUTSWD:
1795	case OP_OUT:
1796	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1797	break;
1798
1799	case OP_MOV_CR:
1800	if (Cpu.param1.flags & USE_REG_GEN32)
1801	{
1802	//read
1803	Assert(Cpu.param2.flags & USE_REG_CR);
1804	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1805	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1806	}
1807	else
1808	{
1809	//write
1810	Assert(Cpu.param1.flags & USE_REG_CR);
1811	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1812	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1813	}
1814	break;
1815
1816	case OP_MOV_DR:
1817	STAM_COUNTER_INC(&pStats->StatMovDRx);
1818	break;
1819	case OP_LLDT:
1820	STAM_COUNTER_INC(&pStats->StatMovLldt);
1821	break;
1822	case OP_LIDT:
1823	STAM_COUNTER_INC(&pStats->StatMovLidt);
1824	break;
1825	case OP_LGDT:
1826	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1827	break;
1828	case OP_SYSENTER:
1829	STAM_COUNTER_INC(&pStats->StatSysEnter);
1830	break;
1831	case OP_SYSEXIT:
1832	STAM_COUNTER_INC(&pStats->StatSysExit);
1833	break;
1834	case OP_SYSCALL:
1835	STAM_COUNTER_INC(&pStats->StatSysCall);
1836	break;
1837	case OP_SYSRET:
1838	STAM_COUNTER_INC(&pStats->StatSysRet);
1839	break;
1840	case OP_HLT:
1841	STAM_COUNTER_INC(&pStats->StatHlt);
1842	break;
1843	default:
1844	STAM_COUNTER_INC(&pStats->StatMisc);
1845	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1846	break;
1847	}
1848	#endif
1849	if ( (pCtx->ss & X86_SEL_RPL) == 0
1850	&& !pCtx->eflags.Bits.u1VM
1851	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1852	{
1853	uint32_t size;
1854
1855	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1856	switch (Cpu.pCurInstr->opcode)
1857	{
1858	case OP_CLI:
1859	pCtx->eflags.u32 &= ~X86_EFL_IF;
1860	Assert(Cpu.opsize == 1);
1861	pCtx->eip += Cpu.opsize;
1862	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1863	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1864
1865	case OP_STI:
1866	pCtx->eflags.u32 \|= X86_EFL_IF;
1867	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1868	Assert(Cpu.opsize == 1);
1869	pCtx->eip += Cpu.opsize;
1870	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1871	return VINF_SUCCESS;
1872
1873	case OP_HLT:
1874	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1875	{
1876	PATMTRANSSTATE enmState;
1877	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1878
1879	if (enmState == PATMTRANS_OVERWRITTEN)
1880	{
1881	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1882	Assert(rc == VERR_PATCH_DISABLED);
1883	/* Conflict detected, patch disabled */
1884	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1885
1886	enmState = PATMTRANS_SAFE;
1887	}
1888
1889	/* The translation had better be successful. Otherwise we can't recover. */
1890	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1891	if (enmState != PATMTRANS_OVERWRITTEN)
1892	pCtx->eip = pOrgInstrGC;
1893	}
1894	/* no break; we could just return VINF_EM_HALT here */
1895
1896	case OP_MOV_CR:
1897	case OP_MOV_DR:
1898	#ifdef LOG_ENABLED
1899	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1900	{
1901	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1902	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1903	}
1904	#endif
1905
1906	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1907	if (VBOX_SUCCESS(rc))
1908	{
1909	pCtx->eip += Cpu.opsize;
1910	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1911
1912	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1913	&& Cpu.param1.flags == USE_REG_CR /* write */
1914	)
1915	{
1916	/* Reschedule is necessary as the execution/paging mode might have changed. */
1917	return VINF_EM_RESCHEDULE;
1918	}
1919	return rc; /* can return VINF_EM_HALT as well. */
1920	}
1921	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1922	break; /* fall back to the recompiler */
1923	}
1924	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1925	}
1926	}
1927
1928	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1929	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1930
1931	return emR3RawExecuteInstruction(pVM, "PRIV");
1932	}
1933
1934
1935	/**
1936	* Update the forced rawmode execution modifier.
1937	*
1938	* This function is called when we're returning from the raw-mode loop(s). If we're
1939	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1940	* if not in patch code, the flag will be cleared.
1941	*
1942	* We should never interrupt patch code while it's being executed. Cli patches can
1943	* contain big code blocks, but they are always executed with IF=0. Other patches
1944	* replace single instructions and should be atomic.
1945	*
1946	* @returns Updated rc.
1947	*
1948	* @param pVM The VM handle.
1949	* @param pCtx The guest CPU context.
1950	* @param rc The result code.
1951	*/
1952	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1953	{
1954	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1955	{
1956	/* ignore reschedule attempts. */
1957	switch (rc)
1958	{
1959	case VINF_EM_RESCHEDULE:
1960	case VINF_EM_RESCHEDULE_REM:
1961	rc = VINF_SUCCESS;
1962	break;
1963	}
1964	pVM->em.s.fForceRAW = true;
1965	}
1966	else
1967	pVM->em.s.fForceRAW = false;
1968	return rc;
1969	}
1970
1971
1972	/**
1973	* Process a subset of the raw-mode return code.
1974	*
1975	* Since we have to share this with raw-mode single stepping, this inline
1976	* function has been created to avoid code duplication.
1977	*
1978	* @returns VINF_SUCCESS if it's ok to continue raw mode.
1979	* @returns VBox status code to return to the EM main loop.
1980	*
1981	* @param pVM The VM handle
1982	* @param rc The return code.
1983	* @param pCtx The guest cpu context.
1984	*/
1985	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
1986	{
1987	switch (rc)
1988	{
1989	/*
1990	* Common & simple ones.
1991	*/
1992	case VINF_SUCCESS:
1993	break;
1994	case VINF_EM_RESCHEDULE_RAW:
1995	case VINF_EM_RESCHEDULE_HWACC:
1996	case VINF_EM_RAW_INTERRUPT:
1997	case VINF_EM_RAW_TO_R3:
1998	case VINF_EM_RAW_TIMER_PENDING:
1999	case VINF_EM_PENDING_REQUEST:
2000	rc = VINF_SUCCESS;
2001	break;
2002
2003	/*
2004	* Privileged instruction.
2005	*/
2006	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2007	case VINF_PATM_PATCH_TRAP_GP:
2008	rc = emR3RawPrivileged(pVM);
2009	break;
2010
2011	/*
2012	* Got a trap which needs dispatching.
2013	*/
2014	case VINF_EM_RAW_GUEST_TRAP:
2015	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2016	{
2017	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2018	rc = VERR_EM_RAW_PATCH_CONFLICT;
2019	break;
2020	}
2021
2022	Assert(TRPMHasTrap(pVM));
2023	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2024
2025	if (TRPMHasTrap(pVM))
2026	{
2027	uint8_t u8Interrupt;
2028	uint32_t uErrorCode;
2029	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2030
2031	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2032	AssertRC(rc);
2033
2034	if (uErrorCode != ~0U)
2035	enmError = TRPM_TRAP_HAS_ERRORCODE;
2036
2037	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2038	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2039	{
2040	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2041	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2042
2043	/** If it was successful, then we could go back to raw mode. */
2044	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2045	{
2046	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2047	EMR3CheckRawForcedActions(pVM);
2048
2049	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2050	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2051	{
2052	TRPMResetTrap(pVM);
2053	return VINF_EM_RESCHEDULE_RAW;
2054	}
2055	}
2056	}
2057	}
2058	rc = emR3RawGuestTrap(pVM);
2059	break;
2060
2061	/*
2062	* Trap in patch code.
2063	*/
2064	case VINF_PATM_PATCH_TRAP_PF:
2065	case VINF_PATM_PATCH_INT3:
2066	rc = emR3PatchTrap(pVM, pCtx, rc);
2067	break;
2068
2069	case VINF_PATM_DUPLICATE_FUNCTION:
2070	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2071	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2072	AssertRC(rc);
2073	rc = VINF_SUCCESS;
2074	break;
2075
2076	case VINF_PATM_CHECK_PATCH_PAGE:
2077	rc = PATMR3HandleMonitoredPage(pVM);
2078	AssertRC(rc);
2079	rc = VINF_SUCCESS;
2080	break;
2081
2082	/*
2083	* Patch manager.
2084	*/
2085	case VERR_EM_RAW_PATCH_CONFLICT:
2086	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2087	break;
2088
2089	/*
2090	* Memory mapped I/O access - attempt to patch the instruction
2091	*/
2092	case VINF_PATM_HC_MMIO_PATCH_READ:
2093	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2094	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2095	if (VBOX_FAILURE(rc))
2096	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2097	break;
2098
2099	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2100	AssertFailed(); /* not yet implemented. */
2101	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2102	break;
2103
2104	/*
2105	* Conflict or out of page tables.
2106	*
2107	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2108	* do here is to execute the pending forced actions.
2109	*/
2110	case VINF_PGM_SYNC_CR3:
2111	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2112	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2113	rc = VINF_SUCCESS;
2114	break;
2115
2116	/*
2117	* Paging mode change.
2118	*/
2119	case VINF_PGM_CHANGE_MODE:
2120	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2121	if (VBOX_SUCCESS(rc))
2122	rc = VINF_EM_RESCHEDULE;
2123	break;
2124
2125	/*
2126	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2127	*/
2128	case VINF_CSAM_PENDING_ACTION:
2129	rc = VINF_SUCCESS;
2130	break;
2131
2132	/*
2133	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2134	*/
2135	case VINF_EM_RAW_INTERRUPT_PENDING:
2136	case VINF_EM_RAW_RING_SWITCH_INT:
2137	{
2138	uint8_t u8Interrupt;
2139
2140	Assert(TRPMHasTrap(pVM));
2141	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2142
2143	if (TRPMHasTrap(pVM))
2144	{
2145	u8Interrupt = TRPMGetTrapNo(pVM);
2146
2147	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2148	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2149	{
2150	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2151	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2152	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2153	}
2154	}
2155	rc = VINF_EM_RESCHEDULE_REM;
2156	break;
2157	}
2158
2159	/*
2160	* Other ring switch types.
2161	*/
2162	case VINF_EM_RAW_RING_SWITCH:
2163	rc = emR3RawRingSwitch(pVM);
2164	break;
2165
2166	/*
2167	* REMGCNotifyInvalidatePage() failed because of overflow.
2168	*/
2169	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2170	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2171	REMR3ReplayInvalidatedPages(pVM);
2172	break;
2173
2174	/*
2175	* I/O Port access - emulate the instruction.
2176	*/
2177	case VINF_IOM_HC_IOPORT_READ:
2178	case VINF_IOM_HC_IOPORT_WRITE:
2179	rc = emR3RawExecuteIOInstruction(pVM);
2180	break;
2181
2182	/*
2183	* Memory mapped I/O access - emulate the instruction.
2184	*/
2185	case VINF_IOM_HC_MMIO_READ:
2186	case VINF_IOM_HC_MMIO_WRITE:
2187	case VINF_IOM_HC_MMIO_READ_WRITE:
2188	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2189	break;
2190
2191	/*
2192	* Execute instruction.
2193	*/
2194	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2195	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2196	break;
2197	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2198	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2199	break;
2200	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2201	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2202	break;
2203	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2204	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2205	break;
2206	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2207	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2208	break;
2209
2210	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2211	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2212	rc = emR3RawPrivileged(pVM);
2213	break;
2214
2215	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2216	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2217	break;
2218
2219	case VINF_EM_RAW_EMULATE_INSTR:
2220	case VINF_PATCH_EMULATE_INSTR:
2221	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2222	break;
2223
2224	/*
2225	* Stale selector and iret traps => REM.
2226	*/
2227	case VINF_EM_RAW_STALE_SELECTOR:
2228	case VINF_EM_RAW_IRET_TRAP:
2229	/* We will not go to the recompiler if EIP points to patch code. */
2230	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2231	{
2232	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2233	}
2234	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2235	rc = VINF_EM_RESCHEDULE_REM;
2236	break;
2237
2238	/*
2239	* Up a level.
2240	*/
2241	case VINF_EM_TERMINATE:
2242	case VINF_EM_OFF:
2243	case VINF_EM_RESET:
2244	case VINF_EM_SUSPEND:
2245	case VINF_EM_HALT:
2246	case VINF_EM_RESUME:
2247	case VINF_EM_RESCHEDULE:
2248	case VINF_EM_RESCHEDULE_REM:
2249	break;
2250
2251	/*
2252	* Up a level and invoke the debugger.
2253	*/
2254	case VINF_EM_DBG_STEPPED:
2255	case VINF_EM_DBG_BREAKPOINT:
2256	case VINF_EM_DBG_STEP:
2257	case VINF_EM_DBG_HYPER_ASSERTION:
2258	case VINF_EM_DBG_HYPER_BREAKPOINT:
2259	case VINF_EM_DBG_HYPER_STEPPED:
2260	case VINF_EM_DBG_STOP:
2261	break;
2262
2263	/*
2264	* Up a level, dump and debug.
2265	*/
2266	case VERR_TRPM_DONT_PANIC:
2267	case VERR_TRPM_PANIC:
2268	break;
2269
2270	/*
2271	* Anything which is not known to us means an internal error
2272	* and the termination of the VM!
2273	*/
2274	default:
2275	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2276	break;
2277	}
2278	return rc;
2279	}
2280
2281	/**
2282	* Check for pending raw actions
2283	*
2284	* @returns VBox status code.
2285	* @param pVM The VM to operate on.
2286	*/
2287	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2288	{
2289	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2290	}
2291
2292
2293	/**
2294	* Process raw-mode specific forced actions.
2295	*
2296	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2297	*
2298	* @returns VBox status code.
2299	* Only the normal success/failure stuff, no VINF_EM_*.
2300	* @param pVM The VM handle.
2301	* @param pCtx The guest CPUM register context.
2302	*/
2303	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2304	{
2305	/*
2306	* Note that the order is vitally important!
2307	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2308	*/
2309
2310
2311	/*
2312	* Sync selector tables.
2313	*/
2314	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2315	{
2316	int rc = SELMR3UpdateFromCPUM(pVM);
2317	if (VBOX_FAILURE(rc))
2318	return rc;
2319	}
2320
2321	/*
2322	* Sync IDT.
2323	*/
2324	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2325	{
2326	int rc = TRPMR3SyncIDT(pVM);
2327	if (VBOX_FAILURE(rc))
2328	return rc;
2329	}
2330
2331	/*
2332	* Sync TSS.
2333	*/
2334	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2335	{
2336	int rc = SELMR3SyncTSS(pVM);
2337	if (VBOX_FAILURE(rc))
2338	return rc;
2339	}
2340
2341	/*
2342	* Sync page directory.
2343	*/
2344	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2345	{
2346	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2347	if (VBOX_FAILURE(rc))
2348	return rc;
2349
2350	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2351
2352	/* Prefetch pages for EIP and ESP */
2353	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2354	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2355	if (rc == VINF_SUCCESS)
2356	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2357	if (rc != VINF_SUCCESS)
2358	{
2359	if (rc != VINF_PGM_SYNC_CR3)
2360	return rc;
2361	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2362	if (VBOX_FAILURE(rc))
2363	return rc;
2364	}
2365	/** @todo maybe prefetch the supervisor stack page as well */
2366	}
2367
2368	return VINF_SUCCESS;
2369	}
2370
2371
2372	/**
2373	* Executes raw code.
2374	*
2375	* This function contains the raw-mode version of the inner
2376	* execution loop (the outer loop being in EMR3ExecuteVM()).
2377	*
2378	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2379	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2380	*
2381	* @param pVM VM handle.
2382	* @param pfFFDone Where to store an indicator telling whether or not
2383	* FFs were done before returning.
2384	*/
2385	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2386	{
2387	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2388
2389	int rc = VERR_INTERNAL_ERROR;
2390	PCPUMCTX pCtx = pVM->em.s.pCtx;
2391	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2392	pVM->em.s.fForceRAW = false;
2393	*pfFFDone = false;
2394
2395
2396	/*
2397	*
2398	* Spin till we get a forced action or raw mode status code resulting in
2399	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2400	*
2401	*/
2402	for (;;)
2403	{
2404	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2405
2406	/*
2407	* Check various preconditions.
2408	*/
2409	#ifdef VBOX_STRICT
2410	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2411	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2412	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2413	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2414	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2415	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2416	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2417	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2418	{
2419	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2420	return VERR_INTERNAL_ERROR;
2421	}
2422	#endif /* VBOX_STRICT */
2423
2424	/*
2425	* Process high priority pre-execution raw-mode FFs.
2426	*/
2427	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2428	{
2429	rc = emR3RawForcedActions(pVM, pCtx);
2430	if (VBOX_FAILURE(rc))
2431	break;
2432	}
2433
2434	/*
2435	* If we're going to execute ring-0 code, the guest state needs to
2436	* be modified a bit and some of the state components (IF, SS/CS RPL,
2437	* and perhaps EIP) needs to be stored with PATM.
2438	*/
2439	rc = CPUMRawEnter(pVM, NULL);
2440	if (rc != VINF_SUCCESS)
2441	{
2442	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2443	break;
2444	}
2445
2446	/*
2447	* Scan code before executing it. Don't bother with user mode or V86 code
2448	*/
2449	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2450	&& !pCtx->eflags.Bits.u1VM
2451	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2452	{
2453	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2454	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2455	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2456	}
2457
2458	#ifdef LOG_ENABLED
2459	/*
2460	* Log important stuff before entering GC.
2461	*/
2462	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2463	if (pCtx->eflags.Bits.u1VM)
2464	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2465	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2466	{
2467	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2468	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2469	}
2470	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2471	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2472	#endif /* LOG_ENABLED */
2473
2474
2475
2476	/*
2477	* Execute the code.
2478	*/
2479	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2480	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2481	VMMR3Unlock(pVM);
2482	rc = VMMR3RawRunGC(pVM);
2483	VMMR3Lock(pVM);
2484	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2485	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2486
2487	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2488	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2489
2490	/*
2491	* Restore the real CPU state and deal with high priority post
2492	* execution FFs before doing anything else.
2493	*/
2494	rc = CPUMRawLeave(pVM, NULL, rc);
2495	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2496	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2497	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2498
2499	#ifdef PGM_CACHE_VERY_STRICT
2500	/*
2501	* Page manager cache checks.
2502	*/
2503	if ( rc == VINF_EM_RAW_INTERRUPT
2504	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2505	\|\| rc == VINF_IOM_HC_IOPORT_READ
2506	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2507	//\|\| rc == VINF_PATM_PATCH_INT3
2508	)
2509	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2510	#endif
2511
2512	#ifdef VBOX_STRICT
2513	/*
2514	* Assert TSS consistency & rc vs patch code.
2515	*/
2516	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2517	&& EMIsRawRing0Enabled(pVM))
2518	SELMR3CheckTSS(pVM);
2519	switch (rc)
2520	{
2521	case VINF_SUCCESS:
2522	case VINF_EM_RAW_INTERRUPT:
2523	case VINF_PATM_PATCH_TRAP_PF:
2524	case VINF_PATM_PATCH_TRAP_GP:
2525	case VINF_PATM_PATCH_INT3:
2526	case VINF_PATM_CHECK_PATCH_PAGE:
2527	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2528	case VINF_EM_RAW_GUEST_TRAP:
2529	case VINF_EM_RESCHEDULE_RAW:
2530	break;
2531
2532	default:
2533	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2534	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2535	break;
2536	}
2537	/*
2538	* Let's go paranoid!
2539	*/
2540	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2541	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2542	{
2543	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2544	return VERR_INTERNAL_ERROR;
2545	}
2546	#endif /* VBOX_STRICT */
2547
2548	/*
2549	* Process the returned status code.
2550	*/
2551	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2552	{
2553	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2554	break;
2555	}
2556	rc = emR3RawHandleRC(pVM, pCtx, rc);
2557	if (rc != VINF_SUCCESS)
2558	{
2559	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2560	if (rc != VINF_SUCCESS)
2561	{
2562	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2563	break;
2564	}
2565	}
2566
2567	/*
2568	* Check and execute forced actions.
2569	*/
2570	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2571	TMTimerPoll(pVM);
2572	#endif
2573	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2574	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2575	{
2576	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2577
2578	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2579	rc = emR3ForcedActions(pVM, rc);
2580	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2581	if ( rc != VINF_SUCCESS
2582	&& rc != VINF_EM_RESCHEDULE_RAW)
2583	{
2584	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2585	if (rc != VINF_SUCCESS)
2586	{
2587	*pfFFDone = true;
2588	break;
2589	}
2590	}
2591	}
2592	}
2593
2594	/*
2595	* Return to outer loop.
2596	*/
2597	#if defined(LOG_ENABLED) && defined(DEBUG)
2598	RTLogFlush(NULL);
2599	#endif
2600	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2601	return rc;
2602	}
2603
2604
2605	/**
2606	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2607	*
2608	* This function contains the raw-mode version of the inner
2609	* execution loop (the outer loop being in EMR3ExecuteVM()).
2610	*
2611	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2612	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2613	*
2614	* @param pVM VM handle.
2615	* @param pfFFDone Where to store an indicator telling whether or not
2616	* FFs were done before returning.
2617	*/
2618	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2619	{
2620	int rc = VERR_INTERNAL_ERROR;
2621	PCPUMCTX pCtx = pVM->em.s.pCtx;
2622
2623	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2624	*pfFFDone = false;
2625
2626	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2627
2628	/*
2629	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2630	*/
2631	for (;;)
2632	{
2633	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2634
2635	/*
2636	* Check various preconditions.
2637	*/
2638	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2639
2640	/*
2641	* Process high priority pre-execution raw-mode FFs.
2642	*/
2643	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2644	{
2645	rc = emR3RawForcedActions(pVM, pCtx);
2646	if (VBOX_FAILURE(rc))
2647	break;
2648	}
2649
2650	#ifdef LOG_ENABLED
2651	uint8_t u8Vector;
2652
2653	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2654	if (rc == VINF_SUCCESS)
2655	{
2656	Log(("Pending hardware interrupt %d\n", u8Vector));
2657	}
2658	/*
2659	* Log important stuff before entering GC.
2660	*/
2661	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2662
2663	if (pCtx->eflags.Bits.u1VM)
2664	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2665	else
2666	Log(("HWR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
2667	#endif
2668
2669	/*
2670	* Execute the code.
2671	*/
2672	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2673	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2674	VMMR3Unlock(pVM);
2675	rc = VMMR3HwAccRunGC(pVM);
2676	VMMR3Lock(pVM);
2677	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2678
2679	/*
2680	* Deal with high priority post execution FFs before doing anything else.
2681	*/
2682	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2683	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2684	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2685
2686	/*
2687	* Process the returned status code.
2688	*/
2689	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2690	break;
2691
2692	rc = emR3RawHandleRC(pVM, pCtx, rc);
2693	if (rc != VINF_SUCCESS)
2694	break;
2695
2696	/*
2697	* Check and execute forced actions.
2698	*/
2699	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2700	TMTimerPoll(pVM);
2701	#endif
2702	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2703	{
2704	rc = emR3ForcedActions(pVM, rc);
2705	if ( rc != VINF_SUCCESS
2706	&& rc != VINF_EM_RESCHEDULE_HWACC)
2707	{
2708	*pfFFDone = true;
2709	break;
2710	}
2711	}
2712	}
2713	/*
2714	* Return to outer loop.
2715	*/
2716	#if defined(LOG_ENABLED) && defined(DEBUG)
2717	RTLogFlush(NULL);
2718	#endif
2719	return rc;
2720	}
2721
2722
2723	/**
2724	* Decides whether to execute RAW, HWACC or REM.
2725	*
2726	* @returns new EM state
2727	* @param pVM The VM.
2728	* @param pCtx The CPU context.
2729	*/
2730	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2731	{
2732	/*
2733	* When forcing raw-mode execution, things are simple.
2734	*/
2735	if (pVM->em.s.fForceRAW)
2736	return EMSTATE_RAW;
2737
2738	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2739	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2740	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2741
2742	X86EFLAGS EFlags = pCtx->eflags;
2743	if (HWACCMIsEnabled(pVM))
2744	{
2745	/* Hardware accelerated raw-mode:
2746	*
2747	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2748	*/
2749	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2750	return EMSTATE_HWACC;
2751
2752	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2753	return EMSTATE_REM;
2754	}
2755
2756	/* Standard raw-mode:
2757	*
2758	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2759	* or 32 bits protected mode ring 0 code
2760	*
2761	* The tests are ordered by the likelyhood of being true during normal execution.
2762	*/
2763	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2764	{
2765	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2766	return EMSTATE_REM;
2767	}
2768
2769	#ifndef VBOX_RAW_V86
2770	if (EFlags.u32 & X86_EFL_VM) {
2771	Log2(("raw mode refused: VM_MASK\n"));
2772	return EMSTATE_REM;
2773	}
2774	#endif
2775
2776	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2777	uint32_t u32CR0 = pCtx->cr0;
2778	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2779	{
2780	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2781	return EMSTATE_REM;
2782	}
2783
2784	if (pCtx->cr4 & X86_CR4_PAE)
2785	{
2786	//Log2(("raw mode refused: PAE\n"));
2787	return EMSTATE_REM;
2788	}
2789
2790	unsigned uSS = pCtx->ss;
2791	if ( pCtx->eflags.Bits.u1VM
2792	\|\| (uSS & X86_SEL_RPL) == 3)
2793	{
2794	if (!EMIsRawRing3Enabled(pVM))
2795	return EMSTATE_REM;
2796
2797	if (!(EFlags.u32 & X86_EFL_IF))
2798	{
2799	Log2(("raw mode refused: IF (RawR3)\n"));
2800	return EMSTATE_REM;
2801	}
2802
2803	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2804	{
2805	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2806	return EMSTATE_REM;
2807	}
2808	}
2809	else
2810	{
2811	if (!EMIsRawRing0Enabled(pVM))
2812	return EMSTATE_REM;
2813
2814	/* Only ring 0 supervisor code. */
2815	if ((uSS & X86_SEL_RPL) != 0)
2816	{
2817	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2818	return EMSTATE_REM;
2819	}
2820
2821	// Let's start with pure 32 bits ring 0 code first
2822	/** @todo What's pure 32-bit mode? flat? */
2823	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2824	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2825	{
2826	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2827	return EMSTATE_REM;
2828	}
2829
2830	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2831	if (!(u32CR0 & X86_CR0_WP))
2832	{
2833	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2834	return EMSTATE_REM;
2835	}
2836
2837	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2838	{
2839	Log2(("raw r0 mode forced: patch code\n"));
2840	return EMSTATE_RAW;
2841	}
2842
2843	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2844	if (!(EFlags.u32 & X86_EFL_IF))
2845	{
2846	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2847	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2848	return EMSTATE_REM;
2849	}
2850	#endif
2851
2852	/** @todo still necessary??? */
2853	if (EFlags.Bits.u2IOPL != 0)
2854	{
2855	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2856	return EMSTATE_REM;
2857	}
2858	}
2859
2860	Assert(PGMPhysIsA20Enabled(pVM));
2861	return EMSTATE_RAW;
2862	}
2863
2864
2865	/**
2866	* Executes all high priority post execution force actions.
2867	*
2868	* @returns rc or a fatal status code.
2869	*
2870	* @param pVM VM handle.
2871	* @param rc The current rc.
2872	*/
2873	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2874	{
2875	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2876	PDMR3CritSectFF(pVM);
2877
2878	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2879	CSAMR3DoPendingAction(pVM);
2880
2881	return rc;
2882	}
2883
2884
2885	/**
2886	* Executes all pending forced actions.
2887	*
2888	* Forced actions can cause execution delays and execution
2889	* rescheduling. The first we deal with using action priority, so
2890	* that for instance pending timers aren't scheduled and ran until
2891	* right before execution. The rescheduling we deal with using
2892	* return codes. The same goes for VM termination, only in that case
2893	* we exit everything.
2894	*
2895	* @returns VBox status code of equal or greater importance/severity than rc.
2896	* The most important ones are: VINF_EM_RESCHEDULE,
2897	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2898	*
2899	* @param pVM VM handle.
2900	* @param rc The current rc.
2901	*
2902	*/
2903	static int emR3ForcedActions(PVM pVM, int rc)
2904	{
2905	#ifdef VBOX_STRICT
2906	int rcIrq = VINF_SUCCESS;
2907	#endif
2908	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2909
2910	#define UPDATE_RC() \
2911	do { \
2912	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2913	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2914	break; \
2915	if (!rc \|\| rc2 < rc) \
2916	rc = rc2; \
2917	} while (0)
2918
2919	int rc2;
2920
2921	/*
2922	* Post execution chunk first.
2923	*/
2924	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2925	{
2926	/*
2927	* Termination request.
2928	*/
2929	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2930	{
2931	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2932	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2933	return VINF_EM_TERMINATE;
2934	}
2935
2936	/*
2937	* Debugger Facility polling.
2938	*/
2939	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2940	{
2941	rc2 = DBGFR3VMMForcedAction(pVM);
2942	UPDATE_RC();
2943	}
2944
2945	/*
2946	* Postponed reset request.
2947	*/
2948	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2949	{
2950	rc2 = VMR3Reset(pVM);
2951	UPDATE_RC();
2952	VM_FF_CLEAR(pVM, VM_FF_RESET);
2953	}
2954
2955	/*
2956	* CSAM page scanning.
2957	*/
2958	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2959	{
2960	PCPUMCTX pCtx = pVM->em.s.pCtx;
2961
2962	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2963	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2964
2965	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2966	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2967	}
2968
2969	/* check that we got them all */
2970	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
2971	}
2972
2973	/*
2974	* Normal priority then.
2975	* (Executed in no particular order.)
2976	*/
2977	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2978	{
2979	/*
2980	* PDM Queues are pending.
2981	*/
2982	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
2983	PDMR3QueueFlushAll(pVM);
2984
2985	/*
2986	* PDM DMA transfers are pending.
2987	*/
2988	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
2989	PDMR3DmaRun(pVM);
2990
2991	/*
2992	* Requests from other threads.
2993	*/
2994	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
2995	{
2996	rc2 = VMR3ReqProcess(pVM);
2997	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
2998	{
2999	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3000	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3001	return rc2;
3002	}
3003	UPDATE_RC();
3004	}
3005
3006	/* check that we got them all */
3007	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3008	}
3009
3010	/*
3011	* Execute polling function ever so often.
3012	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3013	*/
3014	static unsigned cLast = 0;
3015	if (!((++cLast) % 4))
3016	PDMR3Poll(pVM);
3017
3018	/*
3019	* High priority pre execution chunk last.
3020	* (Executed in ascending priority order.)
3021	*/
3022	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3023	{
3024	/*
3025	* Timers before interrupts.
3026	*/
3027	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3028	TMR3TimerQueuesDo(pVM);
3029
3030	/*
3031	* The instruction following an emulated STI should always be executed!
3032	*/
3033	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3034	{
3035	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3036	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3037	{
3038	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3039	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3040	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3041	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3042	*/
3043	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3044	}
3045	if (HWACCMR3IsActive(pVM))
3046	rc2 = VINF_EM_RESCHEDULE_HWACC;
3047	else
3048	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3049
3050	UPDATE_RC();
3051	}
3052
3053	/*
3054	* Interrupts.
3055	*/
3056	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3057	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3058	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3059	&& PATMAreInterruptsEnabled(pVM)
3060	&& !HWACCMR3IsEventPending(pVM))
3061	{
3062	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3063	{
3064	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3065	/** @todo this really isn't nice, should properly handle this */
3066	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3067	#ifdef VBOX_STRICT
3068	rcIrq = rc2;
3069	#endif
3070	UPDATE_RC();
3071	}
3072	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3073	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3074	{
3075	rc2 = VINF_EM_RESCHEDULE_REM;
3076	UPDATE_RC();
3077	}
3078	}
3079
3080	/*
3081	* Debugger Facility request.
3082	*/
3083	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3084	{
3085	rc2 = DBGFR3VMMForcedAction(pVM);
3086	UPDATE_RC();
3087	}
3088
3089	/*
3090	* Termination request.
3091	*/
3092	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3093	{
3094	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3095	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3096	return VINF_EM_TERMINATE;
3097	}
3098
3099	#ifdef DEBUG
3100	/*
3101	* Debug, pause the VM.
3102	*/
3103	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3104	{
3105	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3106	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3107	return VINF_EM_SUSPEND;
3108	}
3109
3110	#endif
3111	/* check that we got them all */
3112	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3113	}
3114
3115	#undef UPDATE_RC
3116	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3117	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3118	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3119	return rc;
3120	}
3121
3122
3123	/**
3124	* Execute VM.
3125	*
3126	* This function is the main loop of the VM. The emulation thread
3127	* calls this function when the VM has been successfully constructed
3128	* and we're ready for executing the VM.
3129	*
3130	* Returning from this function means that the VM is turned off or
3131	* suspended (state already saved) and deconstruction in next in line.
3132	*
3133	* All interaction from other thread are done using forced actions
3134	* and signaling of the wait object.
3135	*
3136	* @returns VBox status code.
3137	* @param pVM The VM to operate on.
3138	*/
3139	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3140	{
3141	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3142	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3143	VM_ASSERT_EMT(pVM);
3144	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3145
3146	VMMR3Lock(pVM);
3147
3148	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3149	if (rc == 0)
3150	{
3151	/*
3152	* Start the virtual time.
3153	*/
3154	rc = TMVirtualResume(pVM);
3155	Assert(rc == VINF_SUCCESS);
3156	rc = TMCpuTickResume(pVM);
3157	Assert(rc == VINF_SUCCESS);
3158
3159	/*
3160	* The Outer Main Loop.
3161	*/
3162	bool fFFDone = false;
3163	rc = VINF_EM_RESCHEDULE;
3164	pVM->em.s.enmState = EMSTATE_REM;
3165	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3166	for (;;)
3167	{
3168	/*
3169	* Before we can schedule anything (we're here because
3170	* scheduling is required) we must service any pending
3171	* forced actions to avoid any pending action causing
3172	* immidate rescheduling upon entering an inner loop
3173	*
3174	* Do forced actions.
3175	*/
3176	if ( !fFFDone
3177	&& rc != VINF_EM_TERMINATE
3178	&& rc != VINF_EM_OFF
3179	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3180	{
3181	rc = emR3ForcedActions(pVM, rc);
3182	if ( ( rc == VINF_EM_RESCHEDULE_REM
3183	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3184	&& pVM->em.s.fForceRAW)
3185	rc = VINF_EM_RESCHEDULE_RAW;
3186	}
3187	else if (fFFDone)
3188	fFFDone = false;
3189
3190	/*
3191	* Now what to do?
3192	*/
3193	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3194	switch (rc)
3195	{
3196	/*
3197	* Keep doing what we're currently doing.
3198	*/
3199	case VINF_SUCCESS:
3200	break;
3201
3202	/*
3203	* Reschedule - to raw-mode execution.
3204	*/
3205	case VINF_EM_RESCHEDULE_RAW:
3206	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3207	pVM->em.s.enmState = EMSTATE_RAW;
3208	break;
3209
3210	/*
3211	* Reschedule - to hardware accelerated raw-mode execution.
3212	*/
3213	case VINF_EM_RESCHEDULE_HWACC:
3214	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3215	Assert(!pVM->em.s.fForceRAW);
3216	pVM->em.s.enmState = EMSTATE_HWACC;
3217	break;
3218
3219	/*
3220	* Reschedule - to recompiled execution.
3221	*/
3222	case VINF_EM_RESCHEDULE_REM:
3223	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3224	pVM->em.s.enmState = EMSTATE_REM;
3225	break;
3226
3227	/*
3228	* Resume.
3229	*/
3230	case VINF_EM_RESUME:
3231	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3232	/* fall through and get scheduled. */
3233
3234	/*
3235	* Reschedule.
3236	*/
3237	case VINF_EM_RESCHEDULE:
3238	{
3239	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3240	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3241	pVM->em.s.enmState = enmState;
3242	break;
3243	}
3244
3245	/*
3246	* Halted.
3247	*/
3248	case VINF_EM_HALT:
3249	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3250	pVM->em.s.enmState = EMSTATE_HALTED;
3251	break;
3252
3253	/*
3254	* Suspend.
3255	*/
3256	case VINF_EM_SUSPEND:
3257	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3258	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3259	break;
3260
3261	/*
3262	* Reset.
3263	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3264	*/
3265	case VINF_EM_RESET:
3266	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3267	pVM->em.s.enmState = EMSTATE_REM;
3268	break;
3269
3270	/*
3271	* Power Off.
3272	*/
3273	case VINF_EM_OFF:
3274	pVM->em.s.enmState = EMSTATE_TERMINATING;
3275	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3276	TMVirtualPause(pVM);
3277	TMCpuTickPause(pVM);
3278	VMMR3Unlock(pVM);
3279	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3280	return rc;
3281
3282	/*
3283	* Terminate the VM.
3284	*/
3285	case VINF_EM_TERMINATE:
3286	pVM->em.s.enmState = EMSTATE_TERMINATING;
3287	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3288	TMVirtualPause(pVM);
3289	TMCpuTickPause(pVM);
3290	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3291	return rc;
3292
3293	/*
3294	* Guest debug events.
3295	*/
3296	case VINF_EM_DBG_STEPPED:
3297	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3298	case VINF_EM_DBG_STOP:
3299	case VINF_EM_DBG_BREAKPOINT:
3300	case VINF_EM_DBG_STEP:
3301	if (pVM->em.s.enmState == EMSTATE_RAW)
3302	{
3303	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3304	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3305	}
3306	else
3307	{
3308	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3309	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3310	}
3311	break;
3312
3313	/*
3314	* Hypervisor debug events.
3315	*/
3316	case VINF_EM_DBG_HYPER_STEPPED:
3317	case VINF_EM_DBG_HYPER_BREAKPOINT:
3318	case VINF_EM_DBG_HYPER_ASSERTION:
3319	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3320	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3321	break;
3322
3323	/*
3324	* Any error code showing up here other than the ones we
3325	* know and process above are considered to be FATAL.
3326	*
3327	* Unknown warnings and informational status codes are also
3328	* included in this.
3329	*/
3330	default:
3331	if (VBOX_SUCCESS(rc))
3332	{
3333	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3334	rc = VERR_EM_INTERNAL_ERROR;
3335	}
3336	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3337	Log(("EMR3ExecuteVM returns %d\n", rc));
3338	break;
3339	}
3340
3341
3342	/*
3343	* Any waiters can now be woken up
3344	*/
3345	VMMR3Unlock(pVM);
3346	VMMR3Lock(pVM);
3347
3348	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3349	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3350
3351	/*
3352	* Act on the state.
3353	*/
3354	switch (pVM->em.s.enmState)
3355	{
3356	/*
3357	* Execute raw.
3358	*/
3359	case EMSTATE_RAW:
3360	rc = emR3RawExecute(pVM, &fFFDone);
3361	break;
3362
3363	/*
3364	* Execute hardware accelerated raw.
3365	*/
3366	case EMSTATE_HWACC:
3367	rc = emR3HwAccExecute(pVM, &fFFDone);
3368	break;
3369
3370	/*
3371	* Execute recompiled.
3372	*/
3373	case EMSTATE_REM:
3374	rc = emR3RemExecute(pVM, &fFFDone);
3375	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3376	break;
3377
3378	/*
3379	* hlt - execution halted until interrupt.
3380	*/
3381	case EMSTATE_HALTED:
3382	{
3383	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3384	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3385	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3386	break;
3387	}
3388
3389	/*
3390	* Suspended - return to VM.cpp.
3391	*/
3392	case EMSTATE_SUSPENDED:
3393	TMVirtualPause(pVM);
3394	TMCpuTickPause(pVM);
3395	VMMR3Unlock(pVM);
3396	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3397	return VINF_EM_SUSPEND;
3398
3399	/*
3400	* Debugging in the guest.
3401	*/
3402	case EMSTATE_DEBUG_GUEST_REM:
3403	case EMSTATE_DEBUG_GUEST_RAW:
3404	TMVirtualPause(pVM);
3405	TMCpuTickPause(pVM);
3406	rc = emR3Debug(pVM, rc);
3407	TMVirtualResume(pVM);
3408	TMCpuTickResume(pVM);
3409	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3410	break;
3411
3412	/*
3413	* Debugging in the hypervisor.
3414	*/
3415	case EMSTATE_DEBUG_HYPER:
3416	{
3417	TMVirtualPause(pVM);
3418	TMCpuTickPause(pVM);
3419	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3420
3421	rc = emR3Debug(pVM, rc);
3422	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3423	if (rc != VINF_SUCCESS)
3424	{
3425	/* switch to guru meditation mode */
3426	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3427	VMMR3FatalDump(pVM, rc);
3428	return rc;
3429	}
3430
3431	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3432	TMVirtualResume(pVM);
3433	TMCpuTickResume(pVM);
3434	break;
3435	}
3436
3437	/*
3438	* Guru meditation takes place in the debugger.
3439	*/
3440	case EMSTATE_GURU_MEDITATION:
3441	{
3442	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3443	TMVirtualPause(pVM);
3444	TMCpuTickPause(pVM);
3445	VMMR3FatalDump(pVM, rc);
3446	int rc2 = emR3Debug(pVM, rc);
3447	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3448	{
3449	VMMR3Unlock(pVM);
3450	/** @todo change the VM state! */
3451	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3452	return rc;
3453	}
3454	TMVirtualResume(pVM);
3455	TMCpuTickResume(pVM);
3456	rc = rc2;
3457	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3458	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3459	break;
3460	}
3461
3462	/*
3463	* The states we don't expect here.
3464	*/
3465	case EMSTATE_NONE:
3466	case EMSTATE_TERMINATING:
3467	default:
3468	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3469	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3470	TMVirtualPause(pVM);
3471	TMCpuTickPause(pVM);
3472	VMMR3Unlock(pVM);
3473	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3474	return VERR_EM_INTERNAL_ERROR;
3475	}
3476	} /* The Outer Main Loop */
3477	}
3478	else
3479	{
3480	/*
3481	* Fatal error.
3482	*/
3483	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3484	TMVirtualPause(pVM);
3485	TMCpuTickPause(pVM);
3486	VMMR3FatalDump(pVM, rc);
3487	emR3Debug(pVM, rc);
3488	VMMR3Unlock(pVM);
3489	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3490	/** @todo change the VM state! */
3491	return rc;
3492	}
3493
3494	/* (won't ever get here). */
3495	AssertFailed();
3496	}
3497

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 2981

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