EM.cpp@ 2881

Last change on this file since 2881 was 2881, checked in by vboxsync, 17 years ago
Completely wrong handling of the VINF_EM_RESCHEDULE_REM case. It was updating eip even though it told us to go to the recompiler!
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 139.4 KB

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1	/* $Id: EM.cpp 2881 2007-05-25 16:12:57Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56	#include <VBox/dbgf.h>
57
58	#include <VBox/log.h>
59	#include <iprt/thread.h>
60	#include <iprt/assert.h>
61	#include <iprt/asm.h>
62	#include <iprt/semaphore.h>
63	#include <iprt/string.h>
64	#include <iprt/avl.h>
65	#include <iprt/stream.h>
66	#include <VBox/param.h>
67	#include <VBox/err.h>
68
69
70	/*******************************************************************************
71	* Internal Functions *
72	*******************************************************************************/
73	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
74	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
75	static int emR3Debug(PVM pVM, int rc);
76	static int emR3RemStep(PVM pVM);
77	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
78	static int emR3RawResumeHyper(PVM pVM);
79	static int emR3RawStep(PVM pVM);
80	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
81	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
82	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
83	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
84	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
85	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
86	static int emR3ForcedActions(PVM pVM, int rc);
87	static int emR3RawGuestTrap(PVM pVM);
88
89
90	/**
91	* Initializes the EM.
92	*
93	* @returns VBox status code.
94	* @param pVM The VM to operate on.
95	*/
96	EMR3DECL(int) EMR3Init(PVM pVM)
97	{
98	LogFlow(("EMR3Init\n"));
99	/*
100	* Assert alignment and sizes.
101	*/
102	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
103	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
104	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
105	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
106
107	/*
108	* Init the structure.
109	*/
110	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
111	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
112	if (VBOX_FAILURE(rc))
113	pVM->fRawR3Enabled = true;
114	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR0Enabled = true;
117	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
118	pVM->em.s.enmState = EMSTATE_NONE;
119	pVM->em.s.fForceRAW = false;
120
121	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
122	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
123	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
124	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
125
126	/*
127	* Saved state.
128	*/
129	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
130	NULL, emR3Save, NULL,
131	NULL, emR3Load, NULL);
132	if (VBOX_FAILURE(rc))
133	return rc;
134
135	/*
136	* Statistics.
137	*/
138	#ifdef VBOX_WITH_STATISTICS
139	PEMSTATS pStats;
140	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
141	if (VBOX_FAILURE(rc))
142	return rc;
143	pVM->em.s.pStatsHC = pStats;
144	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
145
146	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
148
149	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
151
152	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
204
205	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
206	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
207
208	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
246
247	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
271
272	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
274	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
275	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
276
277	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
278	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
279	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
280	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
281	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
282	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
284	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
285	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
289	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
290	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
291	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
292	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
293	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
294	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
295	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
296	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
297	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
298	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
299	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
300	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
301	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
302	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
303
304	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
305	pVM->em.s.pCliStatTree = 0;
306	#endif /* VBOX_WITH_STATISTICS */
307
308	/* these should be considered for release statistics. */
309	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
310	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
311	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
312	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
313	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
314	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
315	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
316	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
317	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
318	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
319	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
320	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
321	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
322	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
323	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
324	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
325
326
327	return VINF_SUCCESS;
328	}
329
330
331
332	/**
333	* Applies relocations to data and code managed by this
334	* component. This function will be called at init and
335	* whenever the VMM need to relocate it self inside the GC.
336	*
337	* @param pVM The VM.
338	*/
339	EMR3DECL(void) EMR3Relocate(PVM pVM)
340	{
341	LogFlow(("EMR3Relocate\n"));
342	if (pVM->em.s.pStatsHC)
343	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
344	}
345
346
347	/**
348	* Reset notification.
349	*
350	* @param pVM
351	*/
352	EMR3DECL(void) EMR3Reset(PVM pVM)
353	{
354	LogFlow(("EMR3Reset: \n"));
355	pVM->em.s.fForceRAW = false;
356	}
357
358
359	/**
360	* Terminates the EM.
361	*
362	* Termination means cleaning up and freeing all resources,
363	* the VM it self is at this point powered off or suspended.
364	*
365	* @returns VBox status code.
366	* @param pVM The VM to operate on.
367	*/
368	EMR3DECL(int) EMR3Term(PVM pVM)
369	{
370	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
371
372	return VINF_SUCCESS;
373	}
374
375
376	/**
377	* Execute state save operation.
378	*
379	* @returns VBox status code.
380	* @param pVM VM Handle.
381	* @param pSSM SSM operation handle.
382	*/
383	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
384	{
385	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
386	}
387
388
389	/**
390	* Execute state load operation.
391	*
392	* @returns VBox status code.
393	* @param pVM VM Handle.
394	* @param pSSM SSM operation handle.
395	* @param u32Version Data layout version.
396	*/
397	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
398	{
399	/*
400	* Validate version.
401	*/
402	if (u32Version != EM_SAVED_STATE_VERSION)
403	{
404	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
405	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
406	}
407
408	/*
409	* Load the saved state.
410	*/
411	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
412	if (VBOX_FAILURE(rc))
413	pVM->em.s.fForceRAW = false;
414
415	Assert(pVM->em.s.pCliStatTree == 0);
416	return rc;
417	}
418
419
420	/**
421	* Enables or disables a set of raw-mode execution modes.
422	*
423	* @returns VINF_SUCCESS on success.
424	* @returns VINF_RESCHEDULE if a rescheduling might be required.
425	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
426	*
427	* @param pVM The VM to operate on.
428	* @param enmMode The execution mode change.
429	* @thread The emulation thread.
430	*/
431	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
432	{
433	switch (enmMode)
434	{
435	case EMRAW_NONE:
436	pVM->fRawR3Enabled = false;
437	pVM->fRawR0Enabled = false;
438	break;
439	case EMRAW_RING3_ENABLE:
440	pVM->fRawR3Enabled = true;
441	break;
442	case EMRAW_RING3_DISABLE:
443	pVM->fRawR3Enabled = false;
444	break;
445	case EMRAW_RING0_ENABLE:
446	pVM->fRawR0Enabled = true;
447	break;
448	case EMRAW_RING0_DISABLE:
449	pVM->fRawR0Enabled = false;
450	break;
451	default:
452	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
453	return VERR_INVALID_PARAMETER;
454	}
455	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
456	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
457	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
458	}
459
460
461	/**
462	* Raise a fatal error.
463	*
464	* Safely terminate the VM with full state report and stuff. This function
465	* will naturally never return.
466	*
467	* @param pVM VM handle.
468	* @param rc VBox status code.
469	*/
470	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
471	{
472	longjmp(pVM->em.s.u.FatalLongJump, rc);
473	AssertReleaseMsgFailed(("longjmp returned!\n"));
474	}
475
476
477	/**
478	* Gets the EM state name.
479	*
480	* @returns pointer to read only state name,
481	* @param enmState The state.
482	*/
483	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
484	{
485	switch (enmState)
486	{
487	case EMSTATE_RAW: return "EMSTATE_RAW";
488	case EMSTATE_HWACC: return "EMSTATE_HWACC";
489	case EMSTATE_REM: return "EMSTATE_REM";
490	case EMSTATE_HALTED: return "EMSTATE_HALTED";
491	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
492	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
493	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
494	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
495	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
496	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
497	default: return "Unknown!";
498	}
499	}
500
501
502	#ifdef VBOX_WITH_STATISTICS
503	/**
504	* Just a braindead function to keep track of cli addresses.
505	* @param pVM VM handle.
506	* @param pInstrGC The EIP of the cli instruction.
507	*/
508	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
509	{
510	PCLISTAT pRec;
511
512	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
513	if (!pRec)
514	{
515	/* New cli instruction; insert into the tree. */
516	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
517	Assert(pRec);
518	if (!pRec)
519	return;
520	pRec->Core.Key = (AVLPVKEY)pInstrGC;
521
522	char szCliStatName[32];
523	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
524	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
525
526	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
527	Assert(fRc); NOREF(fRc);
528	}
529	STAM_COUNTER_INC(&pRec->Counter);
530	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
531	}
532	#endif /* VBOX_WITH_STATISTICS */
533
534
535	/**
536	* Debug loop.
537	*
538	* @returns VBox status code for EM.
539	* @param pVM VM handle.
540	* @param rc Current EM VBox status code..
541	*/
542	static int emR3Debug(PVM pVM, int rc)
543	{
544	for (;;)
545	{
546	Log(("emR3Debug: rc=%Vrc\n", rc));
547	const int rcLast = rc;
548
549	/*
550	* Debug related RC.
551	*/
552	switch (rc)
553	{
554	/*
555	* Single step an instruction.
556	*/
557	case VINF_EM_DBG_STEP:
558	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
559	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
560	\|\| pVM->em.s.fForceRAW /* paranoia */)
561	rc = emR3RawStep(pVM);
562	else
563	{
564	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
565	rc = emR3RemStep(pVM);
566	}
567	break;
568
569	/*
570	* Simple events: stepped, breakpoint, stop/assertion.
571	*/
572	case VINF_EM_DBG_STEPPED:
573	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
574	break;
575
576	case VINF_EM_DBG_BREAKPOINT:
577	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
578	break;
579
580	case VINF_EM_DBG_STOP:
581	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
582	break;
583
584	case VINF_EM_DBG_HYPER_STEPPED:
585	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
586	break;
587
588	case VINF_EM_DBG_HYPER_BREAKPOINT:
589	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
590	break;
591
592	case VINF_EM_DBG_HYPER_ASSERTION:
593	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
594	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
595	break;
596
597	/*
598	* Guru meditation.
599	*/
600	default: /** @todo don't use default for guru, but make special errors code! */
601	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
602	break;
603	}
604
605	/*
606	* Process the result.
607	*/
608	do
609	{
610	switch (rc)
611	{
612	/*
613	* Continue the debugging loop.
614	*/
615	case VINF_EM_DBG_STEP:
616	case VINF_EM_DBG_STOP:
617	case VINF_EM_DBG_STEPPED:
618	case VINF_EM_DBG_BREAKPOINT:
619	case VINF_EM_DBG_HYPER_STEPPED:
620	case VINF_EM_DBG_HYPER_BREAKPOINT:
621	case VINF_EM_DBG_HYPER_ASSERTION:
622	break;
623
624	/*
625	* Resuming execution (in some form) has to be done here if we got
626	* a hypervisor debug event.
627	*/
628	case VINF_SUCCESS:
629	case VINF_EM_RESUME:
630	case VINF_EM_SUSPEND:
631	case VINF_EM_RESCHEDULE:
632	case VINF_EM_RESCHEDULE_RAW:
633	case VINF_EM_RESCHEDULE_REM:
634	case VINF_EM_HALT:
635	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
636	{
637	rc = emR3RawResumeHyper(pVM);
638	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
639	continue;
640	}
641	if (rc == VINF_SUCCESS)
642	rc = VINF_EM_RESCHEDULE;
643	return rc;
644
645	/*
646	* The debugger isn't attached.
647	* We'll simply turn the thing off since that's the easiest thing to do.
648	*/
649	case VERR_DBGF_NOT_ATTACHED:
650	switch (rcLast)
651	{
652	case VINF_EM_DBG_HYPER_ASSERTION:
653	case VINF_EM_DBG_HYPER_STEPPED:
654	case VINF_EM_DBG_HYPER_BREAKPOINT:
655	return rcLast;
656	}
657	return VINF_EM_OFF;
658
659	/*
660	* Status codes terminating the VM in one or another sense.
661	*/
662	case VINF_EM_TERMINATE:
663	case VINF_EM_OFF:
664	case VINF_EM_RESET:
665	case VINF_EM_RAW_STALE_SELECTOR:
666	case VINF_EM_RAW_IRET_TRAP:
667	case VERR_TRPM_PANIC:
668	case VERR_TRPM_DONT_PANIC:
669	case VERR_INTERNAL_ERROR:
670	return rc;
671
672	/*
673	* The rest is unexpected, and will keep us here.
674	*/
675	default:
676	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
677	break;
678	}
679	} while (false);
680	} /* debug for ever */
681	}
682
683
684	/**
685	* Steps recompiled code.
686	*
687	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
688	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
689	*
690	* @param pVM VM handle.
691	*/
692	static int emR3RemStep(PVM pVM)
693	{
694	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
695
696	/*
697	* Switch to REM, step instruction, switch back.
698	*/
699	int rc = REMR3State(pVM);
700	if (VBOX_SUCCESS(rc))
701	{
702	rc = REMR3Step(pVM);
703	REMR3StateBack(pVM);
704	}
705	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
706	return rc;
707	}
708
709	/**
710	* Executes recompiled code.
711	*
712	* This function contains the recompiler version of the inner
713	* execution loop (the outer loop being in EMR3ExecuteVM()).
714	*
715	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
716	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
717	*
718	* @param pVM VM handle.
719	* @param pfFFDone Where to store an indicator telling wheter or not
720	* FFs were done before returning.
721	*
722	*/
723	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
724	{
725	#ifdef LOG_ENABLED
726	PCPUMCTX pCtx = pVM->em.s.pCtx;
727	if (pCtx->eflags.Bits.u1VM)
728	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
729	else if ((pCtx->ss & X86_SEL_RPL) == 0)
730	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
731	else if ((pCtx->ss & X86_SEL_RPL) == 3)
732	Log(("EMR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
733	#endif
734	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
735
736	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
737	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
738	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
739	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
740	#endif
741
742	/*
743	* Spin till we get a forced action which returns anything but VINF_SUCCESS
744	* or the REM suggests raw-mode execution.
745	*/
746	*pfFFDone = false;
747	bool fInREMState = false;
748	int rc = VINF_SUCCESS;
749	for (;;)
750	{
751	/*
752	* Update REM state if not already in sync.
753	*/
754	if (!fInREMState)
755	{
756	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
757	rc = REMR3State(pVM);
758	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
759	if (VBOX_FAILURE(rc))
760	break;
761	fInREMState = true;
762
763	/*
764	* We might have missed the raising of VMREQ, TIMER and some other
765	* imporant FFs while we were busy switching the state. So, check again.
766	*/
767	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
768	{
769	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
770	goto l_REMDoForcedActions;
771	}
772	}
773
774
775	/*
776	* Execute REM.
777	*/
778	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
779	rc = REMR3Run(pVM);
780	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
781
782
783	/*
784	* Deal with high priority post execution FFs before doing anything else.
785	*/
786	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
787	rc = emR3HighPriorityPostForcedActions(pVM, rc);
788
789	/*
790	* Process the returned status code.
791	* (Try keep this short! Call functions!)
792	*/
793	if (rc != VINF_SUCCESS)
794	{
795	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
796	break;
797	if (rc != VINF_REM_INTERRUPED_FF)
798	{
799	/*
800	* Anything which is not known to us means an internal error
801	* and the termination of the VM!
802	*/
803	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
804	break;
805	}
806	}
807
808
809	/*
810	* Check and execute forced actions.
811	* Sync back the VM state before calling any of these.
812	*/
813	#ifdef VBOX_HIGH_RES_TIMERS_HACK
814	TMTimerPoll(pVM);
815	#endif
816	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
817	{
818	l_REMDoForcedActions:
819	if (fInREMState)
820	{
821	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
822	REMR3StateBack(pVM);
823	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
824	fInREMState = false;
825	}
826	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
827	rc = emR3ForcedActions(pVM, rc);
828	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
829	if ( rc != VINF_SUCCESS
830	&& rc != VINF_EM_RESCHEDULE_REM)
831	{
832	*pfFFDone = true;
833	break;
834	}
835	}
836
837	} /* The Inner Loop, recompiled execution mode version. */
838
839
840	/*
841	* Returning. Sync back the VM state if required.
842	*/
843	if (fInREMState)
844	{
845	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
846	REMR3StateBack(pVM);
847	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
848	}
849
850	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
851	return rc;
852	}
853
854
855	/**
856	* Resumes executing hypervisor after a debug event.
857	*
858	* This is kind of special since our current guest state is
859	* potentially out of sync.
860	*
861	* @returns VBox status code.
862	* @param pVM The VM handle.
863	*/
864	static int emR3RawResumeHyper(PVM pVM)
865	{
866	int rc;
867	PCPUMCTX pCtx = pVM->em.s.pCtx;
868	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
869	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
870
871	/*
872	* Resume execution.
873	*/
874	CPUMRawEnter(pVM, NULL);
875	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
876	rc = VMMR3ResumeHyper(pVM);
877	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
878	rc = CPUMRawLeave(pVM, NULL, rc);
879	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
880
881	/*
882	* Deal with the return code.
883	*/
884	rc = emR3HighPriorityPostForcedActions(pVM, rc);
885	rc = emR3RawHandleRC(pVM, pCtx, rc);
886	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
887	return rc;
888	}
889
890
891	/**
892	* Steps rawmode.
893	*
894	* @returns VBox status code.
895	* @param pVM The VM handle.
896	*/
897	static int emR3RawStep(PVM pVM)
898	{
899	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
900	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
901	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
902	int rc;
903	PCPUMCTX pCtx = pVM->em.s.pCtx;
904	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
905	#ifndef DEBUG_sandervl
906	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
907	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
908	#endif
909	if (fGuest)
910	{
911	/*
912	* Check vital forced actions, but ignore pending interrupts and timers.
913	*/
914	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
915	{
916	rc = emR3RawForcedActions(pVM, pCtx);
917	if (VBOX_FAILURE(rc))
918	return rc;
919	}
920
921	/*
922	* Set flags for single stepping.
923	*/
924	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
925	}
926	else
927	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
928
929	/*
930	* Single step.
931	* We do not start time or anything, if anything we should just do a few nanoseconds.
932	*/
933	CPUMRawEnter(pVM, NULL);
934	do
935	{
936	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
937	rc = VMMR3ResumeHyper(pVM);
938	else
939	rc = VMMR3RawRunGC(pVM);
940	#ifndef DEBUG_sandervl
941	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
942	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
943	#endif
944	} while ( rc == VINF_SUCCESS
945	\|\| rc == VINF_EM_RAW_INTERRUPT);
946	rc = CPUMRawLeave(pVM, NULL, rc);
947	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
948
949	/*
950	* Make sure the trap flag is cleared.
951	* (Too bad if the guest is trying to single step too.)
952	*/
953	if (fGuest)
954	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
955	else
956	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
957
958	/*
959	* Deal with the return codes.
960	*/
961	rc = emR3HighPriorityPostForcedActions(pVM, rc);
962	rc = emR3RawHandleRC(pVM, pCtx, rc);
963	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
964	return rc;
965	}
966
967
968	#ifdef DEBUG
969
970	/**
971	* Steps hardware accelerated mode.
972	*
973	* @returns VBox status code.
974	* @param pVM The VM handle.
975	*/
976	static int emR3HwAccStep(PVM pVM)
977	{
978	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
979
980	int rc;
981	PCPUMCTX pCtx = pVM->em.s.pCtx;
982	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
983
984	/*
985	* Check vital forced actions, but ignore pending interrupts and timers.
986	*/
987	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
988	{
989	rc = emR3RawForcedActions(pVM, pCtx);
990	if (VBOX_FAILURE(rc))
991	return rc;
992	}
993	/*
994	* Set flags for single stepping.
995	*/
996	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
997
998	/*
999	* Single step.
1000	* We do not start time or anything, if anything we should just do a few nanoseconds.
1001	*/
1002	do
1003	{
1004	rc = VMMR3HwAccRunGC(pVM);
1005	} while ( rc == VINF_SUCCESS
1006	\|\| rc == VINF_EM_RAW_INTERRUPT);
1007	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1008
1009	/*
1010	* Make sure the trap flag is cleared.
1011	* (Too bad if the guest is trying to single step too.)
1012	*/
1013	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1014
1015	/*
1016	* Deal with the return codes.
1017	*/
1018	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1019	rc = emR3RawHandleRC(pVM, pCtx, rc);
1020	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1021	return rc;
1022	}
1023
1024
1025	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1026	{
1027	EMSTATE enmOldState = pVM->em.s.enmState;
1028
1029	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1030
1031	Log(("Single step BEGIN:\n"));
1032	for(uint32_t i=0;i<cIterations;i++)
1033	{
1034	DBGFR3PrgStep(pVM);
1035	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1036	emR3RawStep(pVM);
1037	}
1038	Log(("Single step END:\n"));
1039	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1040	pVM->em.s.enmState = enmOldState;
1041	}
1042
1043
1044	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1045	{
1046	EMSTATE enmOldState = pVM->em.s.enmState;
1047
1048	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1049
1050	Log(("Single step BEGIN:\n"));
1051	for(uint32_t i=0;i<cIterations;i++)
1052	{
1053	DBGFR3PrgStep(pVM);
1054	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1055	emR3HwAccStep(pVM);
1056	}
1057	Log(("Single step END:\n"));
1058	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1059	pVM->em.s.enmState = enmOldState;
1060	}
1061
1062
1063	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1064	{
1065	EMSTATE enmOldState = pVM->em.s.enmState;
1066
1067	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1068
1069	Log(("Single step BEGIN:\n"));
1070	for(uint32_t i=0;i<cIterations;i++)
1071	{
1072	DBGFR3PrgStep(pVM);
1073	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1074	emR3RemStep(pVM);
1075	}
1076	Log(("Single step END:\n"));
1077	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1078	pVM->em.s.enmState = enmOldState;
1079	}
1080
1081	#endif /* DEBUG */
1082
1083
1084	/**
1085	* Executes one (or perhaps a few more) instruction(s).
1086	*
1087	* @returns VBox status code suitable for EM.
1088	*
1089	* @param pVM VM handle.
1090	* @param rcGC GC return code
1091	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1092	* instruction and prefix the log output with this text.
1093	*/
1094	#ifdef LOG_ENABLED
1095	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1096	#else
1097	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1098	#endif
1099	{
1100	PCPUMCTX pCtx = pVM->em.s.pCtx;
1101	int rc;
1102
1103	/*
1104	*
1105	* The simple solution is to use the recompiler.
1106	* The better solution is to disassemble the current instruction and
1107	* try handle as many as possible without using REM.
1108	*
1109	*/
1110
1111	#ifdef LOG_ENABLED
1112	/*
1113	* Disassemble the instruction if requested.
1114	*/
1115	if (pszPrefix)
1116	{
1117	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1118	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1119	}
1120	#endif /* LOG_ENABLED */
1121
1122	/*
1123	* PATM is making life more interesting.
1124	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1125	* tell PATM there is a trap in this code and have it take the appropriate actions
1126	* to allow us execute the code in REM.
1127	*/
1128	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1129	{
1130	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1131
1132	RTGCPTR pNewEip;
1133	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1134	switch (rc)
1135	{
1136	/*
1137	* It's not very useful to emulate a single instruction and then go back to raw
1138	* mode; just execute the whole block until IF is set again.
1139	*/
1140	case VINF_SUCCESS:
1141	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1142	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1143	pCtx->eip = pNewEip;
1144	Assert(pCtx->eip);
1145
1146	if (pCtx->eflags.Bits.u1IF)
1147	{
1148	/*
1149	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1150	*/
1151	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1152	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1153	}
1154	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1155	{
1156	/* special case: iret, that sets IF, detected a pending irq/event */
1157	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1158	}
1159	return VINF_EM_RESCHEDULE_REM;
1160
1161	/*
1162	* One instruction.
1163	*/
1164	case VINF_PATCH_EMULATE_INSTR:
1165	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1166	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1167	pCtx->eip = pNewEip;
1168	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1169
1170	/*
1171	* The patch was disabled, hand it to the REM.
1172	*/
1173	case VERR_PATCH_DISABLED:
1174	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1175	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1176	pCtx->eip = pNewEip;
1177	if (pCtx->eflags.Bits.u1IF)
1178	{
1179	/*
1180	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1181	*/
1182	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1183	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1184	}
1185	return VINF_EM_RESCHEDULE_REM;
1186
1187	/* Force continued patch exection; usually due to write monitored stack. */
1188	case VINF_PATCH_CONTINUE:
1189	return VINF_SUCCESS;
1190
1191	default:
1192	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1193	return VERR_INTERNAL_ERROR;
1194	}
1195	}
1196
1197	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1198	DISCPUSTATE Cpu;
1199	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1200	if (VBOX_SUCCESS(rc))
1201	{
1202	uint32_t size;
1203
1204	switch (Cpu.pCurInstr->opcode)
1205	{
1206	case OP_MOV:
1207	case OP_AND:
1208	case OP_OR:
1209	case OP_XOR:
1210	case OP_POP:
1211	case OP_INC:
1212	case OP_DEC:
1213	case OP_XCHG:
1214	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1215	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1216	if (VBOX_SUCCESS(rc))
1217	{
1218	pCtx->eip += Cpu.opsize;
1219	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1220	return rc;
1221	}
1222	if (rc != VERR_EM_INTERPRETER)
1223	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1224	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1225	break;
1226	}
1227	}
1228	#endif
1229	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1230	rc = REMR3EmulateInstruction(pVM);
1231	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1232
1233	return rc;
1234	}
1235
1236
1237	/**
1238	* Executes one (or perhaps a few more) instruction(s).
1239	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1240	*
1241	* @returns VBox status code suitable for EM.
1242	* @param pVM VM handle.
1243	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1244	* instruction and prefix the log output with this text.
1245	* @param rcGC GC return code
1246	*/
1247	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1248	{
1249	#ifdef LOG_ENABLED
1250	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1251	#else
1252	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1253	#endif
1254	}
1255
1256	/**
1257	* Executes one (or perhaps a few more) IO instruction(s).
1258	*
1259	* @returns VBox status code suitable for EM.
1260	* @param pVM VM handle.
1261	*/
1262	int emR3RawExecuteIOInstruction(PVM pVM)
1263	{
1264	int rc;
1265	PCPUMCTX pCtx = pVM->em.s.pCtx;
1266
1267	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1268
1269	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1270	* as io instructions tend to come in packages of more than one
1271	*/
1272	DISCPUSTATE Cpu;
1273	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1274	if (VBOX_SUCCESS(rc))
1275	{
1276	rc = VINF_EM_RESCHEDULE_REM;
1277
1278	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1279	{
1280	switch (Cpu.pCurInstr->opcode)
1281	{
1282	case OP_IN:
1283	{
1284	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1285	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1286	break;
1287	}
1288
1289	case OP_OUT:
1290	{
1291	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1292	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1293	break;
1294	}
1295	}
1296	}
1297	else if (Cpu.prefix & PREFIX_REP)
1298	{
1299	switch (Cpu.pCurInstr->opcode)
1300	{
1301	case OP_INSB:
1302	case OP_INSWD:
1303	{
1304	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1305	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1306	break;
1307	}
1308
1309	case OP_OUTSB:
1310	case OP_OUTSWD:
1311	{
1312	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1313	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1314	break;
1315	}
1316	}
1317	}
1318
1319	/*
1320	* Handled the I/O return codes.
1321	* (The unhandled cases ends up with rc == VINF_EM_RESCHEDULE_REM.)
1322	*/
1323	if (rc == VINF_EM_RESCHEDULE_REM)
1324	break; /* emulate this instruction only */
1325
1326	if ( rc == VINF_SUCCESS
1327	\|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST))
1328	{
1329	pCtx->eip += Cpu.opsize;
1330	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1331	return rc;
1332	}
1333
1334	if (rc == VINF_EM_RAW_GUEST_TRAP)
1335	{
1336	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1337	rc = emR3RawGuestTrap(pVM);
1338	return rc;
1339	}
1340	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1341	if (VBOX_FAILURE(rc))
1342	{
1343	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1344	return rc;
1345	}
1346	AssertMsg(rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1347	}
1348
1349	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1350	return emR3RawExecuteInstruction(pVM, "IO: ");
1351	}
1352
1353
1354	/**
1355	* Handle a guest context trap.
1356	*
1357	* @returns VBox status code suitable for EM.
1358	* @param pVM VM handle.
1359	*/
1360	static int emR3RawGuestTrap(PVM pVM)
1361	{
1362	PCPUMCTX pCtx = pVM->em.s.pCtx;
1363
1364	/*
1365	* Get the trap info.
1366	*/
1367	uint8_t u8TrapNo;
1368	TRPMEVENT enmType;;
1369	RTGCUINT uErrorCode;
1370	RTGCUINTPTR uCR2;
1371	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1372	if (VBOX_FAILURE(rc))
1373	{
1374	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1375	return rc;
1376	}
1377
1378	/* Traps can be directly forwarded in hardware accelerated mode. */
1379	if (HWACCMR3IsActive(pVM))
1380	{
1381	#ifdef LOGGING_ENABLED
1382	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1383	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1384	#endif
1385	return VINF_EM_RESCHEDULE_HWACC;
1386	}
1387
1388	/** Scan kernel code that traps; we might not get another chance. */
1389	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1390	&& !pCtx->eflags.Bits.u1VM)
1391	{
1392	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1393	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1394	}
1395
1396	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1397	{
1398	DISCPUSTATE cpu;
1399
1400	/* If MONITOR & MWAIT are supported, then interpret them here. */
1401	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1402	if ( VBOX_SUCCESS(rc)
1403	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1404	{
1405	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1406
1407	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1408
1409	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1410	{
1411	rc = TRPMResetTrap(pVM);
1412	AssertRC(rc);
1413
1414	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1415	if (VBOX_SUCCESS(rc))
1416	{
1417	pCtx->eip += cpu.opsize;
1418	return rc;
1419	}
1420	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1421	}
1422	}
1423	}
1424	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1425	{
1426	DISCPUSTATE cpu;
1427
1428	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1429	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1430	{
1431	/*
1432	* We should really check the TSS for the IO bitmap, but it's not like this
1433	* lazy approach really makes things worse.
1434	*/
1435	rc = TRPMResetTrap(pVM);
1436	AssertRC(rc);
1437	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1438	}
1439	}
1440
1441	#ifdef LOG_ENABLED
1442	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1443	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1444
1445	/* Get guest page information. */
1446	uint64_t fFlags = 0;
1447	RTGCPHYS GCPhys = 0;
1448	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1449	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1450	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1451	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1452	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1453	#endif
1454
1455	/*
1456	* #PG has CR2.
1457	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1458	*/
1459	if (u8TrapNo == 14 /* #PG */)
1460	pCtx->cr2 = uCR2;
1461
1462	return VINF_EM_RESCHEDULE_REM;
1463	}
1464
1465
1466	/**
1467	* Handle a ring switch trap.
1468	* Need to do statistics and to install patches. The result is going to REM.
1469	*
1470	* @returns VBox status code suitable for EM.
1471	* @param pVM VM handle.
1472	*/
1473	int emR3RawRingSwitch(PVM pVM)
1474	{
1475	int rc;
1476	DISCPUSTATE Cpu;
1477	PCPUMCTX pCtx = pVM->em.s.pCtx;
1478
1479	/*
1480	* sysenter, syscall & callgate
1481	*/
1482	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1483	if (VBOX_SUCCESS(rc))
1484	{
1485	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1486	{
1487	if (pCtx->SysEnter.cs != 0)
1488	{
1489	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1490	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1491	if (VBOX_SUCCESS(rc))
1492	{
1493	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1494	return VINF_EM_RESCHEDULE_RAW;
1495	}
1496	}
1497	}
1498
1499	#ifdef VBOX_WITH_STATISTICS
1500	switch (Cpu.pCurInstr->opcode)
1501	{
1502	case OP_SYSENTER:
1503	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1504	break;
1505	case OP_SYSEXIT:
1506	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1507	break;
1508	case OP_SYSCALL:
1509	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1510	break;
1511	case OP_SYSRET:
1512	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1513	break;
1514	}
1515	#endif
1516	}
1517	else
1518	AssertRC(rc);
1519
1520	/* go to the REM to emulate a single instruction */
1521	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1522	}
1523
1524	/**
1525	* Handle a trap (#PF or #GP) in patch code
1526	*
1527	* @returns VBox status code suitable for EM.
1528	* @param pVM VM handle.
1529	* @param pCtx CPU context
1530	* @param gcret GC return code
1531	*/
1532	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1533	{
1534	uint8_t u8TrapNo;
1535	int rc;
1536	TRPMEVENT enmType;
1537	RTGCUINT uErrorCode;
1538	RTGCUINTPTR uCR2;
1539
1540	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1541
1542	if (gcret == VINF_PATM_PATCH_INT3)
1543	{
1544	u8TrapNo = 3;
1545	uCR2 = 0;
1546	uErrorCode = 0;
1547	}
1548	else
1549	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1550	{
1551	/* No active trap in this case. Kind of ugly. */
1552	u8TrapNo = X86_XCPT_GP;
1553	uCR2 = 0;
1554	uErrorCode = 0;
1555	}
1556	else
1557	{
1558	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1559	if (VBOX_FAILURE(rc))
1560	{
1561	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1562	return rc;
1563	}
1564	/* Reset the trap as we'll execute the original instruction again. */
1565	TRPMResetTrap(pVM);
1566	}
1567
1568	/*
1569	* Deal with traps inside patch code.
1570	* (This code won't run outside GC.)
1571	*/
1572	if (u8TrapNo != 1)
1573	{
1574	#ifdef LOG_ENABLED
1575	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1576	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1577
1578	DISCPUSTATE Cpu;
1579	int rc;
1580
1581	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1582	if ( VBOX_SUCCESS(rc)
1583	&& Cpu.pCurInstr->opcode == OP_IRET)
1584	{
1585	uint32_t eip, selCS, uEFlags;
1586
1587	/* Iret crashes are bad as we have already changed the flags on the stack */
1588	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1589	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1590	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1591	if (rc == VINF_SUCCESS)
1592	{
1593	if ( (uEFlags & X86_EFL_VM)
1594	\|\| (selCS & X86_SEL_RPL) == 3)
1595	{
1596	uint32_t selSS, esp;
1597
1598	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1599	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1600
1601	if (uEFlags & X86_EFL_VM)
1602	{
1603	uint32_t selDS, selES, selFS, selGS;
1604	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1605	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1606	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1607	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1608	if (rc == VINF_SUCCESS)
1609	{
1610	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1611	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1612	}
1613	}
1614	else
1615	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1616	}
1617	else
1618	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1619	}
1620	}
1621	#endif
1622	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1623	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1624
1625	RTGCPTR pNewEip;
1626	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1627	switch (rc)
1628	{
1629	/*
1630	* Execute the faulting instruction.
1631	*/
1632	case VINF_SUCCESS:
1633	{
1634	/** @todo execute a whole block */
1635	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1636	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1637	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1638
1639	pCtx->eip = pNewEip;
1640	AssertRelease(pCtx->eip);
1641
1642	if (pCtx->eflags.Bits.u1IF)
1643	{
1644	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1645	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1646	*/
1647	if ( u8TrapNo == X86_XCPT_GP
1648	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1649	{
1650	/** @todo move to PATMR3HandleTrap */
1651	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1652	PATMR3RemovePatch(pVM, pCtx->eip);
1653	}
1654
1655	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1656	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1657
1658	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1659	/* Interrupts are enabled; just go back to the original instruction.
1660	return VINF_SUCCESS; */
1661	}
1662	return VINF_EM_RESCHEDULE_REM;
1663	}
1664
1665	/*
1666	* One instruction.
1667	*/
1668	case VINF_PATCH_EMULATE_INSTR:
1669	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1670	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1671	pCtx->eip = pNewEip;
1672	AssertRelease(pCtx->eip);
1673	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1674
1675	/*
1676	* The patch was disabled, hand it to the REM.
1677	*/
1678	case VERR_PATCH_DISABLED:
1679	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1680	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1681	pCtx->eip = pNewEip;
1682	AssertRelease(pCtx->eip);
1683
1684	if (pCtx->eflags.Bits.u1IF)
1685	{
1686	/*
1687	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1688	*/
1689	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1690	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1691	}
1692	return VINF_EM_RESCHEDULE_REM;
1693
1694	/* Force continued patch exection; usually due to write monitored stack. */
1695	case VINF_PATCH_CONTINUE:
1696	return VINF_SUCCESS;
1697
1698	/*
1699	* Anything else is fatal.
1700	*/
1701	default:
1702	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1703	return VERR_INTERNAL_ERROR;
1704	}
1705	}
1706	return VINF_SUCCESS;
1707	}
1708
1709
1710	/**
1711	* Handle a privileged instruction.
1712	*
1713	* @returns VBox status code suitable for EM.
1714	* @param pVM VM handle.
1715	*/
1716	int emR3RawPrivileged(PVM pVM)
1717	{
1718	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1719	PCPUMCTX pCtx = pVM->em.s.pCtx;
1720
1721	Assert(!pCtx->eflags.Bits.u1VM);
1722
1723	if (PATMIsEnabled(pVM))
1724	{
1725	/*
1726	* Check if in patch code.
1727	*/
1728	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1729	{
1730	#ifdef LOG_ENABLED
1731	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1732	#endif
1733	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1734	return VERR_EM_RAW_PATCH_CONFLICT;
1735	}
1736	if ( (pCtx->ss & X86_SEL_RPL) == 0
1737	&& !pCtx->eflags.Bits.u1VM
1738	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1739	{
1740	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1741	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1742	if (VBOX_SUCCESS(rc))
1743	{
1744	#ifdef LOG_ENABLED
1745	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1746	#endif
1747	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1748	return VINF_SUCCESS;
1749	}
1750	}
1751	}
1752
1753	#ifdef LOG_ENABLED
1754	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1755	{
1756	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1757	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1758	}
1759	#endif
1760
1761	/*
1762	* Instruction statistics and logging.
1763	*/
1764	DISCPUSTATE Cpu;
1765	int rc;
1766
1767	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1768	if (VBOX_SUCCESS(rc))
1769	{
1770	#ifdef VBOX_WITH_STATISTICS
1771	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1772	switch (Cpu.pCurInstr->opcode)
1773	{
1774	case OP_INVLPG:
1775	STAM_COUNTER_INC(&pStats->StatInvlpg);
1776	break;
1777	case OP_IRET:
1778	STAM_COUNTER_INC(&pStats->StatIret);
1779	break;
1780	case OP_CLI:
1781	STAM_COUNTER_INC(&pStats->StatCli);
1782	emR3RecordCli(pVM, pCtx->eip);
1783	break;
1784	case OP_STI:
1785	STAM_COUNTER_INC(&pStats->StatSti);
1786	break;
1787	case OP_INSB:
1788	case OP_INSWD:
1789	case OP_IN:
1790	case OP_OUTSB:
1791	case OP_OUTSWD:
1792	case OP_OUT:
1793	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1794	break;
1795
1796	case OP_MOV_CR:
1797	if (Cpu.param1.flags & USE_REG_GEN32)
1798	{
1799	//read
1800	Assert(Cpu.param2.flags & USE_REG_CR);
1801	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1802	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1803	}
1804	else
1805	{
1806	//write
1807	Assert(Cpu.param1.flags & USE_REG_CR);
1808	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1809	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1810	}
1811	break;
1812
1813	case OP_MOV_DR:
1814	STAM_COUNTER_INC(&pStats->StatMovDRx);
1815	break;
1816	case OP_LLDT:
1817	STAM_COUNTER_INC(&pStats->StatMovLldt);
1818	break;
1819	case OP_LIDT:
1820	STAM_COUNTER_INC(&pStats->StatMovLidt);
1821	break;
1822	case OP_LGDT:
1823	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1824	break;
1825	case OP_SYSENTER:
1826	STAM_COUNTER_INC(&pStats->StatSysEnter);
1827	break;
1828	case OP_SYSEXIT:
1829	STAM_COUNTER_INC(&pStats->StatSysExit);
1830	break;
1831	case OP_SYSCALL:
1832	STAM_COUNTER_INC(&pStats->StatSysCall);
1833	break;
1834	case OP_SYSRET:
1835	STAM_COUNTER_INC(&pStats->StatSysRet);
1836	break;
1837	case OP_HLT:
1838	STAM_COUNTER_INC(&pStats->StatHlt);
1839	break;
1840	default:
1841	STAM_COUNTER_INC(&pStats->StatMisc);
1842	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1843	break;
1844	}
1845	#endif
1846	if ( (pCtx->ss & X86_SEL_RPL) == 0
1847	&& !pCtx->eflags.Bits.u1VM
1848	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1849	{
1850	uint32_t size;
1851
1852	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1853	switch (Cpu.pCurInstr->opcode)
1854	{
1855	case OP_CLI:
1856	pCtx->eflags.u32 &= ~X86_EFL_IF;
1857	Assert(Cpu.opsize == 1);
1858	pCtx->eip += Cpu.opsize;
1859	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1860	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1861
1862	case OP_STI:
1863	pCtx->eflags.u32 \|= X86_EFL_IF;
1864	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1865	Assert(Cpu.opsize == 1);
1866	pCtx->eip += Cpu.opsize;
1867	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1868	return VINF_SUCCESS;
1869
1870	case OP_HLT:
1871	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1872	{
1873	PATMTRANSSTATE enmState;
1874	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1875
1876	if (enmState == PATMTRANS_OVERWRITTEN)
1877	{
1878	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1879	Assert(rc == VERR_PATCH_DISABLED);
1880	/* Conflict detected, patch disabled */
1881	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1882
1883	enmState = PATMTRANS_SAFE;
1884	}
1885
1886	/* The translation had better be successful. Otherwise we can't recover. */
1887	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1888	if (enmState != PATMTRANS_OVERWRITTEN)
1889	pCtx->eip = pOrgInstrGC;
1890	}
1891	/* no break; we could just return VINF_EM_HALT here */
1892
1893	case OP_MOV_CR:
1894	case OP_MOV_DR:
1895	#ifdef LOG_ENABLED
1896	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1897	{
1898	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1899	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1900	}
1901	#endif
1902
1903	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1904	if (VBOX_SUCCESS(rc))
1905	{
1906	pCtx->eip += Cpu.opsize;
1907	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1908
1909	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1910	&& Cpu.param1.flags == USE_REG_CR /* write */
1911	)
1912	{
1913	/* Reschedule is necessary as the execution/paging mode might have changed. */
1914	return VINF_EM_RESCHEDULE;
1915	}
1916	return rc; /* can return VINF_EM_HALT as well. */
1917	}
1918	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1919	break; /* fall back to the recompiler */
1920	}
1921	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1922	}
1923	}
1924
1925	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1926	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1927
1928	return emR3RawExecuteInstruction(pVM, "PRIV");
1929	}
1930
1931
1932	/**
1933	* Update the forced rawmode execution modifier.
1934	*
1935	* This function is called when we're returning from the raw-mode loop(s). If we're
1936	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1937	* if not in patch code, the flag will be cleared.
1938	*
1939	* We should never interrupt patch code while it's being executed. Cli patches can
1940	* contain big code blocks, but they are always executed with IF=0. Other patches
1941	* replace single instructions and should be atomic.
1942	*
1943	* @returns Updated rc.
1944	*
1945	* @param pVM The VM handle.
1946	* @param pCtx The guest CPU context.
1947	* @param rc The result code.
1948	*/
1949	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1950	{
1951	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1952	{
1953	/* ignore reschedule attempts. */
1954	switch (rc)
1955	{
1956	case VINF_EM_RESCHEDULE:
1957	case VINF_EM_RESCHEDULE_REM:
1958	rc = VINF_SUCCESS;
1959	break;
1960	}
1961	pVM->em.s.fForceRAW = true;
1962	}
1963	else
1964	pVM->em.s.fForceRAW = false;
1965	return rc;
1966	}
1967
1968
1969	/**
1970	* Process a subset of the raw-mode return code.
1971	*
1972	* Since we have to share this with raw-mode single stepping, this inline
1973	* function has been created to avoid code duplication.
1974	*
1975	* @returns VINF_SUCCESS if it's ok to continue raw mode.
1976	* @returns VBox status code to return to the EM main loop.
1977	*
1978	* @param pVM The VM handle
1979	* @param rc The return code.
1980	* @param pCtx The guest cpu context.
1981	*/
1982	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
1983	{
1984	switch (rc)
1985	{
1986	/*
1987	* Common & simple ones.
1988	*/
1989	case VINF_SUCCESS:
1990	break;
1991	case VINF_EM_RESCHEDULE_RAW:
1992	case VINF_EM_RESCHEDULE_HWACC:
1993	case VINF_EM_RAW_INTERRUPT:
1994	case VINF_EM_RAW_TO_R3:
1995	case VINF_EM_RAW_TIMER_PENDING:
1996	case VINF_EM_PENDING_REQUEST:
1997	rc = VINF_SUCCESS;
1998	break;
1999
2000	/*
2001	* Privileged instruction.
2002	*/
2003	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2004	case VINF_PATM_PATCH_TRAP_GP:
2005	rc = emR3RawPrivileged(pVM);
2006	break;
2007
2008	/*
2009	* Got a trap which needs dispatching.
2010	*/
2011	case VINF_EM_RAW_GUEST_TRAP:
2012	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2013	{
2014	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2015	rc = VERR_EM_RAW_PATCH_CONFLICT;
2016	break;
2017	}
2018
2019	Assert(TRPMHasTrap(pVM));
2020	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2021
2022	if (TRPMHasTrap(pVM))
2023	{
2024	uint8_t u8Interrupt;
2025	uint32_t uErrorCode;
2026	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2027
2028	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2029	AssertRC(rc);
2030
2031	if (uErrorCode != ~0U)
2032	enmError = TRPM_TRAP_HAS_ERRORCODE;
2033
2034	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2035	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2036	{
2037	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2038	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2039
2040	/** If it was successful, then we could go back to raw mode. */
2041	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2042	{
2043	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2044	EMR3CheckRawForcedActions(pVM);
2045
2046	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2047	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2048	{
2049	TRPMResetTrap(pVM);
2050	return VINF_EM_RESCHEDULE_RAW;
2051	}
2052	}
2053	}
2054	}
2055	rc = emR3RawGuestTrap(pVM);
2056	break;
2057
2058	/*
2059	* Trap in patch code.
2060	*/
2061	case VINF_PATM_PATCH_TRAP_PF:
2062	case VINF_PATM_PATCH_INT3:
2063	rc = emR3PatchTrap(pVM, pCtx, rc);
2064	break;
2065
2066	case VINF_PATM_DUPLICATE_FUNCTION:
2067	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2068	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2069	AssertRC(rc);
2070	rc = VINF_SUCCESS;
2071	break;
2072
2073	case VINF_PATM_CHECK_PATCH_PAGE:
2074	rc = PATMR3HandleMonitoredPage(pVM);
2075	AssertRC(rc);
2076	rc = VINF_SUCCESS;
2077	break;
2078
2079	/*
2080	* Patch manager.
2081	*/
2082	case VERR_EM_RAW_PATCH_CONFLICT:
2083	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2084	break;
2085
2086	/*
2087	* Memory mapped I/O access - attempt to patch the instruction
2088	*/
2089	case VINF_PATM_HC_MMIO_PATCH_READ:
2090	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2091	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2092	if (VBOX_FAILURE(rc))
2093	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2094	break;
2095
2096	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2097	AssertFailed(); /* not yet implemented. */
2098	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2099	break;
2100
2101	/*
2102	* Conflict or out of page tables.
2103	*
2104	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2105	* do here is to execute the pending forced actions.
2106	*/
2107	case VINF_PGM_SYNC_CR3:
2108	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2109	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2110	rc = VINF_SUCCESS;
2111	break;
2112
2113	/*
2114	* Paging mode change.
2115	*/
2116	case VINF_PGM_CHANGE_MODE:
2117	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2118	if (VBOX_SUCCESS(rc))
2119	rc = VINF_EM_RESCHEDULE;
2120	break;
2121
2122	/*
2123	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2124	*/
2125	case VINF_CSAM_PENDING_ACTION:
2126	rc = VINF_SUCCESS;
2127	break;
2128
2129	/*
2130	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2131	*/
2132	case VINF_EM_RAW_INTERRUPT_PENDING:
2133	case VINF_EM_RAW_RING_SWITCH_INT:
2134	{
2135	uint8_t u8Interrupt;
2136
2137	Assert(TRPMHasTrap(pVM));
2138	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2139
2140	if (TRPMHasTrap(pVM))
2141	{
2142	u8Interrupt = TRPMGetTrapNo(pVM);
2143
2144	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2145	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2146	{
2147	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2148	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2149	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2150	}
2151	}
2152	rc = VINF_EM_RESCHEDULE_REM;
2153	break;
2154	}
2155
2156	/*
2157	* Other ring switch types.
2158	*/
2159	case VINF_EM_RAW_RING_SWITCH:
2160	rc = emR3RawRingSwitch(pVM);
2161	break;
2162
2163	/*
2164	* REMGCNotifyInvalidatePage() failed because of overflow.
2165	*/
2166	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2167	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2168	REMR3ReplayInvalidatedPages(pVM);
2169	break;
2170
2171	/*
2172	* I/O Port access - emulate the instruction.
2173	*/
2174	case VINF_IOM_HC_IOPORT_READ:
2175	case VINF_IOM_HC_IOPORT_WRITE:
2176	rc = emR3RawExecuteIOInstruction(pVM);
2177	break;
2178
2179	/*
2180	* Memory mapped I/O access - emulate the instruction.
2181	*/
2182	case VINF_IOM_HC_MMIO_READ:
2183	case VINF_IOM_HC_MMIO_WRITE:
2184	case VINF_IOM_HC_MMIO_READ_WRITE:
2185	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2186	break;
2187
2188	/*
2189	* Execute instruction.
2190	*/
2191	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2192	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2193	break;
2194	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2195	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2196	break;
2197	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2198	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2199	break;
2200	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2201	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2202	break;
2203	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2204	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2205	break;
2206
2207	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2208	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2209	rc = emR3RawPrivileged(pVM);
2210	break;
2211
2212	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2213	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2214	break;
2215
2216	case VINF_EM_RAW_EMULATE_INSTR:
2217	case VINF_PATCH_EMULATE_INSTR:
2218	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2219	break;
2220
2221	/*
2222	* Stale selector and iret traps => REM.
2223	*/
2224	case VINF_EM_RAW_STALE_SELECTOR:
2225	case VINF_EM_RAW_IRET_TRAP:
2226	/* We will not go to the recompiler if EIP points to patch code. */
2227	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2228	{
2229	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2230	}
2231	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2232	rc = VINF_EM_RESCHEDULE_REM;
2233	break;
2234
2235	/*
2236	* Up a level.
2237	*/
2238	case VINF_EM_TERMINATE:
2239	case VINF_EM_OFF:
2240	case VINF_EM_RESET:
2241	case VINF_EM_SUSPEND:
2242	case VINF_EM_HALT:
2243	case VINF_EM_RESUME:
2244	case VINF_EM_RESCHEDULE:
2245	case VINF_EM_RESCHEDULE_REM:
2246	break;
2247
2248	/*
2249	* Up a level and invoke the debugger.
2250	*/
2251	case VINF_EM_DBG_STEPPED:
2252	case VINF_EM_DBG_BREAKPOINT:
2253	case VINF_EM_DBG_STEP:
2254	case VINF_EM_DBG_HYPER_ASSERTION:
2255	case VINF_EM_DBG_HYPER_BREAKPOINT:
2256	case VINF_EM_DBG_HYPER_STEPPED:
2257	case VINF_EM_DBG_STOP:
2258	break;
2259
2260	/*
2261	* Up a level, dump and debug.
2262	*/
2263	case VERR_TRPM_DONT_PANIC:
2264	case VERR_TRPM_PANIC:
2265	break;
2266
2267	/*
2268	* Anything which is not known to us means an internal error
2269	* and the termination of the VM!
2270	*/
2271	default:
2272	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2273	break;
2274	}
2275	return rc;
2276	}
2277
2278	/**
2279	* Check for pending raw actions
2280	*
2281	* @returns VBox status code.
2282	* @param pVM The VM to operate on.
2283	*/
2284	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2285	{
2286	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2287	}
2288
2289
2290	/**
2291	* Process raw-mode specific forced actions.
2292	*
2293	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2294	*
2295	* @returns VBox status code.
2296	* Only the normal success/failure stuff, no VINF_EM_*.
2297	* @param pVM The VM handle.
2298	* @param pCtx The guest CPUM register context.
2299	*/
2300	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2301	{
2302	/*
2303	* Note that the order is vitally important!
2304	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2305	*/
2306
2307
2308	/*
2309	* Sync selector tables.
2310	*/
2311	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2312	{
2313	int rc = SELMR3UpdateFromCPUM(pVM);
2314	if (VBOX_FAILURE(rc))
2315	return rc;
2316	}
2317
2318	/*
2319	* Sync IDT.
2320	*/
2321	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2322	{
2323	int rc = TRPMR3SyncIDT(pVM);
2324	if (VBOX_FAILURE(rc))
2325	return rc;
2326	}
2327
2328	/*
2329	* Sync TSS.
2330	*/
2331	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2332	{
2333	int rc = SELMR3SyncTSS(pVM);
2334	if (VBOX_FAILURE(rc))
2335	return rc;
2336	}
2337
2338	/*
2339	* Sync page directory.
2340	*/
2341	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2342	{
2343	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2344	if (VBOX_FAILURE(rc))
2345	return rc;
2346
2347	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2348
2349	/* Prefetch pages for EIP and ESP */
2350	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2351	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2352	if (rc == VINF_SUCCESS)
2353	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2354	if (rc != VINF_SUCCESS)
2355	{
2356	if (rc != VINF_PGM_SYNC_CR3)
2357	return rc;
2358	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2359	if (VBOX_FAILURE(rc))
2360	return rc;
2361	}
2362	/** @todo maybe prefetch the supervisor stack page as well */
2363	}
2364
2365	return VINF_SUCCESS;
2366	}
2367
2368
2369	/**
2370	* Executes raw code.
2371	*
2372	* This function contains the raw-mode version of the inner
2373	* execution loop (the outer loop being in EMR3ExecuteVM()).
2374	*
2375	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2376	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2377	*
2378	* @param pVM VM handle.
2379	* @param pfFFDone Where to store an indicator telling whether or not
2380	* FFs were done before returning.
2381	*/
2382	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2383	{
2384	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2385
2386	int rc = VERR_INTERNAL_ERROR;
2387	PCPUMCTX pCtx = pVM->em.s.pCtx;
2388	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2389	pVM->em.s.fForceRAW = false;
2390	*pfFFDone = false;
2391
2392
2393	/*
2394	*
2395	* Spin till we get a forced action or raw mode status code resulting in
2396	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2397	*
2398	*/
2399	for (;;)
2400	{
2401	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2402
2403	/*
2404	* Check various preconditions.
2405	*/
2406	#ifdef VBOX_STRICT
2407	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2408	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2409	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2410	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2411	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2412	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2413	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2414	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2415	{
2416	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2417	return VERR_INTERNAL_ERROR;
2418	}
2419	#endif /* VBOX_STRICT */
2420
2421	/*
2422	* Process high priority pre-execution raw-mode FFs.
2423	*/
2424	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2425	{
2426	rc = emR3RawForcedActions(pVM, pCtx);
2427	if (VBOX_FAILURE(rc))
2428	break;
2429	}
2430
2431	/*
2432	* If we're going to execute ring-0 code, the guest state needs to
2433	* be modified a bit and some of the state components (IF, SS/CS RPL,
2434	* and perhaps EIP) needs to be stored with PATM.
2435	*/
2436	rc = CPUMRawEnter(pVM, NULL);
2437	if (rc != VINF_SUCCESS)
2438	{
2439	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2440	break;
2441	}
2442
2443	/*
2444	* Scan code before executing it. Don't bother with user mode or V86 code
2445	*/
2446	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2447	&& !pCtx->eflags.Bits.u1VM
2448	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2449	{
2450	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2451	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2452	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2453	}
2454
2455	#ifdef LOG_ENABLED
2456	/*
2457	* Log important stuff before entering GC.
2458	*/
2459	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2460	if (pCtx->eflags.Bits.u1VM)
2461	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2462	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2463	{
2464	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2465	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2466	}
2467	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2468	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2469	#endif /* LOG_ENABLED */
2470
2471
2472
2473	/*
2474	* Execute the code.
2475	*/
2476	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2477	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2478	VMMR3Unlock(pVM);
2479	rc = VMMR3RawRunGC(pVM);
2480	VMMR3Lock(pVM);
2481	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2482	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2483
2484	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2485	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2486
2487	/*
2488	* Restore the real CPU state and deal with high priority post
2489	* execution FFs before doing anything else.
2490	*/
2491	rc = CPUMRawLeave(pVM, NULL, rc);
2492	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2493	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2494	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2495
2496	#ifdef PGM_CACHE_VERY_STRICT
2497	/*
2498	* Page manager cache checks.
2499	*/
2500	if ( rc == VINF_EM_RAW_INTERRUPT
2501	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2502	\|\| rc == VINF_IOM_HC_IOPORT_READ
2503	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2504	//\|\| rc == VINF_PATM_PATCH_INT3
2505	)
2506	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2507	#endif
2508
2509	#ifdef VBOX_STRICT
2510	/*
2511	* Assert TSS consistency & rc vs patch code.
2512	*/
2513	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2514	&& EMIsRawRing0Enabled(pVM))
2515	SELMR3CheckTSS(pVM);
2516	switch (rc)
2517	{
2518	case VINF_SUCCESS:
2519	case VINF_EM_RAW_INTERRUPT:
2520	case VINF_PATM_PATCH_TRAP_PF:
2521	case VINF_PATM_PATCH_TRAP_GP:
2522	case VINF_PATM_PATCH_INT3:
2523	case VINF_PATM_CHECK_PATCH_PAGE:
2524	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2525	case VINF_EM_RAW_GUEST_TRAP:
2526	case VINF_EM_RESCHEDULE_RAW:
2527	break;
2528
2529	default:
2530	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2531	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2532	break;
2533	}
2534	/*
2535	* Let's go paranoid!
2536	*/
2537	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2538	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2539	{
2540	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2541	return VERR_INTERNAL_ERROR;
2542	}
2543	#endif /* VBOX_STRICT */
2544
2545	/*
2546	* Process the returned status code.
2547	*/
2548	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2549	{
2550	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2551	break;
2552	}
2553	rc = emR3RawHandleRC(pVM, pCtx, rc);
2554	if (rc != VINF_SUCCESS)
2555	{
2556	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2557	if (rc != VINF_SUCCESS)
2558	{
2559	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2560	break;
2561	}
2562	}
2563
2564	/*
2565	* Check and execute forced actions.
2566	*/
2567	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2568	TMTimerPoll(pVM);
2569	#endif
2570	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2571	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2572	{
2573	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2574
2575	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2576	rc = emR3ForcedActions(pVM, rc);
2577	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2578	if ( rc != VINF_SUCCESS
2579	&& rc != VINF_EM_RESCHEDULE_RAW)
2580	{
2581	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2582	if (rc != VINF_SUCCESS)
2583	{
2584	*pfFFDone = true;
2585	break;
2586	}
2587	}
2588	}
2589	}
2590
2591	/*
2592	* Return to outer loop.
2593	*/
2594	#if defined(LOG_ENABLED) && defined(DEBUG)
2595	RTLogFlush(NULL);
2596	#endif
2597	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2598	return rc;
2599	}
2600
2601
2602	/**
2603	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2604	*
2605	* This function contains the raw-mode version of the inner
2606	* execution loop (the outer loop being in EMR3ExecuteVM()).
2607	*
2608	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2609	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2610	*
2611	* @param pVM VM handle.
2612	* @param pfFFDone Where to store an indicator telling whether or not
2613	* FFs were done before returning.
2614	*/
2615	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2616	{
2617	int rc = VERR_INTERNAL_ERROR;
2618	PCPUMCTX pCtx = pVM->em.s.pCtx;
2619
2620	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2621	*pfFFDone = false;
2622
2623	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2624
2625	/*
2626	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2627	*/
2628	for (;;)
2629	{
2630	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2631
2632	/*
2633	* Check various preconditions.
2634	*/
2635	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2636
2637	/*
2638	* Process high priority pre-execution raw-mode FFs.
2639	*/
2640	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2641	{
2642	rc = emR3RawForcedActions(pVM, pCtx);
2643	if (VBOX_FAILURE(rc))
2644	break;
2645	}
2646
2647	#ifdef LOG_ENABLED
2648	uint8_t u8Vector;
2649
2650	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2651	if (rc == VINF_SUCCESS)
2652	{
2653	Log(("Pending hardware interrupt %d\n", u8Vector));
2654	}
2655	/*
2656	* Log important stuff before entering GC.
2657	*/
2658	if (pCtx->eflags.Bits.u1VM)
2659	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2660	else if ((pCtx->ss & X86_SEL_RPL) == 0)
2661	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2662	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2663	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2664	#endif
2665
2666	/*
2667	* Execute the code.
2668	*/
2669	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2670	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2671	VMMR3Unlock(pVM);
2672	rc = VMMR3HwAccRunGC(pVM);
2673	VMMR3Lock(pVM);
2674	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2675
2676	/*
2677	* Deal with high priority post execution FFs before doing anything else.
2678	*/
2679	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2680	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2681	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2682
2683	/*
2684	* Process the returned status code.
2685	*/
2686	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2687	break;
2688
2689	rc = emR3RawHandleRC(pVM, pCtx, rc);
2690	if (rc != VINF_SUCCESS)
2691	break;
2692
2693	/*
2694	* Check and execute forced actions.
2695	*/
2696	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2697	TMTimerPoll(pVM);
2698	#endif
2699	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2700	{
2701	rc = emR3ForcedActions(pVM, rc);
2702	if ( rc != VINF_SUCCESS
2703	&& rc != VINF_EM_RESCHEDULE_HWACC)
2704	{
2705	*pfFFDone = true;
2706	break;
2707	}
2708	}
2709	}
2710	/*
2711	* Return to outer loop.
2712	*/
2713	#if defined(LOG_ENABLED) && defined(DEBUG)
2714	RTLogFlush(NULL);
2715	#endif
2716	return rc;
2717	}
2718
2719
2720	/**
2721	* Decides whether to execute RAW, HWACC or REM.
2722	*
2723	* @returns new EM state
2724	* @param pVM The VM.
2725	* @param pCtx The CPU context.
2726	*/
2727	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2728	{
2729	/*
2730	* When forcing raw-mode execution, things are simple.
2731	*/
2732	if (pVM->em.s.fForceRAW)
2733	return EMSTATE_RAW;
2734
2735	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2736	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2737	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2738
2739	X86EFLAGS EFlags = pCtx->eflags;
2740	if (HWACCMIsEnabled(pVM))
2741	{
2742	/* Hardware accelerated raw-mode:
2743	*
2744	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2745	*/
2746	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2747	return EMSTATE_HWACC;
2748
2749	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2750	return EMSTATE_REM;
2751	}
2752
2753	/* Standard raw-mode:
2754	*
2755	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2756	* or 32 bits protected mode ring 0 code
2757	*
2758	* The tests are ordered by the likelyhood of being true during normal execution.
2759	*/
2760	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2761	{
2762	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2763	return EMSTATE_REM;
2764	}
2765
2766	#ifndef VBOX_RAW_V86
2767	if (EFlags.u32 & X86_EFL_VM) {
2768	Log2(("raw mode refused: VM_MASK\n"));
2769	return EMSTATE_REM;
2770	}
2771	#endif
2772
2773	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2774	uint32_t u32CR0 = pCtx->cr0;
2775	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2776	{
2777	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2778	return EMSTATE_REM;
2779	}
2780
2781	if (pCtx->cr4 & X86_CR4_PAE)
2782	{
2783	//Log2(("raw mode refused: PAE\n"));
2784	return EMSTATE_REM;
2785	}
2786
2787	unsigned uSS = pCtx->ss;
2788	if ( pCtx->eflags.Bits.u1VM
2789	\|\| (uSS & X86_SEL_RPL) == 3)
2790	{
2791	if (!EMIsRawRing3Enabled(pVM))
2792	return EMSTATE_REM;
2793
2794	if (!(EFlags.u32 & X86_EFL_IF))
2795	{
2796	Log2(("raw mode refused: IF (RawR3)\n"));
2797	return EMSTATE_REM;
2798	}
2799
2800	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2801	{
2802	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2803	return EMSTATE_REM;
2804	}
2805	}
2806	else
2807	{
2808	if (!EMIsRawRing0Enabled(pVM))
2809	return EMSTATE_REM;
2810
2811	/* Only ring 0 supervisor code. */
2812	if ((uSS & X86_SEL_RPL) != 0)
2813	{
2814	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2815	return EMSTATE_REM;
2816	}
2817
2818	// Let's start with pure 32 bits ring 0 code first
2819	/** @todo What's pure 32-bit mode? flat? */
2820	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2821	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2822	{
2823	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2824	return EMSTATE_REM;
2825	}
2826
2827	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2828	if (!(u32CR0 & X86_CR0_WP))
2829	{
2830	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2831	return EMSTATE_REM;
2832	}
2833
2834	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2835	{
2836	Log2(("raw r0 mode forced: patch code\n"));
2837	return EMSTATE_RAW;
2838	}
2839
2840	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2841	if (!(EFlags.u32 & X86_EFL_IF))
2842	{
2843	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2844	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2845	return EMSTATE_REM;
2846	}
2847	#endif
2848
2849	/** @todo still necessary??? */
2850	if (EFlags.Bits.u2IOPL != 0)
2851	{
2852	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2853	return EMSTATE_REM;
2854	}
2855	}
2856
2857	Assert(PGMPhysIsA20Enabled(pVM));
2858	return EMSTATE_RAW;
2859	}
2860
2861
2862	/**
2863	* Executes all high priority post execution force actions.
2864	*
2865	* @returns rc or a fatal status code.
2866	*
2867	* @param pVM VM handle.
2868	* @param rc The current rc.
2869	*/
2870	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2871	{
2872	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2873	PDMR3CritSectFF(pVM);
2874
2875	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2876	CSAMR3DoPendingAction(pVM);
2877
2878	return rc;
2879	}
2880
2881
2882	/**
2883	* Executes all pending forced actions.
2884	*
2885	* Forced actions can cause execution delays and execution
2886	* rescheduling. The first we deal with using action priority, so
2887	* that for instance pending timers aren't scheduled and ran until
2888	* right before execution. The rescheduling we deal with using
2889	* return codes. The same goes for VM termination, only in that case
2890	* we exit everything.
2891	*
2892	* @returns VBox status code of equal or greater importance/severity than rc.
2893	* The most important ones are: VINF_EM_RESCHEDULE,
2894	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2895	*
2896	* @param pVM VM handle.
2897	* @param rc The current rc.
2898	*
2899	*/
2900	static int emR3ForcedActions(PVM pVM, int rc)
2901	{
2902	#ifdef VBOX_STRICT
2903	int rcIrq = VINF_SUCCESS;
2904	#endif
2905	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2906
2907	#define UPDATE_RC() \
2908	do { \
2909	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2910	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2911	break; \
2912	if (!rc \|\| rc2 < rc) \
2913	rc = rc2; \
2914	} while (0)
2915
2916	int rc2;
2917
2918	/*
2919	* Post execution chunk first.
2920	*/
2921	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2922	{
2923	/*
2924	* Termination request.
2925	*/
2926	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2927	{
2928	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2929	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2930	return VINF_EM_TERMINATE;
2931	}
2932
2933	/*
2934	* Debugger Facility polling.
2935	*/
2936	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2937	{
2938	rc2 = DBGFR3VMMForcedAction(pVM);
2939	UPDATE_RC();
2940	}
2941
2942	/*
2943	* Postponed reset request.
2944	*/
2945	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2946	{
2947	rc2 = VMR3Reset(pVM);
2948	UPDATE_RC();
2949	VM_FF_CLEAR(pVM, VM_FF_RESET);
2950	}
2951
2952	/*
2953	* CSAM page scanning.
2954	*/
2955	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2956	{
2957	PCPUMCTX pCtx = pVM->em.s.pCtx;
2958
2959	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2960	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2961
2962	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2963	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2964	}
2965
2966	/* check that we got them all */
2967	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
2968	}
2969
2970	/*
2971	* Normal priority then.
2972	* (Executed in no particular order.)
2973	*/
2974	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2975	{
2976	/*
2977	* PDM Queues are pending.
2978	*/
2979	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
2980	PDMR3QueueFlushAll(pVM);
2981
2982	/*
2983	* PDM DMA transfers are pending.
2984	*/
2985	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
2986	PDMR3DmaRun(pVM);
2987
2988	/*
2989	* Requests from other threads.
2990	*/
2991	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
2992	{
2993	rc2 = VMR3ReqProcess(pVM);
2994	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
2995	{
2996	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
2997	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2998	return rc2;
2999	}
3000	UPDATE_RC();
3001	}
3002
3003	/* check that we got them all */
3004	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3005	}
3006
3007	/*
3008	* Execute polling function ever so often.
3009	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3010	*/
3011	static unsigned cLast = 0;
3012	if (!((++cLast) % 4))
3013	PDMR3Poll(pVM);
3014
3015	/*
3016	* High priority pre execution chunk last.
3017	* (Executed in ascending priority order.)
3018	*/
3019	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3020	{
3021	/*
3022	* Timers before interrupts.
3023	*/
3024	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3025	TMR3TimerQueuesDo(pVM);
3026
3027	/*
3028	* The instruction following an emulated STI should always be executed!
3029	*/
3030	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3031	{
3032	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3033	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3034	{
3035	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3036	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3037	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3038	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3039	*/
3040	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3041	}
3042	if (HWACCMR3IsActive(pVM))
3043	rc2 = VINF_EM_RESCHEDULE_HWACC;
3044	else
3045	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3046
3047	UPDATE_RC();
3048	}
3049
3050	/*
3051	* Interrupts.
3052	*/
3053	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3054	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3055	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3056	&& PATMAreInterruptsEnabled(pVM)
3057	&& !HWACCMR3IsEventPending(pVM))
3058	{
3059	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3060	{
3061	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3062	/** @todo this really isn't nice, should properly handle this */
3063	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3064	#ifdef VBOX_STRICT
3065	rcIrq = rc2;
3066	#endif
3067	UPDATE_RC();
3068	}
3069	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3070	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3071	{
3072	rc2 = VINF_EM_RESCHEDULE_REM;
3073	UPDATE_RC();
3074	}
3075	}
3076
3077	/*
3078	* Debugger Facility request.
3079	*/
3080	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3081	{
3082	rc2 = DBGFR3VMMForcedAction(pVM);
3083	UPDATE_RC();
3084	}
3085
3086	/*
3087	* Termination request.
3088	*/
3089	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3090	{
3091	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3092	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3093	return VINF_EM_TERMINATE;
3094	}
3095
3096	#ifdef DEBUG
3097	/*
3098	* Debug, pause the VM.
3099	*/
3100	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3101	{
3102	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3103	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3104	return VINF_EM_SUSPEND;
3105	}
3106
3107	#endif
3108	/* check that we got them all */
3109	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3110	}
3111
3112	#undef UPDATE_RC
3113	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3114	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3115	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3116	return rc;
3117	}
3118
3119
3120	/**
3121	* Execute VM.
3122	*
3123	* This function is the main loop of the VM. The emulation thread
3124	* calls this function when the VM has been successfully constructed
3125	* and we're ready for executing the VM.
3126	*
3127	* Returning from this function means that the VM is turned off or
3128	* suspended (state already saved) and deconstruction in next in line.
3129	*
3130	* All interaction from other thread are done using forced actions
3131	* and signaling of the wait object.
3132	*
3133	* @returns VBox status code.
3134	* @param pVM The VM to operate on.
3135	*/
3136	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3137	{
3138	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3139	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3140	VM_ASSERT_EMT(pVM);
3141	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3142
3143	VMMR3Lock(pVM);
3144
3145	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3146	if (rc == 0)
3147	{
3148	/*
3149	* Start the virtual time.
3150	*/
3151	rc = TMVirtualResume(pVM);
3152	Assert(rc == VINF_SUCCESS);
3153	rc = TMCpuTickResume(pVM);
3154	Assert(rc == VINF_SUCCESS);
3155
3156	/*
3157	* The Outer Main Loop.
3158	*/
3159	bool fFFDone = false;
3160	rc = VINF_EM_RESCHEDULE;
3161	pVM->em.s.enmState = EMSTATE_REM;
3162	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3163	for (;;)
3164	{
3165	/*
3166	* Before we can schedule anything (we're here because
3167	* scheduling is required) we must service any pending
3168	* forced actions to avoid any pending action causing
3169	* immidate rescheduling upon entering an inner loop
3170	*
3171	* Do forced actions.
3172	*/
3173	if ( !fFFDone
3174	&& rc != VINF_EM_TERMINATE
3175	&& rc != VINF_EM_OFF
3176	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3177	{
3178	rc = emR3ForcedActions(pVM, rc);
3179	if ( ( rc == VINF_EM_RESCHEDULE_REM
3180	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3181	&& pVM->em.s.fForceRAW)
3182	rc = VINF_EM_RESCHEDULE_RAW;
3183	}
3184	else if (fFFDone)
3185	fFFDone = false;
3186
3187	/*
3188	* Now what to do?
3189	*/
3190	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3191	switch (rc)
3192	{
3193	/*
3194	* Keep doing what we're currently doing.
3195	*/
3196	case VINF_SUCCESS:
3197	break;
3198
3199	/*
3200	* Reschedule - to raw-mode execution.
3201	*/
3202	case VINF_EM_RESCHEDULE_RAW:
3203	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3204	pVM->em.s.enmState = EMSTATE_RAW;
3205	break;
3206
3207	/*
3208	* Reschedule - to hardware accelerated raw-mode execution.
3209	*/
3210	case VINF_EM_RESCHEDULE_HWACC:
3211	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3212	Assert(!pVM->em.s.fForceRAW);
3213	pVM->em.s.enmState = EMSTATE_HWACC;
3214	break;
3215
3216	/*
3217	* Reschedule - to recompiled execution.
3218	*/
3219	case VINF_EM_RESCHEDULE_REM:
3220	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3221	pVM->em.s.enmState = EMSTATE_REM;
3222	break;
3223
3224	/*
3225	* Resume.
3226	*/
3227	case VINF_EM_RESUME:
3228	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3229	/* fall through and get scheduled. */
3230
3231	/*
3232	* Reschedule.
3233	*/
3234	case VINF_EM_RESCHEDULE:
3235	{
3236	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3237	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3238	pVM->em.s.enmState = enmState;
3239	break;
3240	}
3241
3242	/*
3243	* Halted.
3244	*/
3245	case VINF_EM_HALT:
3246	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3247	pVM->em.s.enmState = EMSTATE_HALTED;
3248	break;
3249
3250	/*
3251	* Suspend.
3252	*/
3253	case VINF_EM_SUSPEND:
3254	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3255	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3256	break;
3257
3258	/*
3259	* Reset.
3260	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3261	*/
3262	case VINF_EM_RESET:
3263	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3264	pVM->em.s.enmState = EMSTATE_REM;
3265	break;
3266
3267	/*
3268	* Power Off.
3269	*/
3270	case VINF_EM_OFF:
3271	pVM->em.s.enmState = EMSTATE_TERMINATING;
3272	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3273	TMVirtualPause(pVM);
3274	TMCpuTickPause(pVM);
3275	VMMR3Unlock(pVM);
3276	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3277	return rc;
3278
3279	/*
3280	* Terminate the VM.
3281	*/
3282	case VINF_EM_TERMINATE:
3283	pVM->em.s.enmState = EMSTATE_TERMINATING;
3284	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3285	TMVirtualPause(pVM);
3286	TMCpuTickPause(pVM);
3287	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3288	return rc;
3289
3290	/*
3291	* Guest debug events.
3292	*/
3293	case VINF_EM_DBG_STEPPED:
3294	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3295	case VINF_EM_DBG_STOP:
3296	case VINF_EM_DBG_BREAKPOINT:
3297	case VINF_EM_DBG_STEP:
3298	if (pVM->em.s.enmState == EMSTATE_RAW)
3299	{
3300	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3301	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3302	}
3303	else
3304	{
3305	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3306	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3307	}
3308	break;
3309
3310	/*
3311	* Hypervisor debug events.
3312	*/
3313	case VINF_EM_DBG_HYPER_STEPPED:
3314	case VINF_EM_DBG_HYPER_BREAKPOINT:
3315	case VINF_EM_DBG_HYPER_ASSERTION:
3316	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3317	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3318	break;
3319
3320	/*
3321	* Any error code showing up here other than the ones we
3322	* know and process above are considered to be FATAL.
3323	*
3324	* Unknown warnings and informational status codes are also
3325	* included in this.
3326	*/
3327	default:
3328	if (VBOX_SUCCESS(rc))
3329	{
3330	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3331	rc = VERR_EM_INTERNAL_ERROR;
3332	}
3333	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3334	Log(("EMR3ExecuteVM returns %d\n", rc));
3335	break;
3336	}
3337
3338
3339	/*
3340	* Any waiters can now be woken up
3341	*/
3342	VMMR3Unlock(pVM);
3343	VMMR3Lock(pVM);
3344
3345	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3346	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3347
3348	/*
3349	* Act on the state.
3350	*/
3351	switch (pVM->em.s.enmState)
3352	{
3353	/*
3354	* Execute raw.
3355	*/
3356	case EMSTATE_RAW:
3357	rc = emR3RawExecute(pVM, &fFFDone);
3358	break;
3359
3360	/*
3361	* Execute hardware accelerated raw.
3362	*/
3363	case EMSTATE_HWACC:
3364	rc = emR3HwAccExecute(pVM, &fFFDone);
3365	break;
3366
3367	/*
3368	* Execute recompiled.
3369	*/
3370	case EMSTATE_REM:
3371	rc = emR3RemExecute(pVM, &fFFDone);
3372	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3373	break;
3374
3375	/*
3376	* hlt - execution halted until interrupt.
3377	*/
3378	case EMSTATE_HALTED:
3379	{
3380	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3381	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3382	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3383	break;
3384	}
3385
3386	/*
3387	* Suspended - return to VM.cpp.
3388	*/
3389	case EMSTATE_SUSPENDED:
3390	TMVirtualPause(pVM);
3391	TMCpuTickPause(pVM);
3392	VMMR3Unlock(pVM);
3393	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3394	return VINF_EM_SUSPEND;
3395
3396	/*
3397	* Debugging in the guest.
3398	*/
3399	case EMSTATE_DEBUG_GUEST_REM:
3400	case EMSTATE_DEBUG_GUEST_RAW:
3401	TMVirtualPause(pVM);
3402	TMCpuTickPause(pVM);
3403	rc = emR3Debug(pVM, rc);
3404	TMVirtualResume(pVM);
3405	TMCpuTickResume(pVM);
3406	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3407	break;
3408
3409	/*
3410	* Debugging in the hypervisor.
3411	*/
3412	case EMSTATE_DEBUG_HYPER:
3413	{
3414	TMVirtualPause(pVM);
3415	TMCpuTickPause(pVM);
3416	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3417
3418	rc = emR3Debug(pVM, rc);
3419	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3420	if (rc != VINF_SUCCESS)
3421	{
3422	/* switch to guru meditation mode */
3423	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3424	VMMR3FatalDump(pVM, rc);
3425	return rc;
3426	}
3427
3428	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3429	TMVirtualResume(pVM);
3430	TMCpuTickResume(pVM);
3431	break;
3432	}
3433
3434	/*
3435	* Guru meditation takes place in the debugger.
3436	*/
3437	case EMSTATE_GURU_MEDITATION:
3438	{
3439	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3440	TMVirtualPause(pVM);
3441	TMCpuTickPause(pVM);
3442	VMMR3FatalDump(pVM, rc);
3443	int rc2 = emR3Debug(pVM, rc);
3444	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3445	{
3446	VMMR3Unlock(pVM);
3447	/** @todo change the VM state! */
3448	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3449	return rc;
3450	}
3451	TMVirtualResume(pVM);
3452	TMCpuTickResume(pVM);
3453	rc = rc2;
3454	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3455	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3456	break;
3457	}
3458
3459	/*
3460	* The states we don't expect here.
3461	*/
3462	case EMSTATE_NONE:
3463	case EMSTATE_TERMINATING:
3464	default:
3465	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3466	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3467	TMVirtualPause(pVM);
3468	TMCpuTickPause(pVM);
3469	VMMR3Unlock(pVM);
3470	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3471	return VERR_EM_INTERNAL_ERROR;
3472	}
3473	} /* The Outer Main Loop */
3474	}
3475	else
3476	{
3477	/*
3478	* Fatal error.
3479	*/
3480	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3481	TMVirtualPause(pVM);
3482	TMCpuTickPause(pVM);
3483	VMMR3FatalDump(pVM, rc);
3484	emR3Debug(pVM, rc);
3485	VMMR3Unlock(pVM);
3486	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3487	/** @todo change the VM state! */
3488	return rc;
3489	}
3490
3491	/* (won't ever get here). */
3492	AssertFailed();
3493	}
3494

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 2881

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