VirtualBox

source: vbox/trunk/src/VBox/VMM/EM.cpp@ 26270

Last change on this file since 26270 was 26260, checked in by vboxsync, 15 years ago

EM: Corrected the pCliStatTree type.
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File size: 96.6 KB
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1/* $Id: EM.cpp 26260 2010-02-05 01:37:57Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_em EM - The Execution Monitor / Manager
23 *
24 * The Execution Monitor/Manager is responsible for running the VM, scheduling
25 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
26 * Interpreted), and keeping the CPU states in sync. The function
27 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
28 * modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
29 * emR3RemExecute).
30 *
31 * The interpreted execution is only used to avoid switching between
32 * raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
33 * The interpretation is thus implemented as part of EM.
34 *
35 * @see grp_em
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_EM
42#include <VBox/em.h>
43#include <VBox/vmm.h>
44#ifdef VBOX_WITH_VMI
45# include <VBox/parav.h>
46#endif
47#include <VBox/patm.h>
48#include <VBox/csam.h>
49#include <VBox/selm.h>
50#include <VBox/trpm.h>
51#include <VBox/iom.h>
52#include <VBox/dbgf.h>
53#include <VBox/pgm.h>
54#include <VBox/rem.h>
55#include <VBox/tm.h>
56#include <VBox/mm.h>
57#include <VBox/ssm.h>
58#include <VBox/pdmapi.h>
59#include <VBox/pdmcritsect.h>
60#include <VBox/pdmqueue.h>
61#include <VBox/hwaccm.h>
62#include <VBox/patm.h>
63#include "EMInternal.h"
64#include <VBox/vm.h>
65#include <VBox/cpumdis.h>
66#include <VBox/dis.h>
67#include <VBox/disopcode.h>
68#include <VBox/dbgf.h>
69
70#include <iprt/string.h>
71#include <iprt/stream.h>
72
73
74/*******************************************************************************
75* Defined Constants And Macros *
76*******************************************************************************/
77#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
78#define EM_NOTIFY_HWACCM
79#endif
80
81
82/*******************************************************************************
83* Internal Functions *
84*******************************************************************************/
85static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
86static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
87static const char *emR3GetStateName(EMSTATE enmState);
88static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
89static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
90static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
91int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
92
93
94/**
95 * Initializes the EM.
96 *
97 * @returns VBox status code.
98 * @param pVM The VM to operate on.
99 */
100VMMR3DECL(int) EMR3Init(PVM pVM)
101{
102 LogFlow(("EMR3Init\n"));
103 /*
104 * Assert alignment and sizes.
105 */
106 AssertCompileMemberAlignment(VM, em.s, 32);
107 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
108 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
109 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
110
111 /*
112 * Init the structure.
113 */
114 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
115 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
116 if (RT_FAILURE(rc))
117 pVM->fRawR3Enabled = true;
118 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
119 if (RT_FAILURE(rc))
120 pVM->fRawR0Enabled = true;
121 Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
122
123 /*
124 * Initialize the REM critical section.
125 */
126 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
127 AssertRCReturn(rc, rc);
128
129 /*
130 * Saved state.
131 */
132 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133 NULL, NULL, NULL,
134 NULL, emR3Save, NULL,
135 NULL, emR3Load, NULL);
136 if (RT_FAILURE(rc))
137 return rc;
138
139 for (VMCPUID i = 0; i < pVM->cCpus; i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
144
145 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
146 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
147 pVCpu->em.s.fForceRAW = false;
148
149 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
150 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
151 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
152
153# define EM_REG_COUNTER(a, b, c) \
154 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
155 AssertRC(rc);
156
157# define EM_REG_COUNTER_USED(a, b, c) \
158 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
159 AssertRC(rc);
160
161# define EM_REG_PROFILE(a, b, c) \
162 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
163 AssertRC(rc);
164
165# define EM_REG_PROFILE_ADV(a, b, c) \
166 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
167 AssertRC(rc);
168
169 /*
170 * Statistics.
171 */
172#ifdef VBOX_WITH_STATISTICS
173 PEMSTATS pStats;
174 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
175 if (RT_FAILURE(rc))
176 return rc;
177
178 pVCpu->em.s.pStatsR3 = pStats;
179 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
180 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
181
182 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
183 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
184
185 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
186 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
187
188 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
189 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
190 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
191 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
192 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
193 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
194 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
195 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
196 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
197 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
198 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
260
261 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
262 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
263
264 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
314
315 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
316 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
317 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
343
344 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
345 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
346 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
347 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
348
349 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
350 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
351 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
352 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
353 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
354 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
355 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
356 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
357 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
358 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
359 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
365 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
376
377 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
378 pVCpu->em.s.pCliStatTree = 0;
379
380 /* these should be considered for release statistics. */
381 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
382 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
383 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
384 EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
385 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
386 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
387 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
388 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
389 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
390 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
391
392#endif /* VBOX_WITH_STATISTICS */
393
394 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
395 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
396 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
397 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
398
399 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
400 }
401
402 return VINF_SUCCESS;
403}
404
405
406/**
407 * Initializes the per-VCPU EM.
408 *
409 * @returns VBox status code.
410 * @param pVM The VM to operate on.
411 */
412VMMR3DECL(int) EMR3InitCPU(PVM pVM)
413{
414 LogFlow(("EMR3InitCPU\n"));
415 return VINF_SUCCESS;
416}
417
418
419/**
420 * Applies relocations to data and code managed by this
421 * component. This function will be called at init and
422 * whenever the VMM need to relocate it self inside the GC.
423 *
424 * @param pVM The VM.
425 */
426VMMR3DECL(void) EMR3Relocate(PVM pVM)
427{
428 LogFlow(("EMR3Relocate\n"));
429 for (VMCPUID i = 0; i < pVM->cCpus; i++)
430 {
431 PVMCPU pVCpu = &pVM->aCpus[i];
432 if (pVCpu->em.s.pStatsR3)
433 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
434 }
435}
436
437
438/**
439 * Reset the EM state for a CPU.
440 *
441 * Called by EMR3Reset and hot plugging.
442 *
443 * @param pVCpu The virtual CPU.
444 */
445VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
446{
447 pVCpu->em.s.fForceRAW = false;
448
449 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
450 out of the HALTED state here so that enmPrevState doesn't end up as
451 HALTED when EMR3Execute returns. */
452 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
453 {
454 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
455 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
456 }
457}
458
459
460/**
461 * Reset notification.
462 *
463 * @param pVM The VM handle.
464 */
465VMMR3DECL(void) EMR3Reset(PVM pVM)
466{
467 Log(("EMR3Reset: \n"));
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 EMR3ResetCpu(&pVM->aCpus[i]);
470}
471
472
473/**
474 * Terminates the EM.
475 *
476 * Termination means cleaning up and freeing all resources,
477 * the VM it self is at this point powered off or suspended.
478 *
479 * @returns VBox status code.
480 * @param pVM The VM to operate on.
481 */
482VMMR3DECL(int) EMR3Term(PVM pVM)
483{
484 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
485
486 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
487 return VINF_SUCCESS;
488}
489
490/**
491 * Terminates the per-VCPU EM.
492 *
493 * Termination means cleaning up and freeing all resources,
494 * the VM it self is at this point powered off or suspended.
495 *
496 * @returns VBox status code.
497 * @param pVM The VM to operate on.
498 */
499VMMR3DECL(int) EMR3TermCPU(PVM pVM)
500{
501 return 0;
502}
503
504/**
505 * Execute state save operation.
506 *
507 * @returns VBox status code.
508 * @param pVM VM Handle.
509 * @param pSSM SSM operation handle.
510 */
511static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
512{
513 for (VMCPUID i = 0; i < pVM->cCpus; i++)
514 {
515 PVMCPU pVCpu = &pVM->aCpus[i];
516
517 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
518 AssertRCReturn(rc, rc);
519
520 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
521 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
522 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
523 AssertRCReturn(rc, rc);
524 }
525 return VINF_SUCCESS;
526}
527
528
529/**
530 * Execute state load operation.
531 *
532 * @returns VBox status code.
533 * @param pVM VM Handle.
534 * @param pSSM SSM operation handle.
535 * @param uVersion Data layout version.
536 * @param uPass The data pass.
537 */
538static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
539{
540 /*
541 * Validate version.
542 */
543 if ( uVersion != EM_SAVED_STATE_VERSION
544 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
545 {
546 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
547 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
548 }
549 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
550
551 /*
552 * Load the saved state.
553 */
554 for (VMCPUID i = 0; i < pVM->cCpus; i++)
555 {
556 PVMCPU pVCpu = &pVM->aCpus[i];
557
558 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
559 if (RT_FAILURE(rc))
560 pVCpu->em.s.fForceRAW = false;
561 AssertRCReturn(rc, rc);
562
563 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
564 {
565 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
566 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
567 AssertRCReturn(rc, rc);
568 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
569
570 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
571 }
572 Assert(!pVCpu->em.s.pCliStatTree);
573 }
574 return VINF_SUCCESS;
575}
576
577
578/**
579 * Raise a fatal error.
580 *
581 * Safely terminate the VM with full state report and stuff. This function
582 * will naturally never return.
583 *
584 * @param pVCpu VMCPU handle.
585 * @param rc VBox status code.
586 */
587VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
588{
589 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
590 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
591 AssertReleaseMsgFailed(("longjmp returned!\n"));
592}
593
594
595/**
596 * Gets the EM state name.
597 *
598 * @returns pointer to read only state name,
599 * @param enmState The state.
600 */
601static const char *emR3GetStateName(EMSTATE enmState)
602{
603 switch (enmState)
604 {
605 case EMSTATE_NONE: return "EMSTATE_NONE";
606 case EMSTATE_RAW: return "EMSTATE_RAW";
607 case EMSTATE_HWACC: return "EMSTATE_HWACC";
608 case EMSTATE_REM: return "EMSTATE_REM";
609 case EMSTATE_PARAV: return "EMSTATE_PARAV";
610 case EMSTATE_HALTED: return "EMSTATE_HALTED";
611 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
612 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
613 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
614 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
615 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
616 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
617 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
618 default: return "Unknown!";
619 }
620}
621
622
623/**
624 * Debug loop.
625 *
626 * @returns VBox status code for EM.
627 * @param pVM VM handle.
628 * @param pVCpu VMCPU handle.
629 * @param rc Current EM VBox status code..
630 */
631static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
632{
633 for (;;)
634 {
635 Log(("emR3Debug: rc=%Rrc\n", rc));
636 const int rcLast = rc;
637
638 /*
639 * Debug related RC.
640 */
641 switch (rc)
642 {
643 /*
644 * Single step an instruction.
645 */
646 case VINF_EM_DBG_STEP:
647 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
648 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
649 || pVCpu->em.s.fForceRAW /* paranoia */)
650 rc = emR3RawStep(pVM, pVCpu);
651 else
652 {
653 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
654 rc = emR3RemStep(pVM, pVCpu);
655 }
656 break;
657
658 /*
659 * Simple events: stepped, breakpoint, stop/assertion.
660 */
661 case VINF_EM_DBG_STEPPED:
662 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
663 break;
664
665 case VINF_EM_DBG_BREAKPOINT:
666 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
667 break;
668
669 case VINF_EM_DBG_STOP:
670 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
671 break;
672
673 case VINF_EM_DBG_HYPER_STEPPED:
674 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
675 break;
676
677 case VINF_EM_DBG_HYPER_BREAKPOINT:
678 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
679 break;
680
681 case VINF_EM_DBG_HYPER_ASSERTION:
682 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
683 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
684 break;
685
686 /*
687 * Guru meditation.
688 */
689 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
690 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
691 break;
692 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
693 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
694 break;
695
696 default: /** @todo don't use default for guru, but make special errors code! */
697 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
698 break;
699 }
700
701 /*
702 * Process the result.
703 */
704 do
705 {
706 switch (rc)
707 {
708 /*
709 * Continue the debugging loop.
710 */
711 case VINF_EM_DBG_STEP:
712 case VINF_EM_DBG_STOP:
713 case VINF_EM_DBG_STEPPED:
714 case VINF_EM_DBG_BREAKPOINT:
715 case VINF_EM_DBG_HYPER_STEPPED:
716 case VINF_EM_DBG_HYPER_BREAKPOINT:
717 case VINF_EM_DBG_HYPER_ASSERTION:
718 break;
719
720 /*
721 * Resuming execution (in some form) has to be done here if we got
722 * a hypervisor debug event.
723 */
724 case VINF_SUCCESS:
725 case VINF_EM_RESUME:
726 case VINF_EM_SUSPEND:
727 case VINF_EM_RESCHEDULE:
728 case VINF_EM_RESCHEDULE_RAW:
729 case VINF_EM_RESCHEDULE_REM:
730 case VINF_EM_HALT:
731 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
732 {
733 rc = emR3RawResumeHyper(pVM, pVCpu);
734 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
735 continue;
736 }
737 if (rc == VINF_SUCCESS)
738 rc = VINF_EM_RESCHEDULE;
739 return rc;
740
741 /*
742 * The debugger isn't attached.
743 * We'll simply turn the thing off since that's the easiest thing to do.
744 */
745 case VERR_DBGF_NOT_ATTACHED:
746 switch (rcLast)
747 {
748 case VINF_EM_DBG_HYPER_STEPPED:
749 case VINF_EM_DBG_HYPER_BREAKPOINT:
750 case VINF_EM_DBG_HYPER_ASSERTION:
751 case VERR_TRPM_PANIC:
752 case VERR_TRPM_DONT_PANIC:
753 case VERR_VMM_RING0_ASSERTION:
754 case VERR_VMM_HYPER_CR3_MISMATCH:
755 case VERR_VMM_RING3_CALL_DISABLED:
756 return rcLast;
757 }
758 return VINF_EM_OFF;
759
760 /*
761 * Status codes terminating the VM in one or another sense.
762 */
763 case VINF_EM_TERMINATE:
764 case VINF_EM_OFF:
765 case VINF_EM_RESET:
766 case VINF_EM_NO_MEMORY:
767 case VINF_EM_RAW_STALE_SELECTOR:
768 case VINF_EM_RAW_IRET_TRAP:
769 case VERR_TRPM_PANIC:
770 case VERR_TRPM_DONT_PANIC:
771 case VERR_VMM_RING0_ASSERTION:
772 case VERR_VMM_HYPER_CR3_MISMATCH:
773 case VERR_VMM_RING3_CALL_DISABLED:
774 case VERR_INTERNAL_ERROR:
775 case VERR_INTERNAL_ERROR_2:
776 case VERR_INTERNAL_ERROR_3:
777 case VERR_INTERNAL_ERROR_4:
778 case VERR_INTERNAL_ERROR_5:
779 case VERR_IPE_UNEXPECTED_STATUS:
780 case VERR_IPE_UNEXPECTED_INFO_STATUS:
781 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
782 return rc;
783
784 /*
785 * The rest is unexpected, and will keep us here.
786 */
787 default:
788 AssertMsgFailed(("Unxpected rc %Rrc!\n", rc));
789 break;
790 }
791 } while (false);
792 } /* debug for ever */
793}
794
795/**
796 * Steps recompiled code.
797 *
798 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
799 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
800 *
801 * @param pVM VM handle.
802 * @param pVCpu VMCPU handle.
803 */
804static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
805{
806 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
807
808 EMRemLock(pVM);
809
810 /*
811 * Switch to REM, step instruction, switch back.
812 */
813 int rc = REMR3State(pVM, pVCpu);
814 if (RT_SUCCESS(rc))
815 {
816 rc = REMR3Step(pVM, pVCpu);
817 REMR3StateBack(pVM, pVCpu);
818 }
819 EMRemUnlock(pVM);
820
821 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
822 return rc;
823}
824
825
826/**
827 * emR3RemExecute helper that syncs the state back from REM and leave the REM
828 * critical section.
829 *
830 * @returns false - new fInREMState value.
831 * @param pVM The VM handle.
832 * @param pVCpu The virtual CPU handle.
833 */
834DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
835{
836 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
837 REMR3StateBack(pVM, pVCpu);
838 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
839
840 EMRemUnlock(pVM);
841 return false;
842}
843
844
845/**
846 * Executes recompiled code.
847 *
848 * This function contains the recompiler version of the inner
849 * execution loop (the outer loop being in EMR3ExecuteVM()).
850 *
851 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
852 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
853 *
854 * @param pVM VM handle.
855 * @param pVCpu VMCPU handle.
856 * @param pfFFDone Where to store an indicator telling wheter or not
857 * FFs were done before returning.
858 *
859 */
860static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
861{
862#ifdef LOG_ENABLED
863 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
864 uint32_t cpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
865
866 if (pCtx->eflags.Bits.u1VM)
867 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
868 else
869 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
870#endif
871 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
872
873#if defined(VBOX_STRICT) && defined(DEBUG_bird)
874 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
875 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo #1419 - get flat address. */
876 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
877#endif
878
879 /*
880 * Spin till we get a forced action which returns anything but VINF_SUCCESS
881 * or the REM suggests raw-mode execution.
882 */
883 *pfFFDone = false;
884 bool fInREMState = false;
885 int rc = VINF_SUCCESS;
886 for (;;)
887 {
888 /*
889 * Lock REM and update the state if not already in sync.
890 *
891 * Note! Big lock, but you are not supposed to own any lock when
892 * coming in here.
893 */
894 if (!fInREMState)
895 {
896 EMRemLock(pVM);
897 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
898
899 /* Flush the recompiler translation blocks if the VCPU has changed,
900 also force a full CPU state resync. */
901 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
902 {
903 REMFlushTBs(pVM);
904 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
905 }
906 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
907
908 rc = REMR3State(pVM, pVCpu);
909
910 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
911 if (RT_FAILURE(rc))
912 break;
913 fInREMState = true;
914
915 /*
916 * We might have missed the raising of VMREQ, TIMER and some other
917 * imporant FFs while we were busy switching the state. So, check again.
918 */
919 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET)
920 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
921 {
922 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
923 goto l_REMDoForcedActions;
924 }
925 }
926
927
928 /*
929 * Execute REM.
930 */
931 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
932 rc = REMR3Run(pVM, pVCpu);
933 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
934
935
936 /*
937 * Deal with high priority post execution FFs before doing anything
938 * else. Sync back the state and leave the lock to be on the safe side.
939 */
940 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
941 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
942 {
943 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
944 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
945 }
946
947 /*
948 * Process the returned status code.
949 */
950 if (rc != VINF_SUCCESS)
951 {
952 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
953 break;
954 if (rc != VINF_REM_INTERRUPED_FF)
955 {
956 /*
957 * Anything which is not known to us means an internal error
958 * and the termination of the VM!
959 */
960 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
961 break;
962 }
963 }
964
965
966 /*
967 * Check and execute forced actions.
968 *
969 * Sync back the VM state and leave the lock before calling any of
970 * these, you never know what's going to happen here.
971 */
972#ifdef VBOX_HIGH_RES_TIMERS_HACK
973 TMTimerPollVoid(pVM, pVCpu);
974#endif
975 AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
976 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
977 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
978 {
979l_REMDoForcedActions:
980 if (fInREMState)
981 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
982 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
983 rc = emR3ForcedActions(pVM, pVCpu, rc);
984 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
985 if ( rc != VINF_SUCCESS
986 && rc != VINF_EM_RESCHEDULE_REM)
987 {
988 *pfFFDone = true;
989 break;
990 }
991 }
992
993 } /* The Inner Loop, recompiled execution mode version. */
994
995
996 /*
997 * Returning. Sync back the VM state if required.
998 */
999 if (fInREMState)
1000 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1001
1002 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1003 return rc;
1004}
1005
1006
1007#ifdef DEBUG
1008
1009int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1010{
1011 EMSTATE enmOldState = pVCpu->em.s.enmState;
1012
1013 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1014
1015 Log(("Single step BEGIN:\n"));
1016 for (uint32_t i = 0; i < cIterations; i++)
1017 {
1018 DBGFR3PrgStep(pVCpu);
1019 DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
1020 emR3RemStep(pVM, pVCpu);
1021 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1022 break;
1023 }
1024 Log(("Single step END:\n"));
1025 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1026 pVCpu->em.s.enmState = enmOldState;
1027 return VINF_EM_RESCHEDULE;
1028}
1029
1030#endif /* DEBUG */
1031
1032
1033/**
1034 * Decides whether to execute RAW, HWACC or REM.
1035 *
1036 * @returns new EM state
1037 * @param pVM The VM.
1038 * @param pVCpu The VMCPU handle.
1039 * @param pCtx The CPU context.
1040 */
1041EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1042{
1043 /*
1044 * When forcing raw-mode execution, things are simple.
1045 */
1046 if (pVCpu->em.s.fForceRAW)
1047 return EMSTATE_RAW;
1048
1049 /*
1050 * We stay in the wait for SIPI state unless explicitly told otherwise.
1051 */
1052 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1053 return EMSTATE_WAIT_SIPI;
1054
1055 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1056 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1057 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1058
1059 X86EFLAGS EFlags = pCtx->eflags;
1060 if (HWACCMIsEnabled(pVM))
1061 {
1062 /* Hardware accelerated raw-mode:
1063 *
1064 * Typically only 32-bits protected mode, with paging enabled, code is allowed here.
1065 */
1066 if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
1067 return EMSTATE_HWACC;
1068
1069 /* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
1070 * off monitoring features essential for raw mode! */
1071 return EMSTATE_REM;
1072 }
1073
1074 /*
1075 * Standard raw-mode:
1076 *
1077 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1078 * or 32 bits protected mode ring 0 code
1079 *
1080 * The tests are ordered by the likelyhood of being true during normal execution.
1081 */
1082 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1083 {
1084 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1085 return EMSTATE_REM;
1086 }
1087
1088#ifndef VBOX_RAW_V86
1089 if (EFlags.u32 & X86_EFL_VM) {
1090 Log2(("raw mode refused: VM_MASK\n"));
1091 return EMSTATE_REM;
1092 }
1093#endif
1094
1095 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1096 uint32_t u32CR0 = pCtx->cr0;
1097 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1098 {
1099 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1100 return EMSTATE_REM;
1101 }
1102
1103 if (pCtx->cr4 & X86_CR4_PAE)
1104 {
1105 uint32_t u32Dummy, u32Features;
1106
1107 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1108 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1109 return EMSTATE_REM;
1110 }
1111
1112 unsigned uSS = pCtx->ss;
1113 if ( pCtx->eflags.Bits.u1VM
1114 || (uSS & X86_SEL_RPL) == 3)
1115 {
1116 if (!EMIsRawRing3Enabled(pVM))
1117 return EMSTATE_REM;
1118
1119 if (!(EFlags.u32 & X86_EFL_IF))
1120 {
1121 Log2(("raw mode refused: IF (RawR3)\n"));
1122 return EMSTATE_REM;
1123 }
1124
1125 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1126 {
1127 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1128 return EMSTATE_REM;
1129 }
1130 }
1131 else
1132 {
1133 if (!EMIsRawRing0Enabled(pVM))
1134 return EMSTATE_REM;
1135
1136 /* Only ring 0 supervisor code. */
1137 if ((uSS & X86_SEL_RPL) != 0)
1138 {
1139 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1140 return EMSTATE_REM;
1141 }
1142
1143 // Let's start with pure 32 bits ring 0 code first
1144 /** @todo What's pure 32-bit mode? flat? */
1145 if ( !(pCtx->ssHid.Attr.n.u1DefBig)
1146 || !(pCtx->csHid.Attr.n.u1DefBig))
1147 {
1148 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1149 return EMSTATE_REM;
1150 }
1151
1152 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1153 if (!(u32CR0 & X86_CR0_WP))
1154 {
1155 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1156 return EMSTATE_REM;
1157 }
1158
1159 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1160 {
1161 Log2(("raw r0 mode forced: patch code\n"));
1162 return EMSTATE_RAW;
1163 }
1164
1165#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1166 if (!(EFlags.u32 & X86_EFL_IF))
1167 {
1168 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1169 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1170 return EMSTATE_REM;
1171 }
1172#endif
1173
1174 /** @todo still necessary??? */
1175 if (EFlags.Bits.u2IOPL != 0)
1176 {
1177 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1178 return EMSTATE_REM;
1179 }
1180 }
1181
1182 Assert(PGMPhysIsA20Enabled(pVCpu));
1183 return EMSTATE_RAW;
1184}
1185
1186
1187/**
1188 * Executes all high priority post execution force actions.
1189 *
1190 * @returns rc or a fatal status code.
1191 *
1192 * @param pVM VM handle.
1193 * @param pVCpu VMCPU handle.
1194 * @param rc The current rc.
1195 */
1196int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1197{
1198 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1199 PDMCritSectFF(pVCpu);
1200
1201 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1202 CSAMR3DoPendingAction(pVM, pVCpu);
1203
1204 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1205 {
1206 if ( rc > VINF_EM_NO_MEMORY
1207 && rc <= VINF_EM_LAST)
1208 rc = VINF_EM_NO_MEMORY;
1209 }
1210
1211 return rc;
1212}
1213
1214
1215/**
1216 * Executes all pending forced actions.
1217 *
1218 * Forced actions can cause execution delays and execution
1219 * rescheduling. The first we deal with using action priority, so
1220 * that for instance pending timers aren't scheduled and ran until
1221 * right before execution. The rescheduling we deal with using
1222 * return codes. The same goes for VM termination, only in that case
1223 * we exit everything.
1224 *
1225 * @returns VBox status code of equal or greater importance/severity than rc.
1226 * The most important ones are: VINF_EM_RESCHEDULE,
1227 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1228 *
1229 * @param pVM VM handle.
1230 * @param pVCpu VMCPU handle.
1231 * @param rc The current rc.
1232 *
1233 */
1234int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1235{
1236 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1237#ifdef VBOX_STRICT
1238 int rcIrq = VINF_SUCCESS;
1239#endif
1240 int rc2;
1241#define UPDATE_RC() \
1242 do { \
1243 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1244 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1245 break; \
1246 if (!rc || rc2 < rc) \
1247 rc = rc2; \
1248 } while (0)
1249
1250 /*
1251 * Post execution chunk first.
1252 */
1253 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1254 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1255 {
1256 /*
1257 * EMT Rendezvous (must be serviced before termination).
1258 */
1259 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1260 {
1261 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1262 UPDATE_RC();
1263 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1264 * stopped/reset before the next VM state change is made. We need a better
1265 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1266 * && rc >= VINF_EM_SUSPEND). */
1267 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1268 {
1269 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1270 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1271 return rc;
1272 }
1273 }
1274
1275 /*
1276 * Termination request.
1277 */
1278 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1279 {
1280 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1281 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1282 return VINF_EM_TERMINATE;
1283 }
1284
1285 /*
1286 * Debugger Facility polling.
1287 */
1288 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1289 {
1290 rc2 = DBGFR3VMMForcedAction(pVM);
1291 UPDATE_RC();
1292 }
1293
1294 /*
1295 * Postponed reset request.
1296 */
1297 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1298 {
1299 rc2 = VMR3Reset(pVM);
1300 UPDATE_RC();
1301 }
1302
1303 /*
1304 * CSAM page scanning.
1305 */
1306 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1307 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1308 {
1309 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1310
1311 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1312 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1313
1314 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1315 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1316 }
1317
1318 /*
1319 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1320 */
1321 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1322 {
1323 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1324 UPDATE_RC();
1325 if (rc == VINF_EM_NO_MEMORY)
1326 return rc;
1327 }
1328
1329 /* check that we got them all */
1330 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1331 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1332 }
1333
1334 /*
1335 * Normal priority then.
1336 * (Executed in no particular order.)
1337 */
1338 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1339 {
1340 /*
1341 * PDM Queues are pending.
1342 */
1343 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1344 PDMR3QueueFlushAll(pVM);
1345
1346 /*
1347 * PDM DMA transfers are pending.
1348 */
1349 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1350 PDMR3DmaRun(pVM);
1351
1352 /*
1353 * EMT Rendezvous (make sure they are handled before the requests).
1354 */
1355 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1356 {
1357 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1358 UPDATE_RC();
1359 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1360 * stopped/reset before the next VM state change is made. We need a better
1361 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1362 * && rc >= VINF_EM_SUSPEND). */
1363 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1364 {
1365 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1366 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1367 return rc;
1368 }
1369 }
1370
1371 /*
1372 * Requests from other threads.
1373 */
1374 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1375 {
1376 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY);
1377 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1378 {
1379 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1380 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1381 return rc2;
1382 }
1383 UPDATE_RC();
1384 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1385 * stopped/reset before the next VM state change is made. We need a better
1386 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1387 * && rc >= VINF_EM_SUSPEND). */
1388 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1389 {
1390 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1391 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1392 return rc;
1393 }
1394 }
1395
1396 /* Replay the handler notification changes. */
1397 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1398 {
1399 /* Try not to cause deadlocks. */
1400 if ( pVM->cCpus == 1
1401 || ( !PGMIsLockOwner(pVM)
1402 && !IOMIsLockOwner(pVM))
1403 )
1404 {
1405 EMRemLock(pVM);
1406 REMR3ReplayHandlerNotifications(pVM);
1407 EMRemUnlock(pVM);
1408 }
1409 }
1410
1411 /* check that we got them all */
1412 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1413 }
1414
1415 /*
1416 * Normal priority then. (per-VCPU)
1417 * (Executed in no particular order.)
1418 */
1419 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1420 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1421 {
1422 /*
1423 * Requests from other threads.
1424 */
1425 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1426 {
1427 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu);
1428 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1429 {
1430 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1431 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1432 return rc2;
1433 }
1434 UPDATE_RC();
1435 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1436 * stopped/reset before the next VM state change is made. We need a better
1437 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1438 * && rc >= VINF_EM_SUSPEND). */
1439 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1440 {
1441 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1442 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1443 return rc;
1444 }
1445 }
1446
1447 /* check that we got them all */
1448 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1449 }
1450
1451 /*
1452 * High priority pre execution chunk last.
1453 * (Executed in ascending priority order.)
1454 */
1455 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1456 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1457 {
1458 /*
1459 * Timers before interrupts.
1460 */
1461 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1462 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1463 TMR3TimerQueuesDo(pVM);
1464
1465 /*
1466 * The instruction following an emulated STI should *always* be executed!
1467 */
1468 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1469 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1470 {
1471 Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1472 if (CPUMGetGuestEIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1473 {
1474 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
1475 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1476 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1477 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1478 */
1479 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1480 }
1481 if (HWACCMR3IsActive(pVCpu))
1482 rc2 = VINF_EM_RESCHEDULE_HWACC;
1483 else
1484 rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
1485
1486 UPDATE_RC();
1487 }
1488
1489 /*
1490 * Interrupts.
1491 */
1492 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1493 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1494 && (!rc || rc >= VINF_EM_RESCHEDULE_HWACC)
1495 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1496 && PATMAreInterruptsEnabled(pVM)
1497 && !HWACCMR3IsEventPending(pVCpu))
1498 {
1499 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1500 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1501 {
1502 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1503 /** @todo this really isn't nice, should properly handle this */
1504 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1505#ifdef VBOX_STRICT
1506 rcIrq = rc2;
1507#endif
1508 UPDATE_RC();
1509 }
1510 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1511 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1512 {
1513 rc2 = VINF_EM_RESCHEDULE_REM;
1514 UPDATE_RC();
1515 }
1516 }
1517
1518 /*
1519 * Allocate handy pages.
1520 */
1521 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1522 {
1523 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1524 UPDATE_RC();
1525 }
1526
1527 /*
1528 * Debugger Facility request.
1529 */
1530 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1531 {
1532 rc2 = DBGFR3VMMForcedAction(pVM);
1533 UPDATE_RC();
1534 }
1535
1536 /*
1537 * EMT Rendezvous (must be serviced before termination).
1538 */
1539 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1540 {
1541 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1542 UPDATE_RC();
1543 /** @todo HACK ALERT! The following test is to make sure EM+TM things the VM is
1544 * stopped/reset before the next VM state change is made. We need a better
1545 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1546 * && rc >= VINF_EM_SUSPEND). */
1547 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1548 {
1549 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1550 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1551 return rc;
1552 }
1553 }
1554
1555 /*
1556 * Termination request.
1557 */
1558 if (VM_FF_ISPENDING(pVM, VM_FF_TERMINATE))
1559 {
1560 Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
1561 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1562 return VINF_EM_TERMINATE;
1563 }
1564
1565 /*
1566 * Out of memory? Since most of our fellow high priority actions may cause us
1567 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1568 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1569 * than us since we can terminate without allocating more memory.
1570 */
1571 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1572 {
1573 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1574 UPDATE_RC();
1575 if (rc == VINF_EM_NO_MEMORY)
1576 return rc;
1577 }
1578
1579 /*
1580 * If the virtual sync clock is still stopped, make TM restart it.
1581 */
1582 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1583 TMR3VirtualSyncFF(pVM, pVCpu);
1584
1585#ifdef DEBUG
1586 /*
1587 * Debug, pause the VM.
1588 */
1589 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1590 {
1591 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1592 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1593 return VINF_EM_SUSPEND;
1594 }
1595#endif
1596
1597 /* check that we got them all */
1598 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1599 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1600 }
1601
1602#undef UPDATE_RC
1603 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1604 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1605 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1606 return rc;
1607}
1608
1609/**
1610 * Release the IOM lock if owned by the current VCPU
1611 *
1612 * @param pVM The VM to operate on.
1613 */
1614VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM)
1615{
1616 while (PDMCritSectIsOwner(&pVM->em.s.CritSectREM))
1617 PDMCritSectLeave(&pVM->em.s.CritSectREM);
1618}
1619
1620
1621/**
1622 * Execute VM.
1623 *
1624 * This function is the main loop of the VM. The emulation thread
1625 * calls this function when the VM has been successfully constructed
1626 * and we're ready for executing the VM.
1627 *
1628 * Returning from this function means that the VM is turned off or
1629 * suspended (state already saved) and deconstruction in next in line.
1630 *
1631 * All interaction from other thread are done using forced actions
1632 * and signaling of the wait object.
1633 *
1634 * @returns VBox status code, informational status codes may indicate failure.
1635 * @param pVM The VM to operate on.
1636 * @param pVCpu The VMCPU to operate on.
1637 */
1638VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1639{
1640 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1641 pVM,
1642 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1643 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1644 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1645 pVCpu->em.s.fForceRAW));
1646 VM_ASSERT_EMT(pVM);
1647 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1648 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1649 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1650 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1651
1652 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1653 if (rc == 0)
1654 {
1655 /*
1656 * Start the virtual time.
1657 */
1658 TMR3NotifyResume(pVM, pVCpu);
1659
1660 /*
1661 * The Outer Main Loop.
1662 */
1663 bool fFFDone = false;
1664
1665 /* Reschedule right away to start in the right state. */
1666 rc = VINF_SUCCESS;
1667
1668 /* If resuming after a pause or a state load, restore the previous
1669 state or else we'll start executing code. Else, just reschedule. */
1670 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1671 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1672 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1673 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1674 else
1675 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1676
1677 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1678 for (;;)
1679 {
1680 /*
1681 * Before we can schedule anything (we're here because
1682 * scheduling is required) we must service any pending
1683 * forced actions to avoid any pending action causing
1684 * immediate rescheduling upon entering an inner loop
1685 *
1686 * Do forced actions.
1687 */
1688 if ( !fFFDone
1689 && rc != VINF_EM_TERMINATE
1690 && rc != VINF_EM_OFF
1691 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK)
1692 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK)))
1693 {
1694 rc = emR3ForcedActions(pVM, pVCpu, rc);
1695 if ( ( rc == VINF_EM_RESCHEDULE_REM
1696 || rc == VINF_EM_RESCHEDULE_HWACC)
1697 && pVCpu->em.s.fForceRAW)
1698 rc = VINF_EM_RESCHEDULE_RAW;
1699 }
1700 else if (fFFDone)
1701 fFFDone = false;
1702
1703 /*
1704 * Now what to do?
1705 */
1706 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
1707 switch (rc)
1708 {
1709 /*
1710 * Keep doing what we're currently doing.
1711 */
1712 case VINF_SUCCESS:
1713 break;
1714
1715 /*
1716 * Reschedule - to raw-mode execution.
1717 */
1718 case VINF_EM_RESCHEDULE_RAW:
1719 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
1720 pVCpu->em.s.enmState = EMSTATE_RAW;
1721 break;
1722
1723 /*
1724 * Reschedule - to hardware accelerated raw-mode execution.
1725 */
1726 case VINF_EM_RESCHEDULE_HWACC:
1727 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
1728 Assert(!pVCpu->em.s.fForceRAW);
1729 pVCpu->em.s.enmState = EMSTATE_HWACC;
1730 break;
1731
1732 /*
1733 * Reschedule - to recompiled execution.
1734 */
1735 case VINF_EM_RESCHEDULE_REM:
1736 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
1737 pVCpu->em.s.enmState = EMSTATE_REM;
1738 break;
1739
1740#ifdef VBOX_WITH_VMI
1741 /*
1742 * Reschedule - parav call.
1743 */
1744 case VINF_EM_RESCHEDULE_PARAV:
1745 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
1746 pVCpu->em.s.enmState = EMSTATE_PARAV;
1747 break;
1748#endif
1749
1750 /*
1751 * Resume.
1752 */
1753 case VINF_EM_RESUME:
1754 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVCpu->em.s.enmState));
1755 /* Don't reschedule in the halted or wait for SIPI case. */
1756 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1757 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
1758 break;
1759 /* fall through and get scheduled. */
1760
1761 /*
1762 * Reschedule.
1763 */
1764 case VINF_EM_RESCHEDULE:
1765 {
1766 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1767 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1768 pVCpu->em.s.enmState = enmState;
1769 break;
1770 }
1771
1772 /*
1773 * Halted.
1774 */
1775 case VINF_EM_HALT:
1776 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_HALTED));
1777 pVCpu->em.s.enmState = EMSTATE_HALTED;
1778 break;
1779
1780 /*
1781 * Switch to the wait for SIPI state (application processor only)
1782 */
1783 case VINF_EM_WAIT_SIPI:
1784 Assert(pVCpu->idCpu != 0);
1785 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_WAIT_SIPI));
1786 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1787 break;
1788
1789
1790 /*
1791 * Suspend.
1792 */
1793 case VINF_EM_SUSPEND:
1794 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1795 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1796 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1797 break;
1798
1799 /*
1800 * Reset.
1801 * We might end up doing a double reset for now, we'll have to clean up the mess later.
1802 */
1803 case VINF_EM_RESET:
1804 {
1805 if (pVCpu->idCpu == 0)
1806 {
1807 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1808 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, emR3GetStateName(enmState)));
1809 pVCpu->em.s.enmState = enmState;
1810 }
1811 else
1812 {
1813 /* All other VCPUs go into the wait for SIPI state. */
1814 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
1815 }
1816 break;
1817 }
1818
1819 /*
1820 * Power Off.
1821 */
1822 case VINF_EM_OFF:
1823 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1824 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1825 TMR3NotifySuspend(pVM, pVCpu);
1826 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1827 return rc;
1828
1829 /*
1830 * Terminate the VM.
1831 */
1832 case VINF_EM_TERMINATE:
1833 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
1834 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
1835 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
1836 TMR3NotifySuspend(pVM, pVCpu);
1837 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1838 return rc;
1839
1840
1841 /*
1842 * Out of memory, suspend the VM and stuff.
1843 */
1844 case VINF_EM_NO_MEMORY:
1845 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", pVCpu->em.s.enmState, EMSTATE_SUSPENDED));
1846 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
1847 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
1848 TMR3NotifySuspend(pVM, pVCpu);
1849 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1850
1851 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
1852 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
1853 if (rc != VINF_EM_SUSPEND)
1854 {
1855 if (RT_SUCCESS_NP(rc))
1856 {
1857 AssertLogRelMsgFailed(("%Rrc\n", rc));
1858 rc = VERR_EM_INTERNAL_ERROR;
1859 }
1860 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1861 }
1862 return rc;
1863
1864 /*
1865 * Guest debug events.
1866 */
1867 case VINF_EM_DBG_STEPPED:
1868 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
1869 case VINF_EM_DBG_STOP:
1870 case VINF_EM_DBG_BREAKPOINT:
1871 case VINF_EM_DBG_STEP:
1872 if (pVCpu->em.s.enmState == EMSTATE_RAW)
1873 {
1874 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
1875 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1876 }
1877 else
1878 {
1879 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
1880 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1881 }
1882 break;
1883
1884 /*
1885 * Hypervisor debug events.
1886 */
1887 case VINF_EM_DBG_HYPER_STEPPED:
1888 case VINF_EM_DBG_HYPER_BREAKPOINT:
1889 case VINF_EM_DBG_HYPER_ASSERTION:
1890 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, pVCpu->em.s.enmState, EMSTATE_DEBUG_HYPER));
1891 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
1892 break;
1893
1894 /*
1895 * Guru mediations.
1896 */
1897 case VERR_VMM_RING0_ASSERTION:
1898 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1899 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1900 break;
1901
1902 /*
1903 * Any error code showing up here other than the ones we
1904 * know and process above are considered to be FATAL.
1905 *
1906 * Unknown warnings and informational status codes are also
1907 * included in this.
1908 */
1909 default:
1910 if (RT_SUCCESS_NP(rc))
1911 {
1912 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
1913 rc = VERR_EM_INTERNAL_ERROR;
1914 }
1915 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
1916 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
1917 break;
1918 }
1919
1920 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
1921 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1922
1923 /*
1924 * Act on the state.
1925 */
1926 switch (pVCpu->em.s.enmState)
1927 {
1928 /*
1929 * Execute raw.
1930 */
1931 case EMSTATE_RAW:
1932 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
1933 break;
1934
1935 /*
1936 * Execute hardware accelerated raw.
1937 */
1938 case EMSTATE_HWACC:
1939 rc = emR3HwAccExecute(pVM, pVCpu, &fFFDone);
1940 break;
1941
1942 /*
1943 * Execute recompiled.
1944 */
1945 case EMSTATE_REM:
1946 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
1947 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
1948 break;
1949
1950#ifdef VBOX_WITH_VMI
1951 /*
1952 * Execute PARAV function.
1953 */
1954 case EMSTATE_PARAV:
1955 rc = PARAVCallFunction(pVM);
1956 pVCpu->em.s.enmState = EMSTATE_REM;
1957 break;
1958#endif
1959
1960 /*
1961 * Application processor execution halted until SIPI.
1962 */
1963 case EMSTATE_WAIT_SIPI:
1964 /* no break */
1965 /*
1966 * hlt - execution halted until interrupt.
1967 */
1968 case EMSTATE_HALTED:
1969 {
1970 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
1971 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
1972 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
1973 break;
1974 }
1975
1976 /*
1977 * Suspended - return to VM.cpp.
1978 */
1979 case EMSTATE_SUSPENDED:
1980 TMR3NotifySuspend(pVM, pVCpu);
1981 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
1982 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
1983 return VINF_EM_SUSPEND;
1984
1985 /*
1986 * Debugging in the guest.
1987 */
1988 case EMSTATE_DEBUG_GUEST_REM:
1989 case EMSTATE_DEBUG_GUEST_RAW:
1990 TMR3NotifySuspend(pVM, pVCpu);
1991 rc = emR3Debug(pVM, pVCpu, rc);
1992 TMR3NotifyResume(pVM, pVCpu);
1993 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
1994 break;
1995
1996 /*
1997 * Debugging in the hypervisor.
1998 */
1999 case EMSTATE_DEBUG_HYPER:
2000 {
2001 TMR3NotifySuspend(pVM, pVCpu);
2002 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2003
2004 rc = emR3Debug(pVM, pVCpu, rc);
2005 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2006 if (rc != VINF_SUCCESS)
2007 {
2008 /* switch to guru meditation mode */
2009 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2010 VMMR3FatalDump(pVM, pVCpu, rc);
2011 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2012 return rc;
2013 }
2014
2015 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2016 TMR3NotifyResume(pVM, pVCpu);
2017 break;
2018 }
2019
2020 /*
2021 * Guru meditation takes place in the debugger.
2022 */
2023 case EMSTATE_GURU_MEDITATION:
2024 {
2025 TMR3NotifySuspend(pVM, pVCpu);
2026 VMMR3FatalDump(pVM, pVCpu, rc);
2027 emR3Debug(pVM, pVCpu, rc);
2028 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2029 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2030 return rc;
2031 }
2032
2033 /*
2034 * The states we don't expect here.
2035 */
2036 case EMSTATE_NONE:
2037 case EMSTATE_TERMINATING:
2038 default:
2039 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2040 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2041 TMR3NotifySuspend(pVM, pVCpu);
2042 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2043 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2044 return VERR_EM_INTERNAL_ERROR;
2045 }
2046 } /* The Outer Main Loop */
2047 }
2048 else
2049 {
2050 /*
2051 * Fatal error.
2052 */
2053 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2054 TMR3NotifySuspend(pVM, pVCpu);
2055 VMMR3FatalDump(pVM, pVCpu, rc);
2056 emR3Debug(pVM, pVCpu, rc);
2057 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2058 /** @todo change the VM state! */
2059 return rc;
2060 }
2061
2062 /* (won't ever get here). */
2063 AssertFailed();
2064}
2065
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