EM.cpp@ 19

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1	/** @file
2	*
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/pdm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/patm.h>
51	#include "EMInternal.h"
52	#include <VBox/vm.h>
53	#include <VBox/cpumdis.h>
54	#include <VBox/dis.h>
55	#include <VBox/disopcode.h>
56
57	#include <VBox/log.h>
58	#include <iprt/thread.h>
59	#include <iprt/assert.h>
60	#include <iprt/asm.h>
61	#include <iprt/semaphore.h>
62	#include <iprt/string.h>
63	#include <iprt/avl.h>
64	#include <iprt/stream.h>
65	#include <VBox/param.h>
66	#include <VBox/err.h>
67
68
69	/*******************************************************************************
70	* Internal Functions *
71	*******************************************************************************/
72	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
73	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
74	static int emR3Debug(PVM pVM, int rc);
75	static int emR3RemStep(PVM pVM);
76	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
77	static int emR3RawResumeHyper(PVM pVM);
78	static int emR3RawStep(PVM pVM);
79	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
80	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
81	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
82	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
83	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix);
84	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
85	static int emR3ForcedActions(PVM pVM, int rc);
86	static int emR3RawGuestTrap(PVM pVM);
87
88
89	/**
90	* Initializes the EM.
91	*
92	* @returns VBox status code.
93	* @param pVM The VM to operate on.
94	*/
95	EMR3DECL(int) EMR3Init(PVM pVM)
96	{
97	LogFlow(("EMR3Init\n"));
98	/*
99	* Assert alignment and sizes.
100	*/
101	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
102	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
103	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
104	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
105
106	/*
107	* Init the structure.
108	*/
109	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
110	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
111	if (VBOX_FAILURE(rc))
112	pVM->fRawR3Enabled = true;
113	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
114	if (VBOX_FAILURE(rc))
115	pVM->fRawR0Enabled = true;
116	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
117	pVM->em.s.enmState = EMSTATE_NONE;
118	pVM->em.s.fForceRAW = false;
119
120	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
121	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
122	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
123	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
124
125	/*
126	* Saved state.
127	*/
128	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
129	NULL, emR3Save, NULL,
130	NULL, emR3Load, NULL);
131	if (VBOX_FAILURE(rc))
132	return rc;
133
134	/*
135	* Statistics.
136	*/
137	#ifdef VBOX_WITH_STATISTICS
138	PEMSTATS pStats;
139	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
140	if (VBOX_FAILURE(rc))
141	return rc;
142	pVM->em.s.pStatsHC = pStats;
143	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
144
145	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
146	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
147
148	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
149	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
150
151	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
152	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
153	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
154	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
155	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
193
194	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
195	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
196
197	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
233
234	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
235	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
236	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
256
257	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
261
262	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
263	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
264	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
265	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
266	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
267	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
268	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
269	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
270	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
271	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
272	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
273	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
274	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
275	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
276	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
277	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
278	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
279	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
280	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
281	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
282	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
283	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
284	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
285	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
286	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
287	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
288
289	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
290	pVM->em.s.pCliStatTree = 0;
291	#endif /* VBOX_WITH_STATISTICS */
292
293	/* these should be considered for release statistics. */
294	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
295	STAM_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
296	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
297	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
298	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
299	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
300	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
301	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
302	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
303	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
304	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
305	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
306	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
307	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
308	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
309	STAM_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
310
311
312	return VINF_SUCCESS;
313	}
314
315
316
317	/**
318	* Applies relocations to data and code managed by this
319	* component. This function will be called at init and
320	* whenever the VMM need to relocate it self inside the GC.
321	*
322	* @param pVM The VM.
323	*/
324	EMR3DECL(void) EMR3Relocate(PVM pVM)
325	{
326	LogFlow(("EMR3Relocate\n"));
327	if (pVM->em.s.pStatsHC)
328	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
329	}
330
331
332	/**
333	* Reset notification.
334	*
335	* @param pVM
336	*/
337	EMR3DECL(void) EMR3Reset(PVM pVM)
338	{
339	LogFlow(("EMR3Reset: \n"));
340	pVM->em.s.fForceRAW = false;
341	}
342
343
344	/**
345	* Terminates the EM.
346	*
347	* Termination means cleaning up and freeing all resources,
348	* the VM it self is at this point powered off or suspended.
349	*
350	* @returns VBox status code.
351	* @param pVM The VM to operate on.
352	*/
353	EMR3DECL(int) EMR3Term(PVM pVM)
354	{
355	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
356
357	return VINF_SUCCESS;
358	}
359
360
361	/**
362	* Execute state save operation.
363	*
364	* @returns VBox status code.
365	* @param pVM VM Handle.
366	* @param pSSM SSM operation handle.
367	*/
368	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
369	{
370	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
371	}
372
373
374	/**
375	* Execute state load operation.
376	*
377	* @returns VBox status code.
378	* @param pVM VM Handle.
379	* @param pSSM SSM operation handle.
380	* @param u32Version Data layout version.
381	*/
382	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
383	{
384	/*
385	* Validate version.
386	*/
387	if (u32Version != EM_SAVED_STATE_VERSION)
388	{
389	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
390	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
391	}
392
393	/*
394	* Load the saved state.
395	*/
396	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
397	if (VBOX_FAILURE(rc))
398	pVM->em.s.fForceRAW = false;
399
400	Assert(pVM->em.s.pCliStatTree == 0);
401	return rc;
402	}
403
404
405	/**
406	* Enables or disables a set of raw-mode execution modes.
407	*
408	* @returns VINF_SUCCESS on success.
409	* @returns VINF_RESCHEDULE if a rescheduling might be required.
410	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
411	*
412	* @param pVM The VM to operate on.
413	* @param enmMode The execution mode change.
414	* @thread The emulation thread.
415	*/
416	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
417	{
418	switch (enmMode)
419	{
420	case EMRAW_NONE:
421	pVM->fRawR3Enabled = false;
422	pVM->fRawR0Enabled = false;
423	break;
424	case EMRAW_RING3_ENABLE:
425	pVM->fRawR3Enabled = true;
426	break;
427	case EMRAW_RING3_DISABLE:
428	pVM->fRawR3Enabled = false;
429	break;
430	case EMRAW_RING0_ENABLE:
431	pVM->fRawR0Enabled = true;
432	break;
433	case EMRAW_RING0_DISABLE:
434	pVM->fRawR0Enabled = false;
435	break;
436	default:
437	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
438	return VERR_INVALID_PARAMETER;
439	}
440	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
441	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
442	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
443	}
444
445
446	/**
447	* Raise a fatal error.
448	*
449	* Safely terminate the VM with full state report and stuff. This function
450	* will naturally never return.
451	*
452	* @param pVM VM handle.
453	* @param rc VBox status code.
454	*/
455	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
456	{
457	longjmp(pVM->em.s.u.FatalLongJump, rc);
458	AssertReleaseMsgFailed(("longjmp returned!\n"));
459	}
460
461
462	/**
463	* Gets the EM state name.
464	*
465	* @returns pointer to read only state name,
466	* @param enmState The state.
467	*/
468	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
469	{
470	switch (enmState)
471	{
472	case EMSTATE_RAW: return "EMSTATE_RAW";
473	case EMSTATE_HWACC: return "EMSTATE_HWACC";
474	case EMSTATE_REM: return "EMSTATE_REM";
475	case EMSTATE_HALTED: return "EMSTATE_HALTED";
476	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
477	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
478	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
479	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
480	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
481	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
482	default: return "Unknown!";
483	}
484	}
485
486
487	#ifdef VBOX_WITH_STATISTICS
488	/**
489	* Just a braindead function to keep track of cli addresses.
490	* @param pVM VM handle.
491	* @param pInstrGC The EIP of the cli instruction.
492	*/
493	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
494	{
495	PCLISTAT pRec;
496
497	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
498	if (!pRec)
499	{
500	/* New cli instruction; insert into the tree. */
501	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
502	Assert(pRec);
503	if (!pRec)
504	return;
505	pRec->Core.Key = (AVLPVKEY)pInstrGC;
506
507	char szCliStatName[32];
508	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
509	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
510
511	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
512	Assert(fRc); NOREF(fRc);
513	}
514	STAM_COUNTER_INC(&pRec->Counter);
515	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
516	}
517	#endif /* VBOX_WITH_STATISTICS */
518
519
520	/**
521	* Debug loop.
522	*
523	* @returns VBox status code for EM.
524	* @param pVM VM handle.
525	* @param rc Current EM VBox status code..
526	*/
527	static int emR3Debug(PVM pVM, int rc)
528	{
529	for (;;)
530	{
531	Log(("emR3Debug: rc=%Vrc\n", rc));
532	const int rcLast = rc;
533
534	/*
535	* Debug related RC.
536	*/
537	switch (rc)
538	{
539	/*
540	* Single step an instruction.
541	*/
542	case VINF_EM_DBG_STEP:
543	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
544	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
545	\|\| pVM->em.s.fForceRAW /* paranoia */)
546	rc = emR3RawStep(pVM);
547	else
548	{
549	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
550	rc = emR3RemStep(pVM);
551	}
552	break;
553
554	/*
555	* Simple events: stepped, breakpoint, stop/assertion.
556	*/
557	case VINF_EM_DBG_STEPPED:
558	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
559	break;
560
561	case VINF_EM_DBG_BREAKPOINT:
562	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
563	break;
564
565	case VINF_EM_DBG_STOP:
566	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
567	break;
568
569	case VINF_EM_DBG_HYPER_STEPPED:
570	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
571	break;
572
573	case VINF_EM_DBG_HYPER_BREAKPOINT:
574	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
575	break;
576
577	case VINF_EM_DBG_HYPER_ASSERTION:
578	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
579	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
580	break;
581
582	/*
583	* Guru meditation.
584	*/
585	default: /** @todo don't use default for guru, but make special errors code! */
586	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
587	break;
588	}
589
590	/*
591	* Process the result.
592	*/
593	do
594	{
595	switch (rc)
596	{
597	/*
598	* Continue the debugging loop.
599	*/
600	case VINF_EM_DBG_STEP:
601	case VINF_EM_DBG_STOP:
602	case VINF_EM_DBG_STEPPED:
603	case VINF_EM_DBG_BREAKPOINT:
604	case VINF_EM_DBG_HYPER_STEPPED:
605	case VINF_EM_DBG_HYPER_BREAKPOINT:
606	case VINF_EM_DBG_HYPER_ASSERTION:
607	break;
608
609	/*
610	* Resuming execution (in some form) has to be done here if we got
611	* a hypervisor debug event.
612	*/
613	case VINF_SUCCESS:
614	case VINF_EM_RESUME:
615	case VINF_EM_SUSPEND:
616	case VINF_EM_RESCHEDULE:
617	case VINF_EM_RESCHEDULE_RAW:
618	case VINF_EM_RESCHEDULE_REM:
619	case VINF_EM_HALT:
620	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
621	{
622	rc = emR3RawResumeHyper(pVM);
623	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
624	continue;
625	}
626	if (rc == VINF_SUCCESS)
627	rc = VINF_EM_RESCHEDULE;
628	return rc;
629
630	/*
631	* The debugger isn't attached.
632	* We'll simply turn the thing off since that's the easiest thing to do.
633	*/
634	case VERR_DBGF_NOT_ATTACHED:
635	switch (rcLast)
636	{
637	case VINF_EM_DBG_HYPER_ASSERTION:
638	case VINF_EM_DBG_HYPER_STEPPED:
639	case VINF_EM_DBG_HYPER_BREAKPOINT:
640	return rcLast;
641	}
642	return VINF_EM_OFF;
643
644	/*
645	* Status codes terminating the VM in one or another sense.
646	*/
647	case VINF_EM_TERMINATE:
648	case VINF_EM_OFF:
649	case VINF_EM_RESET:
650	case VINF_EM_RAW_STALE_SELECTOR:
651	case VINF_EM_RAW_IRET_TRAP:
652	case VERR_TRPM_PANIC:
653	case VERR_TRPM_DONT_PANIC:
654	case VERR_INTERNAL_ERROR:
655	return rc;
656
657	/*
658	* The rest is unexpected, and will keep us here.
659	*/
660	default:
661	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
662	break;
663	}
664	} while (false);
665	} /* debug for ever */
666	}
667
668
669	/**
670	* Steps recompiled code.
671	*
672	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
673	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
674	*
675	* @param pVM VM handle.
676	*/
677	static int emR3RemStep(PVM pVM)
678	{
679	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
680
681	/*
682	* Switch to REM, step instruction, switch back.
683	*/
684	int rc = REMR3State(pVM);
685	if (VBOX_SUCCESS(rc))
686	{
687	rc = REMR3Step(pVM);
688	REMR3StateBack(pVM);
689	}
690	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
691	return rc;
692	}
693
694	/**
695	* Executes recompiled code.
696	*
697	* This function contains the recompiler version of the inner
698	* execution loop (the outer loop being in EMR3ExecuteVM()).
699	*
700	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
701	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
702	*
703	* @param pVM VM handle.
704	* @param pfFFDone Where to store an indicator telling wheter or not
705	* FFs were done before returning.
706	*
707	*/
708	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
709	{
710	#ifdef LOG_ENABLED
711	PCPUMCTX pCtx = pVM->em.s.pCtx;
712	if ((pCtx->ss & X86_SEL_RPL) == 0)
713	Log(("EMR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
714	#endif
715	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
716
717	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
718	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
719	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
720	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
721	#endif
722
723	/*
724	* Spin till we get a forced action which returns anything but VINF_SUCCESS
725	* or the REM suggests raw-mode execution.
726	*/
727	*pfFFDone = false;
728	bool fInREMState = false;
729	int rc = VINF_SUCCESS;
730	for (;;)
731	{
732	/*
733	* Update REM state if not already in sync.
734	*/
735	if (!fInREMState)
736	{
737	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
738	rc = REMR3State(pVM);
739	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
740	if (VBOX_FAILURE(rc))
741	break;
742	fInREMState = true;
743
744	/*
745	* We might have missed the raising of VMREQ, TIMER and some other
746	* imporant FFs while we were busy switching the state. So, check again.
747	*/
748	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
749	{
750	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
751	goto l_REMDoForcedActions;
752	}
753	}
754
755
756	/*
757	* Execute REM.
758	*/
759	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
760	rc = REMR3Run(pVM);
761	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
762
763
764	/*
765	* Deal with high priority post execution FFs before doing anything else.
766	*/
767	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
768	rc = emR3HighPriorityPostForcedActions(pVM, rc);
769
770	/*
771	* Process the returned status code.
772	* (Try keep this short! Call functions!)
773	*/
774	if (rc != VINF_SUCCESS)
775	{
776	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
777	break;
778	if (rc != VINF_REM_INTERRUPED_FF)
779	{
780	/*
781	* Anything which is not known to us means an internal error
782	* and the termination of the VM!
783	*/
784	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
785	break;
786	}
787	}
788
789
790	/*
791	* Check and execute forced actions.
792	* Sync back the VM state before calling any of these.
793	*/
794	#ifdef VBOX_HIGH_RES_TIMERS_HACK
795	TMTimerPoll(pVM);
796	#endif
797	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_FLUSH_DIRTY_PAGE \| VM_FF_CSAM_SCAN_PAGE)))
798	{
799	l_REMDoForcedActions:
800	if (fInREMState)
801	{
802	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
803	REMR3StateBack(pVM);
804	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
805	fInREMState = false;
806	}
807	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
808	rc = emR3ForcedActions(pVM, rc);
809	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
810	if ( rc != VINF_SUCCESS
811	&& rc != VINF_EM_RESCHEDULE_REM)
812	{
813	*pfFFDone = true;
814	break;
815	}
816	}
817
818	} /* The Inner Loop, recompiled execution mode version. */
819
820
821	/*
822	* Returning. Sync back the VM state if required.
823	*/
824	if (fInREMState)
825	{
826	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
827	REMR3StateBack(pVM);
828	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
829	}
830
831	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
832	return rc;
833	}
834
835
836	/**
837	* Resumes executing hypervisor after a debug event.
838	*
839	* This is kind of special since our current guest state is
840	* potentially out of sync.
841	*
842	* @returns VBox status code.
843	* @param pVM The VM handle.
844	*/
845	static int emR3RawResumeHyper(PVM pVM)
846	{
847	int rc;
848	PCPUMCTX pCtx = pVM->em.s.pCtx;
849	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
850	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
851
852	/*
853	* Resume execution.
854	*/
855	CPUMRawEnter(pVM, NULL);
856	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
857	rc = VMMR3ResumeHyper(pVM);
858	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
859	rc = CPUMRawLeave(pVM, NULL, rc);
860	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
861
862	/*
863	* Deal with the return code.
864	*/
865	rc = emR3HighPriorityPostForcedActions(pVM, rc);
866	rc = emR3RawHandleRC(pVM, pCtx, rc);
867	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
868	return rc;
869	}
870
871
872	/**
873	* Steps rawmode.
874	*
875	* @returns VBox status code.
876	* @param pVM The VM handle.
877	*/
878	static int emR3RawStep(PVM pVM)
879	{
880	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
881	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
882	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
883	int rc;
884	PCPUMCTX pCtx = pVM->em.s.pCtx;
885	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
886	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
887	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
888
889	if (fGuest)
890	{
891	/*
892	* Check vital forced actions, but ignore pending interrupts and timers.
893	*/
894	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
895	{
896	rc = emR3RawForcedActions(pVM, pCtx);
897	if (VBOX_FAILURE(rc))
898	return rc;
899	}
900
901	/*
902	* Set flags for single stepping.
903	*/
904	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
905	}
906	else
907	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
908
909	/*
910	* Single step.
911	* We do not start time or anything, if anything we should just do a few nanoseconds.
912	*/
913	CPUMRawEnter(pVM, NULL);
914	do
915	{
916	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
917	rc = VMMR3ResumeHyper(pVM);
918	else
919	rc = VMMR3RawRunGC(pVM);
920	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
921	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
922	} while ( rc == VINF_SUCCESS
923	\|\| rc == VINF_EM_RAW_INTERRUPT);
924	rc = CPUMRawLeave(pVM, NULL, rc);
925	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
926
927	/*
928	* Make sure the trap flag is cleared.
929	* (Too bad if the guest is trying to single step too.)
930	*/
931	if (fGuest)
932	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
933	else
934	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
935
936	/*
937	* Deal with the return codes.
938	*/
939	rc = emR3HighPriorityPostForcedActions(pVM, rc);
940	rc = emR3RawHandleRC(pVM, pCtx, rc);
941	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
942	return rc;
943	}
944
945
946	/**
947	* Executes one (or perhaps a few more) instruction(s).
948	*
949	* @returns VBox status code suitable for EM.
950	*
951	* @param pVM VM handle.
952	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
953	* instruction and prefix the log output with this text.
954	*/
955	#ifdef LOG_ENABLED
956	static int emR3RawExecuteInstructionWorker(PVM pVM, const char *pszPrefix)
957	#else
958	static int emR3RawExecuteInstructionWorker(PVM pVM)
959	#endif
960	{
961	PCPUMCTX pCtx = pVM->em.s.pCtx;
962	int rc;
963
964	/*
965	*
966	* The simple solution is to use the recompiler.
967	* The better solution is to disassemble the current instruction and
968	* try handle as many as possible without using REM.
969	*
970	*/
971
972	#ifdef LOG_ENABLED
973	/*
974	* Disassemble the instruction if requested.
975	*/
976	if (pszPrefix)
977	{
978	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
979	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
980	}
981	#endif /* LOG_ENABLED */
982
983
984	Assert((pCtx->ss & X86_SEL_RPL) != 1);
985
986	/*
987	* PATM is making life more interesting.
988	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
989	* tell PATM there is a trap in this code and have it take the appropriate actions
990	* to allow us execute the code in REM.
991	*/
992	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
993	{
994	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
995
996	RTGCPTR pNewEip;
997	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
998	switch (rc)
999	{
1000	/*
1001	* It's not very useful to emulate a single instruction and then go back to raw
1002	* mode; just execute the whole block until IF is set again.
1003	*/
1004	case VINF_SUCCESS:
1005	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1006	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1007	pCtx->eip = pNewEip;
1008	Assert(pCtx->eip);
1009
1010	if (pCtx->eflags.Bits.u1IF)
1011	{
1012	/*
1013	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1014	*/
1015	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1016	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1017	}
1018	return VINF_EM_RESCHEDULE_REM;
1019
1020	/*
1021	* One instruction.
1022	*/
1023	case VINF_PATCH_EMULATE_INSTR:
1024	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1025	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1026	pCtx->eip = pNewEip;
1027	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1028
1029	/*
1030	* The patch was disabled, hand it to the REM.
1031	*/
1032	case VERR_PATCH_DISABLED:
1033	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1034	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1035	pCtx->eip = pNewEip;
1036	if (pCtx->eflags.Bits.u1IF)
1037	{
1038	/*
1039	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1040	*/
1041	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1042	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1043	}
1044	return VINF_EM_RESCHEDULE_REM;
1045
1046	/* Force continued patch exection; usually due to write monitored stack. */
1047	case VINF_PATCH_CONTINUE:
1048	return VINF_SUCCESS;
1049
1050	default:
1051	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1052	return VERR_INTERNAL_ERROR;
1053	}
1054	}
1055
1056	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1057	DISCPUSTATE Cpu;
1058	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1059	if (VBOX_SUCCESS(rc))
1060	{
1061	uint32_t size;
1062
1063	switch (Cpu.pCurInstr->opcode)
1064	{
1065	case OP_MOV:
1066	case OP_AND:
1067	case OP_OR:
1068	case OP_XOR:
1069	case OP_POP:
1070	case OP_INC:
1071	case OP_DEC:
1072	case OP_XCHG:
1073	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1074	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1075	if (VBOX_SUCCESS(rc))
1076	{
1077	pCtx->eip += Cpu.opsize;
1078	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1079	return rc;
1080	}
1081	if (rc != VERR_EM_INTERPRETER)
1082	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1083	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1084	break;
1085	}
1086	}
1087	#endif
1088	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1089	rc = REMR3EmulateInstruction(pVM);
1090	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1091
1092	return rc;
1093	}
1094
1095
1096	/**
1097	* Executes one (or perhaps a few more) instruction(s).
1098	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1099	*
1100	* @returns VBox status code suitable for EM.
1101	* @param pVM VM handle.
1102	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1103	* instruction and prefix the log output with this text.
1104	*/
1105	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix)
1106	{
1107	#ifdef LOG_ENABLED
1108	return emR3RawExecuteInstructionWorker(pVM, pszPrefix);
1109	#else
1110	return emR3RawExecuteInstructionWorker(pVM);
1111	#endif
1112	}
1113
1114	/**
1115	* Executes one (or perhaps a few more) IO instruction(s).
1116	*
1117	* @returns VBox status code suitable for EM.
1118	* @param pVM VM handle.
1119	*/
1120	int emR3RawExecuteIOInstruction(PVM pVM)
1121	{
1122	int rc;
1123	PCPUMCTX pCtx = pVM->em.s.pCtx;
1124
1125	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1126
1127	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1128	* as io instructions tend to come in packages of more than one
1129	*/
1130	DISCPUSTATE Cpu;
1131	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1132	if (VBOX_SUCCESS(rc))
1133	{
1134	#ifdef VBOX_WITH_STATISTICS
1135	switch (Cpu.pCurInstr->opcode)
1136	{
1137	case OP_INSB:
1138	case OP_INSWD:
1139	case OP_IN:
1140	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1141	break;
1142
1143	case OP_OUTSB:
1144	case OP_OUTSWD:
1145	case OP_OUT:
1146	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1147	break;
1148	}
1149	#endif
1150
1151	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1152	{
1153	OP_PARAMVAL ParmVal;
1154	int rc;
1155	switch (Cpu.pCurInstr->opcode)
1156	{
1157	case OP_IN:
1158	{
1159	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal, PARAM_SOURCE);
1160	if ( VBOX_FAILURE(rc)
1161	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1162	break;
1163
1164	if (!(Cpu.param1.flags & (USE_REG_GEN8 \| USE_REG_GEN16 \| USE_REG_GEN32)))
1165	break;
1166
1167	/* Make sure port access is allowed */
1168	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1169	if (rc != VINF_SUCCESS)
1170	{
1171	if (rc == VINF_EM_RAW_GUEST_TRAP)
1172	rc = emR3RawGuestTrap(pVM);
1173
1174	return rc;
1175	}
1176
1177	uint32_t u32Value = 0;
1178	switch (Cpu.param1.size)
1179	{
1180	case 1:
1181	Assert(Cpu.param1.base.reg_gen8 == USE_REG_AL);
1182	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint8_t));
1183	if (VBOX_SUCCESS(rc))
1184	{
1185	pCtx->eax = (pCtx->eax & ~0xFF) \| (uint8_t)u32Value;
1186	Log(("EMU: in8 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFF));
1187	pCtx->eip += Cpu.opsize;
1188	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1189	return rc;
1190	}
1191	AssertRC(rc);
1192	break;
1193
1194	case 2:
1195	Assert(Cpu.param1.base.reg_gen16 == USE_REG_AX);
1196	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint16_t));
1197	if (VBOX_SUCCESS(rc))
1198	{
1199	pCtx->eax = (pCtx->eax & ~0xFFFF) \| (uint16_t)u32Value;
1200	Log(("EMU: in16 %x, %x\n", ParmVal.val.val16, pCtx->eax & 0xFFFF));
1201	pCtx->eip += Cpu.opsize;
1202	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1203	return rc;
1204	}
1205	AssertRC(rc);
1206	break;
1207
1208	case 4:
1209	Assert(Cpu.param1.base.reg_gen32 == USE_REG_EAX);
1210	rc = IOMIOPortRead(pVM, ParmVal.val.val16, &u32Value, sizeof(uint32_t));
1211	if (VBOX_SUCCESS(rc))
1212	{
1213	pCtx->eax = u32Value;
1214	Log(("EMU: in32 %x, %x\n", ParmVal.val.val16, pCtx->eax));
1215	pCtx->eip += Cpu.opsize;
1216	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1217	return rc;
1218	}
1219	AssertRC(rc);
1220	break;
1221
1222	default:
1223	AssertMsgFailed(("Unexpected port size %d\n", ParmVal.size));
1224	break;
1225	}
1226	break;
1227	}
1228
1229	case OP_OUT:
1230	{
1231	// it really is the destination, but we're interested in the destination value. hence we specify PARAM_SOURCE (bit of a hack)
1232	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &ParmVal, PARAM_SOURCE);
1233	if ( VBOX_FAILURE(rc)
1234	\|\| ParmVal.type != PARMTYPE_IMMEDIATE)
1235	break;
1236	OP_PARAMVAL ParmVal2;
1237	rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param2, &ParmVal2, PARAM_SOURCE);
1238	if ( VBOX_FAILURE(rc)
1239	\|\| ParmVal2.type != PARMTYPE_IMMEDIATE)
1240	break;
1241
1242	/* Make sure port access is allowed */
1243	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), ParmVal.val.val16, Cpu.param1.size);
1244	if (rc != VINF_SUCCESS)
1245	{
1246	if (rc == VINF_EM_RAW_GUEST_TRAP)
1247	rc = emR3RawGuestTrap(pVM);
1248
1249	return rc;
1250	}
1251
1252	AssertMsg(Cpu.param2.size == ParmVal2.size, ("size %d vs %d\n", Cpu.param2.size, ParmVal2.size));
1253	switch (ParmVal2.size)
1254	{
1255	case 1:
1256	Log(("EMU: out8 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val8));
1257	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val8, sizeof(ParmVal2.val.val8));
1258	if (VBOX_SUCCESS(rc))
1259	{
1260	pCtx->eip += Cpu.opsize;
1261	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1262	return rc;
1263	}
1264	AssertRC(rc);
1265	break;
1266
1267	case 2:
1268	Log(("EMU: out16 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val16));
1269	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val16, sizeof(ParmVal2.val.val16));
1270	if (VBOX_SUCCESS(rc))
1271	{
1272	pCtx->eip += Cpu.opsize;
1273	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1274	return rc;
1275	}
1276	AssertRC(rc);
1277	break;
1278
1279	case 4:
1280	Log(("EMU: out32 %x, %x\n", ParmVal.val.val16, ParmVal2.val.val32));
1281	rc = IOMIOPortWrite(pVM, ParmVal.val.val16, ParmVal2.val.val32, sizeof(ParmVal2.val.val32));
1282	if (VBOX_SUCCESS(rc))
1283	{
1284	pCtx->eip += Cpu.opsize;
1285	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1286	return rc;
1287	}
1288	AssertRC(rc);
1289	break;
1290
1291	default:
1292	AssertMsgFailed(("Unexpected port size %d\n", ParmVal2.size));
1293	break;
1294	}
1295	break;
1296	}
1297
1298	default:
1299	break;
1300	}
1301	}//if(!(Cpu.prefix & (PREFIX_REP\|PREFIX_REPNE))
1302	else if (Cpu.prefix & PREFIX_REP)
1303	{
1304	switch (Cpu.pCurInstr->opcode)
1305	{
1306	case OP_INSB:
1307	case OP_INSWD:
1308	{
1309	/*
1310	* Do not optimize the destination address decrement case (not worth the effort)
1311	* and likewise for 16 bit address size (would need to use and update only cx/di).
1312	*/
1313	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1314	break;
1315	/*
1316	* Get port number and transfer count directly from the registers (no need to bother the
1317	* disassembler). And get the I/O register size from the opcode / prefix.
1318	*/
1319	uint32_t uPort = pCtx->edx & 0xffff;
1320	RTGCUINTREG cTransfers = pCtx->ecx;
1321	unsigned cbUnit;
1322	if (Cpu.pCurInstr->opcode == OP_INSB)
1323	cbUnit = 1;
1324	else
1325	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1326
1327	RTGCPTR GCPtrDst = pCtx->edi;
1328	/* Access verification first; we can't recover from traps inside this instruction, as the port read cannot be repeated. */
1329	rc = PGMVerifyAccess(pVM, GCPtrDst, cTransfers * cbUnit,
1330	X86_PTE_RW \| (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1331	if (rc != VINF_SUCCESS)
1332	{
1333	Log(("EMU: rep ins%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1334	break;
1335	}
1336
1337	Log(("EMU: rep ins%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1338
1339	/* Make sure port access is allowed */
1340	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1341	if (rc != VINF_SUCCESS)
1342	{
1343	if (rc == VINF_EM_RAW_GUEST_TRAP)
1344	rc = emR3RawGuestTrap(pVM);
1345
1346	return rc;
1347	}
1348
1349	/*
1350	* If the device supports string transfers, ask it to do as
1351	* much as it wants. The rest is done with single-word transfers.
1352	*/
1353	rc = IOMIOPortReadString(pVM, uPort, &GCPtrDst, &cTransfers, cbUnit);
1354	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1355
1356	while (cTransfers && rc == VINF_SUCCESS)
1357	{
1358	uint32_t u32Value;
1359	rc = IOMIOPortRead(pVM, uPort, &u32Value, cbUnit);
1360	AssertRC(rc);
1361	int rc2 = PGMPhysWriteGCPtrDirty(pVM, GCPtrDst, &u32Value, cbUnit);
1362	AssertRC(rc2);
1363	GCPtrDst += cbUnit;
1364	cTransfers--;
1365	}
1366	pCtx->edi += (pCtx->ecx - cTransfers) * cbUnit;
1367	pCtx->ecx = cTransfers;
1368	if (!cTransfers && VBOX_SUCCESS(rc))
1369	pCtx->eip += Cpu.opsize;
1370	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1371	return rc;
1372	}
1373	case OP_OUTSB:
1374	case OP_OUTSWD:
1375	{
1376	/*
1377	* Do not optimize the source address decrement case (not worth the effort)
1378	* and likewise for 16 bit address size (would need to use and update only cx/si).
1379	*/
1380	if (pCtx->eflags.Bits.u1DF \|\| Cpu.addrmode != CPUMODE_32BIT)
1381	break;
1382	/*
1383	* Get port number and transfer count directly from the registers (no need to bother the
1384	* disassembler). And get the I/O register size from the opcode / prefix.
1385	*/
1386	uint32_t uPort = pCtx->edx & 0xffff;
1387	RTGCUINTREG cTransfers = pCtx->ecx;
1388	unsigned cbUnit;
1389	if (Cpu.pCurInstr->opcode == OP_OUTSB)
1390	cbUnit = 1;
1391	else
1392	cbUnit = Cpu.opmode == CPUMODE_32BIT ? 4 : 2;
1393
1394	RTGCPTR GCPtrSrc = pCtx->esi;
1395	/* Access verification first; we currently can't recover properly from traps inside this instruction */
1396	rc = PGMVerifyAccess(pVM, GCPtrSrc, cTransfers * cbUnit, (((pCtx->ss & X86_SEL_RPL) == 3) ? X86_PTE_US : 0));
1397	if (rc != VINF_SUCCESS)
1398	{
1399	Log(("EMU: rep outs%d will generate a trap -> fallback, rc=%d\n", cbUnit * 8, rc));
1400	break;
1401	}
1402
1403	Log(("EMU: rep outs%d port %#x count %d\n", cbUnit * 8, uPort, cTransfers));
1404
1405	/* Make sure port access is allowed */
1406	rc = IOMInterpretCheckPortIOAccess(pVM, CPUMCTX2CORE(pCtx), uPort, cbUnit);
1407	if (rc != VINF_SUCCESS)
1408	{
1409	if (rc == VINF_EM_RAW_GUEST_TRAP)
1410	rc = emR3RawGuestTrap(pVM);
1411
1412	return rc;
1413	}
1414
1415	/*
1416	* If the device supports string transfers, ask it to do as
1417	* much as it wants. The rest is done with single-word transfers.
1418	*/
1419	rc = IOMIOPortWriteString(pVM, uPort, &GCPtrSrc, &cTransfers, cbUnit);
1420	AssertRC(rc); Assert(cTransfers <= pCtx->ecx);
1421
1422	while (cTransfers && rc == VINF_SUCCESS)
1423	{
1424	uint32_t u32Value;
1425	rc = PGMPhysReadGCPtr(pVM, &u32Value, GCPtrSrc, cbUnit);
1426	Assert(rc == VINF_SUCCESS);
1427	rc = IOMIOPortWrite(pVM, uPort, u32Value, cbUnit);
1428	AssertRC(rc);
1429	GCPtrSrc += cbUnit;
1430	cTransfers--;
1431	}
1432	pCtx->esi += (pCtx->ecx - cTransfers) * cbUnit;
1433	pCtx->ecx = cTransfers;
1434	if (!cTransfers && VBOX_SUCCESS(rc))
1435	pCtx->eip += Cpu.opsize;
1436	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1437	return rc;
1438	}
1439	}
1440	}//if(Cpu.prefix & PREFIX_REP)
1441	}
1442
1443	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1444	return emR3RawExecuteInstruction(pVM, "IO: ");
1445	}
1446
1447
1448	/**
1449	* Handle a guest context trap.
1450	*
1451	* @returns VBox status code suitable for EM.
1452	* @param pVM VM handle.
1453	*/
1454	static int emR3RawGuestTrap(PVM pVM)
1455	{
1456	PCPUMCTX pCtx = pVM->em.s.pCtx;
1457
1458	/*
1459	* Get the trap info.
1460	*/
1461	uint8_t u8TrapNo;
1462	bool fSoftwareInterrupt;
1463	RTGCUINT uErrorCode;
1464	RTGCUINTPTR uCR2;
1465	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1466	if (VBOX_FAILURE(rc))
1467	{
1468	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1469	return rc;
1470	}
1471
1472	/* Traps can be directly forwarded in hardware accelerated mode. */
1473	if (HWACCMR3IsActive(pVM))
1474	{
1475	#ifdef LOGGING_ENABLED
1476	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1477	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1478	#endif
1479	return VINF_EM_RESCHEDULE_HWACC;
1480	}
1481
1482	/** Scan kernel code that traps; we might not get another chance. */
1483	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1484	&& pCtx->eflags.Bits.u1VM == 0)
1485	{
1486	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1487	CSAMR3CheckEIP(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid));
1488	}
1489
1490	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1491	{
1492	DISCPUSTATE cpu;
1493
1494	/* If MONITOR & MWAIT are supported, then interpret them here. */
1495	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1496	if ( VBOX_SUCCESS(rc)
1497	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1498	{
1499	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1500
1501	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1502
1503	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1504	{
1505	rc = TRPMResetTrap(pVM);
1506	AssertRC(rc);
1507
1508	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1509	if (VBOX_SUCCESS(rc))
1510	{
1511	pCtx->eip += cpu.opsize;
1512	return rc;
1513	}
1514	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1515	}
1516	}
1517	}
1518	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1519	{
1520	DISCPUSTATE cpu;
1521
1522	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1523	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1524	{
1525	/*
1526	* We should really check the TSS for the IO bitmap, but it's not like this
1527	* lazy approach really makes things worse.
1528	*/
1529	rc = TRPMResetTrap(pVM);
1530	AssertRC(rc);
1531	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1532	}
1533	}
1534
1535	#ifdef LOG_ENABLED
1536	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1537	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1538
1539	/* Get guest page information. */
1540	uint64_t fFlags = 0;
1541	RTGCPHYS GCPhys = 0;
1542	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1543	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1544	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, fSoftwareInterrupt ? " software" : "", GCPhys, fFlags,
1545	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1546	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1547	#endif
1548
1549	/*
1550	* #PG has CR2.
1551	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1552	*/
1553	if (u8TrapNo == 14 /* #PG */)
1554	pCtx->cr2 = uCR2;
1555
1556	return VINF_EM_RESCHEDULE_REM;
1557	}
1558
1559
1560	/**
1561	* Handle a ring switch trap.
1562	* Need to do statistics and to install patches. The result is going to REM.
1563	*
1564	* @returns VBox status code suitable for EM.
1565	* @param pVM VM handle.
1566	*/
1567	int emR3RawRingSwitch(PVM pVM)
1568	{
1569	int rc;
1570	DISCPUSTATE Cpu;
1571	PCPUMCTX pCtx = pVM->em.s.pCtx;
1572
1573	/*
1574	* sysenter, syscall & callgate
1575	*/
1576	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1577	if (VBOX_SUCCESS(rc))
1578	{
1579	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1580	{
1581	if (pCtx->SysEnter.cs != 0)
1582	{
1583	rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1584	if (VBOX_SUCCESS(rc))
1585	{
1586	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1587	return VINF_EM_RESCHEDULE_RAW;
1588	}
1589	}
1590	}
1591
1592	#ifdef VBOX_WITH_STATISTICS
1593	switch (Cpu.pCurInstr->opcode)
1594	{
1595	case OP_SYSENTER:
1596	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1597	break;
1598	case OP_SYSEXIT:
1599	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1600	break;
1601	case OP_SYSCALL:
1602	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1603	break;
1604	case OP_SYSRET:
1605	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1606	break;
1607	}
1608	#endif
1609	}
1610	else
1611	AssertRC(rc);
1612
1613	/* go to the REM to emulate a single instruction */
1614	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1615	}
1616
1617	/**
1618	* Handle a trap (#PF or #GP) in patch code
1619	*
1620	* @returns VBox status code suitable for EM.
1621	* @param pVM VM handle.
1622	* @param pCtx CPU context
1623	* @param gcret GC return code
1624	*/
1625	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1626	{
1627	uint8_t u8TrapNo;
1628	int rc;
1629	bool fSoftwareInterrupt;
1630	RTGCUINT uErrorCode;
1631	RTGCUINTPTR uCR2;
1632
1633	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1634
1635	if (gcret == VINF_PATM_PATCH_INT3)
1636	{
1637	u8TrapNo = 3;
1638	uCR2 = 0;
1639	uErrorCode = 0;
1640	}
1641	else
1642	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1643	{
1644	/* No active trap in this case. Kind of ugly. */
1645	u8TrapNo = X86_XCPT_GP;
1646	uCR2 = 0;
1647	uErrorCode = 0;
1648	}
1649	else
1650	{
1651	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &fSoftwareInterrupt, &uErrorCode, &uCR2);
1652	if (VBOX_FAILURE(rc))
1653	{
1654	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1655	return rc;
1656	}
1657	/* Reset the trap as we'll execute the original instruction again. */
1658	TRPMResetTrap(pVM);
1659	}
1660
1661	/*
1662	* Deal with traps inside patch code.
1663	* (This code won't run outside GC.)
1664	*/
1665	if (u8TrapNo != 1)
1666	{
1667	#ifdef LOG_ENABLED
1668	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1669	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1670	#endif
1671	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1672	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1673
1674	RTGCPTR pNewEip;
1675	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1676	switch (rc)
1677	{
1678	/*
1679	* Execute the faulting instruction.
1680	*/
1681	case VINF_SUCCESS:
1682	{
1683	/** @todo execute a whole block */
1684	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1685	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1686	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1687
1688	pCtx->eip = pNewEip;
1689	AssertRelease(pCtx->eip);
1690
1691	if (pCtx->eflags.Bits.u1IF)
1692	{
1693	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1694	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1695	*/
1696	if ( u8TrapNo == X86_XCPT_GP
1697	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1698	{
1699	/** @todo move to PATMR3HandleTrap */
1700	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1701	PATMR3RemovePatch(pVM, pCtx->eip);
1702	}
1703
1704	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1705	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1706
1707	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1708	/* Interrupts are enabled; just go back to the original instruction.
1709	return VINF_SUCCESS; */
1710	}
1711	return VINF_EM_RESCHEDULE_REM;
1712	}
1713
1714	/*
1715	* One instruction.
1716	*/
1717	case VINF_PATCH_EMULATE_INSTR:
1718	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1719	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1720	pCtx->eip = pNewEip;
1721	AssertRelease(pCtx->eip);
1722	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1723
1724	/*
1725	* The patch was disabled, hand it to the REM.
1726	*/
1727	case VERR_PATCH_DISABLED:
1728	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1729	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1730	pCtx->eip = pNewEip;
1731	AssertRelease(pCtx->eip);
1732
1733	if (pCtx->eflags.Bits.u1IF)
1734	{
1735	/*
1736	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1737	*/
1738	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1739	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1740	}
1741	return VINF_EM_RESCHEDULE_REM;
1742
1743	/* Force continued patch exection; usually due to write monitored stack. */
1744	case VINF_PATCH_CONTINUE:
1745	return VINF_SUCCESS;
1746
1747	/*
1748	* Anything else is fatal.
1749	*/
1750	default:
1751	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1752	return VERR_INTERNAL_ERROR;
1753	}
1754	}
1755	return VINF_SUCCESS;
1756	}
1757
1758
1759	/**
1760	* Handle a privileged instruction.
1761	*
1762	* @returns VBox status code suitable for EM.
1763	* @param pVM VM handle.
1764	*/
1765	int emR3RawPrivileged(PVM pVM)
1766	{
1767	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1768	PCPUMCTX pCtx = pVM->em.s.pCtx;
1769
1770	if (PATMIsEnabled(pVM))
1771	{
1772	/*
1773	* Check if in patch code.
1774	*/
1775	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1776	{
1777	#ifdef LOG_ENABLED
1778	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1779	#endif
1780	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1781	return VERR_EM_RAW_PATCH_CONFLICT;
1782	}
1783	if ( (pCtx->ss & X86_SEL_RPL) == 0
1784	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1785	{
1786	int rc = PATMR3InstallPatch(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1787	if (VBOX_SUCCESS(rc))
1788	{
1789	#ifdef LOG_ENABLED
1790	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1791	#endif
1792	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1793	return VINF_SUCCESS;
1794	}
1795	}
1796	}
1797
1798	#ifdef LOG_ENABLED
1799	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1800	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1801	#endif
1802
1803	/*
1804	* Instruction statistics and logging.
1805	*/
1806	DISCPUSTATE Cpu;
1807	int rc;
1808
1809	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1810	if (VBOX_SUCCESS(rc))
1811	{
1812	#ifdef VBOX_WITH_STATISTICS
1813	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1814	switch (Cpu.pCurInstr->opcode)
1815	{
1816	case OP_INVLPG:
1817	STAM_COUNTER_INC(&pStats->StatInvlpg);
1818	break;
1819	case OP_IRET:
1820	STAM_COUNTER_INC(&pStats->StatIret);
1821	break;
1822	case OP_CLI:
1823	STAM_COUNTER_INC(&pStats->StatCli);
1824	emR3RecordCli(pVM, pCtx->eip);
1825	break;
1826	case OP_STI:
1827	STAM_COUNTER_INC(&pStats->StatSti);
1828	break;
1829	case OP_INSB:
1830	case OP_INSWD:
1831	case OP_IN:
1832	case OP_OUTSB:
1833	case OP_OUTSWD:
1834	case OP_OUT:
1835	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1836	break;
1837
1838	case OP_MOV_CR:
1839	if (Cpu.param1.flags & USE_REG_GEN32)
1840	{
1841	//read
1842	Assert(Cpu.param2.flags & USE_REG_CR);
1843	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1844	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1845	}
1846	else
1847	{
1848	//write
1849	Assert(Cpu.param1.flags & USE_REG_CR);
1850	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1851	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1852	}
1853	break;
1854
1855	case OP_MOV_DR:
1856	STAM_COUNTER_INC(&pStats->StatMovDRx);
1857	break;
1858	case OP_LLDT:
1859	STAM_COUNTER_INC(&pStats->StatMovLldt);
1860	break;
1861	case OP_LIDT:
1862	STAM_COUNTER_INC(&pStats->StatMovLidt);
1863	break;
1864	case OP_LGDT:
1865	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1866	break;
1867	case OP_SYSENTER:
1868	STAM_COUNTER_INC(&pStats->StatSysEnter);
1869	break;
1870	case OP_SYSEXIT:
1871	STAM_COUNTER_INC(&pStats->StatSysExit);
1872	break;
1873	case OP_SYSCALL:
1874	STAM_COUNTER_INC(&pStats->StatSysCall);
1875	break;
1876	case OP_SYSRET:
1877	STAM_COUNTER_INC(&pStats->StatSysRet);
1878	break;
1879	case OP_HLT:
1880	STAM_COUNTER_INC(&pStats->StatHlt);
1881	break;
1882	default:
1883	STAM_COUNTER_INC(&pStats->StatMisc);
1884	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1885	break;
1886	}
1887	#endif
1888	if ( (pCtx->ss & X86_SEL_RPL) == 0
1889	&& SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid))
1890	{
1891	uint32_t size;
1892
1893	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1894	switch (Cpu.pCurInstr->opcode)
1895	{
1896	case OP_CLI:
1897	pCtx->eflags.u32 &= ~X86_EFL_IF;
1898	Assert(Cpu.opsize == 1);
1899	pCtx->eip += Cpu.opsize;
1900	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1901	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1902
1903	case OP_STI:
1904	pCtx->eflags.u32 \|= X86_EFL_IF;
1905	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1906	Assert(Cpu.opsize == 1);
1907	pCtx->eip += Cpu.opsize;
1908	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1909	return VINF_SUCCESS;
1910
1911	case OP_HLT:
1912	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1913	{
1914	PATMTRANSSTATE enmState;
1915	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1916
1917	if (enmState == PATMTRANS_OVERWRITTEN)
1918	{
1919	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1920	Assert(rc == VERR_PATCH_DISABLED);
1921	/* Conflict detected, patch disabled */
1922	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1923
1924	enmState = PATMTRANS_SAFE;
1925	}
1926
1927	/* The translation had better be successful. Otherwise we can't recover. */
1928	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1929	if (enmState != PATMTRANS_OVERWRITTEN)
1930	pCtx->eip = pOrgInstrGC;
1931	}
1932	/* no break; we could just return VINF_EM_HALT here */
1933
1934	case OP_MOV_CR:
1935	case OP_MOV_DR:
1936	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1937	if (VBOX_SUCCESS(rc))
1938	{
1939	pCtx->eip += Cpu.opsize;
1940	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1941
1942	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1943	&& Cpu.param1.flags == USE_REG_CR /* write */
1944	)
1945	{
1946	/* Reschedule is necessary as the execution/paging mode might have changed. */
1947	return VINF_EM_RESCHEDULE;
1948	}
1949	return rc; /* can return VINF_EM_HALT as well. */
1950	}
1951	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1952	break; /* fall back to the recompiler */
1953	}
1954	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1955	}
1956	}
1957
1958	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1959	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1960
1961	return emR3RawExecuteInstruction(pVM, "PRIV");
1962	}
1963
1964
1965	/**
1966	* Update the forced rawmode execution modifier.
1967	*
1968	* This function is called when we're returning from the raw-mode loop(s). If we're
1969	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1970	* if not in patch code, the flag will be cleared.
1971	*
1972	* We should never interrupt patch code while it's being executed. Cli patches can
1973	* contain big code blocks, but they are always executed with IF=0. Other patches
1974	* replace single instructions and should be atomic.
1975	*
1976	* @returns Updated rc.
1977	*
1978	* @param pVM The VM handle.
1979	* @param pCtx The guest CPU context.
1980	* @param rc The result code.
1981	*/
1982	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1983	{
1984	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1985	{
1986	/* ignore reschedule attempts. */
1987	switch (rc)
1988	{
1989	case VINF_EM_RESCHEDULE:
1990	case VINF_EM_RESCHEDULE_REM:
1991	rc = VINF_SUCCESS;
1992	break;
1993	}
1994	pVM->em.s.fForceRAW = true;
1995	}
1996	else
1997	pVM->em.s.fForceRAW = false;
1998	return rc;
1999	}
2000
2001
2002	/**
2003	* Process a subset of the raw-mode return code.
2004	*
2005	* Since we have to share this with raw-mode single stepping, this inline
2006	* function has been created to avoid code duplication.
2007	*
2008	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2009	* @returns VBox status code to return to the EM main loop.
2010	*
2011	* @param pVM The VM handle
2012	* @param rc The return code.
2013	* @param pCtx The guest cpu context.
2014	*/
2015	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2016	{
2017	switch (rc)
2018	{
2019	/*
2020	* Common & simple ones.
2021	*/
2022	case VINF_SUCCESS:
2023	break;
2024	case VINF_EM_RESCHEDULE_RAW:
2025	case VINF_EM_RESCHEDULE_HWACC:
2026	case VINF_EM_RAW_INTERRUPT:
2027	case VINF_EM_RAW_TO_R3:
2028	case VINF_EM_RAW_TIMER_PENDING:
2029	case VINF_EM_PENDING_REQUEST:
2030	rc = VINF_SUCCESS;
2031	break;
2032
2033	/*
2034	* Privileged instruction.
2035	*/
2036	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2037	case VINF_PATM_PATCH_TRAP_GP:
2038	rc = emR3RawPrivileged(pVM);
2039	break;
2040
2041	/*
2042	* Got a trap which needs dispatching.
2043	*/
2044	case VINF_EM_RAW_GUEST_TRAP:
2045	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2046	{
2047	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2048	rc = VERR_EM_RAW_PATCH_CONFLICT;
2049	break;
2050	}
2051	rc = emR3RawGuestTrap(pVM);
2052	break;
2053
2054	/*
2055	* Trap in patch code.
2056	*/
2057	case VINF_PATM_PATCH_TRAP_PF:
2058	case VINF_PATM_PATCH_INT3:
2059	rc = emR3PatchTrap(pVM, pCtx, rc);
2060	break;
2061
2062	case VINF_PATM_DUPLICATE_FUNCTION:
2063	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2064	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2065	AssertRC(rc);
2066	rc = VINF_SUCCESS;
2067	break;
2068
2069	case VINF_PATM_CHECK_PATCH_PAGE:
2070	rc = PATMR3HandleMonitoredPage(pVM);
2071	AssertRC(rc);
2072	rc = VINF_SUCCESS;
2073	break;
2074
2075	/*
2076	* Patch manager.
2077	*/
2078	case VERR_EM_RAW_PATCH_CONFLICT:
2079	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2080	break;
2081
2082	/*
2083	* Memory mapped I/O access - attempt to patch the instruction
2084	*/
2085	case VINF_PATM_HC_MMIO_PATCH_READ:
2086	rc = PATMR3InstallPatch(pVM, pCtx->eip, PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2087	if (VBOX_FAILURE(rc))
2088	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2089	break;
2090
2091	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2092	AssertFailed(); /* not yet implemented. */
2093	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2094	break;
2095
2096	/*
2097	* Conflict or out of page tables.
2098	*
2099	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2100	* do here is to execute the pending forced actions.
2101	*/
2102	case VINF_PGM_SYNC_CR3:
2103	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2104	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2105	rc = VINF_SUCCESS;
2106	break;
2107
2108	/*
2109	* Paging mode change.
2110	*/
2111	case VINF_PGM_CHANGE_MODE:
2112	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2113	if (VBOX_SUCCESS(rc))
2114	rc = VINF_EM_RESCHEDULE;
2115	break;
2116
2117	/*
2118	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2119	*/
2120	case VINF_CSAM_PENDING_ACTION:
2121	rc = VINF_SUCCESS;
2122	break;
2123
2124	/*
2125	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2126	*/
2127	case VINF_EM_RAW_INTERRUPT_PENDING:
2128	{
2129	uint8_t u8Interrupt;
2130
2131	Assert(TRPMHasTrap(pVM));
2132	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2133
2134	if (TRPMHasTrap(pVM))
2135	{
2136	u8Interrupt = TRPMGetTrapNo(pVM);
2137
2138	/* If the guest gate is marked dirty, then we will check again if we can patch it. */
2139	if (TRPMR3IsGuestTrapHandlerDirty(pVM, u8Interrupt))
2140	{
2141	Assert(TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER);
2142	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2143	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2144	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2145	}
2146	}
2147	rc = VINF_EM_RESCHEDULE_REM;
2148	break;
2149	}
2150
2151	case VINF_EM_RAW_RING_SWITCH_INT:
2152	rc = VINF_EM_RESCHEDULE_REM;
2153	break;
2154
2155	/*
2156	* Other ring switch types.
2157	*/
2158	case VINF_EM_RAW_RING_SWITCH:
2159	rc = emR3RawRingSwitch(pVM);
2160	break;
2161
2162	/*
2163	* REMGCNotifyInvalidatePage() failed because of overflow.
2164	*/
2165	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2166	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2167	REMR3ReplayInvalidatedPages(pVM);
2168	break;
2169
2170	/*
2171	* I/O Port access - emulate the instruction.
2172	*/
2173	case VINF_IOM_HC_IOPORT_READ:
2174	case VINF_IOM_HC_IOPORT_WRITE:
2175	case VINF_IOM_HC_IOPORT_READWRITE:
2176	rc = emR3RawExecuteIOInstruction(pVM);
2177	break;
2178
2179	/*
2180	* Memory mapped I/O access - emulate the instruction.
2181	*/
2182	case VINF_IOM_HC_MMIO_READ:
2183	case VINF_IOM_HC_MMIO_WRITE:
2184	case VINF_IOM_HC_MMIO_READ_WRITE:
2185	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2186	break;
2187
2188	/*
2189	* Execute instruction.
2190	*/
2191	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2192	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2193	break;
2194	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2195	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2196	break;
2197	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2198	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2199	break;
2200	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2201	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2202	break;
2203	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2204	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2205	break;
2206
2207	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2208	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2209	rc = emR3RawPrivileged(pVM);
2210	break;
2211
2212	case VINF_EM_RAW_EMULATE_INSTR:
2213	case VINF_PATCH_EMULATE_INSTR:
2214	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2215	break;
2216
2217	/*
2218	* Stale selector and iret traps => REM.
2219	*/
2220	case VINF_EM_RAW_STALE_SELECTOR:
2221	case VINF_EM_RAW_IRET_TRAP:
2222	/* We will not go to the recompiler if EIP points to patch code. */
2223	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2224	{
2225	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2226	}
2227	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2228	rc = VINF_EM_RESCHEDULE_REM;
2229	break;
2230
2231	/*
2232	* Up a level.
2233	*/
2234	case VINF_EM_TERMINATE:
2235	case VINF_EM_OFF:
2236	case VINF_EM_RESET:
2237	case VINF_EM_SUSPEND:
2238	case VINF_EM_HALT:
2239	case VINF_EM_RESUME:
2240	case VINF_EM_RESCHEDULE:
2241	case VINF_EM_RESCHEDULE_REM:
2242	break;
2243
2244	/*
2245	* Up a level and invoke the debugger.
2246	*/
2247	case VINF_EM_DBG_STEPPED:
2248	case VINF_EM_DBG_BREAKPOINT:
2249	case VINF_EM_DBG_STEP:
2250	case VINF_EM_DBG_HYPER_ASSERTION:
2251	case VINF_EM_DBG_HYPER_BREAKPOINT:
2252	case VINF_EM_DBG_HYPER_STEPPED:
2253	case VINF_EM_DBG_STOP:
2254	break;
2255
2256	/*
2257	* Up a level, dump and debug.
2258	*/
2259	case VERR_TRPM_DONT_PANIC:
2260	case VERR_TRPM_PANIC:
2261	break;
2262
2263	/*
2264	* Anything which is not known to us means an internal error
2265	* and the termination of the VM!
2266	*/
2267	default:
2268	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2269	break;
2270	}
2271	return rc;
2272	}
2273
2274
2275	/**
2276	* Process raw-mode specific forced actions.
2277	*
2278	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2279	*
2280	* @returns VBox status code.
2281	* Only the normal success/failure stuff, no VINF_EM_*.
2282	* @param pVM The VM handle.
2283	* @param pCtx The guest CPUM register context.
2284	*/
2285	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2286	{
2287	/*
2288	* Note that the order is vitally important!
2289	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2290	*/
2291
2292
2293	/*
2294	* Sync selector tables.
2295	*/
2296	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2297	{
2298	int rc = SELMR3UpdateFromCPUM(pVM);
2299	if (VBOX_FAILURE(rc))
2300	return rc;
2301	}
2302
2303	/*
2304	* Sync IDT.
2305	*/
2306	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2307	{
2308	int rc = TRPMR3SyncIDT(pVM);
2309	if (VBOX_FAILURE(rc))
2310	return rc;
2311	}
2312
2313	/*
2314	* Sync TSS.
2315	*/
2316	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2317	{
2318	int rc = SELMR3SyncTSS(pVM);
2319	if (VBOX_FAILURE(rc))
2320	return rc;
2321	}
2322
2323	/*
2324	* Sync page directory.
2325	*/
2326	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2327	{
2328	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2329	if (VBOX_FAILURE(rc))
2330	return rc;
2331
2332	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2333
2334	/* Prefetch pages for EIP and ESP */
2335	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2336	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2337	if (rc == VINF_SUCCESS)
2338	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2339	if (rc != VINF_SUCCESS)
2340	{
2341	if (rc != VINF_PGM_SYNC_CR3)
2342	return rc;
2343	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2344	if (VBOX_FAILURE(rc))
2345	return rc;
2346	}
2347	/** @todo maybe prefetch the supervisor stack page as well */
2348	}
2349
2350	return VINF_SUCCESS;
2351	}
2352
2353
2354	/**
2355	* Executes raw code.
2356	*
2357	* This function contains the raw-mode version of the inner
2358	* execution loop (the outer loop being in EMR3ExecuteVM()).
2359	*
2360	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2361	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2362	*
2363	* @param pVM VM handle.
2364	* @param pfFFDone Where to store an indicator telling whether or not
2365	* FFs were done before returning.
2366	*/
2367	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2368	{
2369	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2370
2371	int rc = VERR_INTERNAL_ERROR;
2372	PCPUMCTX pCtx = pVM->em.s.pCtx;
2373	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2374	pVM->em.s.fForceRAW = false;
2375	*pfFFDone = false;
2376
2377
2378	/*
2379	*
2380	* Spin till we get a forced action or raw mode status code resulting in
2381	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2382	*
2383	*/
2384	for (;;)
2385	{
2386	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2387
2388	/*
2389	* Check various preconditions.
2390	*/
2391	#ifdef VBOX_STRICT
2392	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2393	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2394	Assert((pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2395	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2396	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2397	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2398	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2399	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2400	{
2401	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2402	return VERR_INTERNAL_ERROR;
2403	}
2404	#endif /* VBOX_STRICT */
2405
2406	/*
2407	* Process high priority pre-execution raw-mode FFs.
2408	*/
2409	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2410	{
2411	rc = emR3RawForcedActions(pVM, pCtx);
2412	if (VBOX_FAILURE(rc))
2413	break;
2414	}
2415
2416	/*
2417	* If we're going to execute ring-0 code, the guest state needs to
2418	* be modified a bit and some of the state components (IF, SS/CS RPL,
2419	* and perhaps EIP) needs to be stored with PATM.
2420	*/
2421	rc = CPUMRawEnter(pVM, NULL);
2422	if (rc != VINF_SUCCESS)
2423	{
2424	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2425	break;
2426	}
2427
2428	/*
2429	* Scan code before executing it. Don't bother with user mode or V86 code
2430	*/
2431	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2432	&& pCtx->eflags.Bits.u1VM == 0
2433	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2434	{
2435	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2436	CSAMR3CheckEIP(pVM, pCtx->eip, SELMIsSelector32Bit(pVM, pCtx->cs, &pCtx->csHid));
2437	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2438	}
2439
2440	#ifdef LOG_ENABLED
2441	/*
2442	* Log important stuff before entering GC.
2443	*/
2444	bool fSingleStep = false;
2445	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2446	if ((pCtx->ss & X86_SEL_RPL) == 1 && !fSingleStep)
2447	{
2448	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2449	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2450	}
2451	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2452	Log(("RV86: %08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2453	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2454	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2455	#endif /* LOG_ENABLED */
2456
2457
2458
2459	/*
2460	* Execute the code.
2461	*/
2462	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2463	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2464	VMMR3Unlock(pVM);
2465	rc = VMMR3RawRunGC(pVM);
2466	VMMR3Lock(pVM);
2467	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2468	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2469
2470	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2471	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2472
2473
2474	/*
2475	* Restore the real CPU state and deal with high priority post
2476	* execution FFs before doing anything else.
2477	*/
2478	rc = CPUMRawLeave(pVM, NULL, rc);
2479	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2480	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2481	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2482
2483	#ifdef PGM_CACHE_VERY_STRICT
2484	/*
2485	* Page manager cache checks.
2486	*/
2487	if ( rc == VINF_EM_RAW_INTERRUPT
2488	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2489	\|\| rc == VINF_IOM_HC_IOPORT_READ
2490	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2491	\|\| rc == VINF_IOM_HC_IOPORT_READWRITE
2492	//\|\| rc == VINF_PATM_PATCH_INT3
2493	)
2494	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2495	#endif
2496
2497	#ifdef VBOX_STRICT
2498	/*
2499	* Assert TSS consistency & rc vs patch code.
2500	*/
2501	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2502	&& EMIsRawRing0Enabled(pVM))
2503	SELMR3CheckTSS(pVM);
2504	switch (rc)
2505	{
2506	case VINF_SUCCESS:
2507	case VINF_EM_RAW_INTERRUPT:
2508	case VINF_PATM_PATCH_TRAP_PF:
2509	case VINF_PATM_PATCH_TRAP_GP:
2510	case VINF_PATM_PATCH_INT3:
2511	case VINF_PATM_CHECK_PATCH_PAGE:
2512	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2513	case VINF_EM_RAW_GUEST_TRAP:
2514	case VINF_EM_RESCHEDULE_RAW:
2515	break;
2516
2517	default:
2518	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2519	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2520	break;
2521	}
2522	/*
2523	* Let's go paranoid!
2524	*/
2525	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2526	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2527	{
2528	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2529	return VERR_INTERNAL_ERROR;
2530	}
2531	#endif /* VBOX_STRICT */
2532
2533	/*
2534	* Process the returned status code.
2535	*/
2536	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2537	{
2538	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2539	break;
2540	}
2541	rc = emR3RawHandleRC(pVM, pCtx, rc);
2542	if (rc != VINF_SUCCESS)
2543	{
2544	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2545	if (rc != VINF_SUCCESS)
2546	{
2547	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2548	break;
2549	}
2550	}
2551
2552	/*
2553	* Check and execute forced actions.
2554	*/
2555	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2556	TMTimerPoll(pVM);
2557	#endif
2558	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2559	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2560	{
2561	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2562
2563	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2564	rc = emR3ForcedActions(pVM, rc);
2565	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2566	if ( rc != VINF_SUCCESS
2567	&& rc != VINF_EM_RESCHEDULE_RAW)
2568	{
2569	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2570	if (rc != VINF_SUCCESS)
2571	{
2572	*pfFFDone = true;
2573	break;
2574	}
2575	}
2576	}
2577	}
2578
2579	/*
2580	* Return to outer loop.
2581	*/
2582	#if defined(LOG_ENABLED) && defined(DEBUG)
2583	RTLogFlush(NULL);
2584	#endif
2585	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2586	return rc;
2587	}
2588
2589
2590	/**
2591	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2592	*
2593	* This function contains the raw-mode version of the inner
2594	* execution loop (the outer loop being in EMR3ExecuteVM()).
2595	*
2596	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2597	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2598	*
2599	* @param pVM VM handle.
2600	* @param pfFFDone Where to store an indicator telling whether or not
2601	* FFs were done before returning.
2602	*/
2603	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2604	{
2605	int rc = VERR_INTERNAL_ERROR;
2606	PCPUMCTX pCtx = pVM->em.s.pCtx;
2607
2608	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2609	*pfFFDone = false;
2610
2611	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2612
2613	/*
2614	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2615	*/
2616	for (;;)
2617	{
2618	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2619
2620	/*
2621	* Check various preconditions.
2622	*/
2623	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2624
2625	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2626
2627	/*
2628	* Sync page directory.
2629	*/
2630	if (VM_FF_ISPENDING(pVM, (VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)))
2631	{
2632	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2633	if (VBOX_FAILURE(rc))
2634	return rc;
2635
2636	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2637
2638	/* Prefetch pages for EIP and ESP */
2639	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip));
2640	if (rc == VINF_SUCCESS)
2641	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2642	if (rc != VINF_SUCCESS)
2643	{
2644	if (rc != VINF_PGM_SYNC_CR3)
2645	return rc;
2646	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2647	if (VBOX_FAILURE(rc))
2648	return rc;
2649	}
2650
2651	/** @todo maybe prefetch the supervisor stack page as well */
2652	}
2653
2654	#ifdef LOG_ENABLED
2655	uint8_t u8Vector;
2656
2657	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2658	if (rc == VINF_SUCCESS)
2659	{
2660	Log(("Pending hardware interrupt %d\n", u8Vector));
2661	}
2662	/*
2663	* Log important stuff before entering GC.
2664	*/
2665	bool fSingleStep = false;
2666	if ((pCtx->ss & X86_SEL_RPL) == 0 && !fSingleStep)
2667	Log(("HWR0: %08X ESP=%08X IF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (pCtx->ss & X86_SEL_RPL)));
2668	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep && pCtx->eflags.Bits.u1VM)
2669	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2670	else if ((pCtx->ss & X86_SEL_RPL) == 3 && !fSingleStep)
2671	Log(("HWR3: %08X ESP=%08X IF=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF));
2672	#endif
2673
2674
2675	/*
2676	* Execute the code.
2677	*/
2678	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2679	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2680	VMMR3Unlock(pVM);
2681	rc = VMMR3HwAccRunGC(pVM);
2682	VMMR3Lock(pVM);
2683	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2684
2685
2686	/*
2687	* Deal with high priority post execution FFs before doing anything else.
2688	*/
2689	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2690	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2691	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2692
2693	/*
2694	* Process the returned status code.
2695	*/
2696	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2697	break;
2698
2699	rc = emR3RawHandleRC(pVM, pCtx, rc);
2700	if (rc != VINF_SUCCESS)
2701	break;
2702
2703	/*
2704	* Check and execute forced actions.
2705	*/
2706	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2707	TMTimerPoll(pVM);
2708	#endif
2709	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2710	{
2711	rc = emR3ForcedActions(pVM, rc);
2712	if ( rc != VINF_SUCCESS
2713	&& rc != VINF_EM_RESCHEDULE_HWACC)
2714	{
2715	*pfFFDone = true;
2716	break;
2717	}
2718	}
2719	}
2720	/*
2721	* Return to outer loop.
2722	*/
2723	#if defined(LOG_ENABLED) && defined(DEBUG)
2724	RTLogFlush(NULL);
2725	#endif
2726	return rc;
2727	}
2728
2729
2730	/**
2731	* Decides whether to execute RAW, HWACC or REM.
2732	*
2733	* @returns new EM state
2734	* @param pVM The VM.
2735	* @param pCtx The CPU context.
2736	*/
2737	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2738	{
2739	/*
2740	* When forcing raw-mode execution, things are simple.
2741	*/
2742	if (pVM->em.s.fForceRAW)
2743	return EMSTATE_RAW;
2744
2745	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2746	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2747	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2748
2749	X86EFLAGS EFlags = pCtx->eflags;
2750	if (HWACCMIsEnabled(pVM))
2751	{
2752	/* Hardware accelerated raw-mode:
2753	*
2754	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2755	*/
2756	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2757	return EMSTATE_HWACC;
2758
2759	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2760	return EMSTATE_REM;
2761	}
2762
2763	/* Standard raw-mode:
2764	*
2765	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2766	* or 32 bits protected mode ring 0 code
2767	*
2768	* The tests are ordered by the likelyhood of being true during normal execution.
2769	*/
2770	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2771	{
2772	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2773	return EMSTATE_REM;
2774	}
2775
2776	#ifndef VBOX_RAW_V86
2777	if (EFlags.u32 & X86_EFL_VM) {
2778	Log2(("raw mode refused: VM_MASK\n"));
2779	return EMSTATE_REM;
2780	}
2781	#endif
2782
2783	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2784	uint32_t u32CR0 = pCtx->cr0;
2785	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2786	{
2787	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2788	return EMSTATE_REM;
2789	}
2790
2791	if (pCtx->cr4 & X86_CR4_PAE)
2792	{
2793	//Log2(("raw mode refused: PAE\n"));
2794	return EMSTATE_REM;
2795	}
2796
2797	unsigned uSS = pCtx->ss;
2798	if ((uSS & X86_SEL_RPL) == 3)
2799	{
2800	if (!EMIsRawRing3Enabled(pVM))
2801	return EMSTATE_REM;
2802
2803	if (!(EFlags.u32 & X86_EFL_IF))
2804	{
2805	#ifdef VBOX_RAW_V86
2806	if(!(EFlags.u32 & X86_EFL_VM))
2807	return EMSTATE_REM;
2808	#else
2809	Log2(("raw mode refused: IF (RawR3)\n"));
2810	return EMSTATE_REM;
2811	#endif
2812	}
2813
2814	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2815	{
2816	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2817	return EMSTATE_REM;
2818	}
2819	}
2820	else
2821	{
2822	if (!EMIsRawRing0Enabled(pVM))
2823	return EMSTATE_REM;
2824
2825	/* Only ring 0 supervisor code. */
2826	if ((uSS & X86_SEL_RPL) != 0)
2827	{
2828	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2829	return EMSTATE_REM;
2830	}
2831
2832	// Let's start with pure 32 bits ring 0 code first
2833	/** @todo What's pure 32-bit mode? flat? */
2834	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2835	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2836	{
2837	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2838	return EMSTATE_REM;
2839	}
2840
2841	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2842	if (!(u32CR0 & X86_CR0_WP))
2843	{
2844	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2845	return EMSTATE_REM;
2846	}
2847
2848	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2849	{
2850	Log2(("raw r0 mode forced: patch code\n"));
2851	return EMSTATE_RAW;
2852	}
2853
2854	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2855	if (!(EFlags.u32 & X86_EFL_IF))
2856	{
2857	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2858	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2859	return EMSTATE_REM;
2860	}
2861	#endif
2862
2863	/** @todo still necessary??? */
2864	if (EFlags.Bits.u2IOPL != 0)
2865	{
2866	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2867	return EMSTATE_REM;
2868	}
2869	}
2870
2871	Assert(PGMPhysIsA20Enabled(pVM));
2872	return EMSTATE_RAW;
2873	}
2874
2875
2876	/**
2877	* Executes all high priority post execution force actions.
2878	*
2879	* @returns rc or a fatal status code.
2880	*
2881	* @param pVM VM handle.
2882	* @param rc The current rc.
2883	*/
2884	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2885	{
2886	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2887	PDMR3CritSectFF(pVM);
2888
2889	if (VM_FF_ISSET(pVM, VM_FF_CSAM_FLUSH_DIRTY_PAGE))
2890	CSAMR3FlushDirtyPages(pVM);
2891
2892	return rc;
2893	}
2894
2895
2896	/**
2897	* Executes all pending forced actions.
2898	*
2899	* Forced actions can cause execution delays and execution
2900	* rescheduling. The first we deal with using action priority, so
2901	* that for instance pending timers aren't scheduled and ran until
2902	* right before execution. The rescheduling we deal with using
2903	* return codes. The same goes for VM termination, only in that case
2904	* we exit everything.
2905	*
2906	* @returns VBox status code of equal or greater importance/severity than rc.
2907	* The most important ones are: VINF_EM_RESCHEDULE,
2908	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2909	*
2910	* @param pVM VM handle.
2911	* @param rc The current rc.
2912	*
2913	*/
2914	static int emR3ForcedActions(PVM pVM, int rc)
2915	{
2916	#ifdef VBOX_STRICT
2917	int rcIrq = VINF_SUCCESS;
2918	#endif
2919	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2920
2921	#define UPDATE_RC() \
2922	do { \
2923	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2924	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2925	break; \
2926	if (!rc \|\| rc2 < rc) \
2927	rc = rc2; \
2928	} while (0)
2929
2930	int rc2;
2931
2932	/*
2933	* Post execution chunk first.
2934	*/
2935	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2936	{
2937	/*
2938	* Termination request.
2939	*/
2940	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2941	{
2942	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2943	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2944	return VINF_EM_TERMINATE;
2945	}
2946
2947	/*
2948	* Debugger Facility polling.
2949	*/
2950	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2951	{
2952	rc2 = DBGFR3VMMForcedAction(pVM);
2953	UPDATE_RC();
2954	}
2955
2956	/*
2957	* Postponed reset request.
2958	*/
2959	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2960	{
2961	rc2 = VMR3Reset(pVM);
2962	UPDATE_RC();
2963	VM_FF_CLEAR(pVM, VM_FF_RESET);
2964	}
2965
2966	/*
2967	* CSAM page scanning.
2968	*/
2969	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2970	{
2971	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2972	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2973	CSAMR3CheckEIP(pVM, CPUMGetGuestEIP(pVM), true);
2974	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2975	}
2976
2977	/* check that we got them all */
2978	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
2979	}
2980
2981	/*
2982	* Normal priority then.
2983	* (Executed in no particular order.)
2984	*/
2985	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2986	{
2987	/*
2988	* PDM Queues are pending.
2989	*/
2990	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
2991	PDMR3QueueFlushAll(pVM);
2992
2993	/*
2994	* PDM DMA transfers are pending.
2995	*/
2996	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
2997	PDMR3DmaRun(pVM);
2998
2999	/*
3000	* Requests from other threads.
3001	*/
3002	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3003	{
3004	rc2 = VMR3ReqProcess(pVM);
3005	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3006	{
3007	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3008	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3009	return rc2;
3010	}
3011	UPDATE_RC();
3012	}
3013
3014	/* check that we got them all */
3015	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3016	}
3017
3018	/*
3019	* Execute polling function ever so often.
3020	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3021	*/
3022	static unsigned cLast = 0;
3023	if (!((++cLast) % 4))
3024	PDMR3Poll(pVM);
3025
3026	/*
3027	* High priority pre execution chunk last.
3028	* (Executed in ascending priority order.)
3029	*/
3030	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3031	{
3032	/*
3033	* Timers before interrupts.
3034	*/
3035	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3036	TMR3TimerQueuesDo(pVM);
3037
3038	/*
3039	* The instruction following an emulated STI should always be executed!
3040	*/
3041	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3042	{
3043	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3044	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3045	{
3046	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3047	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3048	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3049	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3050	*/
3051	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3052	}
3053	if (HWACCMR3IsActive(pVM))
3054	rc2 = VINF_EM_RESCHEDULE_HWACC;
3055	else
3056	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3057
3058	UPDATE_RC();
3059	}
3060
3061	/*
3062	* Interrupts.
3063	*/
3064	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3065	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3066	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3067	&& PATMAreInterruptsEnabled(pVM)
3068	&& !HWACCMR3IsEventPending(pVM))
3069	{
3070	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3071	{
3072	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3073	/** @todo this really isn't nice, should properly handle this */
3074	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3075	#ifdef VBOX_STRICT
3076	rcIrq = rc2;
3077	#endif
3078	UPDATE_RC();
3079	}
3080	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3081	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3082	{
3083	rc2 = VINF_EM_RESCHEDULE_REM;
3084	UPDATE_RC();
3085	}
3086	}
3087
3088	/*
3089	* Debugger Facility request.
3090	*/
3091	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3092	{
3093	rc2 = DBGFR3VMMForcedAction(pVM);
3094	UPDATE_RC();
3095	}
3096
3097	/*
3098	* Termination request.
3099	*/
3100	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3101	{
3102	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3103	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3104	return VINF_EM_TERMINATE;
3105	}
3106
3107	#ifdef DEBUG
3108	/*
3109	* Debug, pause the VM.
3110	*/
3111	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3112	{
3113	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3114	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3115	return VINF_EM_SUSPEND;
3116	}
3117
3118	#endif
3119	/* check that we got them all */
3120	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3121	}
3122
3123	#undef UPDATE_RC
3124	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3125	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3126	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3127	return rc;
3128	}
3129
3130
3131	/**
3132	* Execute VM.
3133	*
3134	* This function is the main loop of the VM. The emulation thread
3135	* calls this function when the VM has been successfully constructed
3136	* and we're ready for executing the VM.
3137	*
3138	* Returning from this function means that the VM is turned off or
3139	* suspended (state already saved) and deconstruction in next in line.
3140	*
3141	* All interaction from other thread are done using forced actions
3142	* and signaling of the wait object.
3143	*
3144	* @returns VBox status code.
3145	* @param pVM The VM to operate on.
3146	*/
3147	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3148	{
3149	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3150	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3151	VM_ASSERT_EMT(pVM);
3152	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3153
3154	VMMR3Lock(pVM);
3155
3156	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3157	if (rc == 0)
3158	{
3159	/*
3160	* Start the virtual time.
3161	*/
3162	rc = TMVirtualResume(pVM);
3163	Assert(rc == VINF_SUCCESS);
3164
3165	/*
3166	* The Outer Main Loop.
3167	*/
3168	bool fFFDone = false;
3169	rc = VINF_EM_RESCHEDULE;
3170	pVM->em.s.enmState = EMSTATE_REM;
3171	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3172	for (;;)
3173	{
3174	/*
3175	* Before we can schedule anything (we're here because
3176	* scheduling is required) we must service any pending
3177	* forced actions to avoid any pending action causing
3178	* immidate rescheduling upon entering an inner loop
3179	*
3180	* Do forced actions.
3181	*/
3182	if ( !fFFDone
3183	&& rc != VINF_EM_TERMINATE
3184	&& rc != VINF_EM_OFF
3185	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3186	{
3187	rc = emR3ForcedActions(pVM, rc);
3188	if ( ( rc == VINF_EM_RESCHEDULE_REM
3189	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3190	&& pVM->em.s.fForceRAW)
3191	rc = VINF_EM_RESCHEDULE_RAW;
3192	}
3193	else if (fFFDone)
3194	fFFDone = false;
3195
3196	#if defined(__AMD64__)
3197	Assert(!pVM->fPATMEnabled);
3198	Assert(!pVM->fCSAMEnabled);
3199	#ifndef __WIN__
3200	Assert(!pVM->fRawR0Enabled);
3201	Assert(!pVM->fRawR3Enabled);
3202	#endif
3203	#endif
3204
3205	/*
3206	* Now what to do?
3207	*/
3208	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3209	switch (rc)
3210	{
3211	/*
3212	* Keep doing what we're currently doing.
3213	*/
3214	case VINF_SUCCESS:
3215	break;
3216
3217	/*
3218	* Reschedule - to raw-mode execution.
3219	*/
3220	case VINF_EM_RESCHEDULE_RAW:
3221	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3222	pVM->em.s.enmState = EMSTATE_RAW;
3223	break;
3224
3225	/*
3226	* Reschedule - to hardware accelerated raw-mode execution.
3227	*/
3228	case VINF_EM_RESCHEDULE_HWACC:
3229	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3230	Assert(!pVM->em.s.fForceRAW);
3231	pVM->em.s.enmState = EMSTATE_HWACC;
3232	break;
3233
3234	/*
3235	* Reschedule - to recompiled execution.
3236	*/
3237	case VINF_EM_RESCHEDULE_REM:
3238	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3239	pVM->em.s.enmState = EMSTATE_REM;
3240	break;
3241
3242	/*
3243	* Resume.
3244	*/
3245	case VINF_EM_RESUME:
3246	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3247	/* fall through and get scheduled. */
3248
3249	/*
3250	* Reschedule.
3251	*/
3252	case VINF_EM_RESCHEDULE:
3253	{
3254	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3255	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3256	pVM->em.s.enmState = enmState;
3257	break;
3258	}
3259
3260	/*
3261	* Halted.
3262	*/
3263	case VINF_EM_HALT:
3264	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3265	pVM->em.s.enmState = EMSTATE_HALTED;
3266	break;
3267
3268	/*
3269	* Suspend.
3270	*/
3271	case VINF_EM_SUSPEND:
3272	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3273	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3274	break;
3275
3276	/*
3277	* Reset.
3278	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3279	*/
3280	case VINF_EM_RESET:
3281	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3282	pVM->em.s.enmState = EMSTATE_REM;
3283	break;
3284
3285	/*
3286	* Power Off.
3287	*/
3288	case VINF_EM_OFF:
3289	pVM->em.s.enmState = EMSTATE_TERMINATING;
3290	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3291	TMVirtualPause(pVM);
3292	VMMR3Unlock(pVM);
3293	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3294	return rc;
3295
3296	/*
3297	* Terminate the VM.
3298	*/
3299	case VINF_EM_TERMINATE:
3300	pVM->em.s.enmState = EMSTATE_TERMINATING;
3301	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3302	TMVirtualPause(pVM);
3303	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3304	return rc;
3305
3306	/*
3307	* Guest debug events.
3308	*/
3309	case VINF_EM_DBG_STEPPED:
3310	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3311	case VINF_EM_DBG_STOP:
3312	case VINF_EM_DBG_BREAKPOINT:
3313	case VINF_EM_DBG_STEP:
3314	if (pVM->em.s.enmState == EMSTATE_RAW)
3315	{
3316	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3317	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3318	}
3319	else
3320	{
3321	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3322	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3323	}
3324	break;
3325
3326	/*
3327	* Hypervisor debug events.
3328	*/
3329	case VINF_EM_DBG_HYPER_STEPPED:
3330	case VINF_EM_DBG_HYPER_BREAKPOINT:
3331	case VINF_EM_DBG_HYPER_ASSERTION:
3332	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3333	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3334	break;
3335
3336	/*
3337	* Any error code showing up here other than the ones we
3338	* know and process above are considered to be FATAL.
3339	*
3340	* Unknown warnings and informational status codes are also
3341	* included in this.
3342	*/
3343	default:
3344	if (VBOX_SUCCESS(rc))
3345	{
3346	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3347	rc = VERR_EM_INTERNAL_ERROR;
3348	}
3349	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3350	Log(("EMR3ExecuteVM returns %d\n", rc));
3351	break;
3352	}
3353
3354
3355	/*
3356	* Any waiters can now be woken up
3357	*/
3358	VMMR3Unlock(pVM);
3359	VMMR3Lock(pVM);
3360
3361	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3362	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3363
3364	/*
3365	* Act on the state.
3366	*/
3367	switch (pVM->em.s.enmState)
3368	{
3369	/*
3370	* Execute raw.
3371	*/
3372	case EMSTATE_RAW:
3373	rc = emR3RawExecute(pVM, &fFFDone);
3374	break;
3375
3376	/*
3377	* Execute hardware accelerated raw.
3378	*/
3379	case EMSTATE_HWACC:
3380	rc = emR3HwAccExecute(pVM, &fFFDone);
3381	break;
3382
3383	/*
3384	* Execute recompiled.
3385	*/
3386	case EMSTATE_REM:
3387	rc = emR3RemExecute(pVM, &fFFDone);
3388	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3389	break;
3390
3391	/*
3392	* hlt - execution halted until interrupt.
3393	*/
3394	case EMSTATE_HALTED:
3395	{
3396	STAM_PROFILE_START(&pVM->em.s.StatHalted, y);
3397	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3398	STAM_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3399	break;
3400	}
3401
3402	/*
3403	* Suspended - return to VM.cpp.
3404	*/
3405	case EMSTATE_SUSPENDED:
3406	TMVirtualPause(pVM);
3407	VMMR3Unlock(pVM);
3408	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3409	return VINF_EM_SUSPEND;
3410
3411	/*
3412	* Debugging in the guest.
3413	*/
3414	case EMSTATE_DEBUG_GUEST_REM:
3415	case EMSTATE_DEBUG_GUEST_RAW:
3416	TMVirtualPause(pVM);
3417	rc = emR3Debug(pVM, rc);
3418	TMVirtualResume(pVM);
3419	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3420	break;
3421
3422	/*
3423	* Debugging in the hypervisor.
3424	*/
3425	case EMSTATE_DEBUG_HYPER:
3426	{
3427	TMVirtualPause(pVM);
3428	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3429
3430	rc = emR3Debug(pVM, rc);
3431	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3432	if (rc != VINF_SUCCESS)
3433	{
3434	/* switch to guru meditation mode */
3435	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3436	VMMR3FatalDump(pVM, rc);
3437	return rc;
3438	}
3439
3440	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3441	TMVirtualResume(pVM);
3442	break;
3443	}
3444
3445	/*
3446	* Guru meditation takes place in the debugger.
3447	*/
3448	case EMSTATE_GURU_MEDITATION:
3449	{
3450	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3451	TMVirtualPause(pVM);
3452	VMMR3FatalDump(pVM, rc);
3453	int rc2 = emR3Debug(pVM, rc);
3454	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3455	{
3456	VMMR3Unlock(pVM);
3457	/** @todo change the VM state! */
3458	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3459	return rc;
3460	}
3461	TMVirtualResume(pVM);
3462	rc = rc2;
3463	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3464	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3465	break;
3466	}
3467
3468	/*
3469	* The states we don't expect here.
3470	*/
3471	case EMSTATE_NONE:
3472	case EMSTATE_TERMINATING:
3473	default:
3474	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3475	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3476	TMVirtualPause(pVM);
3477	VMMR3Unlock(pVM);
3478	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3479	return VERR_EM_INTERNAL_ERROR;
3480	}
3481	} /* The Outer Main Loop */
3482	}
3483	else
3484	{
3485	/*
3486	* Fatal error.
3487	*/
3488	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3489	TMVirtualPause(pVM);
3490	VMMR3FatalDump(pVM, rc);
3491	emR3Debug(pVM, rc);
3492	VMMR3Unlock(pVM);
3493	/** @todo change the VM state! */
3494	return rc;
3495	}
3496
3497	/* (won't ever get here). */
3498	AssertFailed();
3499	}
3500

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 19

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