EM.cpp@ 12600

Last change on this file since 12600 was 12305, checked in by vboxsync, 16 years ago
Flush the recompiler's TB cache each time we detect writes to PATM/CSAM monitored pages.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 143.6 KB

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1	/* $Id: EM.cpp 12305 2008-09-09 15:50:15Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/ssm.h>
49	#include <VBox/pdmapi.h>
50	#include <VBox/pdmcritsect.h>
51	#include <VBox/pdmqueue.h>
52	#include <VBox/hwaccm.h>
53	#include <VBox/patm.h>
54	#include "EMInternal.h"
55	#include <VBox/vm.h>
56	#include <VBox/cpumdis.h>
57	#include <VBox/dis.h>
58	#include <VBox/disopcode.h>
59	#include <VBox/dbgf.h>
60
61	#include <VBox/log.h>
62	#include <iprt/thread.h>
63	#include <iprt/assert.h>
64	#include <iprt/asm.h>
65	#include <iprt/semaphore.h>
66	#include <iprt/string.h>
67	#include <iprt/avl.h>
68	#include <iprt/stream.h>
69	#include <VBox/param.h>
70	#include <VBox/err.h>
71
72
73	/*******************************************************************************
74	* Internal Functions *
75	*******************************************************************************/
76	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
77	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
78	static int emR3Debug(PVM pVM, int rc);
79	static int emR3RemStep(PVM pVM);
80	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
81	static int emR3RawResumeHyper(PVM pVM);
82	static int emR3RawStep(PVM pVM);
83	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
84	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
85	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
86	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
87	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
88	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
89	static int emR3ForcedActions(PVM pVM, int rc);
90	static int emR3RawGuestTrap(PVM pVM);
91
92
93	/**
94	* Initializes the EM.
95	*
96	* @returns VBox status code.
97	* @param pVM The VM to operate on.
98	*/
99	EMR3DECL(int) EMR3Init(PVM pVM)
100	{
101	LogFlow(("EMR3Init\n"));
102	/*
103	* Assert alignment and sizes.
104	*/
105	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
106	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
107	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
108	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
109
110	/*
111	* Init the structure.
112	*/
113	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
114	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR3Enabled = true;
117	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
118	if (VBOX_FAILURE(rc))
119	pVM->fRawR0Enabled = true;
120	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
121	pVM->em.s.enmState = EMSTATE_NONE;
122	pVM->em.s.fForceRAW = false;
123
124	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
125	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
126	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
127	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
128
129	/*
130	* Saved state.
131	*/
132	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133	NULL, emR3Save, NULL,
134	NULL, emR3Load, NULL);
135	if (VBOX_FAILURE(rc))
136	return rc;
137
138	/*
139	* Statistics.
140	*/
141	#ifdef VBOX_WITH_STATISTICS
142	PEMSTATS pStats;
143	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
144	if (VBOX_FAILURE(rc))
145	return rc;
146	pVM->em.s.pStatsHC = pStats;
147	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
148
149	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
150	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
151
152	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
153	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
154
155	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
207	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg8b, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
208	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg8b, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was successfully interpreted.");
209	STAM_REG_USED(pVM, &pStats->StatGCXAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
210	STAM_REG_USED(pVM, &pStats->StatHCXAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was successfully interpreted.");
211	STAM_REG_USED(pVM, &pStats->StatHCRdmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatGCRdmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatHCWrmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatGCWrmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatHCStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatGCStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Stoswd", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
217
218	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
219	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
220
221	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
249	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
250	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
251	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
252	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatGCFailedRdmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatHCFailedRdmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdmsr", STAMUNIT_OCCURENCES, "The number of times RDMSR was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatGCFailedWrmsr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatHCFailedWrmsr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Wrmsr", STAMUNIT_OCCURENCES, "The number of times WRMSR was not interpreted.");
263
264	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
265	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
266	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
274	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
275	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
276	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
277	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
278	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
279	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
280	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
281	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg8b, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg8b", STAMUNIT_OCCURENCES, "The number of times CMPXCHG8B was not interpreted.");
282	STAM_REG_USED(pVM, &pStats->StatGCFailedXAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
283	STAM_REG_USED(pVM, &pStats->StatHCFailedXAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/XAdd", STAMUNIT_OCCURENCES, "The number of times XADD was not interpreted.");
284	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
285	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
286	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
287	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
288	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
289	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
290	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
291	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
292
293	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
294	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
295	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
296	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
297
298	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
299	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
300	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
301	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
302	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
303	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
304	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
305	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
306	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
307	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
308	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
309	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
310	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
311	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
312	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
313	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
314	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
315	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
316	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
317	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
318	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
319	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
320	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
321	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
322	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
323	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
324
325	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
326	pVM->em.s.pCliStatTree = 0;
327	#endif /* VBOX_WITH_STATISTICS */
328
329	/* these should be considered for release statistics. */
330	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
331	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
332	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
333	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
334	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
335	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
336	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
337	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
338	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
339	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
340	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
341	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
342	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
343	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
344	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
345	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
346
347
348	return VINF_SUCCESS;
349	}
350
351
352
353	/**
354	* Applies relocations to data and code managed by this
355	* component. This function will be called at init and
356	* whenever the VMM need to relocate it self inside the GC.
357	*
358	* @param pVM The VM.
359	*/
360	EMR3DECL(void) EMR3Relocate(PVM pVM)
361	{
362	LogFlow(("EMR3Relocate\n"));
363	if (pVM->em.s.pStatsHC)
364	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
365	}
366
367
368	/**
369	* Reset notification.
370	*
371	* @param pVM
372	*/
373	EMR3DECL(void) EMR3Reset(PVM pVM)
374	{
375	LogFlow(("EMR3Reset: \n"));
376	pVM->em.s.fForceRAW = false;
377	}
378
379
380	/**
381	* Terminates the EM.
382	*
383	* Termination means cleaning up and freeing all resources,
384	* the VM it self is at this point powered off or suspended.
385	*
386	* @returns VBox status code.
387	* @param pVM The VM to operate on.
388	*/
389	EMR3DECL(int) EMR3Term(PVM pVM)
390	{
391	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
392
393	return VINF_SUCCESS;
394	}
395
396
397	/**
398	* Execute state save operation.
399	*
400	* @returns VBox status code.
401	* @param pVM VM Handle.
402	* @param pSSM SSM operation handle.
403	*/
404	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
405	{
406	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
407	}
408
409
410	/**
411	* Execute state load operation.
412	*
413	* @returns VBox status code.
414	* @param pVM VM Handle.
415	* @param pSSM SSM operation handle.
416	* @param u32Version Data layout version.
417	*/
418	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
419	{
420	/*
421	* Validate version.
422	*/
423	if (u32Version != EM_SAVED_STATE_VERSION)
424	{
425	AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
426	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
427	}
428
429	/*
430	* Load the saved state.
431	*/
432	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
433	if (VBOX_FAILURE(rc))
434	pVM->em.s.fForceRAW = false;
435
436	Assert(pVM->em.s.pCliStatTree == 0);
437	return rc;
438	}
439
440
441	/**
442	* Enables or disables a set of raw-mode execution modes.
443	*
444	* @returns VINF_SUCCESS on success.
445	* @returns VINF_RESCHEDULE if a rescheduling might be required.
446	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
447	*
448	* @param pVM The VM to operate on.
449	* @param enmMode The execution mode change.
450	* @thread The emulation thread.
451	*/
452	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
453	{
454	switch (enmMode)
455	{
456	case EMRAW_NONE:
457	pVM->fRawR3Enabled = false;
458	pVM->fRawR0Enabled = false;
459	break;
460	case EMRAW_RING3_ENABLE:
461	pVM->fRawR3Enabled = true;
462	break;
463	case EMRAW_RING3_DISABLE:
464	pVM->fRawR3Enabled = false;
465	break;
466	case EMRAW_RING0_ENABLE:
467	pVM->fRawR0Enabled = true;
468	break;
469	case EMRAW_RING0_DISABLE:
470	pVM->fRawR0Enabled = false;
471	break;
472	default:
473	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
474	return VERR_INVALID_PARAMETER;
475	}
476	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
477	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
478	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
479	}
480
481
482	/**
483	* Raise a fatal error.
484	*
485	* Safely terminate the VM with full state report and stuff. This function
486	* will naturally never return.
487	*
488	* @param pVM VM handle.
489	* @param rc VBox status code.
490	*/
491	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
492	{
493	longjmp(pVM->em.s.u.FatalLongJump, rc);
494	AssertReleaseMsgFailed(("longjmp returned!\n"));
495	}
496
497
498	/**
499	* Gets the EM state name.
500	*
501	* @returns pointer to read only state name,
502	* @param enmState The state.
503	*/
504	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
505	{
506	switch (enmState)
507	{
508	case EMSTATE_NONE: return "EMSTATE_NONE";
509	case EMSTATE_RAW: return "EMSTATE_RAW";
510	case EMSTATE_HWACC: return "EMSTATE_HWACC";
511	case EMSTATE_REM: return "EMSTATE_REM";
512	case EMSTATE_HALTED: return "EMSTATE_HALTED";
513	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
514	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
515	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
516	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
517	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
518	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
519	default: return "Unknown!";
520	}
521	}
522
523
524	#ifdef VBOX_WITH_STATISTICS
525	/**
526	* Just a braindead function to keep track of cli addresses.
527	* @param pVM VM handle.
528	* @param pInstrGC The EIP of the cli instruction.
529	*/
530	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
531	{
532	PCLISTAT pRec;
533
534	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
535	if (!pRec)
536	{
537	/* New cli instruction; insert into the tree. */
538	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
539	Assert(pRec);
540	if (!pRec)
541	return;
542	pRec->Core.Key = (AVLPVKEY)pInstrGC;
543
544	char szCliStatName[32];
545	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
546	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
547
548	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
549	Assert(fRc); NOREF(fRc);
550	}
551	STAM_COUNTER_INC(&pRec->Counter);
552	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
553	}
554	#endif /* VBOX_WITH_STATISTICS */
555
556
557	/**
558	* Debug loop.
559	*
560	* @returns VBox status code for EM.
561	* @param pVM VM handle.
562	* @param rc Current EM VBox status code..
563	*/
564	static int emR3Debug(PVM pVM, int rc)
565	{
566	for (;;)
567	{
568	Log(("emR3Debug: rc=%Vrc\n", rc));
569	const int rcLast = rc;
570
571	/*
572	* Debug related RC.
573	*/
574	switch (rc)
575	{
576	/*
577	* Single step an instruction.
578	*/
579	case VINF_EM_DBG_STEP:
580	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
581	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
582	\|\| pVM->em.s.fForceRAW /* paranoia */)
583	rc = emR3RawStep(pVM);
584	else
585	{
586	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
587	rc = emR3RemStep(pVM);
588	}
589	break;
590
591	/*
592	* Simple events: stepped, breakpoint, stop/assertion.
593	*/
594	case VINF_EM_DBG_STEPPED:
595	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
596	break;
597
598	case VINF_EM_DBG_BREAKPOINT:
599	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
600	break;
601
602	case VINF_EM_DBG_STOP:
603	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
604	break;
605
606	case VINF_EM_DBG_HYPER_STEPPED:
607	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
608	break;
609
610	case VINF_EM_DBG_HYPER_BREAKPOINT:
611	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
612	break;
613
614	case VINF_EM_DBG_HYPER_ASSERTION:
615	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
616	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
617	break;
618
619	/*
620	* Guru meditation.
621	*/
622	case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
623	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
624	break;
625
626	default: /** @todo don't use default for guru, but make special errors code! */
627	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
628	break;
629	}
630
631	/*
632	* Process the result.
633	*/
634	do
635	{
636	switch (rc)
637	{
638	/*
639	* Continue the debugging loop.
640	*/
641	case VINF_EM_DBG_STEP:
642	case VINF_EM_DBG_STOP:
643	case VINF_EM_DBG_STEPPED:
644	case VINF_EM_DBG_BREAKPOINT:
645	case VINF_EM_DBG_HYPER_STEPPED:
646	case VINF_EM_DBG_HYPER_BREAKPOINT:
647	case VINF_EM_DBG_HYPER_ASSERTION:
648	break;
649
650	/*
651	* Resuming execution (in some form) has to be done here if we got
652	* a hypervisor debug event.
653	*/
654	case VINF_SUCCESS:
655	case VINF_EM_RESUME:
656	case VINF_EM_SUSPEND:
657	case VINF_EM_RESCHEDULE:
658	case VINF_EM_RESCHEDULE_RAW:
659	case VINF_EM_RESCHEDULE_REM:
660	case VINF_EM_HALT:
661	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
662	{
663	rc = emR3RawResumeHyper(pVM);
664	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
665	continue;
666	}
667	if (rc == VINF_SUCCESS)
668	rc = VINF_EM_RESCHEDULE;
669	return rc;
670
671	/*
672	* The debugger isn't attached.
673	* We'll simply turn the thing off since that's the easiest thing to do.
674	*/
675	case VERR_DBGF_NOT_ATTACHED:
676	switch (rcLast)
677	{
678	case VINF_EM_DBG_HYPER_ASSERTION:
679	case VINF_EM_DBG_HYPER_STEPPED:
680	case VINF_EM_DBG_HYPER_BREAKPOINT:
681	return rcLast;
682	}
683	return VINF_EM_OFF;
684
685	/*
686	* Status codes terminating the VM in one or another sense.
687	*/
688	case VINF_EM_TERMINATE:
689	case VINF_EM_OFF:
690	case VINF_EM_RESET:
691	case VINF_EM_RAW_STALE_SELECTOR:
692	case VINF_EM_RAW_IRET_TRAP:
693	case VERR_TRPM_PANIC:
694	case VERR_TRPM_DONT_PANIC:
695	case VERR_INTERNAL_ERROR:
696	return rc;
697
698	/*
699	* The rest is unexpected, and will keep us here.
700	*/
701	default:
702	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
703	break;
704	}
705	} while (false);
706	} /* debug for ever */
707	}
708
709
710	/**
711	* Steps recompiled code.
712	*
713	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
714	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
715	*
716	* @param pVM VM handle.
717	*/
718	static int emR3RemStep(PVM pVM)
719	{
720	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
721
722	/*
723	* Switch to REM, step instruction, switch back.
724	*/
725	int rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
726	if (VBOX_SUCCESS(rc))
727	{
728	rc = REMR3Step(pVM);
729	REMR3StateBack(pVM);
730	pVM->em.s.fREMFlushTBs = false;
731	}
732	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
733	return rc;
734	}
735
736	/**
737	* Executes recompiled code.
738	*
739	* This function contains the recompiler version of the inner
740	* execution loop (the outer loop being in EMR3ExecuteVM()).
741	*
742	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
743	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
744	*
745	* @param pVM VM handle.
746	* @param pfFFDone Where to store an indicator telling wheter or not
747	* FFs were done before returning.
748	*
749	*/
750	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
751	{
752	#ifdef LOG_ENABLED
753	PCPUMCTX pCtx = pVM->em.s.pCtx;
754	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
755
756	if (pCtx->eflags.Bits.u1VM)
757	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
758	else
759	Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
760	#endif
761	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
762
763	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
764	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
765	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
766	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
767	#endif
768
769	/*
770	* Spin till we get a forced action which returns anything but VINF_SUCCESS
771	* or the REM suggests raw-mode execution.
772	*/
773	*pfFFDone = false;
774	bool fInREMState = false;
775	int rc = VINF_SUCCESS;
776	for (;;)
777	{
778	/*
779	* Update REM state if not already in sync.
780	*/
781	if (!fInREMState)
782	{
783	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
784	rc = REMR3State(pVM, pVM->em.s.fREMFlushTBs);
785	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
786	if (VBOX_FAILURE(rc))
787	break;
788	fInREMState = true;
789	pVM->em.s.fREMFlushTBs = false;
790
791	/*
792	* We might have missed the raising of VMREQ, TIMER and some other
793	* imporant FFs while we were busy switching the state. So, check again.
794	*/
795	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
796	{
797	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
798	goto l_REMDoForcedActions;
799	}
800	}
801
802
803	/*
804	* Execute REM.
805	*/
806	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
807	rc = REMR3Run(pVM);
808	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
809
810
811	/*
812	* Deal with high priority post execution FFs before doing anything else.
813	*/
814	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
815	rc = emR3HighPriorityPostForcedActions(pVM, rc);
816
817	/*
818	* Process the returned status code.
819	* (Try keep this short! Call functions!)
820	*/
821	if (rc != VINF_SUCCESS)
822	{
823	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
824	break;
825	if (rc != VINF_REM_INTERRUPED_FF)
826	{
827	/*
828	* Anything which is not known to us means an internal error
829	* and the termination of the VM!
830	*/
831	AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Vra\n", rc));
832	break;
833	}
834	}
835
836
837	/*
838	* Check and execute forced actions.
839	* Sync back the VM state before calling any of these.
840	*/
841	#ifdef VBOX_HIGH_RES_TIMERS_HACK
842	TMTimerPoll(pVM);
843	#endif
844	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
845	{
846	l_REMDoForcedActions:
847	if (fInREMState)
848	{
849	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
850	REMR3StateBack(pVM);
851	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
852	fInREMState = false;
853	}
854	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
855	rc = emR3ForcedActions(pVM, rc);
856	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
857	if ( rc != VINF_SUCCESS
858	&& rc != VINF_EM_RESCHEDULE_REM)
859	{
860	*pfFFDone = true;
861	break;
862	}
863	}
864
865	} /* The Inner Loop, recompiled execution mode version. */
866
867
868	/*
869	* Returning. Sync back the VM state if required.
870	*/
871	if (fInREMState)
872	{
873	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
874	REMR3StateBack(pVM);
875	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
876	}
877
878	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
879	return rc;
880	}
881
882
883	/**
884	* Resumes executing hypervisor after a debug event.
885	*
886	* This is kind of special since our current guest state is
887	* potentially out of sync.
888	*
889	* @returns VBox status code.
890	* @param pVM The VM handle.
891	*/
892	static int emR3RawResumeHyper(PVM pVM)
893	{
894	int rc;
895	PCPUMCTX pCtx = pVM->em.s.pCtx;
896	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
897	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
898
899	/*
900	* Resume execution.
901	*/
902	CPUMRawEnter(pVM, NULL);
903	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
904	rc = VMMR3ResumeHyper(pVM);
905	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
906	rc = CPUMRawLeave(pVM, NULL, rc);
907	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
908
909	/*
910	* Deal with the return code.
911	*/
912	rc = emR3HighPriorityPostForcedActions(pVM, rc);
913	rc = emR3RawHandleRC(pVM, pCtx, rc);
914	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
915	return rc;
916	}
917
918
919	/**
920	* Steps rawmode.
921	*
922	* @returns VBox status code.
923	* @param pVM The VM handle.
924	*/
925	static int emR3RawStep(PVM pVM)
926	{
927	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
928	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
929	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
930	int rc;
931	PCPUMCTX pCtx = pVM->em.s.pCtx;
932	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
933	#ifndef DEBUG_sandervl
934	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
935	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
936	#endif
937	if (fGuest)
938	{
939	/*
940	* Check vital forced actions, but ignore pending interrupts and timers.
941	*/
942	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
943	{
944	rc = emR3RawForcedActions(pVM, pCtx);
945	if (VBOX_FAILURE(rc))
946	return rc;
947	}
948
949	/*
950	* Set flags for single stepping.
951	*/
952	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
953	}
954	else
955	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
956
957	/*
958	* Single step.
959	* We do not start time or anything, if anything we should just do a few nanoseconds.
960	*/
961	CPUMRawEnter(pVM, NULL);
962	do
963	{
964	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
965	rc = VMMR3ResumeHyper(pVM);
966	else
967	rc = VMMR3RawRunGC(pVM);
968	#ifndef DEBUG_sandervl
969	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
970	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
971	#endif
972	} while ( rc == VINF_SUCCESS
973	\|\| rc == VINF_EM_RAW_INTERRUPT);
974	rc = CPUMRawLeave(pVM, NULL, rc);
975	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
976
977	/*
978	* Make sure the trap flag is cleared.
979	* (Too bad if the guest is trying to single step too.)
980	*/
981	if (fGuest)
982	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
983	else
984	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
985
986	/*
987	* Deal with the return codes.
988	*/
989	rc = emR3HighPriorityPostForcedActions(pVM, rc);
990	rc = emR3RawHandleRC(pVM, pCtx, rc);
991	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
992	return rc;
993	}
994
995
996	#ifdef DEBUG
997
998	/**
999	* Steps hardware accelerated mode.
1000	*
1001	* @returns VBox status code.
1002	* @param pVM The VM handle.
1003	*/
1004	static int emR3HwAccStep(PVM pVM)
1005	{
1006	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
1007
1008	int rc;
1009	PCPUMCTX pCtx = pVM->em.s.pCtx;
1010	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
1011
1012	/*
1013	* Check vital forced actions, but ignore pending interrupts and timers.
1014	*/
1015	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1016	{
1017	rc = emR3RawForcedActions(pVM, pCtx);
1018	if (VBOX_FAILURE(rc))
1019	return rc;
1020	}
1021	/*
1022	* Set flags for single stepping.
1023	*/
1024	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1025
1026	/*
1027	* Single step.
1028	* We do not start time or anything, if anything we should just do a few nanoseconds.
1029	*/
1030	do
1031	{
1032	rc = VMMR3HwAccRunGC(pVM);
1033	} while ( rc == VINF_SUCCESS
1034	\|\| rc == VINF_EM_RAW_INTERRUPT);
1035	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1036
1037	/*
1038	* Make sure the trap flag is cleared.
1039	* (Too bad if the guest is trying to single step too.)
1040	*/
1041	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1042
1043	/*
1044	* Deal with the return codes.
1045	*/
1046	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1047	rc = emR3RawHandleRC(pVM, pCtx, rc);
1048	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1049	return rc;
1050	}
1051
1052
1053	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1054	{
1055	EMSTATE enmOldState = pVM->em.s.enmState;
1056
1057	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1058
1059	Log(("Single step BEGIN:\n"));
1060	for(uint32_t i=0;i<cIterations;i++)
1061	{
1062	DBGFR3PrgStep(pVM);
1063	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1064	emR3RawStep(pVM);
1065	}
1066	Log(("Single step END:\n"));
1067	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1068	pVM->em.s.enmState = enmOldState;
1069	}
1070
1071
1072	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1073	{
1074	EMSTATE enmOldState = pVM->em.s.enmState;
1075
1076	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1077
1078	Log(("Single step BEGIN:\n"));
1079	for(uint32_t i=0;i<cIterations;i++)
1080	{
1081	DBGFR3PrgStep(pVM);
1082	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1083	emR3HwAccStep(pVM);
1084	}
1085	Log(("Single step END:\n"));
1086	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1087	pVM->em.s.enmState = enmOldState;
1088	}
1089
1090
1091	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1092	{
1093	EMSTATE enmOldState = pVM->em.s.enmState;
1094
1095	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1096
1097	Log(("Single step BEGIN:\n"));
1098	for(uint32_t i=0;i<cIterations;i++)
1099	{
1100	DBGFR3PrgStep(pVM);
1101	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1102	emR3RemStep(pVM);
1103	}
1104	Log(("Single step END:\n"));
1105	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1106	pVM->em.s.enmState = enmOldState;
1107	}
1108
1109	#endif /* DEBUG */
1110
1111
1112	/**
1113	* Executes one (or perhaps a few more) instruction(s).
1114	*
1115	* @returns VBox status code suitable for EM.
1116	*
1117	* @param pVM VM handle.
1118	* @param rcGC GC return code
1119	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1120	* instruction and prefix the log output with this text.
1121	*/
1122	#ifdef LOG_ENABLED
1123	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1124	#else
1125	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1126	#endif
1127	{
1128	PCPUMCTX pCtx = pVM->em.s.pCtx;
1129	int rc;
1130
1131	/*
1132	*
1133	* The simple solution is to use the recompiler.
1134	* The better solution is to disassemble the current instruction and
1135	* try handle as many as possible without using REM.
1136	*
1137	*/
1138
1139	#ifdef LOG_ENABLED
1140	/*
1141	* Disassemble the instruction if requested.
1142	*/
1143	if (pszPrefix)
1144	{
1145	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1146	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1147	}
1148	#endif /* LOG_ENABLED */
1149
1150	/*
1151	* PATM is making life more interesting.
1152	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1153	* tell PATM there is a trap in this code and have it take the appropriate actions
1154	* to allow us execute the code in REM.
1155	*/
1156	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1157	{
1158	Log(("emR3RawExecuteInstruction: In patch block. eip=%VRv\n", pCtx->eip));
1159
1160	RTGCPTR pNewEip;
1161	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1162	switch (rc)
1163	{
1164	/*
1165	* It's not very useful to emulate a single instruction and then go back to raw
1166	* mode; just execute the whole block until IF is set again.
1167	*/
1168	case VINF_SUCCESS:
1169	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1170	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1171	pCtx->eip = pNewEip;
1172	Assert(pCtx->eip);
1173
1174	if (pCtx->eflags.Bits.u1IF)
1175	{
1176	/*
1177	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1178	*/
1179	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1180	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1181	}
1182	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1183	{
1184	/* special case: iret, that sets IF, detected a pending irq/event */
1185	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1186	}
1187	return VINF_EM_RESCHEDULE_REM;
1188
1189	/*
1190	* One instruction.
1191	*/
1192	case VINF_PATCH_EMULATE_INSTR:
1193	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1194	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1195	pCtx->eip = pNewEip;
1196	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1197
1198	/*
1199	* The patch was disabled, hand it to the REM.
1200	*/
1201	case VERR_PATCH_DISABLED:
1202	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1203	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1204	pCtx->eip = pNewEip;
1205	if (pCtx->eflags.Bits.u1IF)
1206	{
1207	/*
1208	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1209	*/
1210	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1211	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1212	}
1213	return VINF_EM_RESCHEDULE_REM;
1214
1215	/* Force continued patch exection; usually due to write monitored stack. */
1216	case VINF_PATCH_CONTINUE:
1217	return VINF_SUCCESS;
1218
1219	default:
1220	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1221	return VERR_INTERNAL_ERROR;
1222	}
1223	}
1224
1225	#if 0
1226	/* Try our own instruction emulator before falling back to the recompiler. */
1227	DISCPUSTATE Cpu;
1228	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "GEN EMU");
1229	if (VBOX_SUCCESS(rc))
1230	{
1231	uint32_t size;
1232
1233	switch (Cpu.pCurInstr->opcode)
1234	{
1235	/* @todo we can do more now */
1236	case OP_MOV:
1237	case OP_AND:
1238	case OP_OR:
1239	case OP_XOR:
1240	case OP_POP:
1241	case OP_INC:
1242	case OP_DEC:
1243	case OP_XCHG:
1244	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1245	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1246	if (VBOX_SUCCESS(rc))
1247	{
1248	pCtx->rip += Cpu.opsize;
1249	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1250	return rc;
1251	}
1252	if (rc != VERR_EM_INTERPRETER)
1253	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1254	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1255	break;
1256	}
1257	}
1258	#endif
1259	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1260	rc = REMR3EmulateInstruction(pVM);
1261	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1262
1263	return rc;
1264	}
1265
1266
1267	/**
1268	* Executes one (or perhaps a few more) instruction(s).
1269	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1270	*
1271	* @returns VBox status code suitable for EM.
1272	* @param pVM VM handle.
1273	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1274	* instruction and prefix the log output with this text.
1275	* @param rcGC GC return code
1276	*/
1277	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1278	{
1279	#ifdef LOG_ENABLED
1280	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1281	#else
1282	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1283	#endif
1284	}
1285
1286	/**
1287	* Executes one (or perhaps a few more) IO instruction(s).
1288	*
1289	* @returns VBox status code suitable for EM.
1290	* @param pVM VM handle.
1291	*/
1292	int emR3RawExecuteIOInstruction(PVM pVM)
1293	{
1294	int rc;
1295	PCPUMCTX pCtx = pVM->em.s.pCtx;
1296
1297	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1298
1299	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1300	* as io instructions tend to come in packages of more than one
1301	*/
1302	DISCPUSTATE Cpu;
1303	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "IO EMU");
1304	if (VBOX_SUCCESS(rc))
1305	{
1306	rc = VINF_EM_RAW_EMULATE_INSTR;
1307
1308	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1309	{
1310	switch (Cpu.pCurInstr->opcode)
1311	{
1312	case OP_IN:
1313	{
1314	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1315	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1316	break;
1317	}
1318
1319	case OP_OUT:
1320	{
1321	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1322	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1323	break;
1324	}
1325	}
1326	}
1327	else if (Cpu.prefix & PREFIX_REP)
1328	{
1329	switch (Cpu.pCurInstr->opcode)
1330	{
1331	case OP_INSB:
1332	case OP_INSWD:
1333	{
1334	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1335	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1336	break;
1337	}
1338
1339	case OP_OUTSB:
1340	case OP_OUTSWD:
1341	{
1342	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1343	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1344	break;
1345	}
1346	}
1347	}
1348
1349	/*
1350	* Handled the I/O return codes.
1351	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1352	*/
1353	if (IOM_SUCCESS(rc))
1354	{
1355	pCtx->rip += Cpu.opsize;
1356	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1357	return rc;
1358	}
1359
1360	if (rc == VINF_EM_RAW_GUEST_TRAP)
1361	{
1362	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1363	rc = emR3RawGuestTrap(pVM);
1364	return rc;
1365	}
1366	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1367
1368	if (VBOX_FAILURE(rc))
1369	{
1370	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1371	return rc;
1372	}
1373	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1374	}
1375	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1376	return emR3RawExecuteInstruction(pVM, "IO: ");
1377	}
1378
1379
1380	/**
1381	* Handle a guest context trap.
1382	*
1383	* @returns VBox status code suitable for EM.
1384	* @param pVM VM handle.
1385	*/
1386	static int emR3RawGuestTrap(PVM pVM)
1387	{
1388	PCPUMCTX pCtx = pVM->em.s.pCtx;
1389
1390	/*
1391	* Get the trap info.
1392	*/
1393	uint8_t u8TrapNo;
1394	TRPMEVENT enmType;;
1395	RTGCUINT uErrorCode;
1396	RTGCUINTPTR uCR2;
1397	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1398	if (VBOX_FAILURE(rc))
1399	{
1400	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1401	return rc;
1402	}
1403
1404	/* Traps can be directly forwarded in hardware accelerated mode. */
1405	if (HWACCMR3IsActive(pVM))
1406	{
1407	#ifdef LOGGING_ENABLED
1408	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1409	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1410	#endif
1411	return VINF_EM_RESCHEDULE_HWACC;
1412	}
1413
1414	/** Scan kernel code that traps; we might not get another chance. */
1415	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1416	&& !pCtx->eflags.Bits.u1VM)
1417	{
1418	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1419	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1420	}
1421
1422	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1423	{
1424	DISCPUSTATE cpu;
1425
1426	/* If MONITOR & MWAIT are supported, then interpret them here. */
1427	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
1428	if ( VBOX_SUCCESS(rc)
1429	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1430	{
1431	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1432
1433	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1434
1435	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1436	{
1437	rc = TRPMResetTrap(pVM);
1438	AssertRC(rc);
1439
1440	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1441	if (VBOX_SUCCESS(rc))
1442	{
1443	pCtx->rip += cpu.opsize;
1444	return rc;
1445	}
1446	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1447	}
1448	}
1449	}
1450	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1451	{
1452	DISCPUSTATE cpu;
1453
1454	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
1455	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1456	{
1457	/*
1458	* We should really check the TSS for the IO bitmap, but it's not like this
1459	* lazy approach really makes things worse.
1460	*/
1461	rc = TRPMResetTrap(pVM);
1462	AssertRC(rc);
1463	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1464	}
1465	}
1466
1467	#ifdef LOG_ENABLED
1468	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1469	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1470
1471	/* Get guest page information. */
1472	uint64_t fFlags = 0;
1473	RTGCPHYS GCPhys = 0;
1474	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1475	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1476	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1477	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1478	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1479	#endif
1480
1481	/*
1482	* #PG has CR2.
1483	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1484	*/
1485	if (u8TrapNo == 14 /* #PG */)
1486	pCtx->cr2 = uCR2;
1487
1488	return VINF_EM_RESCHEDULE_REM;
1489	}
1490
1491
1492	/**
1493	* Handle a ring switch trap.
1494	* Need to do statistics and to install patches. The result is going to REM.
1495	*
1496	* @returns VBox status code suitable for EM.
1497	* @param pVM VM handle.
1498	*/
1499	int emR3RawRingSwitch(PVM pVM)
1500	{
1501	int rc;
1502	DISCPUSTATE Cpu;
1503	PCPUMCTX pCtx = pVM->em.s.pCtx;
1504
1505	/*
1506	* sysenter, syscall & callgate
1507	*/
1508	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
1509	if (VBOX_SUCCESS(rc))
1510	{
1511	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1512	{
1513	if (pCtx->SysEnter.cs != 0)
1514	{
1515	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1516	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1517	if (VBOX_SUCCESS(rc))
1518	{
1519	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1520	return VINF_EM_RESCHEDULE_RAW;
1521	}
1522	}
1523	}
1524
1525	#ifdef VBOX_WITH_STATISTICS
1526	switch (Cpu.pCurInstr->opcode)
1527	{
1528	case OP_SYSENTER:
1529	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1530	break;
1531	case OP_SYSEXIT:
1532	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1533	break;
1534	case OP_SYSCALL:
1535	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1536	break;
1537	case OP_SYSRET:
1538	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1539	break;
1540	}
1541	#endif
1542	}
1543	else
1544	AssertRC(rc);
1545
1546	/* go to the REM to emulate a single instruction */
1547	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1548	}
1549
1550	/**
1551	* Handle a trap (#PF or #GP) in patch code
1552	*
1553	* @returns VBox status code suitable for EM.
1554	* @param pVM VM handle.
1555	* @param pCtx CPU context
1556	* @param gcret GC return code
1557	*/
1558	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1559	{
1560	uint8_t u8TrapNo;
1561	int rc;
1562	TRPMEVENT enmType;
1563	RTGCUINT uErrorCode;
1564	RTGCUINTPTR uCR2;
1565
1566	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1567
1568	if (gcret == VINF_PATM_PATCH_INT3)
1569	{
1570	u8TrapNo = 3;
1571	uCR2 = 0;
1572	uErrorCode = 0;
1573	}
1574	else
1575	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1576	{
1577	/* No active trap in this case. Kind of ugly. */
1578	u8TrapNo = X86_XCPT_GP;
1579	uCR2 = 0;
1580	uErrorCode = 0;
1581	}
1582	else
1583	{
1584	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1585	if (VBOX_FAILURE(rc))
1586	{
1587	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1588	return rc;
1589	}
1590	/* Reset the trap as we'll execute the original instruction again. */
1591	TRPMResetTrap(pVM);
1592	}
1593
1594	/*
1595	* Deal with traps inside patch code.
1596	* (This code won't run outside GC.)
1597	*/
1598	if (u8TrapNo != 1)
1599	{
1600	#ifdef LOG_ENABLED
1601	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1602	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1603
1604	DISCPUSTATE Cpu;
1605	int rc;
1606
1607	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1608	if ( VBOX_SUCCESS(rc)
1609	&& Cpu.pCurInstr->opcode == OP_IRET)
1610	{
1611	uint32_t eip, selCS, uEFlags;
1612
1613	/* Iret crashes are bad as we have already changed the flags on the stack */
1614	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1615	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1616	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1617	if (rc == VINF_SUCCESS)
1618	{
1619	if ( (uEFlags & X86_EFL_VM)
1620	\|\| (selCS & X86_SEL_RPL) == 3)
1621	{
1622	uint32_t selSS, esp;
1623
1624	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1625	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1626
1627	if (uEFlags & X86_EFL_VM)
1628	{
1629	uint32_t selDS, selES, selFS, selGS;
1630	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1631	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1632	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1633	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1634	if (rc == VINF_SUCCESS)
1635	{
1636	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1637	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1638	}
1639	}
1640	else
1641	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1642	}
1643	else
1644	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1645	}
1646	}
1647	#endif
1648	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1649	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
1650
1651	RTGCPTR pNewEip;
1652	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1653	switch (rc)
1654	{
1655	/*
1656	* Execute the faulting instruction.
1657	*/
1658	case VINF_SUCCESS:
1659	{
1660	/** @todo execute a whole block */
1661	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1662	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1663	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1664
1665	pCtx->eip = pNewEip;
1666	AssertRelease(pCtx->eip);
1667
1668	if (pCtx->eflags.Bits.u1IF)
1669	{
1670	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1671	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1672	*/
1673	if ( u8TrapNo == X86_XCPT_GP
1674	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1675	{
1676	/** @todo move to PATMR3HandleTrap */
1677	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1678	PATMR3RemovePatch(pVM, pCtx->eip);
1679	}
1680
1681	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1682	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1683
1684	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1685	/* Interrupts are enabled; just go back to the original instruction.
1686	return VINF_SUCCESS; */
1687	}
1688	return VINF_EM_RESCHEDULE_REM;
1689	}
1690
1691	/*
1692	* One instruction.
1693	*/
1694	case VINF_PATCH_EMULATE_INSTR:
1695	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1696	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1697	pCtx->eip = pNewEip;
1698	AssertRelease(pCtx->eip);
1699	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1700
1701	/*
1702	* The patch was disabled, hand it to the REM.
1703	*/
1704	case VERR_PATCH_DISABLED:
1705	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1706	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1707	pCtx->eip = pNewEip;
1708	AssertRelease(pCtx->eip);
1709
1710	if (pCtx->eflags.Bits.u1IF)
1711	{
1712	/*
1713	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1714	*/
1715	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1716	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1717	}
1718	return VINF_EM_RESCHEDULE_REM;
1719
1720	/* Force continued patch exection; usually due to write monitored stack. */
1721	case VINF_PATCH_CONTINUE:
1722	return VINF_SUCCESS;
1723
1724	/*
1725	* Anything else is fatal.
1726	*/
1727	default:
1728	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1729	return VERR_INTERNAL_ERROR;
1730	}
1731	}
1732	return VINF_SUCCESS;
1733	}
1734
1735
1736	/**
1737	* Handle a privileged instruction.
1738	*
1739	* @returns VBox status code suitable for EM.
1740	* @param pVM VM handle.
1741	*/
1742	int emR3RawPrivileged(PVM pVM)
1743	{
1744	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1745	PCPUMCTX pCtx = pVM->em.s.pCtx;
1746
1747	Assert(!pCtx->eflags.Bits.u1VM);
1748
1749	if (PATMIsEnabled(pVM))
1750	{
1751	/*
1752	* Check if in patch code.
1753	*/
1754	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1755	{
1756	#ifdef LOG_ENABLED
1757	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1758	#endif
1759	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1760	return VERR_EM_RAW_PATCH_CONFLICT;
1761	}
1762	if ( (pCtx->ss & X86_SEL_RPL) == 0
1763	&& !pCtx->eflags.Bits.u1VM
1764	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1765	{
1766	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
1767	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
1768	if (VBOX_SUCCESS(rc))
1769	{
1770	#ifdef LOG_ENABLED
1771	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1772	#endif
1773	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1774	return VINF_SUCCESS;
1775	}
1776	}
1777	}
1778
1779	#ifdef LOG_ENABLED
1780	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1781	{
1782	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1783	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1784	}
1785	#endif
1786
1787	/*
1788	* Instruction statistics and logging.
1789	*/
1790	DISCPUSTATE Cpu;
1791	int rc;
1792
1793	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1794	if (VBOX_SUCCESS(rc))
1795	{
1796	#ifdef VBOX_WITH_STATISTICS
1797	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1798	switch (Cpu.pCurInstr->opcode)
1799	{
1800	case OP_INVLPG:
1801	STAM_COUNTER_INC(&pStats->StatInvlpg);
1802	break;
1803	case OP_IRET:
1804	STAM_COUNTER_INC(&pStats->StatIret);
1805	break;
1806	case OP_CLI:
1807	STAM_COUNTER_INC(&pStats->StatCli);
1808	emR3RecordCli(pVM, pCtx->rip);
1809	break;
1810	case OP_STI:
1811	STAM_COUNTER_INC(&pStats->StatSti);
1812	break;
1813	case OP_INSB:
1814	case OP_INSWD:
1815	case OP_IN:
1816	case OP_OUTSB:
1817	case OP_OUTSWD:
1818	case OP_OUT:
1819	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1820	break;
1821
1822	case OP_MOV_CR:
1823	if (Cpu.param1.flags & USE_REG_GEN32)
1824	{
1825	//read
1826	Assert(Cpu.param2.flags & USE_REG_CR);
1827	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1828	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1829	}
1830	else
1831	{
1832	//write
1833	Assert(Cpu.param1.flags & USE_REG_CR);
1834	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1835	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1836	}
1837	break;
1838
1839	case OP_MOV_DR:
1840	STAM_COUNTER_INC(&pStats->StatMovDRx);
1841	break;
1842	case OP_LLDT:
1843	STAM_COUNTER_INC(&pStats->StatMovLldt);
1844	break;
1845	case OP_LIDT:
1846	STAM_COUNTER_INC(&pStats->StatMovLidt);
1847	break;
1848	case OP_LGDT:
1849	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1850	break;
1851	case OP_SYSENTER:
1852	STAM_COUNTER_INC(&pStats->StatSysEnter);
1853	break;
1854	case OP_SYSEXIT:
1855	STAM_COUNTER_INC(&pStats->StatSysExit);
1856	break;
1857	case OP_SYSCALL:
1858	STAM_COUNTER_INC(&pStats->StatSysCall);
1859	break;
1860	case OP_SYSRET:
1861	STAM_COUNTER_INC(&pStats->StatSysRet);
1862	break;
1863	case OP_HLT:
1864	STAM_COUNTER_INC(&pStats->StatHlt);
1865	break;
1866	default:
1867	STAM_COUNTER_INC(&pStats->StatMisc);
1868	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1869	break;
1870	}
1871	#endif
1872	if ( (pCtx->ss & X86_SEL_RPL) == 0
1873	&& !pCtx->eflags.Bits.u1VM
1874	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1875	{
1876	uint32_t size;
1877
1878	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1879	switch (Cpu.pCurInstr->opcode)
1880	{
1881	case OP_CLI:
1882	pCtx->eflags.u32 &= ~X86_EFL_IF;
1883	Assert(Cpu.opsize == 1);
1884	pCtx->rip += Cpu.opsize;
1885	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1886	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1887
1888	case OP_STI:
1889	pCtx->eflags.u32 \|= X86_EFL_IF;
1890	EMSetInhibitInterruptsPC(pVM, pCtx->rip + Cpu.opsize);
1891	Assert(Cpu.opsize == 1);
1892	pCtx->rip += Cpu.opsize;
1893	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1894	return VINF_SUCCESS;
1895
1896	case OP_HLT:
1897	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1898	{
1899	PATMTRANSSTATE enmState;
1900	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1901
1902	if (enmState == PATMTRANS_OVERWRITTEN)
1903	{
1904	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1905	Assert(rc == VERR_PATCH_DISABLED);
1906	/* Conflict detected, patch disabled */
1907	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1908
1909	enmState = PATMTRANS_SAFE;
1910	}
1911
1912	/* The translation had better be successful. Otherwise we can't recover. */
1913	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1914	if (enmState != PATMTRANS_OVERWRITTEN)
1915	pCtx->eip = pOrgInstrGC;
1916	}
1917	/* no break; we could just return VINF_EM_HALT here */
1918
1919	case OP_MOV_CR:
1920	case OP_MOV_DR:
1921	#ifdef LOG_ENABLED
1922	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1923	{
1924	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1925	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1926	}
1927	#endif
1928
1929	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1930	if (VBOX_SUCCESS(rc))
1931	{
1932	pCtx->rip += Cpu.opsize;
1933	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1934
1935	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1936	&& Cpu.param1.flags == USE_REG_CR /* write */
1937	)
1938	{
1939	/* Reschedule is necessary as the execution/paging mode might have changed. */
1940	return VINF_EM_RESCHEDULE;
1941	}
1942	return rc; /* can return VINF_EM_HALT as well. */
1943	}
1944	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1945	break; /* fall back to the recompiler */
1946	}
1947	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1948	}
1949	}
1950
1951	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1952	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1953
1954	return emR3RawExecuteInstruction(pVM, "PRIV");
1955	}
1956
1957
1958	/**
1959	* Update the forced rawmode execution modifier.
1960	*
1961	* This function is called when we're returning from the raw-mode loop(s). If we're
1962	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1963	* if not in patch code, the flag will be cleared.
1964	*
1965	* We should never interrupt patch code while it's being executed. Cli patches can
1966	* contain big code blocks, but they are always executed with IF=0. Other patches
1967	* replace single instructions and should be atomic.
1968	*
1969	* @returns Updated rc.
1970	*
1971	* @param pVM The VM handle.
1972	* @param pCtx The guest CPU context.
1973	* @param rc The result code.
1974	*/
1975	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1976	{
1977	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1978	{
1979	/* ignore reschedule attempts. */
1980	switch (rc)
1981	{
1982	case VINF_EM_RESCHEDULE:
1983	case VINF_EM_RESCHEDULE_REM:
1984	rc = VINF_SUCCESS;
1985	break;
1986	}
1987	pVM->em.s.fForceRAW = true;
1988	}
1989	else
1990	pVM->em.s.fForceRAW = false;
1991	return rc;
1992	}
1993
1994
1995	/**
1996	* Process a subset of the raw-mode return code.
1997	*
1998	* Since we have to share this with raw-mode single stepping, this inline
1999	* function has been created to avoid code duplication.
2000	*
2001	* @returns VINF_SUCCESS if it's ok to continue raw mode.
2002	* @returns VBox status code to return to the EM main loop.
2003	*
2004	* @param pVM The VM handle
2005	* @param rc The return code.
2006	* @param pCtx The guest cpu context.
2007	*/
2008	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
2009	{
2010	switch (rc)
2011	{
2012	/*
2013	* Common & simple ones.
2014	*/
2015	case VINF_SUCCESS:
2016	break;
2017	case VINF_EM_RESCHEDULE_RAW:
2018	case VINF_EM_RESCHEDULE_HWACC:
2019	case VINF_EM_RAW_INTERRUPT:
2020	case VINF_EM_RAW_TO_R3:
2021	case VINF_EM_RAW_TIMER_PENDING:
2022	case VINF_EM_PENDING_REQUEST:
2023	rc = VINF_SUCCESS;
2024	break;
2025
2026	/*
2027	* Privileged instruction.
2028	*/
2029	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2030	case VINF_PATM_PATCH_TRAP_GP:
2031	rc = emR3RawPrivileged(pVM);
2032	break;
2033
2034	/*
2035	* Got a trap which needs dispatching.
2036	*/
2037	case VINF_EM_RAW_GUEST_TRAP:
2038	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2039	{
2040	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2041	rc = VERR_EM_RAW_PATCH_CONFLICT;
2042	break;
2043	}
2044
2045	Assert(TRPMHasTrap(pVM));
2046	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2047
2048	if (TRPMHasTrap(pVM))
2049	{
2050	uint8_t u8Interrupt;
2051	RTGCUINT uErrorCode;
2052	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2053
2054	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2055	AssertRC(rc);
2056
2057	if (uErrorCode != ~0U)
2058	enmError = TRPM_TRAP_HAS_ERRORCODE;
2059
2060	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2061	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2062	{
2063	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2064	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2065
2066	/** If it was successful, then we could go back to raw mode. */
2067	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2068	{
2069	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2070	EMR3CheckRawForcedActions(pVM);
2071
2072	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP, -1);
2073	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2074	{
2075	TRPMResetTrap(pVM);
2076	return VINF_EM_RESCHEDULE_RAW;
2077	}
2078	}
2079	}
2080	}
2081	rc = emR3RawGuestTrap(pVM);
2082	break;
2083
2084	/*
2085	* Trap in patch code.
2086	*/
2087	case VINF_PATM_PATCH_TRAP_PF:
2088	case VINF_PATM_PATCH_INT3:
2089	rc = emR3PatchTrap(pVM, pCtx, rc);
2090	break;
2091
2092	case VINF_PATM_DUPLICATE_FUNCTION:
2093	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2094	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2095	AssertRC(rc);
2096	rc = VINF_SUCCESS;
2097	break;
2098
2099	case VINF_PATM_CHECK_PATCH_PAGE:
2100	rc = PATMR3HandleMonitoredPage(pVM);
2101	AssertRC(rc);
2102	rc = VINF_SUCCESS;
2103	break;
2104
2105	/*
2106	* Patch manager.
2107	*/
2108	case VERR_EM_RAW_PATCH_CONFLICT:
2109	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2110	break;
2111
2112	/*
2113	* Memory mapped I/O access - attempt to patch the instruction
2114	*/
2115	case VINF_PATM_HC_MMIO_PATCH_READ:
2116	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
2117	PATMFL_MMIO_ACCESS \| ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
2118	if (VBOX_FAILURE(rc))
2119	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2120	break;
2121
2122	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2123	AssertFailed(); /* not yet implemented. */
2124	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2125	break;
2126
2127	/*
2128	* Conflict or out of page tables.
2129	*
2130	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2131	* do here is to execute the pending forced actions.
2132	*/
2133	case VINF_PGM_SYNC_CR3:
2134	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2135	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2136	rc = VINF_SUCCESS;
2137	break;
2138
2139	/*
2140	* Paging mode change.
2141	*/
2142	case VINF_PGM_CHANGE_MODE:
2143	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
2144	if (VBOX_SUCCESS(rc))
2145	rc = VINF_EM_RESCHEDULE;
2146	break;
2147
2148	/*
2149	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2150	*/
2151	case VINF_CSAM_PENDING_ACTION:
2152	rc = VINF_SUCCESS;
2153	break;
2154
2155	/*
2156	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2157	*/
2158	case VINF_EM_RAW_INTERRUPT_PENDING:
2159	case VINF_EM_RAW_RING_SWITCH_INT:
2160	{
2161	uint8_t u8Interrupt;
2162
2163	Assert(TRPMHasTrap(pVM));
2164	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2165
2166	if (TRPMHasTrap(pVM))
2167	{
2168	u8Interrupt = TRPMGetTrapNo(pVM);
2169
2170	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2171	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2172	{
2173	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2174	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2175	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2176	}
2177	}
2178	rc = VINF_EM_RESCHEDULE_REM;
2179	break;
2180	}
2181
2182	/*
2183	* Other ring switch types.
2184	*/
2185	case VINF_EM_RAW_RING_SWITCH:
2186	rc = emR3RawRingSwitch(pVM);
2187	break;
2188
2189	/*
2190	* REMGCNotifyInvalidatePage() failed because of overflow.
2191	*/
2192	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2193	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2194	REMR3ReplayInvalidatedPages(pVM);
2195	rc = VINF_SUCCESS;
2196	break;
2197
2198	/*
2199	* I/O Port access - emulate the instruction.
2200	*/
2201	case VINF_IOM_HC_IOPORT_READ:
2202	case VINF_IOM_HC_IOPORT_WRITE:
2203	rc = emR3RawExecuteIOInstruction(pVM);
2204	break;
2205
2206	/*
2207	* Memory mapped I/O access - emulate the instruction.
2208	*/
2209	case VINF_IOM_HC_MMIO_READ:
2210	case VINF_IOM_HC_MMIO_WRITE:
2211	case VINF_IOM_HC_MMIO_READ_WRITE:
2212	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2213	break;
2214
2215	/*
2216	* Execute instruction.
2217	*/
2218	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2219	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2220	break;
2221	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2222	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2223	break;
2224	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2225	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2226	break;
2227	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2228	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2229	break;
2230	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2231	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2232	break;
2233
2234	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2235	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2236	rc = emR3RawPrivileged(pVM);
2237	break;
2238
2239	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2240	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2241	break;
2242
2243	case VINF_EM_RAW_EMULATE_INSTR:
2244	case VINF_PATCH_EMULATE_INSTR:
2245	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2246	break;
2247
2248	/*
2249	* Stale selector and iret traps => REM.
2250	*/
2251	case VINF_EM_RAW_STALE_SELECTOR:
2252	case VINF_EM_RAW_IRET_TRAP:
2253	/* We will not go to the recompiler if EIP points to patch code. */
2254	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2255	{
2256	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2257	}
2258	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2259	rc = VINF_EM_RESCHEDULE_REM;
2260	break;
2261
2262	/*
2263	* Up a level.
2264	*/
2265	case VINF_EM_TERMINATE:
2266	case VINF_EM_OFF:
2267	case VINF_EM_RESET:
2268	case VINF_EM_SUSPEND:
2269	case VINF_EM_HALT:
2270	case VINF_EM_RESUME:
2271	case VINF_EM_RESCHEDULE:
2272	case VINF_EM_RESCHEDULE_REM:
2273	break;
2274
2275	/*
2276	* Up a level and invoke the debugger.
2277	*/
2278	case VINF_EM_DBG_STEPPED:
2279	case VINF_EM_DBG_BREAKPOINT:
2280	case VINF_EM_DBG_STEP:
2281	case VINF_EM_DBG_HYPER_ASSERTION:
2282	case VINF_EM_DBG_HYPER_BREAKPOINT:
2283	case VINF_EM_DBG_HYPER_STEPPED:
2284	case VINF_EM_DBG_STOP:
2285	break;
2286
2287	/*
2288	* Up a level, dump and debug.
2289	*/
2290	case VERR_TRPM_DONT_PANIC:
2291	case VERR_TRPM_PANIC:
2292	break;
2293
2294	case VERR_VMX_INVALID_VMCS_FIELD:
2295	case VERR_VMX_INVALID_VMCS_PTR:
2296	case VERR_VMX_INVALID_VMXON_PTR:
2297	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
2298	case VERR_VMX_UNEXPECTED_EXCEPTION:
2299	case VERR_VMX_UNEXPECTED_EXIT_CODE:
2300	case VERR_VMX_INVALID_GUEST_STATE:
2301	HWACCMR3CheckError(pVM, rc);
2302	break;
2303	/*
2304	* Anything which is not known to us means an internal error
2305	* and the termination of the VM!
2306	*/
2307	default:
2308	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2309	break;
2310	}
2311	return rc;
2312	}
2313
2314	/**
2315	* Check for pending raw actions
2316	*
2317	* @returns VBox status code.
2318	* @param pVM The VM to operate on.
2319	*/
2320	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2321	{
2322	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2323	}
2324
2325
2326	/**
2327	* Process raw-mode specific forced actions.
2328	*
2329	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2330	*
2331	* @returns VBox status code.
2332	* Only the normal success/failure stuff, no VINF_EM_*.
2333	* @param pVM The VM handle.
2334	* @param pCtx The guest CPUM register context.
2335	*/
2336	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2337	{
2338	/*
2339	* Note that the order is vitally important!
2340	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2341	*/
2342
2343
2344	/*
2345	* Sync selector tables.
2346	*/
2347	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2348	{
2349	int rc = SELMR3UpdateFromCPUM(pVM);
2350	if (VBOX_FAILURE(rc))
2351	return rc;
2352	}
2353
2354	/*
2355	* Sync IDT.
2356	*/
2357	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2358	{
2359	int rc = TRPMR3SyncIDT(pVM);
2360	if (VBOX_FAILURE(rc))
2361	return rc;
2362	}
2363
2364	/*
2365	* Sync TSS.
2366	*/
2367	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2368	{
2369	int rc = SELMR3SyncTSS(pVM);
2370	if (VBOX_FAILURE(rc))
2371	return rc;
2372	}
2373
2374	/*
2375	* Sync page directory.
2376	*/
2377	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2378	{
2379	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2380	if (VBOX_FAILURE(rc))
2381	return rc;
2382
2383	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2384
2385	/* Prefetch pages for EIP and ESP */
2386	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2387	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
2388	if (rc == VINF_SUCCESS)
2389	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
2390	if (rc != VINF_SUCCESS)
2391	{
2392	if (rc != VINF_PGM_SYNC_CR3)
2393	return rc;
2394	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2395	if (VBOX_FAILURE(rc))
2396	return rc;
2397	}
2398	/** @todo maybe prefetch the supervisor stack page as well */
2399	}
2400
2401	/*
2402	* Allocate handy pages (just in case the above actions have consumed some pages).
2403	*/
2404	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
2405	{
2406	int rc = PGMR3PhysAllocateHandyPages(pVM);
2407	if (VBOX_FAILURE(rc))
2408	return rc;
2409	}
2410
2411	return VINF_SUCCESS;
2412	}
2413
2414
2415	/**
2416	* Executes raw code.
2417	*
2418	* This function contains the raw-mode version of the inner
2419	* execution loop (the outer loop being in EMR3ExecuteVM()).
2420	*
2421	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2422	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2423	*
2424	* @param pVM VM handle.
2425	* @param pfFFDone Where to store an indicator telling whether or not
2426	* FFs were done before returning.
2427	*/
2428	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2429	{
2430	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2431
2432	int rc = VERR_INTERNAL_ERROR;
2433	PCPUMCTX pCtx = pVM->em.s.pCtx;
2434	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2435	pVM->em.s.fForceRAW = false;
2436	*pfFFDone = false;
2437
2438
2439	/*
2440	*
2441	* Spin till we get a forced action or raw mode status code resulting in
2442	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2443	*
2444	*/
2445	for (;;)
2446	{
2447	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2448
2449	/*
2450	* Check various preconditions.
2451	*/
2452	#ifdef VBOX_STRICT
2453	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2454	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2455	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2456	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2457	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2458	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2459	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2460	{
2461	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2462	return VERR_INTERNAL_ERROR;
2463	}
2464	#endif /* VBOX_STRICT */
2465
2466	/*
2467	* Process high priority pre-execution raw-mode FFs.
2468	*/
2469	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2470	{
2471	rc = emR3RawForcedActions(pVM, pCtx);
2472	if (VBOX_FAILURE(rc))
2473	break;
2474	}
2475
2476	/*
2477	* If we're going to execute ring-0 code, the guest state needs to
2478	* be modified a bit and some of the state components (IF, SS/CS RPL,
2479	* and perhaps EIP) needs to be stored with PATM.
2480	*/
2481	rc = CPUMRawEnter(pVM, NULL);
2482	if (rc != VINF_SUCCESS)
2483	{
2484	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2485	break;
2486	}
2487
2488	/*
2489	* Scan code before executing it. Don't bother with user mode or V86 code
2490	*/
2491	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2492	&& !pCtx->eflags.Bits.u1VM
2493	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2494	{
2495	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2496	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
2497	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2498	}
2499
2500	#ifdef LOG_ENABLED
2501	/*
2502	* Log important stuff before entering GC.
2503	*/
2504	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2505	if (pCtx->eflags.Bits.u1VM)
2506	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2507	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2508	{
2509	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2510	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2511	}
2512	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2513	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2514	#endif /* LOG_ENABLED */
2515
2516
2517
2518	/*
2519	* Execute the code.
2520	*/
2521	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2522	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2523	VMMR3Unlock(pVM);
2524	rc = VMMR3RawRunGC(pVM);
2525	VMMR3Lock(pVM);
2526	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2527	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2528
2529	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2530	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2531
2532	/*
2533	* Restore the real CPU state and deal with high priority post
2534	* execution FFs before doing anything else.
2535	*/
2536	rc = CPUMRawLeave(pVM, NULL, rc);
2537	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2538	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2539	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2540
2541	#ifdef VBOX_STRICT
2542	/*
2543	* Assert TSS consistency & rc vs patch code.
2544	*/
2545	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2546	&& EMIsRawRing0Enabled(pVM))
2547	SELMR3CheckTSS(pVM);
2548	switch (rc)
2549	{
2550	case VINF_SUCCESS:
2551	case VINF_EM_RAW_INTERRUPT:
2552	case VINF_PATM_PATCH_TRAP_PF:
2553	case VINF_PATM_PATCH_TRAP_GP:
2554	case VINF_PATM_PATCH_INT3:
2555	case VINF_PATM_CHECK_PATCH_PAGE:
2556	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2557	case VINF_EM_RAW_GUEST_TRAP:
2558	case VINF_EM_RESCHEDULE_RAW:
2559	break;
2560
2561	default:
2562	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2563	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VRv for reason %Vrc\n", (RTRCPTR)CPUMGetGuestEIP(pVM), rc));
2564	break;
2565	}
2566	/*
2567	* Let's go paranoid!
2568	*/
2569	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2570	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2571	{
2572	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2573	return VERR_INTERNAL_ERROR;
2574	}
2575	#endif /* VBOX_STRICT */
2576
2577	/*
2578	* Process the returned status code.
2579	*/
2580	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2581	{
2582	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2583	break;
2584	}
2585	rc = emR3RawHandleRC(pVM, pCtx, rc);
2586	if (rc != VINF_SUCCESS)
2587	{
2588	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2589	if (rc != VINF_SUCCESS)
2590	{
2591	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2592	break;
2593	}
2594	}
2595
2596	/*
2597	* Check and execute forced actions.
2598	*/
2599	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2600	TMTimerPoll(pVM);
2601	#endif
2602	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2603	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2604	{
2605	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2606
2607	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2608	rc = emR3ForcedActions(pVM, rc);
2609	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2610	if ( rc != VINF_SUCCESS
2611	&& rc != VINF_EM_RESCHEDULE_RAW)
2612	{
2613	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2614	if (rc != VINF_SUCCESS)
2615	{
2616	*pfFFDone = true;
2617	break;
2618	}
2619	}
2620	}
2621	}
2622
2623	/*
2624	* Return to outer loop.
2625	*/
2626	#if defined(LOG_ENABLED) && defined(DEBUG)
2627	RTLogFlush(NULL);
2628	#endif
2629	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2630	return rc;
2631	}
2632
2633
2634	/**
2635	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2636	*
2637	* This function contains the raw-mode version of the inner
2638	* execution loop (the outer loop being in EMR3ExecuteVM()).
2639	*
2640	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2641	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2642	*
2643	* @param pVM VM handle.
2644	* @param pfFFDone Where to store an indicator telling whether or not
2645	* FFs were done before returning.
2646	*/
2647	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2648	{
2649	int rc = VERR_INTERNAL_ERROR;
2650	PCPUMCTX pCtx = pVM->em.s.pCtx;
2651
2652	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%VGv)\n", pCtx->cs, pCtx->rip));
2653	*pfFFDone = false;
2654
2655	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2656
2657	/*
2658	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2659	*/
2660	for (;;)
2661	{
2662	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2663
2664	/*
2665	* Check various preconditions.
2666	*/
2667	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2668
2669	/*
2670	* Process high priority pre-execution raw-mode FFs.
2671	*/
2672	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2673	{
2674	rc = emR3RawForcedActions(pVM, pCtx);
2675	if (VBOX_FAILURE(rc))
2676	break;
2677	}
2678
2679	#ifdef LOG_ENABLED
2680	uint8_t u8Vector;
2681
2682	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2683	if (rc == VINF_SUCCESS)
2684	{
2685	Log(("Pending hardware interrupt=0x%x ) cs:eip=%04X:%VGv\n", u8Vector, pCtx->cs, pCtx->rip));
2686	}
2687	/*
2688	* Log important stuff before entering GC.
2689	*/
2690	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2691
2692	if (pCtx->eflags.Bits.u1VM)
2693	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2694	else
2695	if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
2696	Log(("HWR%d: %04X:%VGv ESP=%VGv IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2697	else
2698	Log(("HWR%d: %04X:%08X ESP=%08X IF=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
2699	#endif
2700
2701	/*
2702	* Execute the code.
2703	*/
2704	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2705	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2706	VMMR3Unlock(pVM);
2707	rc = VMMR3HwAccRunGC(pVM);
2708	VMMR3Lock(pVM);
2709	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2710
2711	/*
2712	* Deal with high priority post execution FFs before doing anything else.
2713	*/
2714	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2715	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2716	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2717
2718	/*
2719	* Process the returned status code.
2720	*/
2721	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2722	break;
2723
2724	rc = emR3RawHandleRC(pVM, pCtx, rc);
2725	if (rc != VINF_SUCCESS)
2726	break;
2727
2728	/*
2729	* Check and execute forced actions.
2730	*/
2731	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2732	TMTimerPoll(pVM);
2733	#endif
2734	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2735	{
2736	rc = emR3ForcedActions(pVM, rc);
2737	if ( rc != VINF_SUCCESS
2738	&& rc != VINF_EM_RESCHEDULE_HWACC)
2739	{
2740	*pfFFDone = true;
2741	break;
2742	}
2743	}
2744	}
2745	/*
2746	* Return to outer loop.
2747	*/
2748	#if defined(LOG_ENABLED) && defined(DEBUG)
2749	RTLogFlush(NULL);
2750	#endif
2751	return rc;
2752	}
2753
2754
2755	/**
2756	* Decides whether to execute RAW, HWACC or REM.
2757	*
2758	* @returns new EM state
2759	* @param pVM The VM.
2760	* @param pCtx The CPU context.
2761	*/
2762	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2763	{
2764	/*
2765	* When forcing raw-mode execution, things are simple.
2766	*/
2767	if (pVM->em.s.fForceRAW)
2768	return EMSTATE_RAW;
2769
2770	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2771	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2772	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2773
2774	X86EFLAGS EFlags = pCtx->eflags;
2775	if (HWACCMIsEnabled(pVM))
2776	{
2777	/* Hardware accelerated raw-mode:
2778	*
2779	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2780	*/
2781	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2782	return EMSTATE_HWACC;
2783
2784	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2785	return EMSTATE_REM;
2786	}
2787
2788	/* Standard raw-mode:
2789	*
2790	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2791	* or 32 bits protected mode ring 0 code
2792	*
2793	* The tests are ordered by the likelyhood of being true during normal execution.
2794	*/
2795	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2796	{
2797	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2798	return EMSTATE_REM;
2799	}
2800
2801	#ifndef VBOX_RAW_V86
2802	if (EFlags.u32 & X86_EFL_VM) {
2803	Log2(("raw mode refused: VM_MASK\n"));
2804	return EMSTATE_REM;
2805	}
2806	#endif
2807
2808	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2809	uint32_t u32CR0 = pCtx->cr0;
2810	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2811	{
2812	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2813	return EMSTATE_REM;
2814	}
2815
2816	if (pCtx->cr4 & X86_CR4_PAE)
2817	{
2818	uint32_t u32Dummy, u32Features;
2819
2820	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2821	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
2822	return EMSTATE_REM;
2823	}
2824
2825	unsigned uSS = pCtx->ss;
2826	if ( pCtx->eflags.Bits.u1VM
2827	\|\| (uSS & X86_SEL_RPL) == 3)
2828	{
2829	if (!EMIsRawRing3Enabled(pVM))
2830	return EMSTATE_REM;
2831
2832	if (!(EFlags.u32 & X86_EFL_IF))
2833	{
2834	Log2(("raw mode refused: IF (RawR3)\n"));
2835	return EMSTATE_REM;
2836	}
2837
2838	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2839	{
2840	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2841	return EMSTATE_REM;
2842	}
2843	}
2844	else
2845	{
2846	if (!EMIsRawRing0Enabled(pVM))
2847	return EMSTATE_REM;
2848
2849	/* Only ring 0 supervisor code. */
2850	if ((uSS & X86_SEL_RPL) != 0)
2851	{
2852	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2853	return EMSTATE_REM;
2854	}
2855
2856	// Let's start with pure 32 bits ring 0 code first
2857	/** @todo What's pure 32-bit mode? flat? */
2858	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2859	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2860	{
2861	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2862	return EMSTATE_REM;
2863	}
2864
2865	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2866	if (!(u32CR0 & X86_CR0_WP))
2867	{
2868	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2869	return EMSTATE_REM;
2870	}
2871
2872	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2873	{
2874	Log2(("raw r0 mode forced: patch code\n"));
2875	return EMSTATE_RAW;
2876	}
2877
2878	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2879	if (!(EFlags.u32 & X86_EFL_IF))
2880	{
2881	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2882	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2883	return EMSTATE_REM;
2884	}
2885	#endif
2886
2887	/** @todo still necessary??? */
2888	if (EFlags.Bits.u2IOPL != 0)
2889	{
2890	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2891	return EMSTATE_REM;
2892	}
2893	}
2894
2895	Assert(PGMPhysIsA20Enabled(pVM));
2896	return EMSTATE_RAW;
2897	}
2898
2899
2900	/**
2901	* Executes all high priority post execution force actions.
2902	*
2903	* @returns rc or a fatal status code.
2904	*
2905	* @param pVM VM handle.
2906	* @param rc The current rc.
2907	*/
2908	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2909	{
2910	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2911	PDMR3CritSectFF(pVM);
2912
2913	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2914	CSAMR3DoPendingAction(pVM);
2915
2916	return rc;
2917	}
2918
2919
2920	/**
2921	* Executes all pending forced actions.
2922	*
2923	* Forced actions can cause execution delays and execution
2924	* rescheduling. The first we deal with using action priority, so
2925	* that for instance pending timers aren't scheduled and ran until
2926	* right before execution. The rescheduling we deal with using
2927	* return codes. The same goes for VM termination, only in that case
2928	* we exit everything.
2929	*
2930	* @returns VBox status code of equal or greater importance/severity than rc.
2931	* The most important ones are: VINF_EM_RESCHEDULE,
2932	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2933	*
2934	* @param pVM VM handle.
2935	* @param rc The current rc.
2936	*
2937	*/
2938	static int emR3ForcedActions(PVM pVM, int rc)
2939	{
2940	#ifdef VBOX_STRICT
2941	int rcIrq = VINF_SUCCESS;
2942	#endif
2943	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2944
2945	#define UPDATE_RC() \
2946	do { \
2947	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2948	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2949	break; \
2950	if (!rc \|\| rc2 < rc) \
2951	rc = rc2; \
2952	} while (0)
2953
2954	int rc2;
2955
2956	/*
2957	* Post execution chunk first.
2958	*/
2959	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2960	{
2961	/*
2962	* Termination request.
2963	*/
2964	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2965	{
2966	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2967	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2968	return VINF_EM_TERMINATE;
2969	}
2970
2971	/*
2972	* Debugger Facility polling.
2973	*/
2974	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2975	{
2976	rc2 = DBGFR3VMMForcedAction(pVM);
2977	UPDATE_RC();
2978	}
2979
2980	/*
2981	* Postponed reset request.
2982	*/
2983	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2984	{
2985	rc2 = VMR3Reset(pVM);
2986	UPDATE_RC();
2987	VM_FF_CLEAR(pVM, VM_FF_RESET);
2988	}
2989
2990	/*
2991	* CSAM page scanning.
2992	*/
2993	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2994	{
2995	PCPUMCTX pCtx = pVM->em.s.pCtx;
2996
2997	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2998	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2999
3000	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
3001	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
3002	}
3003
3004	/* check that we got them all */
3005	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
3006	}
3007
3008	/*
3009	* Normal priority then.
3010	* (Executed in no particular order.)
3011	*/
3012	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
3013	{
3014	/*
3015	* PDM Queues are pending.
3016	*/
3017	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
3018	PDMR3QueueFlushAll(pVM);
3019
3020	/*
3021	* PDM DMA transfers are pending.
3022	*/
3023	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
3024	PDMR3DmaRun(pVM);
3025
3026	/*
3027	* Requests from other threads.
3028	*/
3029	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
3030	{
3031	rc2 = VMR3ReqProcessU(pVM->pUVM);
3032	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
3033	{
3034	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
3035	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3036	return rc2;
3037	}
3038	UPDATE_RC();
3039	}
3040
3041	/* Replay the handler notification changes. */
3042	if (VM_FF_ISSET(pVM, VM_FF_REM_HANDLER_NOTIFY))
3043	REMR3ReplayHandlerNotifications(pVM);
3044
3045	/* check that we got them all */
3046	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA \| VM_FF_REM_HANDLER_NOTIFY)));
3047	}
3048
3049	/*
3050	* Execute polling function ever so often.
3051	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3052	*/
3053	static unsigned cLast = 0;
3054	if (!((++cLast) % 4))
3055	PDMR3Poll(pVM);
3056
3057	/*
3058	* High priority pre execution chunk last.
3059	* (Executed in ascending priority order.)
3060	*/
3061	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3062	{
3063	/*
3064	* Timers before interrupts.
3065	*/
3066	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3067	TMR3TimerQueuesDo(pVM);
3068
3069	/*
3070	* The instruction following an emulated STI should always be executed!
3071	*/
3072	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3073	{
3074	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", (RTGCPTR)CPUMGetGuestRIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3075	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3076	{
3077	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3078	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3079	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3080	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3081	*/
3082	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3083	}
3084	if (HWACCMR3IsActive(pVM))
3085	rc2 = VINF_EM_RESCHEDULE_HWACC;
3086	else
3087	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3088
3089	UPDATE_RC();
3090	}
3091
3092	/*
3093	* Interrupts.
3094	*/
3095	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3096	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3097	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3098	&& PATMAreInterruptsEnabled(pVM)
3099	&& !HWACCMR3IsEventPending(pVM))
3100	{
3101	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3102	{
3103	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3104	/** @todo this really isn't nice, should properly handle this */
3105	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3106	#ifdef VBOX_STRICT
3107	rcIrq = rc2;
3108	#endif
3109	UPDATE_RC();
3110	}
3111	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3112	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3113	{
3114	rc2 = VINF_EM_RESCHEDULE_REM;
3115	UPDATE_RC();
3116	}
3117	}
3118
3119	/*
3120	* Allocate handy pages.
3121	*/
3122	if (VM_FF_ISSET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
3123	{
3124	rc2 = PGMR3PhysAllocateHandyPages(pVM);
3125	UPDATE_RC();
3126	}
3127
3128	/*
3129	* Debugger Facility request.
3130	*/
3131	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3132	{
3133	rc2 = DBGFR3VMMForcedAction(pVM);
3134	UPDATE_RC();
3135	}
3136
3137	/*
3138	* Termination request.
3139	*/
3140	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3141	{
3142	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3143	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3144	return VINF_EM_TERMINATE;
3145	}
3146
3147	#ifdef DEBUG
3148	/*
3149	* Debug, pause the VM.
3150	*/
3151	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3152	{
3153	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3154	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3155	return VINF_EM_SUSPEND;
3156	}
3157
3158	#endif
3159	/* check that we got them all */
3160	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS \| VM_FF_PGM_NEED_HANDY_PAGES)));
3161	}
3162
3163	#undef UPDATE_RC
3164	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3165	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3166	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3167	return rc;
3168	}
3169
3170
3171	/**
3172	* Execute VM.
3173	*
3174	* This function is the main loop of the VM. The emulation thread
3175	* calls this function when the VM has been successfully constructed
3176	* and we're ready for executing the VM.
3177	*
3178	* Returning from this function means that the VM is turned off or
3179	* suspended (state already saved) and deconstruction in next in line.
3180	*
3181	* All interaction from other thread are done using forced actions
3182	* and signaling of the wait object.
3183	*
3184	* @returns VBox status code.
3185	* @param pVM The VM to operate on.
3186	*/
3187	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3188	{
3189	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3190	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3191	VM_ASSERT_EMT(pVM);
3192	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3193
3194	VMMR3Lock(pVM);
3195
3196	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3197	if (rc == 0)
3198	{
3199	/*
3200	* Start the virtual time.
3201	*/
3202	rc = TMVirtualResume(pVM);
3203	Assert(rc == VINF_SUCCESS);
3204	rc = TMCpuTickResume(pVM);
3205	Assert(rc == VINF_SUCCESS);
3206
3207	/*
3208	* The Outer Main Loop.
3209	*/
3210	bool fFFDone = false;
3211	rc = VINF_EM_RESCHEDULE;
3212	pVM->em.s.enmState = EMSTATE_REM;
3213	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3214	for (;;)
3215	{
3216	/*
3217	* Before we can schedule anything (we're here because
3218	* scheduling is required) we must service any pending
3219	* forced actions to avoid any pending action causing
3220	* immidate rescheduling upon entering an inner loop
3221	*
3222	* Do forced actions.
3223	*/
3224	if ( !fFFDone
3225	&& rc != VINF_EM_TERMINATE
3226	&& rc != VINF_EM_OFF
3227	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3228	{
3229	rc = emR3ForcedActions(pVM, rc);
3230	if ( ( rc == VINF_EM_RESCHEDULE_REM
3231	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3232	&& pVM->em.s.fForceRAW)
3233	rc = VINF_EM_RESCHEDULE_RAW;
3234	}
3235	else if (fFFDone)
3236	fFFDone = false;
3237
3238	/*
3239	* Now what to do?
3240	*/
3241	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3242	switch (rc)
3243	{
3244	/*
3245	* Keep doing what we're currently doing.
3246	*/
3247	case VINF_SUCCESS:
3248	break;
3249
3250	/*
3251	* Reschedule - to raw-mode execution.
3252	*/
3253	case VINF_EM_RESCHEDULE_RAW:
3254	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3255	pVM->em.s.enmState = EMSTATE_RAW;
3256	break;
3257
3258	/*
3259	* Reschedule - to hardware accelerated raw-mode execution.
3260	*/
3261	case VINF_EM_RESCHEDULE_HWACC:
3262	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3263	Assert(!pVM->em.s.fForceRAW);
3264	pVM->em.s.enmState = EMSTATE_HWACC;
3265	break;
3266
3267	/*
3268	* Reschedule - to recompiled execution.
3269	*/
3270	case VINF_EM_RESCHEDULE_REM:
3271	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3272	pVM->em.s.enmState = EMSTATE_REM;
3273	break;
3274
3275	/*
3276	* Resume.
3277	*/
3278	case VINF_EM_RESUME:
3279	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3280	/* fall through and get scheduled. */
3281
3282	/*
3283	* Reschedule.
3284	*/
3285	case VINF_EM_RESCHEDULE:
3286	{
3287	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3288	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3289	pVM->em.s.enmState = enmState;
3290	break;
3291	}
3292
3293	/*
3294	* Halted.
3295	*/
3296	case VINF_EM_HALT:
3297	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3298	pVM->em.s.enmState = EMSTATE_HALTED;
3299	break;
3300
3301	/*
3302	* Suspend.
3303	*/
3304	case VINF_EM_SUSPEND:
3305	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3306	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3307	break;
3308
3309	/*
3310	* Reset.
3311	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3312	*/
3313	case VINF_EM_RESET:
3314	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3315	pVM->em.s.enmState = EMSTATE_REM;
3316	break;
3317
3318	/*
3319	* Power Off.
3320	*/
3321	case VINF_EM_OFF:
3322	pVM->em.s.enmState = EMSTATE_TERMINATING;
3323	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3324	TMVirtualPause(pVM);
3325	TMCpuTickPause(pVM);
3326	VMMR3Unlock(pVM);
3327	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3328	return rc;
3329
3330	/*
3331	* Terminate the VM.
3332	*/
3333	case VINF_EM_TERMINATE:
3334	pVM->em.s.enmState = EMSTATE_TERMINATING;
3335	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3336	TMVirtualPause(pVM);
3337	TMCpuTickPause(pVM);
3338	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3339	return rc;
3340
3341	/*
3342	* Guest debug events.
3343	*/
3344	case VINF_EM_DBG_STEPPED:
3345	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3346	case VINF_EM_DBG_STOP:
3347	case VINF_EM_DBG_BREAKPOINT:
3348	case VINF_EM_DBG_STEP:
3349	if (pVM->em.s.enmState == EMSTATE_RAW)
3350	{
3351	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3352	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3353	}
3354	else
3355	{
3356	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3357	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3358	}
3359	break;
3360
3361	/*
3362	* Hypervisor debug events.
3363	*/
3364	case VINF_EM_DBG_HYPER_STEPPED:
3365	case VINF_EM_DBG_HYPER_BREAKPOINT:
3366	case VINF_EM_DBG_HYPER_ASSERTION:
3367	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3368	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3369	break;
3370
3371	/*
3372	* Any error code showing up here other than the ones we
3373	* know and process above are considered to be FATAL.
3374	*
3375	* Unknown warnings and informational status codes are also
3376	* included in this.
3377	*/
3378	default:
3379	if (VBOX_SUCCESS(rc))
3380	{
3381	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3382	rc = VERR_EM_INTERNAL_ERROR;
3383	}
3384	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3385	Log(("EMR3ExecuteVM returns %d\n", rc));
3386	break;
3387	}
3388
3389
3390	/*
3391	* Any waiters can now be woken up
3392	*/
3393	VMMR3Unlock(pVM);
3394	VMMR3Lock(pVM);
3395
3396	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3397	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3398
3399	/*
3400	* Act on the state.
3401	*/
3402	switch (pVM->em.s.enmState)
3403	{
3404	/*
3405	* Execute raw.
3406	*/
3407	case EMSTATE_RAW:
3408	rc = emR3RawExecute(pVM, &fFFDone);
3409	break;
3410
3411	/*
3412	* Execute hardware accelerated raw.
3413	*/
3414	case EMSTATE_HWACC:
3415	rc = emR3HwAccExecute(pVM, &fFFDone);
3416	break;
3417
3418	/*
3419	* Execute recompiled.
3420	*/
3421	case EMSTATE_REM:
3422	rc = emR3RemExecute(pVM, &fFFDone);
3423	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3424	break;
3425
3426	/*
3427	* hlt - execution halted until interrupt.
3428	*/
3429	case EMSTATE_HALTED:
3430	{
3431	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3432	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3433	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3434	break;
3435	}
3436
3437	/*
3438	* Suspended - return to VM.cpp.
3439	*/
3440	case EMSTATE_SUSPENDED:
3441	TMVirtualPause(pVM);
3442	TMCpuTickPause(pVM);
3443	VMMR3Unlock(pVM);
3444	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3445	return VINF_EM_SUSPEND;
3446
3447	/*
3448	* Debugging in the guest.
3449	*/
3450	case EMSTATE_DEBUG_GUEST_REM:
3451	case EMSTATE_DEBUG_GUEST_RAW:
3452	TMVirtualPause(pVM);
3453	TMCpuTickPause(pVM);
3454	rc = emR3Debug(pVM, rc);
3455	TMVirtualResume(pVM);
3456	TMCpuTickResume(pVM);
3457	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3458	break;
3459
3460	/*
3461	* Debugging in the hypervisor.
3462	*/
3463	case EMSTATE_DEBUG_HYPER:
3464	{
3465	TMVirtualPause(pVM);
3466	TMCpuTickPause(pVM);
3467	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3468
3469	rc = emR3Debug(pVM, rc);
3470	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3471	if (rc != VINF_SUCCESS)
3472	{
3473	/* switch to guru meditation mode */
3474	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3475	VMMR3FatalDump(pVM, rc);
3476	return rc;
3477	}
3478
3479	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3480	TMVirtualResume(pVM);
3481	TMCpuTickResume(pVM);
3482	break;
3483	}
3484
3485	/*
3486	* Guru meditation takes place in the debugger.
3487	*/
3488	case EMSTATE_GURU_MEDITATION:
3489	{
3490	TMVirtualPause(pVM);
3491	TMCpuTickPause(pVM);
3492	VMMR3FatalDump(pVM, rc);
3493	emR3Debug(pVM, rc);
3494	VMMR3Unlock(pVM);
3495	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3496	return rc;
3497	}
3498
3499	/*
3500	* The states we don't expect here.
3501	*/
3502	case EMSTATE_NONE:
3503	case EMSTATE_TERMINATING:
3504	default:
3505	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3506	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3507	TMVirtualPause(pVM);
3508	TMCpuTickPause(pVM);
3509	VMMR3Unlock(pVM);
3510	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3511	return VERR_EM_INTERNAL_ERROR;
3512	}
3513	} /* The Outer Main Loop */
3514	}
3515	else
3516	{
3517	/*
3518	* Fatal error.
3519	*/
3520	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3521	TMVirtualPause(pVM);
3522	TMCpuTickPause(pVM);
3523	VMMR3FatalDump(pVM, rc);
3524	emR3Debug(pVM, rc);
3525	VMMR3Unlock(pVM);
3526	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3527	/** @todo change the VM state! */
3528	return rc;
3529	}
3530
3531	/* (won't ever get here). */
3532	AssertFailed();
3533	}
3534

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 12600

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