EM.cpp@ 4041

Last change on this file since 4041 was 4013, checked in by vboxsync, 17 years ago
pdm.h = include pdm*.h; pdmapi.h = only the 'core' pdm APIs.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 139.1 KB

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1	/* $Id: EM.cpp 4013 2007-08-03 00:11:38Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor/Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_em EM - The Execution Monitor/Manager
24	*
25	* The Execution Monitor/Manager is responsible for running the VM, scheduling
26	* the right kind of execution (Raw, Recompiled, Interpreted,..), and keeping
27	* the CPU states in sync. The function RMR3ExecuteVM() is the 'main-loop' of
28	* the VM.
29	*
30	*/
31
32	/*******************************************************************************
33	* Header Files *
34	*******************************************************************************/
35	#define LOG_GROUP LOG_GROUP_EM
36	#include <VBox/em.h>
37	#include <VBox/vmm.h>
38	#include <VBox/patm.h>
39	#include <VBox/csam.h>
40	#include <VBox/selm.h>
41	#include <VBox/trpm.h>
42	#include <VBox/iom.h>
43	#include <VBox/dbgf.h>
44	#include <VBox/pgm.h>
45	#include <VBox/rem.h>
46	#include <VBox/tm.h>
47	#include <VBox/mm.h>
48	#include <VBox/ssm.h>
49	#include <VBox/pdmapi.h>
50	#include <VBox/pdmcritsect.h>
51	#include <VBox/pdmqueue.h>
52	#include <VBox/hwaccm.h>
53	#include <VBox/patm.h>
54	#include "EMInternal.h"
55	#include <VBox/vm.h>
56	#include <VBox/cpumdis.h>
57	#include <VBox/dis.h>
58	#include <VBox/disopcode.h>
59	#include <VBox/dbgf.h>
60
61	#include <VBox/log.h>
62	#include <iprt/thread.h>
63	#include <iprt/assert.h>
64	#include <iprt/asm.h>
65	#include <iprt/semaphore.h>
66	#include <iprt/string.h>
67	#include <iprt/avl.h>
68	#include <iprt/stream.h>
69	#include <VBox/param.h>
70	#include <VBox/err.h>
71
72
73	/*******************************************************************************
74	* Internal Functions *
75	*******************************************************************************/
76	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
77	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
78	static int emR3Debug(PVM pVM, int rc);
79	static int emR3RemStep(PVM pVM);
80	static int emR3RemExecute(PVM pVM, bool *pfFFDone);
81	static int emR3RawResumeHyper(PVM pVM);
82	static int emR3RawStep(PVM pVM);
83	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc);
84	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc);
85	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx);
86	static int emR3RawExecute(PVM pVM, bool *pfFFDone);
87	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC = VINF_SUCCESS);
88	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc);
89	static int emR3ForcedActions(PVM pVM, int rc);
90	static int emR3RawGuestTrap(PVM pVM);
91
92
93	/**
94	* Initializes the EM.
95	*
96	* @returns VBox status code.
97	* @param pVM The VM to operate on.
98	*/
99	EMR3DECL(int) EMR3Init(PVM pVM)
100	{
101	LogFlow(("EMR3Init\n"));
102	/*
103	* Assert alignment and sizes.
104	*/
105	AssertRelease(!(RT_OFFSETOF(VM, em.s) & 31));
106	AssertRelease(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
107	AssertReleaseMsg(sizeof(pVM->em.s.u.FatalLongJump) <= sizeof(pVM->em.s.u.achPaddingFatalLongJump),
108	("%d bytes, padding %d\n", sizeof(pVM->em.s.u.FatalLongJump), sizeof(pVM->em.s.u.achPaddingFatalLongJump)));
109
110	/*
111	* Init the structure.
112	*/
113	pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
114	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &pVM->fRawR3Enabled);
115	if (VBOX_FAILURE(rc))
116	pVM->fRawR3Enabled = true;
117	rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &pVM->fRawR0Enabled);
118	if (VBOX_FAILURE(rc))
119	pVM->fRawR0Enabled = true;
120	Log(("EMR3Init: fRawR3Enabled=%d fRawR0Enabled=%d\n", pVM->fRawR3Enabled, pVM->fRawR0Enabled));
121	pVM->em.s.enmState = EMSTATE_NONE;
122	pVM->em.s.fForceRAW = false;
123
124	rc = CPUMQueryGuestCtxPtr(pVM, &pVM->em.s.pCtx);
125	AssertMsgRC(rc, ("CPUMQueryGuestCtxPtr -> %Vrc\n", rc));
126	pVM->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
127	AssertMsg(pVM->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
128
129	/*
130	* Saved state.
131	*/
132	rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
133	NULL, emR3Save, NULL,
134	NULL, emR3Load, NULL);
135	if (VBOX_FAILURE(rc))
136	return rc;
137
138	/*
139	* Statistics.
140	*/
141	#ifdef VBOX_WITH_STATISTICS
142	PEMSTATS pStats;
143	rc = MMHyperAlloc(pVM, sizeof(pStats), 0, MM_TAG_EM, (void *)&pStats);
144	if (VBOX_FAILURE(rc))
145	return rc;
146	pVM->em.s.pStatsHC = pStats;
147	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pStats);
148
149	STAM_REG(pVM, &pStats->StatGCEmulate, STAMTYPE_PROFILE, "/EM/GC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
150	STAM_REG(pVM, &pStats->StatHCEmulate, STAMTYPE_PROFILE, "/EM/HC/Interpret", STAMUNIT_TICKS_PER_CALL, "Profiling of EMInterpretInstruction.");
151
152	STAM_REG(pVM, &pStats->StatGCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
153	STAM_REG(pVM, &pStats->StatHCInterpretSucceeded, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success", STAMUNIT_OCCURENCES, "The number of times an instruction was successfully interpreted.");
154
155	STAM_REG_USED(pVM, &pStats->StatGCAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
156	STAM_REG_USED(pVM, &pStats->StatHCAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/And", STAMUNIT_OCCURENCES, "The number of times AND was successfully interpreted.");
157	STAM_REG_USED(pVM, &pStats->StatGCAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
158	STAM_REG_USED(pVM, &pStats->StatHCAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Add", STAMUNIT_OCCURENCES, "The number of times ADD was successfully interpreted.");
159	STAM_REG_USED(pVM, &pStats->StatGCAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
160	STAM_REG_USED(pVM, &pStats->StatHCAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was successfully interpreted.");
161	STAM_REG_USED(pVM, &pStats->StatGCSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
162	STAM_REG_USED(pVM, &pStats->StatHCSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was successfully interpreted.");
163	STAM_REG_USED(pVM, &pStats->StatGCCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
164	STAM_REG_USED(pVM, &pStats->StatHCCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was successfully interpreted.");
165	STAM_REG_USED(pVM, &pStats->StatGCDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
166	STAM_REG_USED(pVM, &pStats->StatHCDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was successfully interpreted.");
167	STAM_REG_USED(pVM, &pStats->StatGCHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
168	STAM_REG_USED(pVM, &pStats->StatHCHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was successfully interpreted.");
169	STAM_REG_USED(pVM, &pStats->StatGCInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
170	STAM_REG_USED(pVM, &pStats->StatHCInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Inc", STAMUNIT_OCCURENCES, "The number of times INC was successfully interpreted.");
171	STAM_REG_USED(pVM, &pStats->StatGCInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
172	STAM_REG_USED(pVM, &pStats->StatHCInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Invlpg", STAMUNIT_OCCURENCES, "The number of times INVLPG was successfully interpreted.");
173	STAM_REG_USED(pVM, &pStats->StatGCIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
174	STAM_REG_USED(pVM, &pStats->StatHCIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was successfully interpreted.");
175	STAM_REG_USED(pVM, &pStats->StatGCLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
176	STAM_REG_USED(pVM, &pStats->StatHCLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was successfully interpreted.");
177	STAM_REG_USED(pVM, &pStats->StatGCMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
178	STAM_REG_USED(pVM, &pStats->StatHCMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was successfully interpreted.");
179	STAM_REG_USED(pVM, &pStats->StatGCMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
180	STAM_REG_USED(pVM, &pStats->StatHCMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was successfully interpreted.");
181	STAM_REG_USED(pVM, &pStats->StatGCMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
182	STAM_REG_USED(pVM, &pStats->StatHCMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was successfully interpreted.");
183	STAM_REG_USED(pVM, &pStats->StatGCOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
184	STAM_REG_USED(pVM, &pStats->StatHCOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Or", STAMUNIT_OCCURENCES, "The number of times OR was successfully interpreted.");
185	STAM_REG_USED(pVM, &pStats->StatGCPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
186	STAM_REG_USED(pVM, &pStats->StatHCPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Pop", STAMUNIT_OCCURENCES, "The number of times POP was successfully interpreted.");
187	STAM_REG_USED(pVM, &pStats->StatGCRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
188	STAM_REG_USED(pVM, &pStats->StatHCRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was successfully interpreted.");
189	STAM_REG_USED(pVM, &pStats->StatGCSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
190	STAM_REG_USED(pVM, &pStats->StatHCSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Sti", STAMUNIT_OCCURENCES, "The number of times STI was successfully interpreted.");
191	STAM_REG_USED(pVM, &pStats->StatGCXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
192	STAM_REG_USED(pVM, &pStats->StatHCXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was successfully interpreted.");
193	STAM_REG_USED(pVM, &pStats->StatGCXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
194	STAM_REG_USED(pVM, &pStats->StatHCXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was successfully interpreted.");
195	STAM_REG_USED(pVM, &pStats->StatGCMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
196	STAM_REG_USED(pVM, &pStats->StatHCMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was successfully interpreted.");
197	STAM_REG_USED(pVM, &pStats->StatGCMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
198	STAM_REG_USED(pVM, &pStats->StatHCMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/MWait", STAMUNIT_OCCURENCES, "The number of times MWAIT was successfully interpreted.");
199	STAM_REG_USED(pVM, &pStats->StatGCBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
200	STAM_REG_USED(pVM, &pStats->StatHCBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was successfully interpreted.");
201	STAM_REG_USED(pVM, &pStats->StatGCBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
202	STAM_REG_USED(pVM, &pStats->StatHCBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was successfully interpreted.");
203	STAM_REG_USED(pVM, &pStats->StatGCBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
204	STAM_REG_USED(pVM, &pStats->StatHCBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was successfully interpreted.");
205	STAM_REG_USED(pVM, &pStats->StatGCCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
206	STAM_REG_USED(pVM, &pStats->StatHCCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Success/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was successfully interpreted.");
207
208	STAM_REG(pVM, &pStats->StatGCInterpretFailed, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
209	STAM_REG(pVM, &pStats->StatHCInterpretFailed, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed", STAMUNIT_OCCURENCES, "The number of times an instruction was not interpreted.");
210
211	STAM_REG_USED(pVM, &pStats->StatGCFailedAnd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
212	STAM_REG_USED(pVM, &pStats->StatHCFailedAnd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/And", STAMUNIT_OCCURENCES, "The number of times AND was not interpreted.");
213	STAM_REG_USED(pVM, &pStats->StatGCFailedCpuId, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
214	STAM_REG_USED(pVM, &pStats->StatHCFailedCpuId, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CpuId", STAMUNIT_OCCURENCES, "The number of times CPUID was not interpreted.");
215	STAM_REG_USED(pVM, &pStats->StatGCFailedDec, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
216	STAM_REG_USED(pVM, &pStats->StatHCFailedDec, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Dec", STAMUNIT_OCCURENCES, "The number of times DEC was not interpreted.");
217	STAM_REG_USED(pVM, &pStats->StatGCFailedHlt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
218	STAM_REG_USED(pVM, &pStats->StatHCFailedHlt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Hlt", STAMUNIT_OCCURENCES, "The number of times HLT was not interpreted.");
219	STAM_REG_USED(pVM, &pStats->StatGCFailedInc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
220	STAM_REG_USED(pVM, &pStats->StatHCFailedInc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Inc", STAMUNIT_OCCURENCES, "The number of times INC was not interpreted.");
221	STAM_REG_USED(pVM, &pStats->StatGCFailedInvlPg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
222	STAM_REG_USED(pVM, &pStats->StatHCFailedInvlPg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/InvlPg", STAMUNIT_OCCURENCES, "The number of times INVLPG was not interpreted.");
223	STAM_REG_USED(pVM, &pStats->StatGCFailedIret, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
224	STAM_REG_USED(pVM, &pStats->StatHCFailedIret, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Iret", STAMUNIT_OCCURENCES, "The number of times IRET was not interpreted.");
225	STAM_REG_USED(pVM, &pStats->StatGCFailedLLdt, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
226	STAM_REG_USED(pVM, &pStats->StatHCFailedLLdt, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/LLdt", STAMUNIT_OCCURENCES, "The number of times LLDT was not interpreted.");
227	STAM_REG_USED(pVM, &pStats->StatGCFailedMov, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
228	STAM_REG_USED(pVM, &pStats->StatHCFailedMov, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Mov", STAMUNIT_OCCURENCES, "The number of times MOV was not interpreted.");
229	STAM_REG_USED(pVM, &pStats->StatGCFailedMovCRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
230	STAM_REG_USED(pVM, &pStats->StatHCFailedMovCRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovCRx", STAMUNIT_OCCURENCES, "The number of times MOV CRx was not interpreted.");
231	STAM_REG_USED(pVM, &pStats->StatGCFailedMovDRx, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
232	STAM_REG_USED(pVM, &pStats->StatHCFailedMovDRx, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovDRx", STAMUNIT_OCCURENCES, "The number of times MOV DRx was not interpreted.");
233	STAM_REG_USED(pVM, &pStats->StatGCFailedOr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
234	STAM_REG_USED(pVM, &pStats->StatHCFailedOr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Or", STAMUNIT_OCCURENCES, "The number of times OR was not interpreted.");
235	STAM_REG_USED(pVM, &pStats->StatGCFailedPop, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
236	STAM_REG_USED(pVM, &pStats->StatHCFailedPop, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Pop", STAMUNIT_OCCURENCES, "The number of times POP was not interpreted.");
237	STAM_REG_USED(pVM, &pStats->StatGCFailedSti, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
238	STAM_REG_USED(pVM, &pStats->StatHCFailedSti, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sti", STAMUNIT_OCCURENCES, "The number of times STI was not interpreted.");
239	STAM_REG_USED(pVM, &pStats->StatGCFailedXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
240	STAM_REG_USED(pVM, &pStats->StatHCFailedXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xchg", STAMUNIT_OCCURENCES, "The number of times XCHG was not interpreted.");
241	STAM_REG_USED(pVM, &pStats->StatGCFailedXor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
242	STAM_REG_USED(pVM, &pStats->StatHCFailedXor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Xor", STAMUNIT_OCCURENCES, "The number of times XOR was not interpreted.");
243	STAM_REG_USED(pVM, &pStats->StatGCFailedMonitor, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
244	STAM_REG_USED(pVM, &pStats->StatHCFailedMonitor, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Monitor", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
245	STAM_REG_USED(pVM, &pStats->StatGCFailedMWait, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
246	STAM_REG_USED(pVM, &pStats->StatHCFailedMWait, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MWait", STAMUNIT_OCCURENCES, "The number of times MONITOR was not interpreted.");
247	STAM_REG_USED(pVM, &pStats->StatGCFailedRdtsc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
248	STAM_REG_USED(pVM, &pStats->StatHCFailedRdtsc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Rdtsc", STAMUNIT_OCCURENCES, "The number of times RDTSC was not interpreted.");
249
250	STAM_REG_USED(pVM, &pStats->StatGCFailedMisc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
251	STAM_REG_USED(pVM, &pStats->StatHCFailedMisc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Misc", STAMUNIT_OCCURENCES, "The number of times some misc instruction was encountered.");
252	STAM_REG_USED(pVM, &pStats->StatGCFailedAdd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
253	STAM_REG_USED(pVM, &pStats->StatHCFailedAdd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Add", STAMUNIT_OCCURENCES, "The number of times ADD was not interpreted.");
254	STAM_REG_USED(pVM, &pStats->StatGCFailedAdc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
255	STAM_REG_USED(pVM, &pStats->StatHCFailedAdc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Adc", STAMUNIT_OCCURENCES, "The number of times ADC was not interpreted.");
256	STAM_REG_USED(pVM, &pStats->StatGCFailedBtr, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
257	STAM_REG_USED(pVM, &pStats->StatHCFailedBtr, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btr", STAMUNIT_OCCURENCES, "The number of times BTR was not interpreted.");
258	STAM_REG_USED(pVM, &pStats->StatGCFailedBts, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
259	STAM_REG_USED(pVM, &pStats->StatHCFailedBts, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Bts", STAMUNIT_OCCURENCES, "The number of times BTS was not interpreted.");
260	STAM_REG_USED(pVM, &pStats->StatGCFailedBtc, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
261	STAM_REG_USED(pVM, &pStats->StatHCFailedBtc, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Btc", STAMUNIT_OCCURENCES, "The number of times BTC was not interpreted.");
262	STAM_REG_USED(pVM, &pStats->StatGCFailedCli, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
263	STAM_REG_USED(pVM, &pStats->StatHCFailedCli, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Cli", STAMUNIT_OCCURENCES, "The number of times CLI was not interpreted.");
264	STAM_REG_USED(pVM, &pStats->StatGCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
265	STAM_REG_USED(pVM, &pStats->StatHCFailedCmpXchg, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/CmpXchg", STAMUNIT_OCCURENCES, "The number of times CMPXCHG was not interpreted.");
266	STAM_REG_USED(pVM, &pStats->StatGCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
267	STAM_REG_USED(pVM, &pStats->StatHCFailedMovNTPS, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/MovNTPS", STAMUNIT_OCCURENCES, "The number of times MOVNTPS was not interpreted.");
268	STAM_REG_USED(pVM, &pStats->StatGCFailedStosWD, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
269	STAM_REG_USED(pVM, &pStats->StatHCFailedStosWD, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/StosWD", STAMUNIT_OCCURENCES, "The number of times STOSWD was not interpreted.");
270	STAM_REG_USED(pVM, &pStats->StatGCFailedSub, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
271	STAM_REG_USED(pVM, &pStats->StatHCFailedSub, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Sub", STAMUNIT_OCCURENCES, "The number of times SUB was not interpreted.");
272	STAM_REG_USED(pVM, &pStats->StatGCFailedWbInvd, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
273	STAM_REG_USED(pVM, &pStats->StatHCFailedWbInvd, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/WbInvd", STAMUNIT_OCCURENCES, "The number of times WBINVD was not interpreted.");
274
275	STAM_REG_USED(pVM, &pStats->StatGCFailedUserMode, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
276	STAM_REG_USED(pVM, &pStats->StatHCFailedUserMode, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/UserMode", STAMUNIT_OCCURENCES, "The number of rejections because of CPL.");
277	STAM_REG_USED(pVM, &pStats->StatGCFailedPrefix, STAMTYPE_COUNTER, "/EM/GC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
278	STAM_REG_USED(pVM, &pStats->StatHCFailedPrefix, STAMTYPE_COUNTER, "/EM/HC/Interpret/Failed/Prefix", STAMUNIT_OCCURENCES, "The number of rejections because of prefix .");
279
280	STAM_REG_USED(pVM, &pStats->StatCli, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Cli", STAMUNIT_OCCURENCES, "Number of cli instructions.");
281	STAM_REG_USED(pVM, &pStats->StatSti, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sti", STAMUNIT_OCCURENCES, "Number of sli instructions.");
282	STAM_REG_USED(pVM, &pStats->StatIn, STAMTYPE_COUNTER, "/EM/HC/PrivInst/In", STAMUNIT_OCCURENCES, "Number of in instructions.");
283	STAM_REG_USED(pVM, &pStats->StatOut, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Out", STAMUNIT_OCCURENCES, "Number of out instructions.");
284	STAM_REG_USED(pVM, &pStats->StatHlt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Hlt", STAMUNIT_OCCURENCES, "Number of hlt instructions not handled in GC because of PATM.");
285	STAM_REG_USED(pVM, &pStats->StatInvlpg, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Invlpg", STAMUNIT_OCCURENCES, "Number of invlpg instructions.");
286	STAM_REG_USED(pVM, &pStats->StatMisc, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Misc", STAMUNIT_OCCURENCES, "Number of misc. instructions.");
287	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR0, X", STAMUNIT_OCCURENCES, "Number of mov CR0 read instructions.");
288	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR1, X", STAMUNIT_OCCURENCES, "Number of mov CR1 read instructions.");
289	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR2, X", STAMUNIT_OCCURENCES, "Number of mov CR2 read instructions.");
290	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR3, X", STAMUNIT_OCCURENCES, "Number of mov CR3 read instructions.");
291	STAM_REG_USED(pVM, &pStats->StatMovWriteCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov CR4, X", STAMUNIT_OCCURENCES, "Number of mov CR4 read instructions.");
292	STAM_REG_USED(pVM, &pStats->StatMovReadCR[0], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR0", STAMUNIT_OCCURENCES, "Number of mov CR0 write instructions.");
293	STAM_REG_USED(pVM, &pStats->StatMovReadCR[1], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR1", STAMUNIT_OCCURENCES, "Number of mov CR1 write instructions.");
294	STAM_REG_USED(pVM, &pStats->StatMovReadCR[2], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR2", STAMUNIT_OCCURENCES, "Number of mov CR2 write instructions.");
295	STAM_REG_USED(pVM, &pStats->StatMovReadCR[3], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR3", STAMUNIT_OCCURENCES, "Number of mov CR3 write instructions.");
296	STAM_REG_USED(pVM, &pStats->StatMovReadCR[4], STAMTYPE_COUNTER, "/EM/HC/PrivInst/Mov X, CR4", STAMUNIT_OCCURENCES, "Number of mov CR4 write instructions.");
297	STAM_REG_USED(pVM, &pStats->StatMovDRx, STAMTYPE_COUNTER, "/EM/HC/PrivInst/MovDRx", STAMUNIT_OCCURENCES, "Number of mov DRx instructions.");
298	STAM_REG_USED(pVM, &pStats->StatIret, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Iret", STAMUNIT_OCCURENCES, "Number of iret instructions.");
299	STAM_REG_USED(pVM, &pStats->StatMovLgdt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lgdt", STAMUNIT_OCCURENCES, "Number of lgdt instructions.");
300	STAM_REG_USED(pVM, &pStats->StatMovLidt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lidt", STAMUNIT_OCCURENCES, "Number of lidt instructions.");
301	STAM_REG_USED(pVM, &pStats->StatMovLldt, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Lldt", STAMUNIT_OCCURENCES, "Number of lldt instructions.");
302	STAM_REG_USED(pVM, &pStats->StatSysEnter, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysenter", STAMUNIT_OCCURENCES, "Number of sysenter instructions.");
303	STAM_REG_USED(pVM, &pStats->StatSysExit, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysexit", STAMUNIT_OCCURENCES, "Number of sysexit instructions.");
304	STAM_REG_USED(pVM, &pStats->StatSysCall, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Syscall", STAMUNIT_OCCURENCES, "Number of syscall instructions.");
305	STAM_REG_USED(pVM, &pStats->StatSysRet, STAMTYPE_COUNTER, "/EM/HC/PrivInst/Sysret", STAMUNIT_OCCURENCES, "Number of sysret instructions.");
306
307	STAM_REG(pVM, &pVM->em.s.StatTotalClis, STAMTYPE_COUNTER, "/EM/Cli/Total", STAMUNIT_OCCURENCES, "Total number of cli instructions executed.");
308	pVM->em.s.pCliStatTree = 0;
309	#endif /* VBOX_WITH_STATISTICS */
310
311	/* these should be considered for release statistics. */
312	STAM_REG(pVM, &pVM->em.s.StatForcedActions, STAMTYPE_PROFILE, "/PROF/EM/ForcedActions", STAMUNIT_TICKS_PER_CALL, "Profiling forced action execution.");
313	STAM_REL_REG(pVM, &pVM->em.s.StatHalted, STAMTYPE_PROFILE, "/PROF/EM/Halted", STAMUNIT_TICKS_PER_CALL, "Profiling halted state (VMR3WaitHalted).");
314	STAM_REG(pVM, &pVM->em.s.StatHwAccEntry, STAMTYPE_PROFILE, "/PROF/EM/HwAccEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode entry overhead.");
315	STAM_REG(pVM, &pVM->em.s.StatHwAccExec, STAMTYPE_PROFILE, "/PROF/EM/HwAccExec", STAMUNIT_TICKS_PER_CALL, "Profiling Hardware Accelerated Mode execution.");
316	STAM_REG(pVM, &pVM->em.s.StatIOEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/IO", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteIOInstruction.");
317	STAM_REG(pVM, &pVM->em.s.StatPrivEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Priv", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawPrivileged.");
318	STAM_REG(pVM, &pVM->em.s.StatMiscEmu, STAMTYPE_PROFILE, "/PROF/EM/Emulation/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of emR3RawExecuteInstruction.");
319	STAM_REG(pVM, &pVM->em.s.StatREMEmu, STAMTYPE_PROFILE, "/PROF/EM/REMEmuSingle", STAMUNIT_TICKS_PER_CALL, "Profiling single instruction REM execution.");
320	STAM_REG(pVM, &pVM->em.s.StatREMExec, STAMTYPE_PROFILE, "/PROF/EM/REMExec", STAMUNIT_TICKS_PER_CALL, "Profiling REM execution.");
321	STAM_REG(pVM, &pVM->em.s.StatREMSync, STAMTYPE_PROFILE, "/PROF/EM/REMSync", STAMUNIT_TICKS_PER_CALL, "Profiling REM context syncing.");
322	STAM_REG(pVM, &pVM->em.s.StatREMTotal, STAMTYPE_PROFILE, "/PROF/EM/REMTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RemExecute (excluding FFs).");
323	STAM_REG(pVM, &pVM->em.s.StatRAWEntry, STAMTYPE_PROFILE, "/PROF/EM/RAWEnter", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode entry overhead.");
324	STAM_REG(pVM, &pVM->em.s.StatRAWExec, STAMTYPE_PROFILE, "/PROF/EM/RAWExec", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode execution.");
325	STAM_REG(pVM, &pVM->em.s.StatRAWTail, STAMTYPE_PROFILE, "/PROF/EM/RAWTail", STAMUNIT_TICKS_PER_CALL, "Profiling Raw Mode tail overhead.");
326	STAM_REG(pVM, &pVM->em.s.StatRAWTotal, STAMTYPE_PROFILE, "/PROF/EM/RAWTotal", STAMUNIT_TICKS_PER_CALL, "Profiling emR3RawExecute (excluding FFs).");
327	STAM_REL_REG(pVM, &pVM->em.s.StatTotal, STAMTYPE_PROFILE_ADV, "/PROF/EM/Total", STAMUNIT_TICKS_PER_CALL, "Profiling EMR3ExecuteVM.");
328
329
330	return VINF_SUCCESS;
331	}
332
333
334
335	/**
336	* Applies relocations to data and code managed by this
337	* component. This function will be called at init and
338	* whenever the VMM need to relocate it self inside the GC.
339	*
340	* @param pVM The VM.
341	*/
342	EMR3DECL(void) EMR3Relocate(PVM pVM)
343	{
344	LogFlow(("EMR3Relocate\n"));
345	if (pVM->em.s.pStatsHC)
346	pVM->em.s.pStatsGC = MMHyperHC2GC(pVM, pVM->em.s.pStatsHC);
347	}
348
349
350	/**
351	* Reset notification.
352	*
353	* @param pVM
354	*/
355	EMR3DECL(void) EMR3Reset(PVM pVM)
356	{
357	LogFlow(("EMR3Reset: \n"));
358	pVM->em.s.fForceRAW = false;
359	}
360
361
362	/**
363	* Terminates the EM.
364	*
365	* Termination means cleaning up and freeing all resources,
366	* the VM it self is at this point powered off or suspended.
367	*
368	* @returns VBox status code.
369	* @param pVM The VM to operate on.
370	*/
371	EMR3DECL(int) EMR3Term(PVM pVM)
372	{
373	AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
374
375	return VINF_SUCCESS;
376	}
377
378
379	/**
380	* Execute state save operation.
381	*
382	* @returns VBox status code.
383	* @param pVM VM Handle.
384	* @param pSSM SSM operation handle.
385	*/
386	static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
387	{
388	return SSMR3PutBool(pSSM, pVM->em.s.fForceRAW);
389	}
390
391
392	/**
393	* Execute state load operation.
394	*
395	* @returns VBox status code.
396	* @param pVM VM Handle.
397	* @param pSSM SSM operation handle.
398	* @param u32Version Data layout version.
399	*/
400	static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
401	{
402	/*
403	* Validate version.
404	*/
405	if (u32Version != EM_SAVED_STATE_VERSION)
406	{
407	Log(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
408	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
409	}
410
411	/*
412	* Load the saved state.
413	*/
414	int rc = SSMR3GetBool(pSSM, &pVM->em.s.fForceRAW);
415	if (VBOX_FAILURE(rc))
416	pVM->em.s.fForceRAW = false;
417
418	Assert(pVM->em.s.pCliStatTree == 0);
419	return rc;
420	}
421
422
423	/**
424	* Enables or disables a set of raw-mode execution modes.
425	*
426	* @returns VINF_SUCCESS on success.
427	* @returns VINF_RESCHEDULE if a rescheduling might be required.
428	* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
429	*
430	* @param pVM The VM to operate on.
431	* @param enmMode The execution mode change.
432	* @thread The emulation thread.
433	*/
434	EMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode)
435	{
436	switch (enmMode)
437	{
438	case EMRAW_NONE:
439	pVM->fRawR3Enabled = false;
440	pVM->fRawR0Enabled = false;
441	break;
442	case EMRAW_RING3_ENABLE:
443	pVM->fRawR3Enabled = true;
444	break;
445	case EMRAW_RING3_DISABLE:
446	pVM->fRawR3Enabled = false;
447	break;
448	case EMRAW_RING0_ENABLE:
449	pVM->fRawR0Enabled = true;
450	break;
451	case EMRAW_RING0_DISABLE:
452	pVM->fRawR0Enabled = false;
453	break;
454	default:
455	AssertMsgFailed(("Invalid enmMode=%d\n", enmMode));
456	return VERR_INVALID_PARAMETER;
457	}
458	Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool pVM->fRawR3Enabled=%RTbool\n",
459	pVM->fRawR3Enabled, pVM->fRawR0Enabled, pVM->fRawR3Enabled));
460	return pVM->em.s.enmState == EMSTATE_RAW ? VINF_EM_RESCHEDULE : VINF_SUCCESS;
461	}
462
463
464	/**
465	* Raise a fatal error.
466	*
467	* Safely terminate the VM with full state report and stuff. This function
468	* will naturally never return.
469	*
470	* @param pVM VM handle.
471	* @param rc VBox status code.
472	*/
473	EMR3DECL(void) EMR3FatalError(PVM pVM, int rc)
474	{
475	longjmp(pVM->em.s.u.FatalLongJump, rc);
476	AssertReleaseMsgFailed(("longjmp returned!\n"));
477	}
478
479
480	/**
481	* Gets the EM state name.
482	*
483	* @returns pointer to read only state name,
484	* @param enmState The state.
485	*/
486	EMR3DECL(const char *) EMR3GetStateName(EMSTATE enmState)
487	{
488	switch (enmState)
489	{
490	case EMSTATE_RAW: return "EMSTATE_RAW";
491	case EMSTATE_HWACC: return "EMSTATE_HWACC";
492	case EMSTATE_REM: return "EMSTATE_REM";
493	case EMSTATE_HALTED: return "EMSTATE_HALTED";
494	case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
495	case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
496	case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
497	case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
498	case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
499	case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
500	default: return "Unknown!";
501	}
502	}
503
504
505	#ifdef VBOX_WITH_STATISTICS
506	/**
507	* Just a braindead function to keep track of cli addresses.
508	* @param pVM VM handle.
509	* @param pInstrGC The EIP of the cli instruction.
510	*/
511	static void emR3RecordCli(PVM pVM, RTGCPTR pInstrGC)
512	{
513	PCLISTAT pRec;
514
515	pRec = (PCLISTAT)RTAvlPVGet(&pVM->em.s.pCliStatTree, (AVLPVKEY)pInstrGC);
516	if (!pRec)
517	{
518	/* New cli instruction; insert into the tree. */
519	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
520	Assert(pRec);
521	if (!pRec)
522	return;
523	pRec->Core.Key = (AVLPVKEY)pInstrGC;
524
525	char szCliStatName[32];
526	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%VGv", pInstrGC);
527	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
528
529	bool fRc = RTAvlPVInsert(&pVM->em.s.pCliStatTree, &pRec->Core);
530	Assert(fRc); NOREF(fRc);
531	}
532	STAM_COUNTER_INC(&pRec->Counter);
533	STAM_COUNTER_INC(&pVM->em.s.StatTotalClis);
534	}
535	#endif /* VBOX_WITH_STATISTICS */
536
537
538	/**
539	* Debug loop.
540	*
541	* @returns VBox status code for EM.
542	* @param pVM VM handle.
543	* @param rc Current EM VBox status code..
544	*/
545	static int emR3Debug(PVM pVM, int rc)
546	{
547	for (;;)
548	{
549	Log(("emR3Debug: rc=%Vrc\n", rc));
550	const int rcLast = rc;
551
552	/*
553	* Debug related RC.
554	*/
555	switch (rc)
556	{
557	/*
558	* Single step an instruction.
559	*/
560	case VINF_EM_DBG_STEP:
561	if ( pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
562	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
563	\|\| pVM->em.s.fForceRAW /* paranoia */)
564	rc = emR3RawStep(pVM);
565	else
566	{
567	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
568	rc = emR3RemStep(pVM);
569	}
570	break;
571
572	/*
573	* Simple events: stepped, breakpoint, stop/assertion.
574	*/
575	case VINF_EM_DBG_STEPPED:
576	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
577	break;
578
579	case VINF_EM_DBG_BREAKPOINT:
580	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
581	break;
582
583	case VINF_EM_DBG_STOP:
584	rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
585	break;
586
587	case VINF_EM_DBG_HYPER_STEPPED:
588	rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
589	break;
590
591	case VINF_EM_DBG_HYPER_BREAKPOINT:
592	rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
593	break;
594
595	case VINF_EM_DBG_HYPER_ASSERTION:
596	RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
597	rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetGCAssertMsg1(pVM), VMMR3GetGCAssertMsg2(pVM));
598	break;
599
600	/*
601	* Guru meditation.
602	*/
603	default: /** @todo don't use default for guru, but make special errors code! */
604	rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
605	break;
606	}
607
608	/*
609	* Process the result.
610	*/
611	do
612	{
613	switch (rc)
614	{
615	/*
616	* Continue the debugging loop.
617	*/
618	case VINF_EM_DBG_STEP:
619	case VINF_EM_DBG_STOP:
620	case VINF_EM_DBG_STEPPED:
621	case VINF_EM_DBG_BREAKPOINT:
622	case VINF_EM_DBG_HYPER_STEPPED:
623	case VINF_EM_DBG_HYPER_BREAKPOINT:
624	case VINF_EM_DBG_HYPER_ASSERTION:
625	break;
626
627	/*
628	* Resuming execution (in some form) has to be done here if we got
629	* a hypervisor debug event.
630	*/
631	case VINF_SUCCESS:
632	case VINF_EM_RESUME:
633	case VINF_EM_SUSPEND:
634	case VINF_EM_RESCHEDULE:
635	case VINF_EM_RESCHEDULE_RAW:
636	case VINF_EM_RESCHEDULE_REM:
637	case VINF_EM_HALT:
638	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
639	{
640	rc = emR3RawResumeHyper(pVM);
641	if (rc != VINF_SUCCESS && VBOX_SUCCESS(rc))
642	continue;
643	}
644	if (rc == VINF_SUCCESS)
645	rc = VINF_EM_RESCHEDULE;
646	return rc;
647
648	/*
649	* The debugger isn't attached.
650	* We'll simply turn the thing off since that's the easiest thing to do.
651	*/
652	case VERR_DBGF_NOT_ATTACHED:
653	switch (rcLast)
654	{
655	case VINF_EM_DBG_HYPER_ASSERTION:
656	case VINF_EM_DBG_HYPER_STEPPED:
657	case VINF_EM_DBG_HYPER_BREAKPOINT:
658	return rcLast;
659	}
660	return VINF_EM_OFF;
661
662	/*
663	* Status codes terminating the VM in one or another sense.
664	*/
665	case VINF_EM_TERMINATE:
666	case VINF_EM_OFF:
667	case VINF_EM_RESET:
668	case VINF_EM_RAW_STALE_SELECTOR:
669	case VINF_EM_RAW_IRET_TRAP:
670	case VERR_TRPM_PANIC:
671	case VERR_TRPM_DONT_PANIC:
672	case VERR_INTERNAL_ERROR:
673	return rc;
674
675	/*
676	* The rest is unexpected, and will keep us here.
677	*/
678	default:
679	AssertMsgFailed(("Unxpected rc %Vrc!\n", rc));
680	break;
681	}
682	} while (false);
683	} /* debug for ever */
684	}
685
686
687	/**
688	* Steps recompiled code.
689	*
690	* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
691	* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
692	*
693	* @param pVM VM handle.
694	*/
695	static int emR3RemStep(PVM pVM)
696	{
697	LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
698
699	/*
700	* Switch to REM, step instruction, switch back.
701	*/
702	int rc = REMR3State(pVM);
703	if (VBOX_SUCCESS(rc))
704	{
705	rc = REMR3Step(pVM);
706	REMR3StateBack(pVM);
707	}
708	LogFlow(("emR3RemStep: returns %Vrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
709	return rc;
710	}
711
712	/**
713	* Executes recompiled code.
714	*
715	* This function contains the recompiler version of the inner
716	* execution loop (the outer loop being in EMR3ExecuteVM()).
717	*
718	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
719	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
720	*
721	* @param pVM VM handle.
722	* @param pfFFDone Where to store an indicator telling wheter or not
723	* FFs were done before returning.
724	*
725	*/
726	static int emR3RemExecute(PVM pVM, bool *pfFFDone)
727	{
728	#ifdef LOG_ENABLED
729	PCPUMCTX pCtx = pVM->em.s.pCtx;
730	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
731
732	if (pCtx->eflags.Bits.u1VM)
733	Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF));
734	else
735	Log(("EMR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
736	#endif
737	STAM_PROFILE_ADV_START(&pVM->em.s.StatREMTotal, a);
738
739	#if defined(VBOX_STRICT) && defined(DEBUG_bird)
740	AssertMsg( VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3\|VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
741	\|\| !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVM)), /** @todo #1419 - get flat address. */
742	("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVM), CPUMGetGuestEIP(pVM)));
743	#endif
744
745	/*
746	* Spin till we get a forced action which returns anything but VINF_SUCCESS
747	* or the REM suggests raw-mode execution.
748	*/
749	*pfFFDone = false;
750	bool fInREMState = false;
751	int rc = VINF_SUCCESS;
752	for (;;)
753	{
754	/*
755	* Update REM state if not already in sync.
756	*/
757	if (!fInREMState)
758	{
759	STAM_PROFILE_START(&pVM->em.s.StatREMSync, b);
760	rc = REMR3State(pVM);
761	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, b);
762	if (VBOX_FAILURE(rc))
763	break;
764	fInREMState = true;
765
766	/*
767	* We might have missed the raising of VMREQ, TIMER and some other
768	* imporant FFs while we were busy switching the state. So, check again.
769	*/
770	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST \| VM_FF_TIMER \| VM_FF_PDM_QUEUES \| VM_FF_DBGF \| VM_FF_TERMINATE \| VM_FF_RESET))
771	{
772	LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fForcedActions));
773	goto l_REMDoForcedActions;
774	}
775	}
776
777
778	/*
779	* Execute REM.
780	*/
781	STAM_PROFILE_START(&pVM->em.s.StatREMExec, c);
782	rc = REMR3Run(pVM);
783	STAM_PROFILE_STOP(&pVM->em.s.StatREMExec, c);
784
785
786	/*
787	* Deal with high priority post execution FFs before doing anything else.
788	*/
789	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
790	rc = emR3HighPriorityPostForcedActions(pVM, rc);
791
792	/*
793	* Process the returned status code.
794	* (Try keep this short! Call functions!)
795	*/
796	if (rc != VINF_SUCCESS)
797	{
798	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
799	break;
800	if (rc != VINF_REM_INTERRUPED_FF)
801	{
802	/*
803	* Anything which is not known to us means an internal error
804	* and the termination of the VM!
805	*/
806	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
807	break;
808	}
809	}
810
811
812	/*
813	* Check and execute forced actions.
814	* Sync back the VM state before calling any of these.
815	*/
816	#ifdef VBOX_HIGH_RES_TIMERS_HACK
817	TMTimerPoll(pVM);
818	#endif
819	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK & ~(VM_FF_CSAM_PENDING_ACTION \| VM_FF_CSAM_SCAN_PAGE)))
820	{
821	l_REMDoForcedActions:
822	if (fInREMState)
823	{
824	STAM_PROFILE_START(&pVM->em.s.StatREMSync, d);
825	REMR3StateBack(pVM);
826	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, d);
827	fInREMState = false;
828	}
829	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatREMTotal, a);
830	rc = emR3ForcedActions(pVM, rc);
831	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatREMTotal, a);
832	if ( rc != VINF_SUCCESS
833	&& rc != VINF_EM_RESCHEDULE_REM)
834	{
835	*pfFFDone = true;
836	break;
837	}
838	}
839
840	} /* The Inner Loop, recompiled execution mode version. */
841
842
843	/*
844	* Returning. Sync back the VM state if required.
845	*/
846	if (fInREMState)
847	{
848	STAM_PROFILE_START(&pVM->em.s.StatREMSync, e);
849	REMR3StateBack(pVM);
850	STAM_PROFILE_STOP(&pVM->em.s.StatREMSync, e);
851	}
852
853	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatREMTotal, a);
854	return rc;
855	}
856
857
858	/**
859	* Resumes executing hypervisor after a debug event.
860	*
861	* This is kind of special since our current guest state is
862	* potentially out of sync.
863	*
864	* @returns VBox status code.
865	* @param pVM The VM handle.
866	*/
867	static int emR3RawResumeHyper(PVM pVM)
868	{
869	int rc;
870	PCPUMCTX pCtx = pVM->em.s.pCtx;
871	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_HYPER);
872	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
873
874	/*
875	* Resume execution.
876	*/
877	CPUMRawEnter(pVM, NULL);
878	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_RF);
879	rc = VMMR3ResumeHyper(pVM);
880	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Vrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
881	rc = CPUMRawLeave(pVM, NULL, rc);
882	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
883
884	/*
885	* Deal with the return code.
886	*/
887	rc = emR3HighPriorityPostForcedActions(pVM, rc);
888	rc = emR3RawHandleRC(pVM, pCtx, rc);
889	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
890	return rc;
891	}
892
893
894	/**
895	* Steps rawmode.
896	*
897	* @returns VBox status code.
898	* @param pVM The VM handle.
899	*/
900	static int emR3RawStep(PVM pVM)
901	{
902	Assert( pVM->em.s.enmState == EMSTATE_DEBUG_HYPER
903	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
904	\|\| pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
905	int rc;
906	PCPUMCTX pCtx = pVM->em.s.pCtx;
907	bool fGuest = pVM->em.s.enmState != EMSTATE_DEBUG_HYPER;
908	#ifndef DEBUG_sandervl
909	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
910	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM)));
911	#endif
912	if (fGuest)
913	{
914	/*
915	* Check vital forced actions, but ignore pending interrupts and timers.
916	*/
917	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
918	{
919	rc = emR3RawForcedActions(pVM, pCtx);
920	if (VBOX_FAILURE(rc))
921	return rc;
922	}
923
924	/*
925	* Set flags for single stepping.
926	*/
927	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
928	}
929	else
930	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
931
932	/*
933	* Single step.
934	* We do not start time or anything, if anything we should just do a few nanoseconds.
935	*/
936	CPUMRawEnter(pVM, NULL);
937	do
938	{
939	if (pVM->em.s.enmState == EMSTATE_DEBUG_HYPER)
940	rc = VMMR3ResumeHyper(pVM);
941	else
942	rc = VMMR3RawRunGC(pVM);
943	#ifndef DEBUG_sandervl
944	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Vrc\n", fGuest ? CPUMGetGuestCS(pVM) : CPUMGetHyperCS(pVM),
945	fGuest ? CPUMGetGuestEIP(pVM) : CPUMGetHyperEIP(pVM), fGuest ? CPUMGetGuestEFlags(pVM) : CPUMGetHyperEFlags(pVM), rc));
946	#endif
947	} while ( rc == VINF_SUCCESS
948	\|\| rc == VINF_EM_RAW_INTERRUPT);
949	rc = CPUMRawLeave(pVM, NULL, rc);
950	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
951
952	/*
953	* Make sure the trap flag is cleared.
954	* (Too bad if the guest is trying to single step too.)
955	*/
956	if (fGuest)
957	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
958	else
959	CPUMSetHyperEFlags(pVM, CPUMGetHyperEFlags(pVM) & ~X86_EFL_TF);
960
961	/*
962	* Deal with the return codes.
963	*/
964	rc = emR3HighPriorityPostForcedActions(pVM, rc);
965	rc = emR3RawHandleRC(pVM, pCtx, rc);
966	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
967	return rc;
968	}
969
970
971	#ifdef DEBUG
972
973	/**
974	* Steps hardware accelerated mode.
975	*
976	* @returns VBox status code.
977	* @param pVM The VM handle.
978	*/
979	static int emR3HwAccStep(PVM pVM)
980	{
981	Assert(pVM->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
982
983	int rc;
984	PCPUMCTX pCtx = pVM->em.s.pCtx;
985	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
986
987	/*
988	* Check vital forced actions, but ignore pending interrupts and timers.
989	*/
990	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
991	{
992	rc = emR3RawForcedActions(pVM, pCtx);
993	if (VBOX_FAILURE(rc))
994	return rc;
995	}
996	/*
997	* Set flags for single stepping.
998	*/
999	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) \| X86_EFL_TF \| X86_EFL_RF);
1000
1001	/*
1002	* Single step.
1003	* We do not start time or anything, if anything we should just do a few nanoseconds.
1004	*/
1005	do
1006	{
1007	rc = VMMR3HwAccRunGC(pVM);
1008	} while ( rc == VINF_SUCCESS
1009	\|\| rc == VINF_EM_RAW_INTERRUPT);
1010	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
1011
1012	/*
1013	* Make sure the trap flag is cleared.
1014	* (Too bad if the guest is trying to single step too.)
1015	*/
1016	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1017
1018	/*
1019	* Deal with the return codes.
1020	*/
1021	rc = emR3HighPriorityPostForcedActions(pVM, rc);
1022	rc = emR3RawHandleRC(pVM, pCtx, rc);
1023	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
1024	return rc;
1025	}
1026
1027
1028	void emR3SingleStepExecRaw(PVM pVM, uint32_t cIterations)
1029	{
1030	EMSTATE enmOldState = pVM->em.s.enmState;
1031
1032	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
1033
1034	Log(("Single step BEGIN:\n"));
1035	for(uint32_t i=0;i<cIterations;i++)
1036	{
1037	DBGFR3PrgStep(pVM);
1038	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1039	emR3RawStep(pVM);
1040	}
1041	Log(("Single step END:\n"));
1042	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1043	pVM->em.s.enmState = enmOldState;
1044	}
1045
1046
1047	void emR3SingleStepExecHwAcc(PVM pVM, uint32_t cIterations)
1048	{
1049	EMSTATE enmOldState = pVM->em.s.enmState;
1050
1051	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_HWACC;
1052
1053	Log(("Single step BEGIN:\n"));
1054	for(uint32_t i=0;i<cIterations;i++)
1055	{
1056	DBGFR3PrgStep(pVM);
1057	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1058	emR3HwAccStep(pVM);
1059	}
1060	Log(("Single step END:\n"));
1061	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1062	pVM->em.s.enmState = enmOldState;
1063	}
1064
1065
1066	void emR3SingleStepExecRem(PVM pVM, uint32_t cIterations)
1067	{
1068	EMSTATE enmOldState = pVM->em.s.enmState;
1069
1070	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1071
1072	Log(("Single step BEGIN:\n"));
1073	for(uint32_t i=0;i<cIterations;i++)
1074	{
1075	DBGFR3PrgStep(pVM);
1076	DBGFR3DisasInstrCurrentLog(pVM, "RSS: ");
1077	emR3RemStep(pVM);
1078	}
1079	Log(("Single step END:\n"));
1080	CPUMSetGuestEFlags(pVM, CPUMGetGuestEFlags(pVM) & ~X86_EFL_TF);
1081	pVM->em.s.enmState = enmOldState;
1082	}
1083
1084	#endif /* DEBUG */
1085
1086
1087	/**
1088	* Executes one (or perhaps a few more) instruction(s).
1089	*
1090	* @returns VBox status code suitable for EM.
1091	*
1092	* @param pVM VM handle.
1093	* @param rcGC GC return code
1094	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1095	* instruction and prefix the log output with this text.
1096	*/
1097	#ifdef LOG_ENABLED
1098	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC, const char *pszPrefix)
1099	#else
1100	static int emR3RawExecuteInstructionWorker(PVM pVM, int rcGC)
1101	#endif
1102	{
1103	PCPUMCTX pCtx = pVM->em.s.pCtx;
1104	int rc;
1105
1106	/*
1107	*
1108	* The simple solution is to use the recompiler.
1109	* The better solution is to disassemble the current instruction and
1110	* try handle as many as possible without using REM.
1111	*
1112	*/
1113
1114	#ifdef LOG_ENABLED
1115	/*
1116	* Disassemble the instruction if requested.
1117	*/
1118	if (pszPrefix)
1119	{
1120	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
1121	DBGFR3DisasInstrCurrentLog(pVM, pszPrefix);
1122	}
1123	#endif /* LOG_ENABLED */
1124
1125	/*
1126	* PATM is making life more interesting.
1127	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
1128	* tell PATM there is a trap in this code and have it take the appropriate actions
1129	* to allow us execute the code in REM.
1130	*/
1131	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1132	{
1133	Log(("emR3RawExecuteInstruction: In patch block. eip=%VGv\n", pCtx->eip));
1134
1135	RTGCPTR pNewEip;
1136	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1137	switch (rc)
1138	{
1139	/*
1140	* It's not very useful to emulate a single instruction and then go back to raw
1141	* mode; just execute the whole block until IF is set again.
1142	*/
1143	case VINF_SUCCESS:
1144	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %VGv IF=%d VMIF=%x\n",
1145	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1146	pCtx->eip = pNewEip;
1147	Assert(pCtx->eip);
1148
1149	if (pCtx->eflags.Bits.u1IF)
1150	{
1151	/*
1152	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1153	*/
1154	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1155	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1156	}
1157	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
1158	{
1159	/* special case: iret, that sets IF, detected a pending irq/event */
1160	return emR3RawExecuteInstruction(pVM, "PATCHIRET");
1161	}
1162	return VINF_EM_RESCHEDULE_REM;
1163
1164	/*
1165	* One instruction.
1166	*/
1167	case VINF_PATCH_EMULATE_INSTR:
1168	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1169	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1170	pCtx->eip = pNewEip;
1171	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1172
1173	/*
1174	* The patch was disabled, hand it to the REM.
1175	*/
1176	case VERR_PATCH_DISABLED:
1177	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %VGv IF=%d VMIF=%x\n",
1178	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1179	pCtx->eip = pNewEip;
1180	if (pCtx->eflags.Bits.u1IF)
1181	{
1182	/*
1183	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1184	*/
1185	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1186	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1187	}
1188	return VINF_EM_RESCHEDULE_REM;
1189
1190	/* Force continued patch exection; usually due to write monitored stack. */
1191	case VINF_PATCH_CONTINUE:
1192	return VINF_SUCCESS;
1193
1194	default:
1195	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap\n", rc));
1196	return VERR_INTERNAL_ERROR;
1197	}
1198	}
1199
1200	#if 0 /// @todo Sander, this breaks the linux image (panics). So, I'm disabling it for now. (OP_MOV triggers it btw.)
1201	DISCPUSTATE Cpu;
1202	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "GEN EMU");
1203	if (VBOX_SUCCESS(rc))
1204	{
1205	uint32_t size;
1206
1207	switch (Cpu.pCurInstr->opcode)
1208	{
1209	case OP_MOV:
1210	case OP_AND:
1211	case OP_OR:
1212	case OP_XOR:
1213	case OP_POP:
1214	case OP_INC:
1215	case OP_DEC:
1216	case OP_XCHG:
1217	STAM_PROFILE_START(&pVM->em.s.StatMiscEmu, a);
1218	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1219	if (VBOX_SUCCESS(rc))
1220	{
1221	pCtx->eip += Cpu.opsize;
1222	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1223	return rc;
1224	}
1225	if (rc != VERR_EM_INTERPRETER)
1226	AssertMsgFailedReturn(("rc=%Vrc\n", rc), rc);
1227	STAM_PROFILE_STOP(&pVM->em.s.StatMiscEmu, a);
1228	break;
1229	}
1230	}
1231	#endif
1232	STAM_PROFILE_START(&pVM->em.s.StatREMEmu, a);
1233	rc = REMR3EmulateInstruction(pVM);
1234	STAM_PROFILE_STOP(&pVM->em.s.StatREMEmu, a);
1235
1236	return rc;
1237	}
1238
1239
1240	/**
1241	* Executes one (or perhaps a few more) instruction(s).
1242	* This is just a wrapper for discarding pszPrefix in non-logging builds.
1243	*
1244	* @returns VBox status code suitable for EM.
1245	* @param pVM VM handle.
1246	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
1247	* instruction and prefix the log output with this text.
1248	* @param rcGC GC return code
1249	*/
1250	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, const char *pszPrefix, int rcGC)
1251	{
1252	#ifdef LOG_ENABLED
1253	return emR3RawExecuteInstructionWorker(pVM, rcGC, pszPrefix);
1254	#else
1255	return emR3RawExecuteInstructionWorker(pVM, rcGC);
1256	#endif
1257	}
1258
1259	/**
1260	* Executes one (or perhaps a few more) IO instruction(s).
1261	*
1262	* @returns VBox status code suitable for EM.
1263	* @param pVM VM handle.
1264	*/
1265	int emR3RawExecuteIOInstruction(PVM pVM)
1266	{
1267	int rc;
1268	PCPUMCTX pCtx = pVM->em.s.pCtx;
1269
1270	STAM_PROFILE_START(&pVM->em.s.StatIOEmu, a);
1271
1272	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
1273	* as io instructions tend to come in packages of more than one
1274	*/
1275	DISCPUSTATE Cpu;
1276	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "IO EMU");
1277	if (VBOX_SUCCESS(rc))
1278	{
1279	rc = VINF_EM_RAW_EMULATE_INSTR;
1280
1281	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
1282	{
1283	switch (Cpu.pCurInstr->opcode)
1284	{
1285	case OP_IN:
1286	{
1287	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1288	rc = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1289	break;
1290	}
1291
1292	case OP_OUT:
1293	{
1294	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1295	rc = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1296	break;
1297	}
1298	}
1299	}
1300	else if (Cpu.prefix & PREFIX_REP)
1301	{
1302	switch (Cpu.pCurInstr->opcode)
1303	{
1304	case OP_INSB:
1305	case OP_INSWD:
1306	{
1307	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatIn);
1308	rc = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1309	break;
1310	}
1311
1312	case OP_OUTSB:
1313	case OP_OUTSWD:
1314	{
1315	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatOut);
1316	rc = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
1317	break;
1318	}
1319	}
1320	}
1321
1322	/*
1323	* Handled the I/O return codes.
1324	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1325	*/
1326	if (IOM_SUCCESS(rc))
1327	{
1328	pCtx->eip += Cpu.opsize;
1329	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1330	return rc;
1331	}
1332
1333	if (rc == VINF_EM_RAW_GUEST_TRAP)
1334	{
1335	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1336	rc = emR3RawGuestTrap(pVM);
1337	return rc;
1338	}
1339	AssertMsg(rc != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
1340
1341	if (VBOX_FAILURE(rc))
1342	{
1343	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1344	return rc;
1345	}
1346	AssertMsg(rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RESCHEDULE_REM, ("rc=%Vrc\n", rc));
1347	}
1348	STAM_PROFILE_STOP(&pVM->em.s.StatIOEmu, a);
1349	return emR3RawExecuteInstruction(pVM, "IO: ");
1350	}
1351
1352
1353	/**
1354	* Handle a guest context trap.
1355	*
1356	* @returns VBox status code suitable for EM.
1357	* @param pVM VM handle.
1358	*/
1359	static int emR3RawGuestTrap(PVM pVM)
1360	{
1361	PCPUMCTX pCtx = pVM->em.s.pCtx;
1362
1363	/*
1364	* Get the trap info.
1365	*/
1366	uint8_t u8TrapNo;
1367	TRPMEVENT enmType;;
1368	RTGCUINT uErrorCode;
1369	RTGCUINTPTR uCR2;
1370	int rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1371	if (VBOX_FAILURE(rc))
1372	{
1373	AssertReleaseMsgFailed(("No trap! (rc=%Vrc)\n", rc));
1374	return rc;
1375	}
1376
1377	/* Traps can be directly forwarded in hardware accelerated mode. */
1378	if (HWACCMR3IsActive(pVM))
1379	{
1380	#ifdef LOGGING_ENABLED
1381	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1382	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1383	#endif
1384	return VINF_EM_RESCHEDULE_HWACC;
1385	}
1386
1387	/** Scan kernel code that traps; we might not get another chance. */
1388	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1389	&& !pCtx->eflags.Bits.u1VM)
1390	{
1391	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1392	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
1393	}
1394
1395	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
1396	{
1397	DISCPUSTATE cpu;
1398
1399	/* If MONITOR & MWAIT are supported, then interpret them here. */
1400	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap (#UD): ");
1401	if ( VBOX_SUCCESS(rc)
1402	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
1403	{
1404	uint32_t u32Dummy, u32Features, u32ExtFeatures, size;
1405
1406	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
1407
1408	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
1409	{
1410	rc = TRPMResetTrap(pVM);
1411	AssertRC(rc);
1412
1413	rc = EMInterpretInstructionCPU(pVM, &cpu, CPUMCTX2CORE(pCtx), 0, &size);
1414	if (VBOX_SUCCESS(rc))
1415	{
1416	pCtx->eip += cpu.opsize;
1417	return rc;
1418	}
1419	return emR3RawExecuteInstruction(pVM, "Monitor: ");
1420	}
1421	}
1422	}
1423	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
1424	{
1425	DISCPUSTATE cpu;
1426
1427	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &cpu, "Guest Trap: ");
1428	if (VBOX_SUCCESS(rc) && (cpu.pCurInstr->optype & OPTYPE_PORTIO))
1429	{
1430	/*
1431	* We should really check the TSS for the IO bitmap, but it's not like this
1432	* lazy approach really makes things worse.
1433	*/
1434	rc = TRPMResetTrap(pVM);
1435	AssertRC(rc);
1436	return emR3RawExecuteInstruction(pVM, "IO Guest Trap: ");
1437	}
1438	}
1439
1440	#ifdef LOG_ENABLED
1441	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
1442	DBGFR3DisasInstrCurrentLog(pVM, "Guest trap");
1443
1444	/* Get guest page information. */
1445	uint64_t fFlags = 0;
1446	RTGCPHYS GCPhys = 0;
1447	int rc2 = PGMGstGetPage(pVM, uCR2, &fFlags, &GCPhys);
1448	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%VGp fFlags=%08llx %s %s %s%s rc2=%d\n",
1449	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
1450	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
1451	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
1452	#endif
1453
1454	/*
1455	* #PG has CR2.
1456	* (Because of stuff like above we must set CR2 in a delayed fashion.)
1457	*/
1458	if (u8TrapNo == 14 /* #PG */)
1459	pCtx->cr2 = uCR2;
1460
1461	return VINF_EM_RESCHEDULE_REM;
1462	}
1463
1464
1465	/**
1466	* Handle a ring switch trap.
1467	* Need to do statistics and to install patches. The result is going to REM.
1468	*
1469	* @returns VBox status code suitable for EM.
1470	* @param pVM VM handle.
1471	*/
1472	int emR3RawRingSwitch(PVM pVM)
1473	{
1474	int rc;
1475	DISCPUSTATE Cpu;
1476	PCPUMCTX pCtx = pVM->em.s.pCtx;
1477
1478	/*
1479	* sysenter, syscall & callgate
1480	*/
1481	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "RSWITCH: ");
1482	if (VBOX_SUCCESS(rc))
1483	{
1484	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
1485	{
1486	if (pCtx->SysEnter.cs != 0)
1487	{
1488	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1489	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1490	if (VBOX_SUCCESS(rc))
1491	{
1492	DBGFR3DisasInstrCurrentLog(pVM, "Patched sysenter instruction");
1493	return VINF_EM_RESCHEDULE_RAW;
1494	}
1495	}
1496	}
1497
1498	#ifdef VBOX_WITH_STATISTICS
1499	switch (Cpu.pCurInstr->opcode)
1500	{
1501	case OP_SYSENTER:
1502	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysEnter);
1503	break;
1504	case OP_SYSEXIT:
1505	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysExit);
1506	break;
1507	case OP_SYSCALL:
1508	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysCall);
1509	break;
1510	case OP_SYSRET:
1511	STAM_COUNTER_INC(&pVM->em.s.CTXSUFF(pStats)->StatSysRet);
1512	break;
1513	}
1514	#endif
1515	}
1516	else
1517	AssertRC(rc);
1518
1519	/* go to the REM to emulate a single instruction */
1520	return emR3RawExecuteInstruction(pVM, "RSWITCH: ");
1521	}
1522
1523	/**
1524	* Handle a trap (#PF or #GP) in patch code
1525	*
1526	* @returns VBox status code suitable for EM.
1527	* @param pVM VM handle.
1528	* @param pCtx CPU context
1529	* @param gcret GC return code
1530	*/
1531	int emR3PatchTrap(PVM pVM, PCPUMCTX pCtx, int gcret)
1532	{
1533	uint8_t u8TrapNo;
1534	int rc;
1535	TRPMEVENT enmType;
1536	RTGCUINT uErrorCode;
1537	RTGCUINTPTR uCR2;
1538
1539	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
1540
1541	if (gcret == VINF_PATM_PATCH_INT3)
1542	{
1543	u8TrapNo = 3;
1544	uCR2 = 0;
1545	uErrorCode = 0;
1546	}
1547	else
1548	if (gcret == VINF_PATM_PATCH_TRAP_GP)
1549	{
1550	/* No active trap in this case. Kind of ugly. */
1551	u8TrapNo = X86_XCPT_GP;
1552	uCR2 = 0;
1553	uErrorCode = 0;
1554	}
1555	else
1556	{
1557	rc = TRPMQueryTrapAll(pVM, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
1558	if (VBOX_FAILURE(rc))
1559	{
1560	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Vrc) gcret=%Vrc\n", rc, gcret));
1561	return rc;
1562	}
1563	/* Reset the trap as we'll execute the original instruction again. */
1564	TRPMResetTrap(pVM);
1565	}
1566
1567	/*
1568	* Deal with traps inside patch code.
1569	* (This code won't run outside GC.)
1570	*/
1571	if (u8TrapNo != 1)
1572	{
1573	#ifdef LOG_ENABLED
1574	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
1575	DBGFR3DisasInstrCurrentLog(pVM, "Patch code");
1576
1577	DISCPUSTATE Cpu;
1578	int rc;
1579
1580	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "Patch code: ");
1581	if ( VBOX_SUCCESS(rc)
1582	&& Cpu.pCurInstr->opcode == OP_IRET)
1583	{
1584	uint32_t eip, selCS, uEFlags;
1585
1586	/* Iret crashes are bad as we have already changed the flags on the stack */
1587	rc = PGMPhysReadGCPtr(pVM, &eip, pCtx->esp, 4);
1588	rc \|= PGMPhysReadGCPtr(pVM, &selCS, pCtx->esp+4, 4);
1589	rc \|= PGMPhysReadGCPtr(pVM, &uEFlags, pCtx->esp+8, 4);
1590	if (rc == VINF_SUCCESS)
1591	{
1592	if ( (uEFlags & X86_EFL_VM)
1593	\|\| (selCS & X86_SEL_RPL) == 3)
1594	{
1595	uint32_t selSS, esp;
1596
1597	rc \|= PGMPhysReadGCPtr(pVM, &esp, pCtx->esp + 12, 4);
1598	rc \|= PGMPhysReadGCPtr(pVM, &selSS, pCtx->esp + 16, 4);
1599
1600	if (uEFlags & X86_EFL_VM)
1601	{
1602	uint32_t selDS, selES, selFS, selGS;
1603	rc = PGMPhysReadGCPtr(pVM, &selES, pCtx->esp + 20, 4);
1604	rc \|= PGMPhysReadGCPtr(pVM, &selDS, pCtx->esp + 24, 4);
1605	rc \|= PGMPhysReadGCPtr(pVM, &selFS, pCtx->esp + 28, 4);
1606	rc \|= PGMPhysReadGCPtr(pVM, &selGS, pCtx->esp + 32, 4);
1607	if (rc == VINF_SUCCESS)
1608	{
1609	Log(("Patch code: IRET->VM stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1610	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
1611	}
1612	}
1613	else
1614	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x ss:esp=%04X:%VGv\n", selCS, eip, uEFlags, selSS, esp));
1615	}
1616	else
1617	Log(("Patch code: IRET stack frame: return address %04X:%VGv eflags=%08x\n", selCS, eip, uEFlags));
1618	}
1619	}
1620	#endif
1621	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
1622	pCtx->eip, u8TrapNo, uErrorCode, uCR2, pCtx->cr0));
1623
1624	RTGCPTR pNewEip;
1625	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
1626	switch (rc)
1627	{
1628	/*
1629	* Execute the faulting instruction.
1630	*/
1631	case VINF_SUCCESS:
1632	{
1633	/** @todo execute a whole block */
1634	Log(("emR3PatchTrap: Executing faulting instruction at new address %VGv\n", pNewEip));
1635	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1636	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1637
1638	pCtx->eip = pNewEip;
1639	AssertRelease(pCtx->eip);
1640
1641	if (pCtx->eflags.Bits.u1IF)
1642	{
1643	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
1644	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
1645	*/
1646	if ( u8TrapNo == X86_XCPT_GP
1647	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
1648	{
1649	/** @todo move to PATMR3HandleTrap */
1650	Log(("Possible Windows XP iret fault at %VGv\n", pCtx->eip));
1651	PATMR3RemovePatch(pVM, pCtx->eip);
1652	}
1653
1654	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
1655	/** @note possibly because a reschedule is required (e.g. iret to V86 code) */
1656
1657	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1658	/* Interrupts are enabled; just go back to the original instruction.
1659	return VINF_SUCCESS; */
1660	}
1661	return VINF_EM_RESCHEDULE_REM;
1662	}
1663
1664	/*
1665	* One instruction.
1666	*/
1667	case VINF_PATCH_EMULATE_INSTR:
1668	Log(("emR3PatchTrap: Emulate patched instruction at %VGv IF=%d VMIF=%x\n",
1669	pNewEip, pCtx->eflags.Bits.u1IF, pVM->em.s.pPatmGCState->uVMFlags));
1670	pCtx->eip = pNewEip;
1671	AssertRelease(pCtx->eip);
1672	return emR3RawExecuteInstruction(pVM, "PATCHEMUL: ");
1673
1674	/*
1675	* The patch was disabled, hand it to the REM.
1676	*/
1677	case VERR_PATCH_DISABLED:
1678	if (!(pVM->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
1679	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
1680	pCtx->eip = pNewEip;
1681	AssertRelease(pCtx->eip);
1682
1683	if (pCtx->eflags.Bits.u1IF)
1684	{
1685	/*
1686	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
1687	*/
1688	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
1689	return emR3RawExecuteInstruction(pVM, "PATCHIR");
1690	}
1691	return VINF_EM_RESCHEDULE_REM;
1692
1693	/* Force continued patch exection; usually due to write monitored stack. */
1694	case VINF_PATCH_CONTINUE:
1695	return VINF_SUCCESS;
1696
1697	/*
1698	* Anything else is fatal.
1699	*/
1700	default:
1701	AssertReleaseMsgFailed(("Unknown return code %Vrc from PATMR3HandleTrap!\n", rc));
1702	return VERR_INTERNAL_ERROR;
1703	}
1704	}
1705	return VINF_SUCCESS;
1706	}
1707
1708
1709	/**
1710	* Handle a privileged instruction.
1711	*
1712	* @returns VBox status code suitable for EM.
1713	* @param pVM VM handle.
1714	*/
1715	int emR3RawPrivileged(PVM pVM)
1716	{
1717	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1718	PCPUMCTX pCtx = pVM->em.s.pCtx;
1719
1720	Assert(!pCtx->eflags.Bits.u1VM);
1721
1722	if (PATMIsEnabled(pVM))
1723	{
1724	/*
1725	* Check if in patch code.
1726	*/
1727	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
1728	{
1729	#ifdef LOG_ENABLED
1730	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1731	#endif
1732	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
1733	return VERR_EM_RAW_PATCH_CONFLICT;
1734	}
1735	if ( (pCtx->ss & X86_SEL_RPL) == 0
1736	&& !pCtx->eflags.Bits.u1VM
1737	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1738	{
1739	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
1740	SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0);
1741	if (VBOX_SUCCESS(rc))
1742	{
1743	#ifdef LOG_ENABLED
1744	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1745	#endif
1746	DBGFR3DisasInstrCurrentLog(pVM, "Patched privileged instruction");
1747	return VINF_SUCCESS;
1748	}
1749	}
1750	}
1751
1752	#ifdef LOG_ENABLED
1753	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
1754	{
1755	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1756	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1757	}
1758	#endif
1759
1760	/*
1761	* Instruction statistics and logging.
1762	*/
1763	DISCPUSTATE Cpu;
1764	int rc;
1765
1766	rc = CPUMR3DisasmInstrCPU(pVM, pCtx, pCtx->eip, &Cpu, "PRIV: ");
1767	if (VBOX_SUCCESS(rc))
1768	{
1769	#ifdef VBOX_WITH_STATISTICS
1770	PEMSTATS pStats = pVM->em.s.CTXSUFF(pStats);
1771	switch (Cpu.pCurInstr->opcode)
1772	{
1773	case OP_INVLPG:
1774	STAM_COUNTER_INC(&pStats->StatInvlpg);
1775	break;
1776	case OP_IRET:
1777	STAM_COUNTER_INC(&pStats->StatIret);
1778	break;
1779	case OP_CLI:
1780	STAM_COUNTER_INC(&pStats->StatCli);
1781	emR3RecordCli(pVM, pCtx->eip);
1782	break;
1783	case OP_STI:
1784	STAM_COUNTER_INC(&pStats->StatSti);
1785	break;
1786	case OP_INSB:
1787	case OP_INSWD:
1788	case OP_IN:
1789	case OP_OUTSB:
1790	case OP_OUTSWD:
1791	case OP_OUT:
1792	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1793	break;
1794
1795	case OP_MOV_CR:
1796	if (Cpu.param1.flags & USE_REG_GEN32)
1797	{
1798	//read
1799	Assert(Cpu.param2.flags & USE_REG_CR);
1800	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1801	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1802	}
1803	else
1804	{
1805	//write
1806	Assert(Cpu.param1.flags & USE_REG_CR);
1807	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1808	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1809	}
1810	break;
1811
1812	case OP_MOV_DR:
1813	STAM_COUNTER_INC(&pStats->StatMovDRx);
1814	break;
1815	case OP_LLDT:
1816	STAM_COUNTER_INC(&pStats->StatMovLldt);
1817	break;
1818	case OP_LIDT:
1819	STAM_COUNTER_INC(&pStats->StatMovLidt);
1820	break;
1821	case OP_LGDT:
1822	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1823	break;
1824	case OP_SYSENTER:
1825	STAM_COUNTER_INC(&pStats->StatSysEnter);
1826	break;
1827	case OP_SYSEXIT:
1828	STAM_COUNTER_INC(&pStats->StatSysExit);
1829	break;
1830	case OP_SYSCALL:
1831	STAM_COUNTER_INC(&pStats->StatSysCall);
1832	break;
1833	case OP_SYSRET:
1834	STAM_COUNTER_INC(&pStats->StatSysRet);
1835	break;
1836	case OP_HLT:
1837	STAM_COUNTER_INC(&pStats->StatHlt);
1838	break;
1839	default:
1840	STAM_COUNTER_INC(&pStats->StatMisc);
1841	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1842	break;
1843	}
1844	#endif
1845	if ( (pCtx->ss & X86_SEL_RPL) == 0
1846	&& !pCtx->eflags.Bits.u1VM
1847	&& SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid))
1848	{
1849	uint32_t size;
1850
1851	STAM_PROFILE_START(&pVM->em.s.StatPrivEmu, a);
1852	switch (Cpu.pCurInstr->opcode)
1853	{
1854	case OP_CLI:
1855	pCtx->eflags.u32 &= ~X86_EFL_IF;
1856	Assert(Cpu.opsize == 1);
1857	pCtx->eip += Cpu.opsize;
1858	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1859	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1860
1861	case OP_STI:
1862	pCtx->eflags.u32 \|= X86_EFL_IF;
1863	EMSetInhibitInterruptsPC(pVM, pCtx->eip + Cpu.opsize);
1864	Assert(Cpu.opsize == 1);
1865	pCtx->eip += Cpu.opsize;
1866	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1867	return VINF_SUCCESS;
1868
1869	case OP_HLT:
1870	if (PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip))
1871	{
1872	PATMTRANSSTATE enmState;
1873	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1874
1875	if (enmState == PATMTRANS_OVERWRITTEN)
1876	{
1877	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1878	Assert(rc == VERR_PATCH_DISABLED);
1879	/* Conflict detected, patch disabled */
1880	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %VGv\n", pCtx->eip));
1881
1882	enmState = PATMTRANS_SAFE;
1883	}
1884
1885	/* The translation had better be successful. Otherwise we can't recover. */
1886	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %VGv\n", pCtx->eip));
1887	if (enmState != PATMTRANS_OVERWRITTEN)
1888	pCtx->eip = pOrgInstrGC;
1889	}
1890	/* no break; we could just return VINF_EM_HALT here */
1891
1892	case OP_MOV_CR:
1893	case OP_MOV_DR:
1894	#ifdef LOG_ENABLED
1895	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1896	{
1897	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1898	DBGFR3DisasInstrCurrentLog(pVM, "Privileged instr: ");
1899	}
1900	#endif
1901
1902	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
1903	if (VBOX_SUCCESS(rc))
1904	{
1905	pCtx->eip += Cpu.opsize;
1906	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1907
1908	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1909	&& Cpu.param1.flags == USE_REG_CR /* write */
1910	)
1911	{
1912	/* Reschedule is necessary as the execution/paging mode might have changed. */
1913	return VINF_EM_RESCHEDULE;
1914	}
1915	return rc; /* can return VINF_EM_HALT as well. */
1916	}
1917	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Vrc\n", rc), rc);
1918	break; /* fall back to the recompiler */
1919	}
1920	STAM_PROFILE_STOP(&pVM->em.s.StatPrivEmu, a);
1921	}
1922	}
1923
1924	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1925	return emR3PatchTrap(pVM, pCtx, VINF_PATM_PATCH_TRAP_GP);
1926
1927	return emR3RawExecuteInstruction(pVM, "PRIV");
1928	}
1929
1930
1931	/**
1932	* Update the forced rawmode execution modifier.
1933	*
1934	* This function is called when we're returning from the raw-mode loop(s). If we're
1935	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1936	* if not in patch code, the flag will be cleared.
1937	*
1938	* We should never interrupt patch code while it's being executed. Cli patches can
1939	* contain big code blocks, but they are always executed with IF=0. Other patches
1940	* replace single instructions and should be atomic.
1941	*
1942	* @returns Updated rc.
1943	*
1944	* @param pVM The VM handle.
1945	* @param pCtx The guest CPU context.
1946	* @param rc The result code.
1947	*/
1948	DECLINLINE(int) emR3RawUpdateForceFlag(PVM pVM, PCPUMCTX pCtx, int rc)
1949	{
1950	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1951	{
1952	/* ignore reschedule attempts. */
1953	switch (rc)
1954	{
1955	case VINF_EM_RESCHEDULE:
1956	case VINF_EM_RESCHEDULE_REM:
1957	rc = VINF_SUCCESS;
1958	break;
1959	}
1960	pVM->em.s.fForceRAW = true;
1961	}
1962	else
1963	pVM->em.s.fForceRAW = false;
1964	return rc;
1965	}
1966
1967
1968	/**
1969	* Process a subset of the raw-mode return code.
1970	*
1971	* Since we have to share this with raw-mode single stepping, this inline
1972	* function has been created to avoid code duplication.
1973	*
1974	* @returns VINF_SUCCESS if it's ok to continue raw mode.
1975	* @returns VBox status code to return to the EM main loop.
1976	*
1977	* @param pVM The VM handle
1978	* @param rc The return code.
1979	* @param pCtx The guest cpu context.
1980	*/
1981	DECLINLINE(int) emR3RawHandleRC(PVM pVM, PCPUMCTX pCtx, int rc)
1982	{
1983	switch (rc)
1984	{
1985	/*
1986	* Common & simple ones.
1987	*/
1988	case VINF_SUCCESS:
1989	break;
1990	case VINF_EM_RESCHEDULE_RAW:
1991	case VINF_EM_RESCHEDULE_HWACC:
1992	case VINF_EM_RAW_INTERRUPT:
1993	case VINF_EM_RAW_TO_R3:
1994	case VINF_EM_RAW_TIMER_PENDING:
1995	case VINF_EM_PENDING_REQUEST:
1996	rc = VINF_SUCCESS;
1997	break;
1998
1999	/*
2000	* Privileged instruction.
2001	*/
2002	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2003	case VINF_PATM_PATCH_TRAP_GP:
2004	rc = emR3RawPrivileged(pVM);
2005	break;
2006
2007	/*
2008	* Got a trap which needs dispatching.
2009	*/
2010	case VINF_EM_RAW_GUEST_TRAP:
2011	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
2012	{
2013	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVM)));
2014	rc = VERR_EM_RAW_PATCH_CONFLICT;
2015	break;
2016	}
2017
2018	Assert(TRPMHasTrap(pVM));
2019	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2020
2021	if (TRPMHasTrap(pVM))
2022	{
2023	uint8_t u8Interrupt;
2024	uint32_t uErrorCode;
2025	TRPMERRORCODE enmError = TRPM_TRAP_NO_ERRORCODE;
2026
2027	rc = TRPMQueryTrapAll(pVM, &u8Interrupt, NULL, &uErrorCode, NULL);
2028	AssertRC(rc);
2029
2030	if (uErrorCode != ~0U)
2031	enmError = TRPM_TRAP_HAS_ERRORCODE;
2032
2033	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2034	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2035	{
2036	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2037	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2038
2039	/** If it was successful, then we could go back to raw mode. */
2040	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER)
2041	{
2042	/* Must check pending forced actions as our IDT or GDT might be out of sync */
2043	EMR3CheckRawForcedActions(pVM);
2044
2045	rc = TRPMForwardTrap(pVM, CPUMCTX2CORE(pCtx), u8Interrupt, uErrorCode, enmError, TRPM_TRAP);
2046	if (rc == VINF_SUCCESS /* Don't use VBOX_SUCCESS */)
2047	{
2048	TRPMResetTrap(pVM);
2049	return VINF_EM_RESCHEDULE_RAW;
2050	}
2051	}
2052	}
2053	}
2054	rc = emR3RawGuestTrap(pVM);
2055	break;
2056
2057	/*
2058	* Trap in patch code.
2059	*/
2060	case VINF_PATM_PATCH_TRAP_PF:
2061	case VINF_PATM_PATCH_INT3:
2062	rc = emR3PatchTrap(pVM, pCtx, rc);
2063	break;
2064
2065	case VINF_PATM_DUPLICATE_FUNCTION:
2066	Assert(PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2067	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
2068	AssertRC(rc);
2069	rc = VINF_SUCCESS;
2070	break;
2071
2072	case VINF_PATM_CHECK_PATCH_PAGE:
2073	rc = PATMR3HandleMonitoredPage(pVM);
2074	AssertRC(rc);
2075	rc = VINF_SUCCESS;
2076	break;
2077
2078	/*
2079	* Patch manager.
2080	*/
2081	case VERR_EM_RAW_PATCH_CONFLICT:
2082	AssertReleaseMsgFailed(("%Vrc handling is not yet implemented\n", rc));
2083	break;
2084
2085	/*
2086	* Memory mapped I/O access - attempt to patch the instruction
2087	*/
2088	case VINF_PATM_HC_MMIO_PATCH_READ:
2089	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),
2090	PATMFL_MMIO_ACCESS \| (SELMIsSelector32Bit(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) ? PATMFL_CODE32 : 0));
2091	if (VBOX_FAILURE(rc))
2092	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2093	break;
2094
2095	case VINF_PATM_HC_MMIO_PATCH_WRITE:
2096	AssertFailed(); /* not yet implemented. */
2097	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2098	break;
2099
2100	/*
2101	* Conflict or out of page tables.
2102	*
2103	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
2104	* do here is to execute the pending forced actions.
2105	*/
2106	case VINF_PGM_SYNC_CR3:
2107	AssertMsg(VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL),
2108	("VINF_PGM_SYNC_CR3 and no VM_FF_PGM_SYNC_CR3*!\n"));
2109	rc = VINF_SUCCESS;
2110	break;
2111
2112	/*
2113	* Paging mode change.
2114	*/
2115	case VINF_PGM_CHANGE_MODE:
2116	rc = PGMChangeMode(pVM, pCtx->cr0, pCtx->cr4, 0);
2117	if (VBOX_SUCCESS(rc))
2118	rc = VINF_EM_RESCHEDULE;
2119	break;
2120
2121	/*
2122	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
2123	*/
2124	case VINF_CSAM_PENDING_ACTION:
2125	rc = VINF_SUCCESS;
2126	break;
2127
2128	/*
2129	* Invoked Interrupt gate - must directly (!) go to the recompiler.
2130	*/
2131	case VINF_EM_RAW_INTERRUPT_PENDING:
2132	case VINF_EM_RAW_RING_SWITCH_INT:
2133	{
2134	uint8_t u8Interrupt;
2135
2136	Assert(TRPMHasTrap(pVM));
2137	Assert(!PATMIsPatchGCAddr(pVM, (RTGCPTR)pCtx->eip));
2138
2139	if (TRPMHasTrap(pVM))
2140	{
2141	u8Interrupt = TRPMGetTrapNo(pVM);
2142
2143	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
2144	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
2145	{
2146	CSAMR3CheckGates(pVM, u8Interrupt, 1);
2147	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
2148	/** @note If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
2149	}
2150	}
2151	rc = VINF_EM_RESCHEDULE_REM;
2152	break;
2153	}
2154
2155	/*
2156	* Other ring switch types.
2157	*/
2158	case VINF_EM_RAW_RING_SWITCH:
2159	rc = emR3RawRingSwitch(pVM);
2160	break;
2161
2162	/*
2163	* REMGCNotifyInvalidatePage() failed because of overflow.
2164	*/
2165	case VERR_REM_FLUSHED_PAGES_OVERFLOW:
2166	Assert((pCtx->ss & X86_SEL_RPL) != 1);
2167	REMR3ReplayInvalidatedPages(pVM);
2168	break;
2169
2170	/*
2171	* I/O Port access - emulate the instruction.
2172	*/
2173	case VINF_IOM_HC_IOPORT_READ:
2174	case VINF_IOM_HC_IOPORT_WRITE:
2175	rc = emR3RawExecuteIOInstruction(pVM);
2176	break;
2177
2178	/*
2179	* Memory mapped I/O access - emulate the instruction.
2180	*/
2181	case VINF_IOM_HC_MMIO_READ:
2182	case VINF_IOM_HC_MMIO_WRITE:
2183	case VINF_IOM_HC_MMIO_READ_WRITE:
2184	rc = emR3RawExecuteInstruction(pVM, "MMIO");
2185	break;
2186
2187	/*
2188	* Execute instruction.
2189	*/
2190	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
2191	rc = emR3RawExecuteInstruction(pVM, "LDT FAULT: ");
2192	break;
2193	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
2194	rc = emR3RawExecuteInstruction(pVM, "GDT FAULT: ");
2195	break;
2196	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
2197	rc = emR3RawExecuteInstruction(pVM, "IDT FAULT: ");
2198	break;
2199	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
2200	rc = emR3RawExecuteInstruction(pVM, "TSS FAULT: ");
2201	break;
2202	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
2203	rc = emR3RawExecuteInstruction(pVM, "PD FAULT: ");
2204	break;
2205
2206	case VINF_EM_RAW_EMULATE_INSTR_HLT:
2207	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
2208	rc = emR3RawPrivileged(pVM);
2209	break;
2210
2211	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
2212	rc = emR3RawExecuteInstruction(pVM, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
2213	break;
2214
2215	case VINF_EM_RAW_EMULATE_INSTR:
2216	case VINF_PATCH_EMULATE_INSTR:
2217	rc = emR3RawExecuteInstruction(pVM, "EMUL: ");
2218	break;
2219
2220	/*
2221	* Stale selector and iret traps => REM.
2222	*/
2223	case VINF_EM_RAW_STALE_SELECTOR:
2224	case VINF_EM_RAW_IRET_TRAP:
2225	/* We will not go to the recompiler if EIP points to patch code. */
2226	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
2227	{
2228	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
2229	}
2230	LogFlow(("emR3RawHandleRC: %Vrc -> %Vrc\n", rc, VINF_EM_RESCHEDULE_REM));
2231	rc = VINF_EM_RESCHEDULE_REM;
2232	break;
2233
2234	/*
2235	* Up a level.
2236	*/
2237	case VINF_EM_TERMINATE:
2238	case VINF_EM_OFF:
2239	case VINF_EM_RESET:
2240	case VINF_EM_SUSPEND:
2241	case VINF_EM_HALT:
2242	case VINF_EM_RESUME:
2243	case VINF_EM_RESCHEDULE:
2244	case VINF_EM_RESCHEDULE_REM:
2245	break;
2246
2247	/*
2248	* Up a level and invoke the debugger.
2249	*/
2250	case VINF_EM_DBG_STEPPED:
2251	case VINF_EM_DBG_BREAKPOINT:
2252	case VINF_EM_DBG_STEP:
2253	case VINF_EM_DBG_HYPER_ASSERTION:
2254	case VINF_EM_DBG_HYPER_BREAKPOINT:
2255	case VINF_EM_DBG_HYPER_STEPPED:
2256	case VINF_EM_DBG_STOP:
2257	break;
2258
2259	/*
2260	* Up a level, dump and debug.
2261	*/
2262	case VERR_TRPM_DONT_PANIC:
2263	case VERR_TRPM_PANIC:
2264	break;
2265
2266	/*
2267	* Anything which is not known to us means an internal error
2268	* and the termination of the VM!
2269	*/
2270	default:
2271	AssertMsgFailed(("Unknown GC return code: %Vra\n", rc));
2272	break;
2273	}
2274	return rc;
2275	}
2276
2277	/**
2278	* Check for pending raw actions
2279	*
2280	* @returns VBox status code.
2281	* @param pVM The VM to operate on.
2282	*/
2283	EMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM)
2284	{
2285	return emR3RawForcedActions(pVM, pVM->em.s.pCtx);
2286	}
2287
2288
2289	/**
2290	* Process raw-mode specific forced actions.
2291	*
2292	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
2293	*
2294	* @returns VBox status code.
2295	* Only the normal success/failure stuff, no VINF_EM_*.
2296	* @param pVM The VM handle.
2297	* @param pCtx The guest CPUM register context.
2298	*/
2299	static int emR3RawForcedActions(PVM pVM, PCPUMCTX pCtx)
2300	{
2301	/*
2302	* Note that the order is vitally important!
2303	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
2304	*/
2305
2306
2307	/*
2308	* Sync selector tables.
2309	*/
2310	if (VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT))
2311	{
2312	int rc = SELMR3UpdateFromCPUM(pVM);
2313	if (VBOX_FAILURE(rc))
2314	return rc;
2315	}
2316
2317	/*
2318	* Sync IDT.
2319	*/
2320	if (VM_FF_ISSET(pVM, VM_FF_TRPM_SYNC_IDT))
2321	{
2322	int rc = TRPMR3SyncIDT(pVM);
2323	if (VBOX_FAILURE(rc))
2324	return rc;
2325	}
2326
2327	/*
2328	* Sync TSS.
2329	*/
2330	if (VM_FF_ISSET(pVM, VM_FF_SELM_SYNC_TSS))
2331	{
2332	int rc = SELMR3SyncTSS(pVM);
2333	if (VBOX_FAILURE(rc))
2334	return rc;
2335	}
2336
2337	/*
2338	* Sync page directory.
2339	*/
2340	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
2341	{
2342	int rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2343	if (VBOX_FAILURE(rc))
2344	return rc;
2345
2346	Assert(!VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT));
2347
2348	/* Prefetch pages for EIP and ESP */
2349	/** @todo This is rather expensive. Should investigate if it really helps at all. */
2350	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));
2351	if (rc == VINF_SUCCESS)
2352	rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));
2353	if (rc != VINF_SUCCESS)
2354	{
2355	if (rc != VINF_PGM_SYNC_CR3)
2356	return rc;
2357	rc = PGMSyncCR3(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
2358	if (VBOX_FAILURE(rc))
2359	return rc;
2360	}
2361	/** @todo maybe prefetch the supervisor stack page as well */
2362	}
2363
2364	return VINF_SUCCESS;
2365	}
2366
2367
2368	/**
2369	* Executes raw code.
2370	*
2371	* This function contains the raw-mode version of the inner
2372	* execution loop (the outer loop being in EMR3ExecuteVM()).
2373	*
2374	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
2375	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2376	*
2377	* @param pVM VM handle.
2378	* @param pfFFDone Where to store an indicator telling whether or not
2379	* FFs were done before returning.
2380	*/
2381	static int emR3RawExecute(PVM pVM, bool *pfFFDone)
2382	{
2383	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTotal, a);
2384
2385	int rc = VERR_INTERNAL_ERROR;
2386	PCPUMCTX pCtx = pVM->em.s.pCtx;
2387	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2388	pVM->em.s.fForceRAW = false;
2389	*pfFFDone = false;
2390
2391
2392	/*
2393	*
2394	* Spin till we get a forced action or raw mode status code resulting in
2395	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
2396	*
2397	*/
2398	for (;;)
2399	{
2400	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWEntry, b);
2401
2402	/*
2403	* Check various preconditions.
2404	*/
2405	#ifdef VBOX_STRICT
2406	Assert(REMR3QueryPendingInterrupt(pVM) == REM_NO_PENDING_IRQ);
2407	Assert(!(pCtx->cr4 & X86_CR4_PAE));
2408	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
2409	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
2410	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
2411	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
2412	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2413	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2414	{
2415	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2416	return VERR_INTERNAL_ERROR;
2417	}
2418	#endif /* VBOX_STRICT */
2419
2420	/*
2421	* Process high priority pre-execution raw-mode FFs.
2422	*/
2423	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2424	{
2425	rc = emR3RawForcedActions(pVM, pCtx);
2426	if (VBOX_FAILURE(rc))
2427	break;
2428	}
2429
2430	/*
2431	* If we're going to execute ring-0 code, the guest state needs to
2432	* be modified a bit and some of the state components (IF, SS/CS RPL,
2433	* and perhaps EIP) needs to be stored with PATM.
2434	*/
2435	rc = CPUMRawEnter(pVM, NULL);
2436	if (rc != VINF_SUCCESS)
2437	{
2438	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2439	break;
2440	}
2441
2442	/*
2443	* Scan code before executing it. Don't bother with user mode or V86 code
2444	*/
2445	if ( (pCtx->ss & X86_SEL_RPL) <= 1
2446	&& !pCtx->eflags.Bits.u1VM
2447	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
2448	{
2449	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b);
2450	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2451	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b);
2452	}
2453
2454	#ifdef LOG_ENABLED
2455	/*
2456	* Log important stuff before entering GC.
2457	*/
2458	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
2459	if (pCtx->eflags.Bits.u1VM)
2460	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2461	else if ((pCtx->ss & X86_SEL_RPL) == 1)
2462	{
2463	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
2464	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
2465	}
2466	else if ((pCtx->ss & X86_SEL_RPL) == 3)
2467	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
2468	#endif /* LOG_ENABLED */
2469
2470
2471
2472	/*
2473	* Execute the code.
2474	*/
2475	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWEntry, b);
2476	STAM_PROFILE_START(&pVM->em.s.StatRAWExec, c);
2477	VMMR3Unlock(pVM);
2478	rc = VMMR3RawRunGC(pVM);
2479	VMMR3Lock(pVM);
2480	STAM_PROFILE_STOP(&pVM->em.s.StatRAWExec, c);
2481	STAM_PROFILE_ADV_START(&pVM->em.s.StatRAWTail, d);
2482
2483	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
2484	LogFlow(("VMMR3RawRunGC returned %Vrc\n", rc));
2485
2486	/*
2487	* Restore the real CPU state and deal with high priority post
2488	* execution FFs before doing anything else.
2489	*/
2490	rc = CPUMRawLeave(pVM, NULL, rc);
2491	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2492	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2493	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2494
2495	#ifdef PGM_CACHE_VERY_STRICT
2496	/*
2497	* Page manager cache checks.
2498	*/
2499	if ( rc == VINF_EM_RAW_INTERRUPT
2500	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2501	\|\| rc == VINF_IOM_HC_IOPORT_READ
2502	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2503	//\|\| rc == VINF_PATM_PATCH_INT3
2504	)
2505	pgmCacheCheckPD(pVM, pCtx->cr0, pCtx->cr3, pCtx->cr4);
2506	#endif
2507
2508	#ifdef VBOX_STRICT
2509	/*
2510	* Assert TSS consistency & rc vs patch code.
2511	*/
2512	if ( !VM_FF_ISPENDING(pVM, VM_FF_SELM_SYNC_TSS \| VM_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
2513	&& EMIsRawRing0Enabled(pVM))
2514	SELMR3CheckTSS(pVM);
2515	switch (rc)
2516	{
2517	case VINF_SUCCESS:
2518	case VINF_EM_RAW_INTERRUPT:
2519	case VINF_PATM_PATCH_TRAP_PF:
2520	case VINF_PATM_PATCH_TRAP_GP:
2521	case VINF_PATM_PATCH_INT3:
2522	case VINF_PATM_CHECK_PATCH_PAGE:
2523	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
2524	case VINF_EM_RAW_GUEST_TRAP:
2525	case VINF_EM_RESCHEDULE_RAW:
2526	break;
2527
2528	default:
2529	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
2530	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %VGv for reason %Vrc\n", CPUMGetGuestEIP(pVM), rc));
2531	break;
2532	}
2533	/*
2534	* Let's go paranoid!
2535	*/
2536	if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
2537	&& PGMR3MapHasConflicts(pVM, pCtx->cr3, pVM->fRawR0Enabled))
2538	{
2539	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
2540	return VERR_INTERNAL_ERROR;
2541	}
2542	#endif /* VBOX_STRICT */
2543
2544	/*
2545	* Process the returned status code.
2546	*/
2547	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2548	{
2549	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2550	break;
2551	}
2552	rc = emR3RawHandleRC(pVM, pCtx, rc);
2553	if (rc != VINF_SUCCESS)
2554	{
2555	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2556	if (rc != VINF_SUCCESS)
2557	{
2558	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2559	break;
2560	}
2561	}
2562
2563	/*
2564	* Check and execute forced actions.
2565	*/
2566	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2567	TMTimerPoll(pVM);
2568	#endif
2569	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTail, d);
2570	if (VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2571	{
2572	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
2573
2574	STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWTotal, a);
2575	rc = emR3ForcedActions(pVM, rc);
2576	STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWTotal, a);
2577	if ( rc != VINF_SUCCESS
2578	&& rc != VINF_EM_RESCHEDULE_RAW)
2579	{
2580	rc = emR3RawUpdateForceFlag(pVM, pCtx, rc);
2581	if (rc != VINF_SUCCESS)
2582	{
2583	*pfFFDone = true;
2584	break;
2585	}
2586	}
2587	}
2588	}
2589
2590	/*
2591	* Return to outer loop.
2592	*/
2593	#if defined(LOG_ENABLED) && defined(DEBUG)
2594	RTLogFlush(NULL);
2595	#endif
2596	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatRAWTotal, a);
2597	return rc;
2598	}
2599
2600
2601	/**
2602	* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
2603	*
2604	* This function contains the raw-mode version of the inner
2605	* execution loop (the outer loop being in EMR3ExecuteVM()).
2606	*
2607	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
2608	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2609	*
2610	* @param pVM VM handle.
2611	* @param pfFFDone Where to store an indicator telling whether or not
2612	* FFs were done before returning.
2613	*/
2614	static int emR3HwAccExecute(PVM pVM, bool *pfFFDone)
2615	{
2616	int rc = VERR_INTERNAL_ERROR;
2617	PCPUMCTX pCtx = pVM->em.s.pCtx;
2618
2619	LogFlow(("emR3HwAccExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
2620	*pfFFDone = false;
2621
2622	STAM_COUNTER_INC(&pVM->em.s.StatHwAccExecuteEntry);
2623
2624	/*
2625	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
2626	*/
2627	for (;;)
2628	{
2629	STAM_PROFILE_ADV_START(&pVM->em.s.StatHwAccEntry, a);
2630
2631	/*
2632	* Check various preconditions.
2633	*/
2634	VM_FF_CLEAR(pVM, (VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_TSS));
2635
2636	/*
2637	* Process high priority pre-execution raw-mode FFs.
2638	*/
2639	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK))
2640	{
2641	rc = emR3RawForcedActions(pVM, pCtx);
2642	if (VBOX_FAILURE(rc))
2643	break;
2644	}
2645
2646	#ifdef LOG_ENABLED
2647	uint8_t u8Vector;
2648
2649	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
2650	if (rc == VINF_SUCCESS)
2651	{
2652	Log(("Pending hardware interrupt %d\n", u8Vector));
2653	}
2654	/*
2655	* Log important stuff before entering GC.
2656	*/
2657	uint32_t cpl = CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx));
2658
2659	if (pCtx->eflags.Bits.u1VM)
2660	Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
2661	else
2662	Log(("HWR%d: %08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->cr0));
2663	#endif
2664
2665	/*
2666	* Execute the code.
2667	*/
2668	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatHwAccEntry, a);
2669	STAM_PROFILE_START(&pVM->em.s.StatHwAccExec, x);
2670	VMMR3Unlock(pVM);
2671	rc = VMMR3HwAccRunGC(pVM);
2672	VMMR3Lock(pVM);
2673	STAM_PROFILE_STOP(&pVM->em.s.StatHwAccExec, x);
2674
2675	/*
2676	* Deal with high priority post execution FFs before doing anything else.
2677	*/
2678	VM_FF_CLEAR(pVM, VM_FF_RESUME_GUEST_MASK);
2679	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK))
2680	rc = emR3HighPriorityPostForcedActions(pVM, rc);
2681
2682	/*
2683	* Process the returned status code.
2684	*/
2685	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
2686	break;
2687
2688	rc = emR3RawHandleRC(pVM, pCtx, rc);
2689	if (rc != VINF_SUCCESS)
2690	break;
2691
2692	/*
2693	* Check and execute forced actions.
2694	*/
2695	#ifdef VBOX_HIGH_RES_TIMERS_HACK
2696	TMTimerPoll(pVM);
2697	#endif
2698	if (VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK))
2699	{
2700	rc = emR3ForcedActions(pVM, rc);
2701	if ( rc != VINF_SUCCESS
2702	&& rc != VINF_EM_RESCHEDULE_HWACC)
2703	{
2704	*pfFFDone = true;
2705	break;
2706	}
2707	}
2708	}
2709	/*
2710	* Return to outer loop.
2711	*/
2712	#if defined(LOG_ENABLED) && defined(DEBUG)
2713	RTLogFlush(NULL);
2714	#endif
2715	return rc;
2716	}
2717
2718
2719	/**
2720	* Decides whether to execute RAW, HWACC or REM.
2721	*
2722	* @returns new EM state
2723	* @param pVM The VM.
2724	* @param pCtx The CPU context.
2725	*/
2726	inline EMSTATE emR3Reschedule(PVM pVM, PCPUMCTX pCtx)
2727	{
2728	/*
2729	* When forcing raw-mode execution, things are simple.
2730	*/
2731	if (pVM->em.s.fForceRAW)
2732	return EMSTATE_RAW;
2733
2734	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2735	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2736	/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
2737
2738	X86EFLAGS EFlags = pCtx->eflags;
2739	if (HWACCMIsEnabled(pVM))
2740	{
2741	/* Hardware accelerated raw-mode:
2742	*
2743	* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
2744	*/
2745	if (HWACCMR3CanExecuteGuest(pVM, pCtx) == true)
2746	return EMSTATE_HWACC;
2747
2748	/** @note Raw mode and hw accelerated mode are incompatible. The latter turns off monitoring features essential for raw mode! */
2749	return EMSTATE_REM;
2750	}
2751
2752	/* Standard raw-mode:
2753	*
2754	* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
2755	* or 32 bits protected mode ring 0 code
2756	*
2757	* The tests are ordered by the likelyhood of being true during normal execution.
2758	*/
2759	if (EFlags.u32 & (X86_EFL_TF /* \| HF_INHIBIT_IRQ_MASK*/))
2760	{
2761	Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
2762	return EMSTATE_REM;
2763	}
2764
2765	#ifndef VBOX_RAW_V86
2766	if (EFlags.u32 & X86_EFL_VM) {
2767	Log2(("raw mode refused: VM_MASK\n"));
2768	return EMSTATE_REM;
2769	}
2770	#endif
2771
2772	/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
2773	uint32_t u32CR0 = pCtx->cr0;
2774	if ((u32CR0 & (X86_CR0_PG \| X86_CR0_PE)) != (X86_CR0_PG \| X86_CR0_PE))
2775	{
2776	//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
2777	return EMSTATE_REM;
2778	}
2779
2780	if (pCtx->cr4 & X86_CR4_PAE)
2781	{
2782	//Log2(("raw mode refused: PAE\n"));
2783	return EMSTATE_REM;
2784	}
2785
2786	unsigned uSS = pCtx->ss;
2787	if ( pCtx->eflags.Bits.u1VM
2788	\|\| (uSS & X86_SEL_RPL) == 3)
2789	{
2790	if (!EMIsRawRing3Enabled(pVM))
2791	return EMSTATE_REM;
2792
2793	if (!(EFlags.u32 & X86_EFL_IF))
2794	{
2795	Log2(("raw mode refused: IF (RawR3)\n"));
2796	return EMSTATE_REM;
2797	}
2798
2799	if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
2800	{
2801	Log2(("raw mode refused: CR0.WP + RawR0\n"));
2802	return EMSTATE_REM;
2803	}
2804	}
2805	else
2806	{
2807	if (!EMIsRawRing0Enabled(pVM))
2808	return EMSTATE_REM;
2809
2810	/* Only ring 0 supervisor code. */
2811	if ((uSS & X86_SEL_RPL) != 0)
2812	{
2813	Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
2814	return EMSTATE_REM;
2815	}
2816
2817	// Let's start with pure 32 bits ring 0 code first
2818	/** @todo What's pure 32-bit mode? flat? */
2819	if ( !(pCtx->ssHid.Attr.n.u1DefBig)
2820	\|\| !(pCtx->csHid.Attr.n.u1DefBig))
2821	{
2822	Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
2823	return EMSTATE_REM;
2824	}
2825
2826	/* Write protection muts be turned on, or else the guest can overwrite our hypervisor code and data. */
2827	if (!(u32CR0 & X86_CR0_WP))
2828	{
2829	Log2(("raw r0 mode refused: CR0.WP=0!\n"));
2830	return EMSTATE_REM;
2831	}
2832
2833	if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
2834	{
2835	Log2(("raw r0 mode forced: patch code\n"));
2836	return EMSTATE_RAW;
2837	}
2838
2839	#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
2840	if (!(EFlags.u32 & X86_EFL_IF))
2841	{
2842	////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
2843	//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
2844	return EMSTATE_REM;
2845	}
2846	#endif
2847
2848	/** @todo still necessary??? */
2849	if (EFlags.Bits.u2IOPL != 0)
2850	{
2851	Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
2852	return EMSTATE_REM;
2853	}
2854	}
2855
2856	Assert(PGMPhysIsA20Enabled(pVM));
2857	return EMSTATE_RAW;
2858	}
2859
2860
2861	/**
2862	* Executes all high priority post execution force actions.
2863	*
2864	* @returns rc or a fatal status code.
2865	*
2866	* @param pVM VM handle.
2867	* @param rc The current rc.
2868	*/
2869	static int emR3HighPriorityPostForcedActions(PVM pVM, int rc)
2870	{
2871	if (VM_FF_ISSET(pVM, VM_FF_PDM_CRITSECT))
2872	PDMR3CritSectFF(pVM);
2873
2874	if (VM_FF_ISSET(pVM, VM_FF_CSAM_PENDING_ACTION))
2875	CSAMR3DoPendingAction(pVM);
2876
2877	return rc;
2878	}
2879
2880
2881	/**
2882	* Executes all pending forced actions.
2883	*
2884	* Forced actions can cause execution delays and execution
2885	* rescheduling. The first we deal with using action priority, so
2886	* that for instance pending timers aren't scheduled and ran until
2887	* right before execution. The rescheduling we deal with using
2888	* return codes. The same goes for VM termination, only in that case
2889	* we exit everything.
2890	*
2891	* @returns VBox status code of equal or greater importance/severity than rc.
2892	* The most important ones are: VINF_EM_RESCHEDULE,
2893	* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
2894	*
2895	* @param pVM VM handle.
2896	* @param rc The current rc.
2897	*
2898	*/
2899	static int emR3ForcedActions(PVM pVM, int rc)
2900	{
2901	#ifdef VBOX_STRICT
2902	int rcIrq = VINF_SUCCESS;
2903	#endif
2904	STAM_PROFILE_START(&pVM->em.s.StatForcedActions, a);
2905
2906	#define UPDATE_RC() \
2907	do { \
2908	AssertMsg(rc2 <= 0 \|\| (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Vra\n", rc2)); \
2909	if (rc2 == VINF_SUCCESS \|\| rc < VINF_SUCCESS) \
2910	break; \
2911	if (!rc \|\| rc2 < rc) \
2912	rc = rc2; \
2913	} while (0)
2914
2915	int rc2;
2916
2917	/*
2918	* Post execution chunk first.
2919	*/
2920	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK))
2921	{
2922	/*
2923	* Termination request.
2924	*/
2925	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
2926	{
2927	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
2928	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2929	return VINF_EM_TERMINATE;
2930	}
2931
2932	/*
2933	* Debugger Facility polling.
2934	*/
2935	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
2936	{
2937	rc2 = DBGFR3VMMForcedAction(pVM);
2938	UPDATE_RC();
2939	}
2940
2941	/*
2942	* Postponed reset request.
2943	*/
2944	if (VM_FF_ISSET(pVM, VM_FF_RESET))
2945	{
2946	rc2 = VMR3Reset(pVM);
2947	UPDATE_RC();
2948	VM_FF_CLEAR(pVM, VM_FF_RESET);
2949	}
2950
2951	/*
2952	* CSAM page scanning.
2953	*/
2954	if (VM_FF_ISSET(pVM, VM_FF_CSAM_SCAN_PAGE))
2955	{
2956	PCPUMCTX pCtx = pVM->em.s.pCtx;
2957
2958	/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
2959	Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n"));
2960
2961	CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);
2962	VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE);
2963	}
2964
2965	/* check that we got them all */
2966	Assert(!(VM_FF_NORMAL_PRIORITY_POST_MASK & ~(VM_FF_TERMINATE \| VM_FF_DBGF \| VM_FF_RESET \| VM_FF_CSAM_SCAN_PAGE)));
2967	}
2968
2969	/*
2970	* Normal priority then.
2971	* (Executed in no particular order.)
2972	*/
2973	if (VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_MASK))
2974	{
2975	/*
2976	* PDM Queues are pending.
2977	*/
2978	if (VM_FF_ISSET(pVM, VM_FF_PDM_QUEUES))
2979	PDMR3QueueFlushAll(pVM);
2980
2981	/*
2982	* PDM DMA transfers are pending.
2983	*/
2984	if (VM_FF_ISSET(pVM, VM_FF_PDM_DMA))
2985	PDMR3DmaRun(pVM);
2986
2987	/*
2988	* Requests from other threads.
2989	*/
2990	if (VM_FF_ISSET(pVM, VM_FF_REQUEST))
2991	{
2992	rc2 = VMR3ReqProcess(pVM);
2993	if (rc2 == VINF_EM_OFF \|\| rc2 == VINF_EM_TERMINATE)
2994	{
2995	Log2(("emR3ForcedActions: returns %Vrc\n", rc2));
2996	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
2997	return rc2;
2998	}
2999	UPDATE_RC();
3000	}
3001
3002	/* check that we got them all */
3003	Assert(!(VM_FF_NORMAL_PRIORITY_MASK & ~(VM_FF_REQUEST \| VM_FF_PDM_QUEUES \| VM_FF_PDM_DMA)));
3004	}
3005
3006	/*
3007	* Execute polling function ever so often.
3008	* THIS IS A HACK, IT WILL BE REPLACED BY PROPER ASYNC NETWORKING SOON!
3009	*/
3010	static unsigned cLast = 0;
3011	if (!((++cLast) % 4))
3012	PDMR3Poll(pVM);
3013
3014	/*
3015	* High priority pre execution chunk last.
3016	* (Executed in ascending priority order.)
3017	*/
3018	if (VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK))
3019	{
3020	/*
3021	* Timers before interrupts.
3022	*/
3023	if (VM_FF_ISSET(pVM, VM_FF_TIMER))
3024	TMR3TimerQueuesDo(pVM);
3025
3026	/*
3027	* The instruction following an emulated STI should always be executed!
3028	*/
3029	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
3030	{
3031	Log(("VM_FF_EMULATED_STI at %VGv successor %VGv\n", CPUMGetGuestEIP(pVM), EMGetInhibitInterruptsPC(pVM)));
3032	if (CPUMGetGuestEIP(pVM) != EMGetInhibitInterruptsPC(pVM))
3033	{
3034	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
3035	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
3036	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
3037	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
3038	*/
3039	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
3040	}
3041	if (HWACCMR3IsActive(pVM))
3042	rc2 = VINF_EM_RESCHEDULE_HWACC;
3043	else
3044	rc2 = PATMAreInterruptsEnabled(pVM) ? VINF_EM_RESCHEDULE_RAW : VINF_EM_RESCHEDULE_REM;
3045
3046	UPDATE_RC();
3047	}
3048
3049	/*
3050	* Interrupts.
3051	*/
3052	if ( !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS)
3053	&& (!rc \|\| rc >= VINF_EM_RESCHEDULE_RAW)
3054	&& !TRPMHasTrap(pVM) /* an interrupt could already be scheduled for dispatching in the recompiler. */
3055	&& PATMAreInterruptsEnabled(pVM)
3056	&& !HWACCMR3IsEventPending(pVM))
3057	{
3058	if (VM_FF_ISPENDING(pVM, VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC))
3059	{
3060	/** @note it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
3061	/** @todo this really isn't nice, should properly handle this */
3062	rc2 = TRPMR3InjectEvent(pVM, TRPM_HARDWARE_INT);
3063	#ifdef VBOX_STRICT
3064	rcIrq = rc2;
3065	#endif
3066	UPDATE_RC();
3067	}
3068	/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
3069	else if (REMR3QueryPendingInterrupt(pVM) != REM_NO_PENDING_IRQ)
3070	{
3071	rc2 = VINF_EM_RESCHEDULE_REM;
3072	UPDATE_RC();
3073	}
3074	}
3075
3076	/*
3077	* Debugger Facility request.
3078	*/
3079	if (VM_FF_ISSET(pVM, VM_FF_DBGF))
3080	{
3081	rc2 = DBGFR3VMMForcedAction(pVM);
3082	UPDATE_RC();
3083	}
3084
3085	/*
3086	* Termination request.
3087	*/
3088	if (VM_FF_ISSET(pVM, VM_FF_TERMINATE))
3089	{
3090	Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
3091	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3092	return VINF_EM_TERMINATE;
3093	}
3094
3095	#ifdef DEBUG
3096	/*
3097	* Debug, pause the VM.
3098	*/
3099	if (VM_FF_ISSET(pVM, VM_FF_DEBUG_SUSPEND))
3100	{
3101	VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
3102	Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
3103	return VINF_EM_SUSPEND;
3104	}
3105
3106	#endif
3107	/* check that we got them all */
3108	Assert(!(VM_FF_HIGH_PRIORITY_PRE_MASK & ~(VM_FF_TIMER \| VM_FF_INTERRUPT_APIC \| VM_FF_INTERRUPT_PIC \| VM_FF_DBGF \| VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL \| VM_FF_SELM_SYNC_TSS \| VM_FF_TRPM_SYNC_IDT \| VM_FF_SELM_SYNC_GDT \| VM_FF_SELM_SYNC_LDT \| VM_FF_TERMINATE \| VM_FF_DEBUG_SUSPEND \| VM_FF_INHIBIT_INTERRUPTS)));
3109	}
3110
3111	#undef UPDATE_RC
3112	Log2(("emR3ForcedActions: returns %Vrc\n", rc));
3113	STAM_PROFILE_STOP(&pVM->em.s.StatForcedActions, a);
3114	Assert(rcIrq == VINF_SUCCESS \|\| rcIrq == rc);
3115	return rc;
3116	}
3117
3118
3119	/**
3120	* Execute VM.
3121	*
3122	* This function is the main loop of the VM. The emulation thread
3123	* calls this function when the VM has been successfully constructed
3124	* and we're ready for executing the VM.
3125	*
3126	* Returning from this function means that the VM is turned off or
3127	* suspended (state already saved) and deconstruction in next in line.
3128	*
3129	* All interaction from other thread are done using forced actions
3130	* and signaling of the wait object.
3131	*
3132	* @returns VBox status code.
3133	* @param pVM The VM to operate on.
3134	*/
3135	EMR3DECL(int) EMR3ExecuteVM(PVM pVM)
3136	{
3137	LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
3138	pVM->em.s.enmState, EMR3GetStateName(pVM->em.s.enmState), pVM->em.s.fForceRAW));
3139	VM_ASSERT_EMT(pVM);
3140	Assert(pVM->em.s.enmState == EMSTATE_NONE \|\| pVM->em.s.enmState == EMSTATE_SUSPENDED);
3141
3142	VMMR3Lock(pVM);
3143
3144	int rc = setjmp(pVM->em.s.u.FatalLongJump);
3145	if (rc == 0)
3146	{
3147	/*
3148	* Start the virtual time.
3149	*/
3150	rc = TMVirtualResume(pVM);
3151	Assert(rc == VINF_SUCCESS);
3152	rc = TMCpuTickResume(pVM);
3153	Assert(rc == VINF_SUCCESS);
3154
3155	/*
3156	* The Outer Main Loop.
3157	*/
3158	bool fFFDone = false;
3159	rc = VINF_EM_RESCHEDULE;
3160	pVM->em.s.enmState = EMSTATE_REM;
3161	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3162	for (;;)
3163	{
3164	/*
3165	* Before we can schedule anything (we're here because
3166	* scheduling is required) we must service any pending
3167	* forced actions to avoid any pending action causing
3168	* immidate rescheduling upon entering an inner loop
3169	*
3170	* Do forced actions.
3171	*/
3172	if ( !fFFDone
3173	&& rc != VINF_EM_TERMINATE
3174	&& rc != VINF_EM_OFF
3175	&& VM_FF_ISPENDING(pVM, VM_FF_ALL_BUT_RAW_MASK))
3176	{
3177	rc = emR3ForcedActions(pVM, rc);
3178	if ( ( rc == VINF_EM_RESCHEDULE_REM
3179	\|\| rc == VINF_EM_RESCHEDULE_HWACC)
3180	&& pVM->em.s.fForceRAW)
3181	rc = VINF_EM_RESCHEDULE_RAW;
3182	}
3183	else if (fFFDone)
3184	fFFDone = false;
3185
3186	/*
3187	* Now what to do?
3188	*/
3189	Log2(("EMR3ExecuteVM: rc=%Vrc\n", rc));
3190	switch (rc)
3191	{
3192	/*
3193	* Keep doing what we're currently doing.
3194	*/
3195	case VINF_SUCCESS:
3196	break;
3197
3198	/*
3199	* Reschedule - to raw-mode execution.
3200	*/
3201	case VINF_EM_RESCHEDULE_RAW:
3202	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVM->em.s.enmState, EMSTATE_RAW));
3203	pVM->em.s.enmState = EMSTATE_RAW;
3204	break;
3205
3206	/*
3207	* Reschedule - to hardware accelerated raw-mode execution.
3208	*/
3209	case VINF_EM_RESCHEDULE_HWACC:
3210	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVM->em.s.enmState, EMSTATE_HWACC));
3211	Assert(!pVM->em.s.fForceRAW);
3212	pVM->em.s.enmState = EMSTATE_HWACC;
3213	break;
3214
3215	/*
3216	* Reschedule - to recompiled execution.
3217	*/
3218	case VINF_EM_RESCHEDULE_REM:
3219	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVM->em.s.enmState, EMSTATE_REM));
3220	pVM->em.s.enmState = EMSTATE_REM;
3221	break;
3222
3223	/*
3224	* Resume.
3225	*/
3226	case VINF_EM_RESUME:
3227	Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", pVM->em.s.enmState));
3228	/* fall through and get scheduled. */
3229
3230	/*
3231	* Reschedule.
3232	*/
3233	case VINF_EM_RESCHEDULE:
3234	{
3235	EMSTATE enmState = emR3Reschedule(pVM, pVM->em.s.pCtx);
3236	Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVM->em.s.enmState, enmState, EMR3GetStateName(enmState)));
3237	pVM->em.s.enmState = enmState;
3238	break;
3239	}
3240
3241	/*
3242	* Halted.
3243	*/
3244	case VINF_EM_HALT:
3245	Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", pVM->em.s.enmState, EMSTATE_HALTED));
3246	pVM->em.s.enmState = EMSTATE_HALTED;
3247	break;
3248
3249	/*
3250	* Suspend.
3251	*/
3252	case VINF_EM_SUSPEND:
3253	Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", pVM->em.s.enmState, EMSTATE_SUSPENDED));
3254	pVM->em.s.enmState = EMSTATE_SUSPENDED;
3255	break;
3256
3257	/*
3258	* Reset.
3259	* We might end up doing a double reset for now, we'll have to clean up the mess later.
3260	*/
3261	case VINF_EM_RESET:
3262	Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d\n", pVM->em.s.enmState, EMSTATE_REM));
3263	pVM->em.s.enmState = EMSTATE_REM;
3264	break;
3265
3266	/*
3267	* Power Off.
3268	*/
3269	case VINF_EM_OFF:
3270	pVM->em.s.enmState = EMSTATE_TERMINATING;
3271	Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3272	TMVirtualPause(pVM);
3273	TMCpuTickPause(pVM);
3274	VMMR3Unlock(pVM);
3275	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3276	return rc;
3277
3278	/*
3279	* Terminate the VM.
3280	*/
3281	case VINF_EM_TERMINATE:
3282	pVM->em.s.enmState = EMSTATE_TERMINATING;
3283	Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVM->em.s.enmState, EMSTATE_TERMINATING));
3284	TMVirtualPause(pVM);
3285	TMCpuTickPause(pVM);
3286	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3287	return rc;
3288
3289	/*
3290	* Guest debug events.
3291	*/
3292	case VINF_EM_DBG_STEPPED:
3293	AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
3294	case VINF_EM_DBG_STOP:
3295	case VINF_EM_DBG_BREAKPOINT:
3296	case VINF_EM_DBG_STEP:
3297	if (pVM->em.s.enmState == EMSTATE_RAW)
3298	{
3299	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_RAW));
3300	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
3301	}
3302	else
3303	{
3304	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_GUEST_REM));
3305	pVM->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
3306	}
3307	break;
3308
3309	/*
3310	* Hypervisor debug events.
3311	*/
3312	case VINF_EM_DBG_HYPER_STEPPED:
3313	case VINF_EM_DBG_HYPER_BREAKPOINT:
3314	case VINF_EM_DBG_HYPER_ASSERTION:
3315	Log2(("EMR3ExecuteVM: %Vrc: %d -> %d\n", rc, pVM->em.s.enmState, EMSTATE_DEBUG_HYPER));
3316	pVM->em.s.enmState = EMSTATE_DEBUG_HYPER;
3317	break;
3318
3319	/*
3320	* Any error code showing up here other than the ones we
3321	* know and process above are considered to be FATAL.
3322	*
3323	* Unknown warnings and informational status codes are also
3324	* included in this.
3325	*/
3326	default:
3327	if (VBOX_SUCCESS(rc))
3328	{
3329	AssertMsgFailed(("Unexpected warning or informational status code %Vra!\n", rc));
3330	rc = VERR_EM_INTERNAL_ERROR;
3331	}
3332	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3333	Log(("EMR3ExecuteVM returns %d\n", rc));
3334	break;
3335	}
3336
3337
3338	/*
3339	* Any waiters can now be woken up
3340	*/
3341	VMMR3Unlock(pVM);
3342	VMMR3Lock(pVM);
3343
3344	STAM_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x); /* (skip this in release) */
3345	STAM_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3346
3347	/*
3348	* Act on the state.
3349	*/
3350	switch (pVM->em.s.enmState)
3351	{
3352	/*
3353	* Execute raw.
3354	*/
3355	case EMSTATE_RAW:
3356	rc = emR3RawExecute(pVM, &fFFDone);
3357	break;
3358
3359	/*
3360	* Execute hardware accelerated raw.
3361	*/
3362	case EMSTATE_HWACC:
3363	rc = emR3HwAccExecute(pVM, &fFFDone);
3364	break;
3365
3366	/*
3367	* Execute recompiled.
3368	*/
3369	case EMSTATE_REM:
3370	rc = emR3RemExecute(pVM, &fFFDone);
3371	Log2(("EMR3ExecuteVM: emR3RemExecute -> %Vrc\n", rc));
3372	break;
3373
3374	/*
3375	* hlt - execution halted until interrupt.
3376	*/
3377	case EMSTATE_HALTED:
3378	{
3379	STAM_REL_PROFILE_START(&pVM->em.s.StatHalted, y);
3380	rc = VMR3WaitHalted(pVM, !(CPUMGetGuestEFlags(pVM) & X86_EFL_IF));
3381	STAM_REL_PROFILE_STOP(&pVM->em.s.StatHalted, y);
3382	break;
3383	}
3384
3385	/*
3386	* Suspended - return to VM.cpp.
3387	*/
3388	case EMSTATE_SUSPENDED:
3389	TMVirtualPause(pVM);
3390	TMCpuTickPause(pVM);
3391	VMMR3Unlock(pVM);
3392	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3393	return VINF_EM_SUSPEND;
3394
3395	/*
3396	* Debugging in the guest.
3397	*/
3398	case EMSTATE_DEBUG_GUEST_REM:
3399	case EMSTATE_DEBUG_GUEST_RAW:
3400	TMVirtualPause(pVM);
3401	TMCpuTickPause(pVM);
3402	rc = emR3Debug(pVM, rc);
3403	TMVirtualResume(pVM);
3404	TMCpuTickResume(pVM);
3405	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3406	break;
3407
3408	/*
3409	* Debugging in the hypervisor.
3410	*/
3411	case EMSTATE_DEBUG_HYPER:
3412	{
3413	TMVirtualPause(pVM);
3414	TMCpuTickPause(pVM);
3415	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3416
3417	rc = emR3Debug(pVM, rc);
3418	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3419	if (rc != VINF_SUCCESS)
3420	{
3421	/* switch to guru meditation mode */
3422	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3423	VMMR3FatalDump(pVM, rc);
3424	return rc;
3425	}
3426
3427	STAM_REL_PROFILE_ADV_START(&pVM->em.s.StatTotal, x);
3428	TMVirtualResume(pVM);
3429	TMCpuTickResume(pVM);
3430	break;
3431	}
3432
3433	/*
3434	* Guru meditation takes place in the debugger.
3435	*/
3436	case EMSTATE_GURU_MEDITATION:
3437	{
3438	/** @todo this ain't entirely safe. make a better return code check and specify this in DBGF/emR3Debug. */
3439	TMVirtualPause(pVM);
3440	TMCpuTickPause(pVM);
3441	VMMR3FatalDump(pVM, rc);
3442	int rc2 = emR3Debug(pVM, rc);
3443	if (rc2 == VERR_DBGF_NOT_ATTACHED)
3444	{
3445	VMMR3Unlock(pVM);
3446	/** @todo change the VM state! */
3447	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3448	return rc;
3449	}
3450	TMVirtualResume(pVM);
3451	TMCpuTickResume(pVM);
3452	rc = rc2;
3453	/** @todo we're not doing the right thing in emR3Debug and will cause code to be executed on disconnect and stuff.. */
3454	Log2(("EMR3ExecuteVM: enmr3Debug -> %Vrc (state %d)\n", rc, pVM->em.s.enmState));
3455	break;
3456	}
3457
3458	/*
3459	* The states we don't expect here.
3460	*/
3461	case EMSTATE_NONE:
3462	case EMSTATE_TERMINATING:
3463	default:
3464	AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVM->em.s.enmState));
3465	pVM->em.s.enmState = EMSTATE_GURU_MEDITATION;
3466	TMVirtualPause(pVM);
3467	TMCpuTickPause(pVM);
3468	VMMR3Unlock(pVM);
3469	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3470	return VERR_EM_INTERNAL_ERROR;
3471	}
3472	} /* The Outer Main Loop */
3473	}
3474	else
3475	{
3476	/*
3477	* Fatal error.
3478	*/
3479	LogFlow(("EMR3ExecuteVM: returns %Vrc (longjmp / fatal error)\n", rc));
3480	TMVirtualPause(pVM);
3481	TMCpuTickPause(pVM);
3482	VMMR3FatalDump(pVM, rc);
3483	emR3Debug(pVM, rc);
3484	VMMR3Unlock(pVM);
3485	STAM_REL_PROFILE_ADV_STOP(&pVM->em.s.StatTotal, x);
3486	/** @todo change the VM state! */
3487	return rc;
3488	}
3489
3490	/* (won't ever get here). */
3491	AssertFailed();
3492	}
3493

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source: vbox/trunk/src/VBox/VMM/EM.cpp@ 4041

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