DBGFDisas.cpp@ 9154

Last change on this file since 9154 was 9154, checked in by vboxsync, 16 years ago
Corrected code that doesn't compile with GC_ARCH_BITS=64.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 25.5 KB

Line
1	/* $Id: DBGFDisas.cpp 9154 2008-05-27 11:33:58Z vboxsync $ */
2	/** @file
3	* VMM DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DBGF
27	#include <VBox/dbgf.h>
28	#include <VBox/selm.h>
29	#include <VBox/mm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/cpum.h>
32	#include "DBGFInternal.h"
33	#include <VBox/dis.h>
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36
37	#include <VBox/log.h>
38	#include <iprt/assert.h>
39	#include <iprt/string.h>
40	#include <iprt/alloca.h>
41	#include <iprt/ctype.h>
42
43
44	/*******************************************************************************
45	* Internal Functions *
46	*******************************************************************************/
47	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
48
49
50	/**
51	* Structure used when disassembling and instructions in DBGF.
52	* This is used so the reader function can get the stuff it needs.
53	*/
54	typedef struct
55	{
56	/** The core structure. */
57	DISCPUSTATE Cpu;
58	/** The VM handle. */
59	PVM pVM;
60	/** Pointer to the first byte in the segemnt. */
61	RTGCUINTPTR GCPtrSegBase;
62	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
63	RTGCUINTPTR GCPtrSegEnd;
64	/** The size of the segment minus 1. */
65	RTGCUINTPTR cbSegLimit;
66	/** The guest paging mode. */
67	PGMMODE enmMode;
68	/** Pointer to the current page - HC Ptr. */
69	void const *pvPageHC;
70	/** Pointer to the current page - GC Ptr. */
71	RTGCPTR pvPageGC;
72	/** Pointer to the next instruction (relative to GCPtrSegBase). */
73	RTGCUINTPTR GCPtrNext;
74	/** The lock information that PGMPhysReleasePageMappingLock needs. */
75	PGMPAGEMAPLOCK PageMapLock;
76	/** Whether the PageMapLock is valid or not. */
77	bool fLocked;
78	} DBGFDISASSTATE, *PDBGFDISASSTATE;
79
80
81
82	/**
83	* Calls the dissassembler with the proper reader functions and such for disa
84	*
85	* @returns VBox status code.
86	* @param pVM VM handle
87	* @param pSelInfo The selector info.
88	* @param enmMode The guest paging mode.
89	* @param GCPtr The GC pointer (selector offset).
90	* @param pState The disas CPU state.
91	*/
92	static int dbgfR3DisasInstrFirst(PVM pVM, PSELMSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
93	{
94	pState->Cpu.mode = pSelInfo->Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
95	pState->Cpu.pfnReadBytes = dbgfR3DisasInstrRead;
96	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
97	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
98	pState->cbSegLimit = pSelInfo->cbLimit;
99	pState->enmMode = enmMode;
100	pState->pvPageGC = 0;
101	pState->pvPageHC = NULL;
102	pState->pVM = pVM;
103	pState->fLocked = false;
104	Assert((uintptr_t)GCPtr == GCPtr);
105	uint32_t cbInstr;
106	int rc = DISInstr(&pState->Cpu, GCPtr, 0, &cbInstr, NULL);
107	if (VBOX_SUCCESS(rc))
108	{
109	pState->GCPtrNext = GCPtr + cbInstr;
110	return VINF_SUCCESS;
111	}
112
113	/* cleanup */
114	if (pState->fLocked)
115	{
116	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
117	pState->fLocked = false;
118	}
119	return rc;
120	}
121
122
123	#if 0
124	/**
125	* Calls the dissassembler for disassembling the next instruction.
126	*
127	* @returns VBox status code.
128	* @param pState The disas CPU state.
129	*/
130	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
131	{
132	uint32_t cbInstr;
133	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
134	if (VBOX_SUCCESS(rc))
135	{
136	pState->GCPtrNext = GCPtr + cbInstr;
137	return VINF_SUCCESS;
138	}
139	return rc;
140	}
141	#endif
142
143
144	/**
145	* Done with the dissassembler state, free associated resources.
146	*
147	* @param pState The disas CPU state ++.
148	*/
149	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
150	{
151	if (pState->fLocked)
152	{
153	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
154	pState->fLocked = false;
155	}
156	}
157
158
159	/**
160	* Instruction reader.
161	*
162	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
163	* @param PtrSrc Address to read from.
164	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
165	* @param pu8Dst Where to store the bytes.
166	* @param cbRead Number of bytes to read.
167	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
168	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
169	*/
170	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
171	{
172	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
173	Assert(cbRead > 0);
174	for (;;)
175	{
176	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
177
178	/* Need to update the page translation? */
179	if ( !pState->pvPageHC
180	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
181	{
182	int rc = VINF_SUCCESS;
183
184	/* translate the address */
185	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
186	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
187	{
188	pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
189	if (!pState->pvPageHC)
190	rc = VERR_INVALID_POINTER;
191	}
192	else
193	{
194	if (pState->fLocked)
195	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
196
197	if (pState->enmMode <= PGMMODE_PROTECTED)
198	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
199	else
200	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
201	pState->fLocked = RT_SUCCESS_NP(rc);
202	}
203	if (VBOX_FAILURE(rc))
204	{
205	pState->pvPageHC = NULL;
206	return rc;
207	}
208	}
209
210	/* check the segemnt limit */
211	if (PtrSrc > pState->cbSegLimit)
212	return VERR_OUT_OF_SELECTOR_BOUNDS;
213
214	/* calc how much we can read */
215	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
216	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
217	if (cb > cbSeg && cbSeg)
218	cb = cbSeg;
219	if (cb > cbRead)
220	cb = cbRead;
221
222	/* read and advance */
223	memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
224	cbRead -= cb;
225	if (!cbRead)
226	return VINF_SUCCESS;
227	pu8Dst += cb;
228	PtrSrc += cb;
229	}
230	}
231
232
233	/**
234	* Copy a string and return pointer to the terminator char in the copy.
235	*/
236	inline char mystrpcpy(char pszDst, const char *pszSrc)
237	{
238	size_t cch = strlen(pszSrc);
239	memcpy(pszDst, pszSrc, cch + 1);
240	return pszDst + cch;
241	}
242
243
244	/**
245	* Disassembles the one instruction according to the specified flags and address.
246	*
247	* @returns VBox status code.
248	* @param pVM VM handle.
249	* @param Sel The code selector. This used to determin the 32/16 bit ness and
250	* calculation of the actual instruction address.
251	* @param GCPtr The code address relative to the base of Sel.
252	* @param fFlags Flags controlling where to start and how to format.
253	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
254	* @param pszOutput Output buffer.
255	* @param cchOutput Size of the output buffer.
256	* @param pcbInstr Where to return the size of the instruction.
257	*/
258	DBGFR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags, char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
259	{
260	/*
261	* Get the Sel and GCPtr if fFlags requests that.
262	*/
263	PCCPUMCTXCORE pCtxCore = NULL;
264	CPUMSELREGHID *pHiddenSel = NULL;
265	int rc;
266	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
267	{
268	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
269	pCtxCore = CPUMGetGuestCtxCore(pVM);
270	else
271	pCtxCore = CPUMGetHyperCtxCore(pVM);
272	Sel = pCtxCore->cs;
273	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
274	GCPtr = pCtxCore->eip;
275	}
276
277	/*
278	* Read the selector info - assume no stale selectors and nasty stuff like that.
279	* Since the selector flags in the CPUMCTX structures aren't up to date unless
280	* we recently visited REM, we'll not search for the selector there.
281	*/
282	SELMSELINFO SelInfo;
283	const PGMMODE enmMode = PGMGetGuestMode(pVM);
284	bool fRealModeAddress = false;
285
286	if ( pHiddenSel
287	&& CPUMAreHiddenSelRegsValid(pVM))
288	{
289	SelInfo.GCPtrBase = pHiddenSel->u32Base;
290	SelInfo.cbLimit = pHiddenSel->u32Limit;
291	SelInfo.fHyper = false;
292	SelInfo.fRealMode = !!((pCtxCore && pCtxCore->eflags.Bits.u1VM) \|\| enmMode == PGMMODE_REAL);
293	SelInfo.Raw.au32[0] = 0;
294	SelInfo.Raw.au32[1] = 0;
295	SelInfo.Raw.Gen.u16LimitLow = ~0;
296	SelInfo.Raw.Gen.u4LimitHigh = ~0;
297	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
298	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
299	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
300	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
301	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
302	fRealModeAddress = SelInfo.fRealMode;
303	}
304	else if (Sel == DBGF_SEL_FLAT)
305	{
306	SelInfo.GCPtrBase = 0;
307	SelInfo.cbLimit = ~0;
308	SelInfo.fHyper = false;
309	SelInfo.fRealMode = false;
310	SelInfo.Raw.au32[0] = 0;
311	SelInfo.Raw.au32[1] = 0;
312	SelInfo.Raw.Gen.u16LimitLow = ~0;
313	SelInfo.Raw.Gen.u4LimitHigh = ~0;
314	SelInfo.Raw.Gen.u1Present = 1;
315	SelInfo.Raw.Gen.u1Granularity = 1;
316	SelInfo.Raw.Gen.u1DefBig = 1;
317	SelInfo.Raw.Gen.u1DescType = 1;
318	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
319	}
320	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
321	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
322	\|\| enmMode == PGMMODE_REAL) )
323	{ /* V86 mode or real mode - real mode addressing */
324	SelInfo.GCPtrBase = Sel * 16;
325	SelInfo.cbLimit = ~0;
326	SelInfo.fHyper = false;
327	SelInfo.fRealMode = true;
328	SelInfo.Raw.au32[0] = 0;
329	SelInfo.Raw.au32[1] = 0;
330	SelInfo.Raw.Gen.u16LimitLow = ~0;
331	SelInfo.Raw.Gen.u4LimitHigh = ~0;
332	SelInfo.Raw.Gen.u1Present = 1;
333	SelInfo.Raw.Gen.u1Granularity = 1;
334	SelInfo.Raw.Gen.u1DefBig = 0; /* 16 bits */
335	SelInfo.Raw.Gen.u1DescType = 1;
336	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
337	fRealModeAddress = true;
338	}
339	else
340	{
341	rc = SELMR3GetSelectorInfo(pVM, Sel, &SelInfo);
342	if (VBOX_FAILURE(rc))
343	{
344	RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Vrc\n", Sel, rc);
345	return rc;
346	}
347	}
348
349	/*
350	* Disassemble it.
351	*/
352	DBGFDISASSTATE State;
353	rc = dbgfR3DisasInstrFirst(pVM, &SelInfo, enmMode, GCPtr, &State);
354	if (VBOX_FAILURE(rc))
355	{
356	RTStrPrintf(pszOutput, cchOutput, "Disas -> %Vrc\n", rc);
357	return rc;
358	}
359
360	/*
361	* Format it.
362	*/
363	char szBuf[512];
364	char *psz = &szBuf[0];
365
366	/* prefix */
367	if (State.Cpu.prefix & PREFIX_LOCK)
368	psz = (char *)memcpy(psz, "lock ", sizeof("lock ")) + sizeof("lock ") - 1;
369	if (State.Cpu.prefix & PREFIX_REP)
370	psz = (char *)memcpy(psz, "rep(e) ", sizeof("rep(e) ")) + sizeof("rep(e) ") - 1;
371	else if(State.Cpu.prefix & PREFIX_REPNE)
372	psz = (char *)memcpy(psz, "repne ", sizeof("repne ")) + sizeof("repne ") - 1;
373
374	/* the instruction */
375	const char *pszFormat = State.Cpu.pszOpcode;
376	char ch;
377	while ((ch = *pszFormat) && !isspace(ch) && ch != '%')
378	{
379	*psz++ = ch;
380	pszFormat++;
381	}
382	if (isspace(ch))
383	{
384	do *psz++ = ' ';
385	#ifdef DEBUG_bird /* Not sure if Sander want's this because of log size */
386	while (psz - szBuf < 8);
387	#else
388	while (0);
389	#endif
390	while (isspace(*pszFormat))
391	pszFormat++;
392	}
393
394	if (fFlags & DBGF_DISAS_FLAGS_NO_ANNOTATION)
395	pCtxCore = NULL;
396
397	/** @todo implement annotation and symbol lookup! */
398	int iParam = 1;
399	for (;;)
400	{
401	ch = *pszFormat;
402	if (ch == '%')
403	{
404	ch = pszFormat[1];
405	switch (ch)
406	{
407	/*
408	* Relative jump offset.
409	*/
410	case 'J':
411	{
412	AssertMsg(iParam == 1, ("Invalid branch parameter nr %d\n", iParam));
413	int32_t i32Disp;
414	if (State.Cpu.param1.flags & USE_IMMEDIATE8_REL)
415	i32Disp = (int32_t)(int8_t)State.Cpu.param1.parval;
416	else if (State.Cpu.param1.flags & USE_IMMEDIATE16_REL)
417	i32Disp = (int32_t)(int16_t)State.Cpu.param1.parval;
418	else if (State.Cpu.param1.flags & USE_IMMEDIATE32_REL)
419	i32Disp = (int32_t)State.Cpu.param1.parval;
420	else
421	{
422	AssertMsgFailed(("Oops!\n"));
423	dbgfR3DisasInstrDone(&State);
424	return VERR_GENERAL_FAILURE;
425	}
426	RTGCUINTPTR GCPtrTarget = (RTGCUINTPTR)GCPtr + State.Cpu.opsize + i32Disp;
427	switch (State.Cpu.opmode)
428	{
429	case CPUMODE_16BIT: GCPtrTarget &= UINT16_MAX; break;
430	case CPUMODE_32BIT: GCPtrTarget &= UINT32_MAX; break;
431	default: break;
432	}
433	#ifdef DEBUG_bird /* an experiment. */
434	DBGFSYMBOL Sym;
435	RTGCINTPTR off;
436	int rc = DBGFR3SymbolByAddr(pVM, GCPtrTarget + SelInfo.GCPtrBase, &off, &Sym);
437	if ( VBOX_SUCCESS(rc)
438	&& Sym.Value - SelInfo.GCPtrBase <= SelInfo.cbLimit
439	&& off < _1M * 16 && off > -_1M * 16)
440	{
441	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz, "%s", Sym.szName);
442	if (off > 0)
443	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz, "+%#x", (int)off);
444	else if (off > 0)
445	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz, "-%#x", -(int)off);
446	switch (State.Cpu.opmode)
447	{
448	case CPUMODE_16BIT:
449	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
450	i32Disp >= 0 ? " (%04VGv/+%x)" : " (%04VGv/-%x)",
451	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
452	break;
453	case CPUMODE_32BIT:
454	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
455	i32Disp >= 0 ? " (%08VGv/+%x)" : " (%08VGv/-%x)",
456	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
457	break;
458	default:
459	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
460	i32Disp >= 0 ? " (%VGv/+%x)" : " (%VGv/-%x)",
461	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
462	break;
463	}
464	}
465	else
466	#endif /* DEBUG_bird */
467	{
468	switch (State.Cpu.opmode)
469	{
470	case CPUMODE_16BIT:
471	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
472	i32Disp >= 0 ? "%04VGv (+%x)" : "%04VGv (-%x)",
473	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
474	break;
475	case CPUMODE_32BIT:
476	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
477	i32Disp >= 0 ? "%08VGv (+%x)" : "%08VGv (-%x)",
478	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
479	break;
480	default:
481	psz += RTStrPrintf(psz, &szBuf[sizeof(szBuf)] - psz,
482	i32Disp >= 0 ? "%VGv (+%x)" : "%VGv (-%x)",
483	GCPtrTarget, i32Disp >= 0 ? i32Disp : -i32Disp);
484	break;
485	}
486	}
487	break;
488	}
489
490	case 'A': //direct address
491	case 'C': //control register
492	case 'D': //debug register
493	case 'E': //ModRM specifies parameter
494	case 'F': //Eflags register
495	case 'G': //ModRM selects general register
496	case 'I': //Immediate data
497	case 'M': //ModRM may only refer to memory
498	case 'O': //No ModRM byte
499	case 'P': //ModRM byte selects MMX register
500	case 'Q': //ModRM byte selects MMX register or memory address
501	case 'R': //ModRM byte may only refer to a general register
502	case 'S': //ModRM byte selects a segment register
503	case 'T': //ModRM byte selects a test register
504	case 'V': //ModRM byte selects an XMM/SSE register
505	case 'W': //ModRM byte selects an XMM/SSE register or a memory address
506	case 'X': //DS:SI
507	case 'Y': //ES:DI
508	switch (iParam)
509	{
510	case 1: psz = mystrpcpy(psz, State.Cpu.param1.szParam); break;
511	case 2: psz = mystrpcpy(psz, State.Cpu.param2.szParam); break;
512	case 3: psz = mystrpcpy(psz, State.Cpu.param3.szParam); break;
513	}
514	pszFormat += 2;
515	break;
516
517	case 'e': //register based on operand size (e.g. %eAX)
518	if (State.Cpu.opmode == CPUMODE_32BIT)
519	*psz++ = 'E';
520	*psz++ = pszFormat[2];
521	*psz++ = pszFormat[3];
522	pszFormat += 4;
523	break;
524
525	default:
526	AssertMsgFailed(("Oops! ch=%c\n", ch));
527	break;
528	}
529
530	/* Skip to the next parameter in the format string. */
531	pszFormat = strchr(pszFormat, ',');
532	if (!pszFormat)
533	break;
534	pszFormat++;
535	*psz++ = ch = ',';
536	iParam++;
537	}
538	else
539	{
540	/* output char, but check for parameter separator first. */
541	if (ch == ',')
542	iParam++;
543	*psz++ = ch;
544	if (!ch)
545	break;
546	pszFormat++;
547	}
548
549	#ifdef DEBUG_bird /* Not sure if Sander want's this because of log size */
550	/* space after commas */
551	if (ch == ',')
552	{
553	while (isspace(*pszFormat))
554	pszFormat++;
555	*psz++ = ' ';
556	}
557	#endif
558	} /* foreach char in pszFormat */
559	*psz = '\0';
560
561	/*
562	* Print it to the user specified buffer.
563	*/
564	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
565	{
566	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
567	RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
568	else if (fRealModeAddress)
569	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
570	else if (Sel == DBGF_SEL_FLAT)
571	RTStrPrintf(pszOutput, cchOutput, "%VGv %s", GCPtr, szBuf);
572	else
573	RTStrPrintf(pszOutput, cchOutput, "%04x:%VGv %s", Sel, GCPtr, szBuf);
574	}
575	else
576	{
577	uint32_t cbBits = State.Cpu.opsize;
578	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
579	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
580	AssertRC(rc);
581	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
582	RTStrPrintf(pszOutput, cchOutput, "%.Vhxs%s %s",
583	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
584	szBuf);
585	else if (fRealModeAddress)
586	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.Vhxs%s %s",
587	Sel, (unsigned)GCPtr,
588	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
589	szBuf);
590	else if (Sel == DBGF_SEL_FLAT)
591	RTStrPrintf(pszOutput, cchOutput, "%VGv %.Vhxs%s %s",
592	GCPtr,
593	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
594	szBuf);
595	else
596	RTStrPrintf(pszOutput, cchOutput, "%04x:%VGv %.Vhxs%s %s",
597	Sel, GCPtr,
598	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
599	szBuf);
600
601	}
602
603	if (pcbInstr)
604	*pcbInstr = State.Cpu.opsize;
605
606	dbgfR3DisasInstrDone(&State);
607	return VINF_SUCCESS;
608	}
609
610
611	/**
612	* Disassembles an instruction.
613	* Addresses will be tried resolved to symbols
614	*
615	* @returns VBox status code.
616	* @param pVM VM handle.
617	* @param Sel The code selector. This used to determin the 32/16 bit ness and
618	* calculation of the actual instruction address.
619	* @param GCPtr The code address relative to the base of Sel.
620	* @param pszOutput Output buffer.
621	* @param cchOutput Size of the output buffer.
622	*/
623	DBGFR3DECL(int) DBGFR3DisasInstr(PVM pVM, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cchOutput)
624	{
625	return DBGFR3DisasInstrEx(pVM, Sel, GCPtr, 0, pszOutput, cchOutput, NULL);
626	}
627
628
629	/**
630	* Disassembles the current guest context instruction.
631	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
632	*
633	* @returns VBox status code.
634	* @param pVM VM handle.
635	* @param pszOutput Output buffer.
636	* @param cchOutput Size of the output buffer.
637	*/
638	DBGFR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cchOutput)
639	{
640	return DBGFR3DisasInstrEx(pVM, 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST, pszOutput, cchOutput, NULL);
641	}
642
643
644	/**
645	* Disassembles the current guest context instruction and writes it to the log.
646	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
647	*
648	* @returns VBox status code.
649	* @param pVM VM handle.
650	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
651	*/
652	DBGFR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix)
653	{
654	char szBuf[256];
655	szBuf[0] = '\0';
656	int rc = DBGFR3DisasInstrCurrent(pVM, &szBuf[0], sizeof(szBuf));
657	if (VBOX_FAILURE(rc))
658	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Vrc\n", rc);
659	if (pszPrefix && *pszPrefix)
660	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
661	else
662	RTLogPrintf("%s\n", szBuf);
663	return rc;
664	}
665
666
667
668	/**
669	* Disassembles the specified guest context instruction and writes it to the log.
670	* Addresses will be attempted resolved to symbols.
671	*
672	* @returns VBox status code.
673	* @param pVM VM handle.
674	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
675	* calculation of the actual instruction address.
676	* @param GCPtr The code address relative to the base of Sel.
677	*/
678	DBGFR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, RTSEL Sel, RTGCPTR GCPtr)
679	{
680	char szBuf[256];
681	szBuf[0] = '\0';
682	int rc = DBGFR3DisasInstr(pVM, Sel, GCPtr, &szBuf[0], sizeof(szBuf));
683	if (VBOX_FAILURE(rc))
684	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Vrc\n", Sel, GCPtr, rc);
685	RTLogPrintf("%s\n", szBuf);
686	return rc;
687	}
688

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 9154

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