DBGFDisas.cpp@ 30453

Last change on this file since 30453 was 30453, checked in by vboxsync, 14 years ago
DBGFR3DisasInstrEx: Flags for overriding the instruction set, adding u64, u32, u16 and uv86 to the debugger.
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1	/* $Id: DBGFDisas.cpp 30453 2010-06-27 19:43:20Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/dbgf.h>
23	#include <VBox/selm.h>
24	#include <VBox/mm.h>
25	#include <VBox/pgm.h>
26	#include <VBox/cpum.h>
27	#include "DBGFInternal.h"
28	#include <VBox/dis.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <VBox/vm.h>
32
33	#include <VBox/log.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#include <iprt/alloca.h>
37	#include <iprt/ctype.h>
38
39
40	/*******************************************************************************
41	* Structures and Typedefs *
42	*******************************************************************************/
43	/**
44	* Structure used when disassembling and instructions in DBGF.
45	* This is used so the reader function can get the stuff it needs.
46	*/
47	typedef struct
48	{
49	/** The core structure. */
50	DISCPUSTATE Cpu;
51	/** The VM handle. */
52	PVM pVM;
53	/** The VMCPU handle. */
54	PVMCPU pVCpu;
55	/** The address space for resolving symbol. */
56	RTDBGAS hAs;
57	/** Pointer to the first byte in the segemnt. */
58	RTGCUINTPTR GCPtrSegBase;
59	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
60	RTGCUINTPTR GCPtrSegEnd;
61	/** The size of the segment minus 1. */
62	RTGCUINTPTR cbSegLimit;
63	/** The guest paging mode. */
64	PGMMODE enmMode;
65	/** Pointer to the current page - R3 Ptr. */
66	void const *pvPageR3;
67	/** Pointer to the current page - GC Ptr. */
68	RTGCPTR pvPageGC;
69	/** Pointer to the next instruction (relative to GCPtrSegBase). */
70	RTGCUINTPTR GCPtrNext;
71	/** The lock information that PGMPhysReleasePageMappingLock needs. */
72	PGMPAGEMAPLOCK PageMapLock;
73	/** Whether the PageMapLock is valid or not. */
74	bool fLocked;
75	/** 64 bits mode or not. */
76	bool f64Bits;
77	} DBGFDISASSTATE, *PDBGFDISASSTATE;
78
79
80	/*******************************************************************************
81	* Internal Functions *
82	*******************************************************************************/
83	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
84
85
86
87	/**
88	* Calls the dissassembler with the proper reader functions and such for disa
89	*
90	* @returns VBox status code.
91	* @param pVM VM handle
92	* @param pVCpu VMCPU handle
93	* @param pSelInfo The selector info.
94	* @param enmMode The guest paging mode.
95	* @param fFlags DBGF_DISAS_FLAGS_XXX.
96	* @param GCPtr The GC pointer (selector offset).
97	* @param pState The disas CPU state.
98	*/
99	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
100	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
101	{
102	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
103	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
104	pState->cbSegLimit = pSelInfo->cbLimit;
105	pState->enmMode = enmMode;
106	pState->pvPageGC = 0;
107	pState->pvPageR3 = NULL;
108	pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas. /
109	? DBGF_AS_RC_AND_GC_GLOBAL
110	: DBGF_AS_GLOBAL;
111	pState->pVM = pVM;
112	pState->pVCpu = pVCpu;
113	pState->fLocked = false;
114	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
115
116	DISCPUMODE enmCpuMode;
117	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
118	{
119	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
120	enmCpuMode = pState->f64Bits
121	? CPUMODE_64BIT
122	: pSelInfo->u.Raw.Gen.u1DefBig
123	? CPUMODE_32BIT
124	: CPUMODE_16BIT;
125	break;
126	case DBGF_DISAS_FLAGS_16BIT_MODE:
127	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
128	enmCpuMode = CPUMODE_16BIT;
129	break;
130	case DBGF_DISAS_FLAGS_32BIT_MODE:
131	enmCpuMode = CPUMODE_32BIT;
132	break;
133	case DBGF_DISAS_FLAGS_64BIT_MODE:
134	enmCpuMode = CPUMODE_64BIT;
135	break;
136	}
137
138	uint32_t cbInstr;
139	int rc = DISCoreOneEx(GCPtr,
140	enmCpuMode,
141	dbgfR3DisasInstrRead,
142	&pState->Cpu,
143	&pState->Cpu,
144	&cbInstr);
145	if (RT_SUCCESS(rc))
146	{
147	pState->GCPtrNext = GCPtr + cbInstr;
148	return VINF_SUCCESS;
149	}
150
151	/* cleanup */
152	if (pState->fLocked)
153	{
154	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
155	pState->fLocked = false;
156	}
157	return rc;
158	}
159
160
161	#if 0
162	/**
163	* Calls the dissassembler for disassembling the next instruction.
164	*
165	* @returns VBox status code.
166	* @param pState The disas CPU state.
167	*/
168	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
169	{
170	uint32_t cbInstr;
171	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
172	if (RT_SUCCESS(rc))
173	{
174	pState->GCPtrNext = GCPtr + cbInstr;
175	return VINF_SUCCESS;
176	}
177	return rc;
178	}
179	#endif
180
181
182	/**
183	* Done with the dissassembler state, free associated resources.
184	*
185	* @param pState The disas CPU state ++.
186	*/
187	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
188	{
189	if (pState->fLocked)
190	{
191	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
192	pState->fLocked = false;
193	}
194	}
195
196
197	/**
198	* Instruction reader.
199	*
200	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
201	* @param PtrSrc Address to read from.
202	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
203	* @param pu8Dst Where to store the bytes.
204	* @param cbRead Number of bytes to read.
205	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
206	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
207	*/
208	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
209	{
210	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
211	Assert(cbRead > 0);
212	for (;;)
213	{
214	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
215
216	/* Need to update the page translation? */
217	if ( !pState->pvPageR3
218	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
219	{
220	int rc = VINF_SUCCESS;
221
222	/* translate the address */
223	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
224	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
225	{
226	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
227	if (!pState->pvPageR3)
228	rc = VERR_INVALID_POINTER;
229	}
230	else
231	{
232	if (pState->fLocked)
233	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
234
235	if (pState->enmMode <= PGMMODE_PROTECTED)
236	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
237	else
238	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
239	pState->fLocked = RT_SUCCESS_NP(rc);
240	}
241	if (RT_FAILURE(rc))
242	{
243	pState->pvPageR3 = NULL;
244	return rc;
245	}
246	}
247
248	/* check the segemnt limit */
249	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
250	return VERR_OUT_OF_SELECTOR_BOUNDS;
251
252	/* calc how much we can read */
253	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
254	if (!pState->f64Bits)
255	{
256	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
257	if (cb > cbSeg && cbSeg)
258	cb = cbSeg;
259	}
260	if (cb > cbRead)
261	cb = cbRead;
262
263	/* read and advance */
264	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
265	cbRead -= cb;
266	if (!cbRead)
267	return VINF_SUCCESS;
268	pu8Dst += cb;
269	PtrSrc += cb;
270	}
271	}
272
273
274	/**
275	* @copydoc FNDISGETSYMBOL
276	*/
277	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
278	{
279	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
280	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
281	DBGFADDRESS Addr;
282	RTDBGSYMBOL Sym;
283	RTGCINTPTR off;
284	int rc;
285
286	if ( DIS_FMT_SEL_IS_REG(u32Sel)
287	? DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS
288	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
289	{
290	rc = DBGFR3AddrFromSelInfoOff(pState->pVM, &Addr, pSelInfo, uAddress);
291	if (RT_SUCCESS(rc))
292	rc = DBGFR3AsSymbolByAddr(pState->pVM, pState->hAs, &Addr, &off, &Sym, NULL /phMod/);
293	}
294	else
295	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
296	if (RT_SUCCESS(rc))
297	{
298	size_t cchName = strlen(Sym.szName);
299	if (cchName >= cchBuf)
300	cchName = cchBuf - 1;
301	memcpy(pszBuf, Sym.szName, cchName);
302	pszBuf[cchName] = '\0';
303
304	*poff = off;
305	}
306
307	return rc;
308	}
309
310
311	/**
312	* Disassembles the one instruction according to the specified flags and
313	* address, internal worker executing on the EMT of the specified virtual CPU.
314	*
315	* @returns VBox status code.
316	* @param pVM The VM handle.
317	* @param pVCpu The virtual CPU handle.
318	* @param Sel The code selector. This used to determin the 32/16 bit ness and
319	* calculation of the actual instruction address.
320	* @param pGCPtr Pointer to the variable holding the code address
321	* relative to the base of Sel.
322	* @param fFlags Flags controlling where to start and how to format.
323	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
324	* @param pszOutput Output buffer.
325	* @param cbOutput Size of the output buffer.
326	* @param pcbInstr Where to return the size of the instruction.
327	*/
328	static DECLCALLBACK(int)
329	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
330	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
331	{
332	VMCPU_ASSERT_EMT(pVCpu);
333	RTGCPTR GCPtr = *pGCPtr;
334
335	/*
336	* Get the Sel and GCPtr if fFlags requests that.
337	*/
338	PCCPUMCTXCORE pCtxCore = NULL;
339	PCPUMSELREGHID pHiddenSel = NULL;
340	int rc;
341	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
342	{
343	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
344	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
345	else
346	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
347	Sel = pCtxCore->cs;
348	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
349	GCPtr = pCtxCore->rip;
350	}
351
352	/*
353	* Read the selector info - assume no stale selectors and nasty stuff like that.
354	* Since the selector flags in the CPUMCTX structures aren't up to date unless
355	* we recently visited REM, we'll not search for the selector there.
356	*/
357	DBGFSELINFO SelInfo;
358	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
359	bool fRealModeAddress = false;
360
361	if ( pHiddenSel
362	&& CPUMAreHiddenSelRegsValid(pVCpu))
363	{
364	SelInfo.Sel = Sel;
365	SelInfo.SelGate = 0;
366	SelInfo.GCPtrBase = pHiddenSel->u64Base;
367	SelInfo.cbLimit = pHiddenSel->u32Limit;
368	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
369	? DBGFSELINFO_FLAGS_LONG_MODE
370	: enmMode != PGMMODE_REAL && (!pCtxCore \|\| !pCtxCore->eflags.Bits.u1VM)
371	? DBGFSELINFO_FLAGS_PROT_MODE
372	: DBGFSELINFO_FLAGS_REAL_MODE;
373
374	SelInfo.u.Raw.au32[0] = 0;
375	SelInfo.u.Raw.au32[1] = 0;
376	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
377	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
378	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
379	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
380	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
381	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
382	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
383	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
384	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
385	}
386	else if (Sel == DBGF_SEL_FLAT)
387	{
388	SelInfo.Sel = Sel;
389	SelInfo.SelGate = 0;
390	SelInfo.GCPtrBase = 0;
391	SelInfo.cbLimit = ~0;
392	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
393	? DBGFSELINFO_FLAGS_LONG_MODE
394	: enmMode != PGMMODE_REAL
395	? DBGFSELINFO_FLAGS_PROT_MODE
396	: DBGFSELINFO_FLAGS_REAL_MODE;
397	SelInfo.u.Raw.au32[0] = 0;
398	SelInfo.u.Raw.au32[1] = 0;
399	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
400	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
401
402	if (CPUMAreHiddenSelRegsValid(pVCpu))
403	{ /* Assume the current CS defines the execution mode. */
404	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
405	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
406
407	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
408	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
409	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
410	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
411	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
412	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
413	}
414	else
415	{
416	SelInfo.u.Raw.Gen.u1Present = 1;
417	SelInfo.u.Raw.Gen.u1Granularity = 1;
418	SelInfo.u.Raw.Gen.u1DefBig = 1;
419	SelInfo.u.Raw.Gen.u1DescType = 1;
420	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
421	}
422	}
423	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
424	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
425	\|\| enmMode == PGMMODE_REAL
426	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
427	)
428	)
429	{ /* V86 mode or real mode - real mode addressing */
430	SelInfo.Sel = Sel;
431	SelInfo.SelGate = 0;
432	SelInfo.GCPtrBase = Sel * 16;
433	SelInfo.cbLimit = ~0;
434	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
435	SelInfo.u.Raw.au32[0] = 0;
436	SelInfo.u.Raw.au32[1] = 0;
437	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
438	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
439	SelInfo.u.Raw.Gen.u1Present = 1;
440	SelInfo.u.Raw.Gen.u1Granularity = 1;
441	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
442	SelInfo.u.Raw.Gen.u1DescType = 1;
443	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
444	fRealModeAddress = true;
445	}
446	else
447	{
448	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
449	if (RT_FAILURE(rc))
450	{
451	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
452	return rc;
453	}
454	}
455
456	/*
457	* Disassemble it.
458	*/
459	DBGFDISASSTATE State;
460	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
461	if (RT_FAILURE(rc))
462	{
463	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
464	return rc;
465	}
466
467	/*
468	* Format it.
469	*/
470	char szBuf[512];
471	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
472	DIS_FMT_FLAGS_RELATIVE_BRANCH,
473	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
474	&SelInfo);
475
476	/*
477	* Print it to the user specified buffer.
478	*/
479	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
480	{
481	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
482	RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
483	else if (fRealModeAddress)
484	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
485	else if (Sel == DBGF_SEL_FLAT)
486	{
487	if (enmMode >= PGMMODE_AMD64)
488	RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
489	else
490	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
491	}
492	else
493	{
494	if (enmMode >= PGMMODE_AMD64)
495	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
496	else
497	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
498	}
499	}
500	else
501	{
502	uint32_t cbBits = State.Cpu.opsize;
503	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
504	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
505	AssertRC(rc);
506	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
507	RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
508	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
509	szBuf);
510	else if (fRealModeAddress)
511	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
512	Sel, (unsigned)GCPtr,
513	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
514	szBuf);
515	else if (Sel == DBGF_SEL_FLAT)
516	{
517	if (enmMode >= PGMMODE_AMD64)
518	RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
519	GCPtr,
520	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
521	szBuf);
522	else
523	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
524	(uint32_t)GCPtr,
525	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
526	szBuf);
527	}
528	else
529	{
530	if (enmMode >= PGMMODE_AMD64)
531	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
532	Sel, GCPtr,
533	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
534	szBuf);
535	else
536	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
537	Sel, (uint32_t)GCPtr,
538	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
539	szBuf);
540	}
541	}
542
543	if (pcbInstr)
544	*pcbInstr = State.Cpu.opsize;
545
546	dbgfR3DisasInstrDone(&State);
547	return VINF_SUCCESS;
548	}
549
550
551	/**
552	* Disassembles the one instruction according to the specified flags and address.
553	*
554	* @returns VBox status code.
555	* @param pVM VM handle.
556	* @param idCpu The ID of virtual CPU.
557	* @param Sel The code selector. This used to determin the 32/16 bit ness and
558	* calculation of the actual instruction address.
559	* @param GCPtr The code address relative to the base of Sel.
560	* @param fFlags Flags controlling where to start and how to format.
561	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
562	* @param pszOutput Output buffer. This will always be properly
563	* terminated if @a cbOutput is greater than zero.
564	* @param cbOutput Size of the output buffer.
565	* @param pcbInstr Where to return the size of the instruction.
566	*
567	* @remarks May have to switch to the EMT of the virtual CPU in order to do
568	* address conversion.
569	*/
570	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
571	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
572	{
573	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
574	*pszOutput = '\0';
575	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
576	AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID);
577	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
578	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
579
580	/*
581	* Optimize the common case where we're called on the EMT of idCpu since
582	* we're using this all the time when logging.
583	*/
584	int rc;
585	PVMCPU pVCpu = VMMGetCpu(pVM);
586	if ( pVCpu
587	&& pVCpu->idCpu == idCpu)
588	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
589	else
590	rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
591	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
592	return rc;
593	}
594
595
596	/**
597	* Disassembles the current guest context instruction.
598	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
599	*
600	* @returns VBox status code.
601	* @param pVCpu VMCPU handle.
602	* @param pszOutput Output buffer. This will always be properly
603	* terminated if @a cbOutput is greater than zero.
604	* @param cbOutput Size of the output buffer.
605	*/
606	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
607	{
608	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
609	*pszOutput = '\0';
610	AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
611	return DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, 0, 0,
612	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
613	pszOutput, cbOutput, NULL);
614	}
615
616
617	/**
618	* Disassembles the current guest context instruction and writes it to the log.
619	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
620	*
621	* @returns VBox status code.
622	* @param pVCpu VMCPU handle.
623	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
624	*/
625	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
626	{
627	char szBuf[256];
628	szBuf[0] = '\0';
629	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
630	if (RT_FAILURE(rc))
631	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
632	if (pszPrefix && *pszPrefix)
633	RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
634	else
635	RTLogPrintf("%s\n", szBuf);
636	return rc;
637	}
638
639
640
641	/**
642	* Disassembles the specified guest context instruction and writes it to the log.
643	* Addresses will be attempted resolved to symbols.
644	*
645	* @returns VBox status code.
646	* @param pVM VM handle.
647	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
648	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
649	* calculation of the actual instruction address.
650	* @param GCPtr The code address relative to the base of Sel.
651	*/
652	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
653	{
654	char szBuf[256];
655	int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, Sel, GCPtr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
656	&szBuf[0], sizeof(szBuf), NULL);
657	if (RT_FAILURE(rc))
658	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
659	RTLogPrintf("%s\n", szBuf);
660	return rc;
661	}
662

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 30453

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