DBGFDisas.cpp@ 19279

Last change on this file since 19279 was 19181, checked in by vboxsync, 16 years ago
DBGFDisas: switch to the EMT of the VCpu in DBGFR3DisasInstrEx if we're not on it.
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1	/* $Id: DBGFDisas.cpp 19181 2009-04-24 18:36:01Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DBGF
26	#include <VBox/dbgf.h>
27	#include <VBox/selm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pgm.h>
30	#include <VBox/cpum.h>
31	#include "DBGFInternal.h"
32	#include <VBox/dis.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35	#include <VBox/vm.h>
36
37	#include <VBox/log.h>
38	#include <iprt/assert.h>
39	#include <iprt/string.h>
40	#include <iprt/alloca.h>
41	#include <iprt/ctype.h>
42
43
44	/*******************************************************************************
45	* Structures and Typedefs *
46	*******************************************************************************/
47	/**
48	* Structure used when disassembling and instructions in DBGF.
49	* This is used so the reader function can get the stuff it needs.
50	*/
51	typedef struct
52	{
53	/** The core structure. */
54	DISCPUSTATE Cpu;
55	/** The VM handle. */
56	PVM pVM;
57	/** The VMCPU handle. */
58	PVMCPU pVCpu;
59	/** Pointer to the first byte in the segemnt. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - R3 Ptr. */
68	void const *pvPageR3;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR pvPageGC;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
86
87
88
89	/**
90	* Calls the dissassembler with the proper reader functions and such for disa
91	*
92	* @returns VBox status code.
93	* @param pVM VM handle
94	* @param pVCpu VMCPU handle
95	* @param pSelInfo The selector info.
96	* @param enmMode The guest paging mode.
97	* @param GCPtr The GC pointer (selector offset).
98	* @param pState The disas CPU state.
99	*/
100	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PSELMSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
101	{
102	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
103	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
104	pState->cbSegLimit = pSelInfo->cbLimit;
105	pState->enmMode = enmMode;
106	pState->pvPageGC = 0;
107	pState->pvPageR3 = NULL;
108	pState->pVM = pVM;
109	pState->pVCpu = pVCpu;
110	pState->fLocked = false;
111	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->Raw.Gen.u1Long;
112	uint32_t cbInstr;
113	int rc = DISCoreOneEx(GCPtr,
114	pState->f64Bits
115	? CPUMODE_64BIT
116	: pSelInfo->Raw.Gen.u1DefBig
117	? CPUMODE_32BIT
118	: CPUMODE_16BIT,
119	dbgfR3DisasInstrRead,
120	&pState->Cpu,
121	&pState->Cpu,
122	&cbInstr);
123	if (RT_SUCCESS(rc))
124	{
125	pState->GCPtrNext = GCPtr + cbInstr;
126	return VINF_SUCCESS;
127	}
128
129	/* cleanup */
130	if (pState->fLocked)
131	{
132	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
133	pState->fLocked = false;
134	}
135	return rc;
136	}
137
138
139	#if 0
140	/**
141	* Calls the dissassembler for disassembling the next instruction.
142	*
143	* @returns VBox status code.
144	* @param pState The disas CPU state.
145	*/
146	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
147	{
148	uint32_t cbInstr;
149	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
150	if (RT_SUCCESS(rc))
151	{
152	pState->GCPtrNext = GCPtr + cbInstr;
153	return VINF_SUCCESS;
154	}
155	return rc;
156	}
157	#endif
158
159
160	/**
161	* Done with the dissassembler state, free associated resources.
162	*
163	* @param pState The disas CPU state ++.
164	*/
165	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
166	{
167	if (pState->fLocked)
168	{
169	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
170	pState->fLocked = false;
171	}
172	}
173
174
175	/**
176	* Instruction reader.
177	*
178	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
179	* @param PtrSrc Address to read from.
180	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
181	* @param pu8Dst Where to store the bytes.
182	* @param cbRead Number of bytes to read.
183	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
184	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
185	*/
186	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
187	{
188	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
189	Assert(cbRead > 0);
190	for (;;)
191	{
192	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
193
194	/* Need to update the page translation? */
195	if ( !pState->pvPageR3
196	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
197	{
198	int rc = VINF_SUCCESS;
199
200	/* translate the address */
201	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
202	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
203	{
204	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
205	if (!pState->pvPageR3)
206	rc = VERR_INVALID_POINTER;
207	}
208	else
209	{
210	if (pState->fLocked)
211	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
212
213	if (pState->enmMode <= PGMMODE_PROTECTED)
214	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
215	else
216	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
217	pState->fLocked = RT_SUCCESS_NP(rc);
218	}
219	if (RT_FAILURE(rc))
220	{
221	pState->pvPageR3 = NULL;
222	return rc;
223	}
224	}
225
226	/* check the segemnt limit */
227	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
228	return VERR_OUT_OF_SELECTOR_BOUNDS;
229
230	/* calc how much we can read */
231	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
232	if (!pState->f64Bits)
233	{
234	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
235	if (cb > cbSeg && cbSeg)
236	cb = cbSeg;
237	}
238	if (cb > cbRead)
239	cb = cbRead;
240
241	/* read and advance */
242	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
243	cbRead -= cb;
244	if (!cbRead)
245	return VINF_SUCCESS;
246	pu8Dst += cb;
247	PtrSrc += cb;
248	}
249	}
250
251
252	/**
253	* @copydoc FNDISGETSYMBOL
254	*/
255	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
256	{
257	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
258	PCSELMSELINFO pSelInfo = (PCSELMSELINFO)pvUser;
259	DBGFSYMBOL Sym;
260	RTGCINTPTR off;
261	int rc;
262
263	if (DIS_FMT_SEL_IS_REG(u32Sel))
264	{
265	if (DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS)
266	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
267	else
268	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
269	}
270	else
271	{
272	if (pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
273	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
274	else
275	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
276	}
277
278	if (RT_SUCCESS(rc))
279	{
280	size_t cchName = strlen(Sym.szName);
281	if (cchName >= cchBuf)
282	cchName = cchBuf - 1;
283	memcpy(pszBuf, Sym.szName, cchName);
284	pszBuf[cchName] = '\0';
285
286	*poff = off;
287	}
288
289	return rc;
290	}
291
292
293	/**
294	* Disassembles the one instruction according to the specified flags and
295	* address, internal worker executing on the EMT of the specified virtual CPU.
296	*
297	* @returns VBox status code.
298	* @param pVM The VM handle.
299	* @param pVCpu The virtual CPU handle.
300	* @param Sel The code selector. This used to determin the 32/16 bit ness and
301	* calculation of the actual instruction address.
302	* @param pGCPtr Pointer to the variable holding the code address
303	* relative to the base of Sel.
304	* @param fFlags Flags controlling where to start and how to format.
305	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
306	* @param pszOutput Output buffer.
307	* @param cchOutput Size of the output buffer.
308	* @param pcbInstr Where to return the size of the instruction.
309	*/
310	static DECLCALLBACK(int)
311	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, unsigned fFlags,
312	char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
313	{
314	RTGCPTR GCPtr = *pGCPtr;
315
316	/*
317	* Get the Sel and GCPtr if fFlags requests that.
318	*/
319	PCCPUMCTXCORE pCtxCore = NULL;
320	CPUMSELREGHID *pHiddenSel = NULL;
321	int rc;
322	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
323	{
324	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
325	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
326	else
327	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
328	Sel = pCtxCore->cs;
329	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
330	GCPtr = pCtxCore->rip;
331	}
332
333	/*
334	* Read the selector info - assume no stale selectors and nasty stuff like that.
335	* Since the selector flags in the CPUMCTX structures aren't up to date unless
336	* we recently visited REM, we'll not search for the selector there.
337	*/
338	SELMSELINFO SelInfo;
339	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
340	bool fRealModeAddress = false;
341
342	if ( pHiddenSel
343	&& CPUMAreHiddenSelRegsValid(pVM))
344	{
345	SelInfo.GCPtrBase = pHiddenSel->u64Base;
346	SelInfo.cbLimit = pHiddenSel->u32Limit;
347	SelInfo.fHyper = false;
348	SelInfo.fRealMode = !!((pCtxCore && pCtxCore->eflags.Bits.u1VM) \|\| enmMode == PGMMODE_REAL);
349	SelInfo.Raw.au32[0] = 0;
350	SelInfo.Raw.au32[1] = 0;
351	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
352	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
353	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
354	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
355	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
356	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
357	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
358	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
359	fRealModeAddress = SelInfo.fRealMode;
360	}
361	else if (Sel == DBGF_SEL_FLAT)
362	{
363	SelInfo.GCPtrBase = 0;
364	SelInfo.cbLimit = ~0;
365	SelInfo.fHyper = false;
366	SelInfo.fRealMode = false;
367	SelInfo.Raw.au32[0] = 0;
368	SelInfo.Raw.au32[1] = 0;
369	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
370	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
371
372	if (CPUMAreHiddenSelRegsValid(pVM))
373	{ /* Assume the current CS defines the execution mode. */
374	pCtxCore = CPUMGetGuestCtxCore(VMMGetCpu(pVM)); /* @todo SMP support!! */
375	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
376
377	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
378	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
379	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
380	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
381	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
382	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
383	}
384	else
385	{
386	SelInfo.Raw.Gen.u1Present = 1;
387	SelInfo.Raw.Gen.u1Granularity = 1;
388	SelInfo.Raw.Gen.u1DefBig = 1;
389	SelInfo.Raw.Gen.u1DescType = 1;
390	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
391	}
392	}
393	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
394	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
395	\|\| enmMode == PGMMODE_REAL) )
396	{ /* V86 mode or real mode - real mode addressing */
397	SelInfo.GCPtrBase = Sel * 16;
398	SelInfo.cbLimit = ~0;
399	SelInfo.fHyper = false;
400	SelInfo.fRealMode = true;
401	SelInfo.Raw.au32[0] = 0;
402	SelInfo.Raw.au32[1] = 0;
403	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
404	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
405	SelInfo.Raw.Gen.u1Present = 1;
406	SelInfo.Raw.Gen.u1Granularity = 1;
407	SelInfo.Raw.Gen.u1DefBig = 0; /* 16 bits */
408	SelInfo.Raw.Gen.u1DescType = 1;
409	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
410	fRealModeAddress = true;
411	}
412	else
413	{
414	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
415	if (RT_FAILURE(rc))
416	{
417	RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
418	return rc;
419	}
420	}
421
422	/*
423	* Disassemble it.
424	*/
425	DBGFDISASSTATE State;
426	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, &State);
427	if (RT_FAILURE(rc))
428	{
429	RTStrPrintf(pszOutput, cchOutput, "Disas -> %Rrc\n", rc);
430	return rc;
431	}
432
433	/*
434	* Format it.
435	*/
436	char szBuf[512];
437	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
438	DIS_FMT_FLAGS_RELATIVE_BRANCH,
439	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
440	&SelInfo);
441
442	/*
443	* Print it to the user specified buffer.
444	*/
445	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
446	{
447	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
448	RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
449	else if (fRealModeAddress)
450	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
451	else if (Sel == DBGF_SEL_FLAT)
452	{
453	if (enmMode >= PGMMODE_AMD64)
454	RTStrPrintf(pszOutput, cchOutput, "%RGv %s", GCPtr, szBuf);
455	else
456	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
457	}
458	else
459	{
460	if (enmMode >= PGMMODE_AMD64)
461	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
462	else
463	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
464	}
465	}
466	else
467	{
468	uint32_t cbBits = State.Cpu.opsize;
469	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
470	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
471	AssertRC(rc);
472	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
473	RTStrPrintf(pszOutput, cchOutput, "%.Rhxs%s %s",
474	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
475	szBuf);
476	else if (fRealModeAddress)
477	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.Rhxs%s %s",
478	Sel, (unsigned)GCPtr,
479	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
480	szBuf);
481	else if (Sel == DBGF_SEL_FLAT)
482	{
483	if (enmMode >= PGMMODE_AMD64)
484	RTStrPrintf(pszOutput, cchOutput, "%RGv %.Rhxs%s %s",
485	GCPtr,
486	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
487	szBuf);
488	else
489	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %.Rhxs%s %s",
490	(uint32_t)GCPtr,
491	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
492	szBuf);
493	}
494	else
495	{
496	if (enmMode >= PGMMODE_AMD64)
497	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %.Rhxs%s %s",
498	Sel, GCPtr,
499	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
500	szBuf);
501	else
502	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %.Rhxs%s %s",
503	Sel, (uint32_t)GCPtr,
504	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
505	szBuf);
506	}
507	}
508
509	if (pcbInstr)
510	*pcbInstr = State.Cpu.opsize;
511
512	dbgfR3DisasInstrDone(&State);
513	return VINF_SUCCESS;
514	}
515
516
517	/**
518	* Disassembles the one instruction according to the specified flags and address.
519	*
520	* @returns VBox status code.
521	* @param pVM VM handle.
522	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
523	* @param Sel The code selector. This used to determin the 32/16 bit ness and
524	* calculation of the actual instruction address.
525	* @param GCPtr The code address relative to the base of Sel.
526	* @param fFlags Flags controlling where to start and how to format.
527	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
528	* @param pszOutput Output buffer.
529	* @param cchOutput Size of the output buffer.
530	* @param pcbInstr Where to return the size of the instruction.
531	*
532	* @remarks May have to switch to the EMT of the virtual CPU in order to do
533	* address conversion.
534	*/
535	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags,
536	char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
537	{
538	/* If not specified, assume CPU 0. */
539	if (!pVCpu)
540	pVCpu = &pVM->aCpus[0];
541
542	int rc;
543	if (VMCPU_IS_EMT(pVCpu)) /* not necessary, but it's faster. */
544	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
545	else
546	{
547	PVMREQ pReq = NULL;
548	rc = VMR3ReqCall(pVCpu->pVMR3, VMREQDEST_FROM_VMCPU(pVCpu), &pReq, RT_INDEFINITE_WAIT,
549	(PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
550	pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cchOutput, pcbInstr);
551	if (RT_SUCCESS(rc))
552	{
553	rc = pReq->iStatus;
554	VMR3ReqFree(pReq);
555	}
556	}
557	return rc;
558	}
559
560
561	/**
562	* Disassembles an instruction.
563	* Addresses will be tried resolved to symbols
564	*
565	* @returns VBox status code.
566	* @param pVM VM handle.
567	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
568	* @param Sel The code selector. This used to determin the 32/16 bit ness and
569	* calculation of the actual instruction address.
570	* @param GCPtr The code address relative to the base of Sel.
571	* @param pszOutput Output buffer.
572	* @param cchOutput Size of the output buffer.
573	*/
574	VMMR3DECL(int) DBGFR3DisasInstr(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cchOutput)
575	{
576	return DBGFR3DisasInstrEx(pVM, pVCpu, Sel, GCPtr, 0, pszOutput, cchOutput, NULL);
577	}
578
579
580	/**
581	* Disassembles the current guest context instruction.
582	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
583	*
584	* @returns VBox status code.
585	* @param pVM VM handle.
586	* @param pszOutput Output buffer.
587	* @param cchOutput Size of the output buffer.
588	*/
589	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cchOutput)
590	{
591	return DBGFR3DisasInstrEx(pVM, VMMGetCpu(pVM), 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST, pszOutput, cchOutput, NULL);
592	}
593
594
595	/**
596	* Disassembles the current guest context instruction and writes it to the log.
597	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
598	*
599	* @returns VBox status code.
600	* @param pVM VM handle.
601	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
602	*/
603	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix)
604	{
605	char szBuf[256];
606	szBuf[0] = '\0';
607	int rc = DBGFR3DisasInstrCurrent(pVM, &szBuf[0], sizeof(szBuf));
608	if (RT_FAILURE(rc))
609	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
610	if (pszPrefix && *pszPrefix)
611	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
612	else
613	RTLogPrintf("%s\n", szBuf);
614	return rc;
615	}
616
617
618
619	/**
620	* Disassembles the specified guest context instruction and writes it to the log.
621	* Addresses will be attempted resolved to symbols.
622	*
623	* @returns VBox status code.
624	* @param pVM VM handle.
625	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
626	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
627	* calculation of the actual instruction address.
628	* @param GCPtr The code address relative to the base of Sel.
629	*/
630	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
631	{
632	char szBuf[256];
633	szBuf[0] = '\0';
634	int rc = DBGFR3DisasInstr(pVM, pVCpu, Sel, GCPtr, &szBuf[0], sizeof(szBuf));
635	if (RT_FAILURE(rc))
636	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
637	RTLogPrintf("%s\n", szBuf);
638	return rc;
639	}
640

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 19279

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