DBGFDisas.cpp@ 18927

Last change on this file since 18927 was 18927, checked in by vboxsync, 16 years ago
Big step to separate VMM data structures for guest SMP. (pgm, em)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 21.3 KB

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1	/* $Id: DBGFDisas.cpp 18927 2009-04-16 11:41:38Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/*******************************************************************************
23	* Header Files *
24	*******************************************************************************/
25	#define LOG_GROUP LOG_GROUP_DBGF
26	#include <VBox/dbgf.h>
27	#include <VBox/selm.h>
28	#include <VBox/mm.h>
29	#include <VBox/pgm.h>
30	#include <VBox/cpum.h>
31	#include "DBGFInternal.h"
32	#include <VBox/dis.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35	#include <VBox/vm.h>
36
37	#include <VBox/log.h>
38	#include <iprt/assert.h>
39	#include <iprt/string.h>
40	#include <iprt/alloca.h>
41	#include <iprt/ctype.h>
42
43
44	/*******************************************************************************
45	* Structures and Typedefs *
46	*******************************************************************************/
47	/**
48	* Structure used when disassembling and instructions in DBGF.
49	* This is used so the reader function can get the stuff it needs.
50	*/
51	typedef struct
52	{
53	/** The core structure. */
54	DISCPUSTATE Cpu;
55	/** The VM handle. */
56	PVM pVM;
57	/** The VMCPU handle. */
58	PVMCPU pVCpu;
59	/** Pointer to the first byte in the segemnt. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - R3 Ptr. */
68	void const *pvPageR3;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR pvPageGC;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR pSrc, uint8_t pDest, uint32_t size, void pvUserdata);
86
87
88
89	/**
90	* Calls the dissassembler with the proper reader functions and such for disa
91	*
92	* @returns VBox status code.
93	* @param pVM VM handle
94	* @param pVCpu VMCPU handle
95	* @param pSelInfo The selector info.
96	* @param enmMode The guest paging mode.
97	* @param GCPtr The GC pointer (selector offset).
98	* @param pState The disas CPU state.
99	*/
100	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PSELMSELINFO pSelInfo, PGMMODE enmMode, RTGCPTR GCPtr, PDBGFDISASSTATE pState)
101	{
102	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
103	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
104	pState->cbSegLimit = pSelInfo->cbLimit;
105	pState->enmMode = enmMode;
106	pState->pvPageGC = 0;
107	pState->pvPageR3 = NULL;
108	pState->pVM = pVM;
109	pState->pVCpu = pVCpu;
110	pState->fLocked = false;
111	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->Raw.Gen.u1Long;
112	uint32_t cbInstr;
113	int rc = DISCoreOneEx(GCPtr,
114	pState->f64Bits
115	? CPUMODE_64BIT
116	: pSelInfo->Raw.Gen.u1DefBig
117	? CPUMODE_32BIT
118	: CPUMODE_16BIT,
119	dbgfR3DisasInstrRead,
120	&pState->Cpu,
121	&pState->Cpu,
122	&cbInstr);
123	if (RT_SUCCESS(rc))
124	{
125	pState->GCPtrNext = GCPtr + cbInstr;
126	return VINF_SUCCESS;
127	}
128
129	/* cleanup */
130	if (pState->fLocked)
131	{
132	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
133	pState->fLocked = false;
134	}
135	return rc;
136	}
137
138
139	#if 0
140	/**
141	* Calls the dissassembler for disassembling the next instruction.
142	*
143	* @returns VBox status code.
144	* @param pState The disas CPU state.
145	*/
146	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
147	{
148	uint32_t cbInstr;
149	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
150	if (RT_SUCCESS(rc))
151	{
152	pState->GCPtrNext = GCPtr + cbInstr;
153	return VINF_SUCCESS;
154	}
155	return rc;
156	}
157	#endif
158
159
160	/**
161	* Done with the dissassembler state, free associated resources.
162	*
163	* @param pState The disas CPU state ++.
164	*/
165	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
166	{
167	if (pState->fLocked)
168	{
169	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
170	pState->fLocked = false;
171	}
172	}
173
174
175	/**
176	* Instruction reader.
177	*
178	* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
179	* @param PtrSrc Address to read from.
180	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
181	* @param pu8Dst Where to store the bytes.
182	* @param cbRead Number of bytes to read.
183	* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
184	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
185	*/
186	static DECLCALLBACK(int) dbgfR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, uint32_t cbRead, void pvDisCpu)
187	{
188	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pvDisCpu;
189	Assert(cbRead > 0);
190	for (;;)
191	{
192	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
193
194	/* Need to update the page translation? */
195	if ( !pState->pvPageR3
196	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
197	{
198	int rc = VINF_SUCCESS;
199
200	/* translate the address */
201	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
202	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
203	{
204	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
205	if (!pState->pvPageR3)
206	rc = VERR_INVALID_POINTER;
207	}
208	else
209	{
210	if (pState->fLocked)
211	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
212
213	if (pState->enmMode <= PGMMODE_PROTECTED)
214	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
215	else
216	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
217	pState->fLocked = RT_SUCCESS_NP(rc);
218	}
219	if (RT_FAILURE(rc))
220	{
221	pState->pvPageR3 = NULL;
222	return rc;
223	}
224	}
225
226	/* check the segemnt limit */
227	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
228	return VERR_OUT_OF_SELECTOR_BOUNDS;
229
230	/* calc how much we can read */
231	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
232	if (!pState->f64Bits)
233	{
234	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
235	if (cb > cbSeg && cbSeg)
236	cb = cbSeg;
237	}
238	if (cb > cbRead)
239	cb = cbRead;
240
241	/* read and advance */
242	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
243	cbRead -= cb;
244	if (!cbRead)
245	return VINF_SUCCESS;
246	pu8Dst += cb;
247	PtrSrc += cb;
248	}
249	}
250
251
252	/**
253	* @copydoc FNDISGETSYMBOL
254	*/
255	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
256	{
257	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
258	PCSELMSELINFO pSelInfo = (PCSELMSELINFO)pvUser;
259	DBGFSYMBOL Sym;
260	RTGCINTPTR off;
261	int rc;
262
263	if (DIS_FMT_SEL_IS_REG(u32Sel))
264	{
265	if (DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS)
266	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
267	else
268	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
269	}
270	else
271	{
272	if (pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
273	rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym);
274	else
275	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
276	}
277
278	if (RT_SUCCESS(rc))
279	{
280	size_t cchName = strlen(Sym.szName);
281	if (cchName >= cchBuf)
282	cchName = cchBuf - 1;
283	memcpy(pszBuf, Sym.szName, cchName);
284	pszBuf[cchName] = '\0';
285
286	*poff = off;
287	}
288
289	return rc;
290	}
291
292
293	/**
294	* Disassembles the one instruction according to the specified flags and address.
295	*
296	* @returns VBox status code.
297	* @param pVM VM handle.
298	* @param pVCpu VMCPU handle.
299	* @param Sel The code selector. This used to determin the 32/16 bit ness and
300	* calculation of the actual instruction address.
301	* @param GCPtr The code address relative to the base of Sel.
302	* @param fFlags Flags controlling where to start and how to format.
303	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
304	* @param pszOutput Output buffer.
305	* @param cchOutput Size of the output buffer.
306	* @param pcbInstr Where to return the size of the instruction.
307	*/
308	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, unsigned fFlags, char pszOutput, uint32_t cchOutput, uint32_t pcbInstr)
309	{
310	/* If not specified, assume CPU 0. */
311	if (!pVCpu)
312	pVCpu = &pVM->aCpus[0];
313
314	/*
315	* Get the Sel and GCPtr if fFlags requests that.
316	*/
317	PCCPUMCTXCORE pCtxCore = NULL;
318	CPUMSELREGHID *pHiddenSel = NULL;
319	int rc;
320	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
321	{
322	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
323	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
324	else
325	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
326	Sel = pCtxCore->cs;
327	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
328	GCPtr = pCtxCore->rip;
329	}
330
331	/*
332	* Read the selector info - assume no stale selectors and nasty stuff like that.
333	* Since the selector flags in the CPUMCTX structures aren't up to date unless
334	* we recently visited REM, we'll not search for the selector there.
335	*/
336	SELMSELINFO SelInfo;
337	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
338	bool fRealModeAddress = false;
339
340	if ( pHiddenSel
341	&& CPUMAreHiddenSelRegsValid(pVM))
342	{
343	SelInfo.GCPtrBase = pHiddenSel->u64Base;
344	SelInfo.cbLimit = pHiddenSel->u32Limit;
345	SelInfo.fHyper = false;
346	SelInfo.fRealMode = !!((pCtxCore && pCtxCore->eflags.Bits.u1VM) \|\| enmMode == PGMMODE_REAL);
347	SelInfo.Raw.au32[0] = 0;
348	SelInfo.Raw.au32[1] = 0;
349	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
350	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
351	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
352	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
353	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
354	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
355	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
356	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
357	fRealModeAddress = SelInfo.fRealMode;
358	}
359	else if (Sel == DBGF_SEL_FLAT)
360	{
361	SelInfo.GCPtrBase = 0;
362	SelInfo.cbLimit = ~0;
363	SelInfo.fHyper = false;
364	SelInfo.fRealMode = false;
365	SelInfo.Raw.au32[0] = 0;
366	SelInfo.Raw.au32[1] = 0;
367	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
368	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
369
370	if (CPUMAreHiddenSelRegsValid(pVM))
371	{ /* Assume the current CS defines the execution mode. */
372	pCtxCore = CPUMGetGuestCtxCore(VMMGetCpu(pVM)); /* @todo SMP support!! */
373	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
374
375	SelInfo.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
376	SelInfo.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
377	SelInfo.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
378	SelInfo.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
379	SelInfo.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
380	SelInfo.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
381	}
382	else
383	{
384	SelInfo.Raw.Gen.u1Present = 1;
385	SelInfo.Raw.Gen.u1Granularity = 1;
386	SelInfo.Raw.Gen.u1DefBig = 1;
387	SelInfo.Raw.Gen.u1DescType = 1;
388	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
389	}
390	}
391	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
392	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
393	\|\| enmMode == PGMMODE_REAL) )
394	{ /* V86 mode or real mode - real mode addressing */
395	SelInfo.GCPtrBase = Sel * 16;
396	SelInfo.cbLimit = ~0;
397	SelInfo.fHyper = false;
398	SelInfo.fRealMode = true;
399	SelInfo.Raw.au32[0] = 0;
400	SelInfo.Raw.au32[1] = 0;
401	SelInfo.Raw.Gen.u16LimitLow = 0xffff;
402	SelInfo.Raw.Gen.u4LimitHigh = 0xf;
403	SelInfo.Raw.Gen.u1Present = 1;
404	SelInfo.Raw.Gen.u1Granularity = 1;
405	SelInfo.Raw.Gen.u1DefBig = 0; /* 16 bits */
406	SelInfo.Raw.Gen.u1DescType = 1;
407	SelInfo.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
408	fRealModeAddress = true;
409	}
410	else
411	{
412	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
413	if (RT_FAILURE(rc))
414	{
415	RTStrPrintf(pszOutput, cchOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
416	return rc;
417	}
418	}
419
420	/*
421	* Disassemble it.
422	*/
423	DBGFDISASSTATE State;
424	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, &State);
425	if (RT_FAILURE(rc))
426	{
427	RTStrPrintf(pszOutput, cchOutput, "Disas -> %Rrc\n", rc);
428	return rc;
429	}
430
431	/*
432	* Format it.
433	*/
434	char szBuf[512];
435	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
436	DIS_FMT_FLAGS_RELATIVE_BRANCH,
437	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
438	&SelInfo);
439
440	/*
441	* Print it to the user specified buffer.
442	*/
443	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
444	{
445	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
446	RTStrPrintf(pszOutput, cchOutput, "%s", szBuf);
447	else if (fRealModeAddress)
448	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
449	else if (Sel == DBGF_SEL_FLAT)
450	{
451	if (enmMode >= PGMMODE_AMD64)
452	RTStrPrintf(pszOutput, cchOutput, "%RGv %s", GCPtr, szBuf);
453	else
454	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
455	}
456	else
457	{
458	if (enmMode >= PGMMODE_AMD64)
459	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
460	else
461	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
462	}
463	}
464	else
465	{
466	uint32_t cbBits = State.Cpu.opsize;
467	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
468	rc = dbgfR3DisasInstrRead(GCPtr, pau8Bits, cbBits, &State);
469	AssertRC(rc);
470	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
471	RTStrPrintf(pszOutput, cchOutput, "%.Rhxs%s %s",
472	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
473	szBuf);
474	else if (fRealModeAddress)
475	RTStrPrintf(pszOutput, cchOutput, "%04x:%04x %.Rhxs%s %s",
476	Sel, (unsigned)GCPtr,
477	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
478	szBuf);
479	else if (Sel == DBGF_SEL_FLAT)
480	{
481	if (enmMode >= PGMMODE_AMD64)
482	RTStrPrintf(pszOutput, cchOutput, "%RGv %.Rhxs%s %s",
483	GCPtr,
484	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
485	szBuf);
486	else
487	RTStrPrintf(pszOutput, cchOutput, "%08RX32 %.Rhxs%s %s",
488	(uint32_t)GCPtr,
489	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
490	szBuf);
491	}
492	else
493	{
494	if (enmMode >= PGMMODE_AMD64)
495	RTStrPrintf(pszOutput, cchOutput, "%04x:%RGv %.Rhxs%s %s",
496	Sel, GCPtr,
497	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
498	szBuf);
499	else
500	RTStrPrintf(pszOutput, cchOutput, "%04x:%08RX32 %.Rhxs%s %s",
501	Sel, (uint32_t)GCPtr,
502	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
503	szBuf);
504	}
505	}
506
507	if (pcbInstr)
508	*pcbInstr = State.Cpu.opsize;
509
510	dbgfR3DisasInstrDone(&State);
511	return VINF_SUCCESS;
512	}
513
514
515	/**
516	* Disassembles an instruction.
517	* Addresses will be tried resolved to symbols
518	*
519	* @returns VBox status code.
520	* @param pVM VM handle.
521	* @param pVCpu VMCPU handle.
522	* @param Sel The code selector. This used to determin the 32/16 bit ness and
523	* calculation of the actual instruction address.
524	* @param GCPtr The code address relative to the base of Sel.
525	* @param pszOutput Output buffer.
526	* @param cchOutput Size of the output buffer.
527	*/
528	VMMR3DECL(int) DBGFR3DisasInstr(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, char *pszOutput, uint32_t cchOutput)
529	{
530	return DBGFR3DisasInstrEx(pVM, pVCpu, Sel, GCPtr, 0, pszOutput, cchOutput, NULL);
531	}
532
533
534	/**
535	* Disassembles the current guest context instruction.
536	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
537	*
538	* @returns VBox status code.
539	* @param pVM VM handle.
540	* @param pszOutput Output buffer.
541	* @param cchOutput Size of the output buffer.
542	*/
543	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVM pVM, char *pszOutput, uint32_t cchOutput)
544	{
545	return DBGFR3DisasInstrEx(pVM, VMMGetCpu(pVM), 0, 0, DBGF_DISAS_FLAGS_CURRENT_GUEST, pszOutput, cchOutput, NULL);
546	}
547
548
549	/**
550	* Disassembles the current guest context instruction and writes it to the log.
551	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
552	*
553	* @returns VBox status code.
554	* @param pVM VM handle.
555	* @param pszPrefix Short prefix string to the dissassembly string. (optional)
556	*/
557	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVM pVM, const char *pszPrefix)
558	{
559	char szBuf[256];
560	szBuf[0] = '\0';
561	int rc = DBGFR3DisasInstrCurrent(pVM, &szBuf[0], sizeof(szBuf));
562	if (RT_FAILURE(rc))
563	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
564	if (pszPrefix && *pszPrefix)
565	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
566	else
567	RTLogPrintf("%s\n", szBuf);
568	return rc;
569	}
570
571
572
573	/**
574	* Disassembles the specified guest context instruction and writes it to the log.
575	* Addresses will be attempted resolved to symbols.
576	*
577	* @returns VBox status code.
578	* @param pVM VM handle.
579	* @param pVCpu VMCPU handle.
580	* @param Sel The code selector. This used to determin the 32/16 bit-ness and
581	* calculation of the actual instruction address.
582	* @param GCPtr The code address relative to the base of Sel.
583	*/
584	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVM pVM, PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
585	{
586	char szBuf[256];
587	szBuf[0] = '\0';
588	int rc = DBGFR3DisasInstr(pVM, pVCpu, Sel, GCPtr, &szBuf[0], sizeof(szBuf));
589	if (RT_FAILURE(rc))
590	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
591	RTLogPrintf("%s\n", szBuf);
592	return rc;
593	}
594

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source: vbox/trunk/src/VBox/VMM/DBGFDisas.cpp@ 18927

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