CPUMInternal.h@ 8155

Last change on this file since 8155 was 8155, checked in by vboxsync, 16 years ago
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1	/* $Id: CPUMInternal.h 8155 2008-04-18 15:16:47Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___CPUMInternal_h
23	#define ___CPUMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/x86.h>
28
29
30	#if !defined(IN_CPUM_R3) && !defined(IN_CPUM_R0) && !defined(IN_CPUM_GC)
31	# error "Not in CPUM! This is an internal header!"
32	#endif
33
34
35	/** @defgroup grp_cpum_int Internals
36	* @ingroup grp_cpum
37	* @internal
38	* @{
39	*/
40
41	/** Flags and types for CPUM fault handlers
42	* @{ */
43	/** Type: Load DS */
44	#define CPUM_HANDLER_DS 1
45	/** Type: Load ES */
46	#define CPUM_HANDLER_ES 2
47	/** Type: Load FS */
48	#define CPUM_HANDLER_FS 3
49	/** Type: Load GS */
50	#define CPUM_HANDLER_GS 4
51	/** Type: IRET */
52	#define CPUM_HANDLER_IRET 5
53	/** Type mask. */
54	#define CPUM_HANDLER_TYPEMASK 0xff
55	/** If set EBP points to the CPUMCTXCORE that's being used. */
56	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
57	/** @} */
58
59
60	/** Use flags (CPUM::fUseFlags).
61	* (Don't forget to sync this with CPUMInternal.mac!)
62	* @{ */
63	/** Used the FPU, SSE or such stuff. */
64	#define CPUM_USED_FPU RT_BIT(0)
65	/** Used the FPU, SSE or such stuff since last we were in REM.
66	* REM syncing is clearing this, lazy FPU is setting it. */
67	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
68	/** Host OS is using SYSENTER and we must NULL the CS. */
69	#define CPUM_USE_SYSENTER RT_BIT(2)
70	/** Host OS is using SYSENTER and we must NULL the CS. */
71	#define CPUM_USE_SYSCALL RT_BIT(3)
72	/** Debug registers are used by host and must be disabled. */
73	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
74	/** Enabled use of debug registers in guest context. */
75	#define CPUM_USE_DEBUG_REGS RT_BIT(5)
76	/** @} */
77
78	/* Sanity check. */
79	#if defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
80	# error "VBOX_WITH_HYBIRD_32BIT_KERNEL is only for 32 bit builds."
81	#endif
82
83
84	/**
85	* The save host CPU state.
86	*
87	* @remark The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
88	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
89	*/
90	typedef struct CPUMHOSTCTX
91	{
92	/** FPU state. (16-byte alignment)
93	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
94	X86FXSTATE fpu;
95
96	/** General purpose register, selectors, flags and more
97	* @{ */
98	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
99	/** General purpose register ++
100	* { */
101	//uint64_t rax; - scratch
102	uint64_t rbx;
103	//uint64_t rcx; - scratch
104	//uint64_t rdx; - scratch
105	uint64_t rdi;
106	uint64_t rsi;
107	uint64_t rbp;
108	uint64_t rsp;
109	//uint64_t r8; - scratch
110	//uint64_t r9; - scratch
111	uint64_t r10;
112	uint64_t r11;
113	uint64_t r12;
114	uint64_t r13;
115	uint64_t r14;
116	uint64_t r15;
117	//uint64_t rip; - scratch
118	uint64_t rflags;
119	#endif
120
121	#if HC_ARCH_BITS == 32
122	//uint32_t eax; - scratch
123	uint32_t ebx;
124	//uint32_t ecx; - scratch
125	//uint32_t edx; - scratch
126	uint32_t edi;
127	uint32_t esi;
128	uint32_t ebp;
129	X86EFLAGS eflags;
130	//uint32_t eip; - scratch
131	/* lss pair! */
132	uint32_t esp;
133	#endif
134	/** @} */
135
136	/** Selector registers
137	* @{ */
138	RTSEL ss;
139	RTSEL ssPadding;
140	RTSEL gs;
141	RTSEL gsPadding;
142	RTSEL fs;
143	RTSEL fsPadding;
144	RTSEL es;
145	RTSEL esPadding;
146	RTSEL ds;
147	RTSEL dsPadding;
148	RTSEL cs;
149	RTSEL csPadding;
150	/** @} */
151
152	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
153	/** Control registers.
154	* @{ */
155	uint32_t cr0;
156	//uint32_t cr2; - scratch
157	uint32_t cr3;
158	uint32_t cr4;
159	/** @} */
160
161	/** Debug registers.
162	* @{ */
163	uint32_t dr0;
164	uint32_t dr1;
165	uint32_t dr2;
166	uint32_t dr3;
167	uint32_t dr6;
168	uint32_t dr7;
169	/** @} */
170
171	/** Global Descriptor Table register. */
172	X86XDTR32 gdtr;
173	uint16_t gdtrPadding;
174	/** Interrupt Descriptor Table register. */
175	X86XDTR32 idtr;
176	uint16_t idtrPadding;
177	/** The task register. */
178	RTSEL ldtr;
179	RTSEL ldtrPadding;
180	/** The task register. */
181	RTSEL tr;
182	RTSEL trPadding;
183	uint32_t SysEnterPadding;
184
185	/** The sysenter msr registers.
186	* This member is not used by the hypervisor context. */
187	CPUMSYSENTER SysEnter;
188
189	/* padding to get 32byte aligned size */
190	uint8_t auPadding[24];
191
192	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
193
194	/** Control registers.
195	* @{ */
196	uint64_t cr0;
197	//uint64_t cr2; - scratch
198	uint64_t cr3;
199	uint64_t cr4;
200	uint64_t cr8;
201	/** @} */
202
203	/** Debug registers.
204	* @{ */
205	uint64_t dr0;
206	uint64_t dr1;
207	uint64_t dr2;
208	uint64_t dr3;
209	uint64_t dr6;
210	uint64_t dr7;
211	/** @} */
212
213	/** Global Descriptor Table register. */
214	X86XDTR64 gdtr;
215	uint16_t gdtrPadding;
216	/** Interrupt Descriptor Table register. */
217	X86XDTR64 idtr;
218	uint16_t idtrPadding;
219	/** The task register. */
220	RTSEL ldtr;
221	RTSEL ldtrPadding;
222	/** The task register. */
223	RTSEL tr;
224	RTSEL trPadding;
225
226	/** MSRs
227	* @{ */
228	CPUMSYSENTER SysEnter;
229	uint64_t FSbase;
230	uint64_t GSbase;
231	uint64_t efer;
232	/** @} */
233
234	/* padding to get 32byte aligned size */
235	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
236	uint8_t auPadding[16];
237	# else
238	uint8_t auPadding[8];
239	# endif
240
241	#else
242	# error HC_ARCH_BITS not defined
243	#endif
244	} CPUMHOSTCTX, *PCPUMHOSTCTX;
245
246
247	/**
248	* Converts a CPUM pointer into a VM pointer.
249	* @returns Pointer to the VM structure the CPUM is part of.
250	* @param pCPUM Pointer to CPUM instance data.
251	*/
252	#define CPUM2VM(pCPUM) ( (PVM)((char*)pCPUM - pCPUM->offVM) )
253
254
255	/**
256	* CPUM Data (part of VM)
257	*/
258	#pragma pack(1)
259	typedef struct CPUM
260	{
261	/** Offset to the VM structure. */
262	RTUINT offVM;
263	/** Pointer to CPU structure in GC. */
264	GCPTRTYPE(struct CPUM *) pCPUMGC;
265	/** Pointer to CPU structure in HC. */
266	R3R0PTRTYPE(struct CPUM *) pCPUMHC;
267
268	/** Force 32byte alignment of the next member. */
269	uint32_t padding[4 + (HC_ARCH_BITS == 32)];
270
271	/**
272	* Saved host context. Only valid while inside GC.
273	* Must be aligned on 16 byte boundrary.
274	*/
275	CPUMHOSTCTX Host;
276
277	/**
278	* Hypervisor context.
279	* Must be aligned on 16 byte boundrary.
280	*/
281	CPUMCTX Hyper;
282
283	/**
284	* Guest context.
285	* Must be aligned on 16 byte boundrary.
286	*/
287	CPUMCTX Guest;
288
289
290	/** Pointer to the current hypervisor core context - R3Ptr. */
291	R3PTRTYPE(PCPUMCTXCORE) pHyperCoreR3;
292	/** Pointer to the current hypervisor core context - R3Ptr. */
293	R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
294	/** Pointer to the current hypervisor core context - GCPtr. */
295	GCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
296
297	/** Use flags.
298	* These flags indicates both what is to be used and what have been used.
299	*/
300	uint32_t fUseFlags;
301
302	/** Changed flags.
303	* These flags indicates to REM (and others) which important guest
304	* registers which has been changed since last time the flags were cleared.
305	* See the CPUM_CHANGED_* defines for what we keep track of.
306	*/
307	uint32_t fChanged;
308
309	/** Hidden selector registers state.
310	* Valid (hw accelerated raw mode) or not (normal raw mode)
311	*/
312	uint32_t fValidHiddenSelRegs;
313
314	/** Host CPU Features - ECX */
315	struct
316	{
317	/** edx part */
318	X86CPUIDFEATEDX edx;
319	/** ecx part */
320	X86CPUIDFEATECX ecx;
321	} CPUFeatures;
322
323	/** CR4 mask */
324	struct
325	{
326	uint32_t AndMask;
327	uint32_t OrMask;
328	} CR4;
329
330	/** Have we entered rawmode? */
331	bool fRawEntered;
332	uint8_t abPadding[3 + (HC_ARCH_BITS == 64) * 4];
333
334	/** The standard set of CpuId leafs. */
335	CPUMCPUID aGuestCpuIdStd[5];
336	/** The extended set of CpuId leafs. */
337	CPUMCPUID aGuestCpuIdExt[10];
338	/** The centaur set of CpuId leafs. */
339	CPUMCPUID aGuestCpuIdCentaur[4];
340	/** The default set of CpuId leafs. */
341	CPUMCPUID GuestCpuIdDef;
342
343	/**
344	* Guest context on raw mode entry.
345	* This a debug feature.
346	*/
347	CPUMCTX GuestEntry;
348	} CPUM, *PCPUM;
349	#pragma pack()
350
351	#ifdef IN_RING3
352
353	#endif
354
355	__BEGIN_DECLS
356
357	DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
358	DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
359
360	__END_DECLS
361
362	/** @} */
363
364	#endif

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source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 8155

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