CPUMInternal.h@ 15605

Last change on this file since 15605 was 15563, checked in by vboxsync, 16 years ago
Save and restore the host's EFER msr in the 32->64 switcher.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 11.2 KB

Line
1	/* $Id: CPUMInternal.h 15563 2008-12-16 09:25:08Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___CPUMInternal_h
23	#define ___CPUMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/x86.h>
28
29
30
31	/** @defgroup grp_cpum_int Internals
32	* @ingroup grp_cpum
33	* @internal
34	* @{
35	*/
36
37	/** Flags and types for CPUM fault handlers
38	* @{ */
39	/** Type: Load DS */
40	#define CPUM_HANDLER_DS 1
41	/** Type: Load ES */
42	#define CPUM_HANDLER_ES 2
43	/** Type: Load FS */
44	#define CPUM_HANDLER_FS 3
45	/** Type: Load GS */
46	#define CPUM_HANDLER_GS 4
47	/** Type: IRET */
48	#define CPUM_HANDLER_IRET 5
49	/** Type mask. */
50	#define CPUM_HANDLER_TYPEMASK 0xff
51	/** If set EBP points to the CPUMCTXCORE that's being used. */
52	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
53	/** @} */
54
55
56	/** Use flags (CPUM::fUseFlags).
57	* (Don't forget to sync this with CPUMInternal.mac!)
58	* @{ */
59	/** Used the FPU, SSE or such stuff. */
60	#define CPUM_USED_FPU RT_BIT(0)
61	/** Used the FPU, SSE or such stuff since last we were in REM.
62	* REM syncing is clearing this, lazy FPU is setting it. */
63	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
64	/** Host OS is using SYSENTER and we must NULL the CS. */
65	#define CPUM_USE_SYSENTER RT_BIT(2)
66	/** Host OS is using SYSENTER and we must NULL the CS. */
67	#define CPUM_USE_SYSCALL RT_BIT(3)
68	/** Debug registers are used by host and must be disabled. */
69	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(4)
70	/** Enabled use of debug registers in guest context. */
71	#define CPUM_USE_DEBUG_REGS RT_BIT(5)
72	/** The XMM state was manually restored. (AMD only) */
73	#define CPUM_MANUAL_XMM_RESTORE RT_BIT(6)
74	/** Sync the FPU state on entry (32->64 switcher only). */
75	#define CPUM_SYNC_FPU_STATE RT_BIT(7)
76	/** Sync the debug state on entry (32->64 switcher only). */
77	#define CPUM_SYNC_DEBUG_STATE RT_BIT(8)
78	/** @} */
79
80	/* Sanity check. */
81	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
82	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
83	#endif
84
85
86	/**
87	* The saved host CPU state.
88	*
89	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
90	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
91	*/
92	typedef struct CPUMHOSTCTX
93	{
94	/** FPU state. (16-byte alignment)
95	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
96	X86FXSTATE fpu;
97
98	/** General purpose register, selectors, flags and more
99	* @{ */
100	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
101	/** General purpose register ++
102	* { */
103	//uint64_t rax; - scratch
104	uint64_t rbx;
105	//uint64_t rcx; - scratch
106	//uint64_t rdx; - scratch
107	uint64_t rdi;
108	uint64_t rsi;
109	uint64_t rbp;
110	uint64_t rsp;
111	//uint64_t r8; - scratch
112	//uint64_t r9; - scratch
113	uint64_t r10;
114	uint64_t r11;
115	uint64_t r12;
116	uint64_t r13;
117	uint64_t r14;
118	uint64_t r15;
119	//uint64_t rip; - scratch
120	uint64_t rflags;
121	#endif
122
123	#if HC_ARCH_BITS == 32
124	//uint32_t eax; - scratch
125	uint32_t ebx;
126	//uint32_t ecx; - scratch
127	//uint32_t edx; - scratch
128	uint32_t edi;
129	uint32_t esi;
130	uint32_t ebp;
131	X86EFLAGS eflags;
132	//uint32_t eip; - scratch
133	/* lss pair! */
134	uint32_t esp;
135	#endif
136	/** @} */
137
138	/** Selector registers
139	* @{ */
140	RTSEL ss;
141	RTSEL ssPadding;
142	RTSEL gs;
143	RTSEL gsPadding;
144	RTSEL fs;
145	RTSEL fsPadding;
146	RTSEL es;
147	RTSEL esPadding;
148	RTSEL ds;
149	RTSEL dsPadding;
150	RTSEL cs;
151	RTSEL csPadding;
152	/** @} */
153
154	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
155	/** Control registers.
156	* @{ */
157	uint32_t cr0;
158	//uint32_t cr2; - scratch
159	uint32_t cr3;
160	uint32_t cr4;
161	/** @} */
162
163	/** Debug registers.
164	* @{ */
165	uint32_t dr0;
166	uint32_t dr1;
167	uint32_t dr2;
168	uint32_t dr3;
169	uint32_t dr6;
170	uint32_t dr7;
171	/** @} */
172
173	/** Global Descriptor Table register. */
174	X86XDTR32 gdtr;
175	uint16_t gdtrPadding;
176	/** Interrupt Descriptor Table register. */
177	X86XDTR32 idtr;
178	uint16_t idtrPadding;
179	/** The task register. */
180	RTSEL ldtr;
181	RTSEL ldtrPadding;
182	/** The task register. */
183	RTSEL tr;
184	RTSEL trPadding;
185	uint32_t SysEnterPadding;
186
187	/** The sysenter msr registers.
188	* This member is not used by the hypervisor context. */
189	CPUMSYSENTER SysEnter;
190
191	/** MSRs
192	* @{ */
193	uint64_t efer;
194	/** @} */
195
196	/* padding to get 64byte aligned size */
197	uint8_t auPadding[16+32];
198
199	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
200
201	/** Control registers.
202	* @{ */
203	uint64_t cr0;
204	//uint64_t cr2; - scratch
205	uint64_t cr3;
206	uint64_t cr4;
207	uint64_t cr8;
208	/** @} */
209
210	/** Debug registers.
211	* @{ */
212	uint64_t dr0;
213	uint64_t dr1;
214	uint64_t dr2;
215	uint64_t dr3;
216	uint64_t dr6;
217	uint64_t dr7;
218	/** @} */
219
220	/** Global Descriptor Table register. */
221	X86XDTR64 gdtr;
222	uint16_t gdtrPadding;
223	/** Interrupt Descriptor Table register. */
224	X86XDTR64 idtr;
225	uint16_t idtrPadding;
226	/** The task register. */
227	RTSEL ldtr;
228	RTSEL ldtrPadding;
229	/** The task register. */
230	RTSEL tr;
231	RTSEL trPadding;
232
233	/** MSRs
234	* @{ */
235	CPUMSYSENTER SysEnter;
236	uint64_t FSbase;
237	uint64_t GSbase;
238	uint64_t efer;
239	/** @} */
240
241	/* padding to get 32byte aligned size */
242	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
243	uint8_t auPadding[16];
244	# else
245	uint8_t auPadding[8+32];
246	# endif
247
248	#else
249	# error HC_ARCH_BITS not defined
250	#endif
251	} CPUMHOSTCTX;
252	/** Pointer to the saved host CPU state. */
253	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
254
255
256	/**
257	* CPUM Data (part of VM)
258	*/
259	typedef struct CPUM
260	{
261	/**
262	* Hypervisor context.
263	* Aligned on a 64-byte boundrary.
264	*/
265	CPUMCTX Hyper;
266
267	/** Pointer to the current hypervisor core context - R3Ptr. */
268	R3PTRTYPE(PCPUMCTXCORE) pHyperCoreR3;
269	/** Pointer to the current hypervisor core context - R0Ptr. */
270	R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
271	/** Pointer to the current hypervisor core context - RCPtr. */
272	RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
273
274	/* Offset from CPUM to CPUMCPU for the first CPU. */
275	uint32_t ulOffCPUMCPU;
276
277	/** Hidden selector registers state.
278	* Valid (hw accelerated raw mode) or not (normal raw mode)
279	*/
280	uint32_t fValidHiddenSelRegs;
281
282	/** Host CPU Features - ECX */
283	struct
284	{
285	/** edx part */
286	X86CPUIDFEATEDX edx;
287	/** ecx part */
288	X86CPUIDFEATECX ecx;
289	} CPUFeatures;
290	/** Host extended CPU features. */
291	struct
292	{
293	/** edx part */
294	uint32_t edx;
295	/** ecx part */
296	uint32_t ecx;
297	} CPUFeaturesExt;
298
299	/* CPU manufacturer. */
300	CPUMCPUVENDOR enmCPUVendor;
301
302	/** CR4 mask */
303	struct
304	{
305	uint32_t AndMask;
306	uint32_t OrMask;
307	} CR4;
308
309	/** Have we entered rawmode? */
310	bool fRawEntered;
311	uint8_t abPadding[3 + (HC_ARCH_BITS == 64) * 4];
312
313	/** The standard set of CpuId leafs. */
314	CPUMCPUID aGuestCpuIdStd[6];
315	/** The extended set of CpuId leafs. */
316	CPUMCPUID aGuestCpuIdExt[10];
317	/** The centaur set of CpuId leafs. */
318	CPUMCPUID aGuestCpuIdCentaur[4];
319	/** The default set of CpuId leafs. */
320	CPUMCPUID GuestCpuIdDef;
321
322	/** Align the next member, and thereby the structure, on a 64-byte boundrary. */
323	uint8_t abPadding2[HC_ARCH_BITS == 32 ? 60 : 48];
324
325	/**
326	* Guest context on raw mode entry.
327	* This a debug feature, see CPUMR3SaveEntryCtx.
328	*/
329	CPUMCTX GuestEntry;
330	} CPUM;
331	/** Pointer to the CPUM instance data residing in the shared VM structure. */
332	typedef CPUM *PCPUM;
333
334	/**
335	* CPUM Data (part of VMCPU)
336	*/
337	typedef struct CPUMCPU
338	{
339	/**
340	* Saved host context. Only valid while inside GC.
341	* Aligned on a 64-byte boundrary.
342	*/
343	CPUMHOSTCTX Host;
344
345	/**
346	* Guest context.
347	* Aligned on a 64-byte boundrary.
348	*/
349	CPUMCTX Guest;
350
351	/**
352	* Guest context - misc MSRs
353	* Aligned on a 64-byte boundrary.
354	*/
355	CPUMCTXMSR GuestMsr;
356
357	/** Use flags.
358	* These flags indicates both what is to be used and what has been used.
359	*/
360	uint32_t fUseFlags;
361
362	/** Changed flags.
363	* These flags indicates to REM (and others) which important guest
364	* registers which has been changed since last time the flags were cleared.
365	* See the CPUM_CHANGED_* defines for what we keep track of.
366	*/
367	uint32_t fChanged;
368
369	/* Offset to CPUM. (subtract from the pointer to get to CPUM) */
370	uint32_t ulOffCPUM;
371
372	/* Temporary storage for the return code of the function called in the 32-64 switcher. */
373	uint32_t u32RetCode;
374
375	/* Round to 16 byte size.
376	uint32_t uPadding;
377	*/
378	} CPUMCPU, *PCPUMCPU;
379	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
380	typedef CPUMCPU *PCPUMCPU;
381
382	__BEGIN_DECLS
383
384	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
385
386	#ifdef IN_RING0
387	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
388	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
389	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
390	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
391	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
392	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
393	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
394	DECLASM(uint16_t) cpumR0GetFCW(void);
395	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
396	DECLASM(uint32_t) cpumR0GetMXCSR(void);
397	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
398	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
399	#endif
400
401	__END_DECLS
402
403	/** @} */
404
405	#endif
406

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 15605

Download in other formats: