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source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 140

Last change on this file since 140 was 140, checked in by vboxsync, 18 years ago

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1/* $Id: CPUMInternal.h 140 2007-01-18 15:28:16Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22#ifndef __CPUMInternal_h__
23#define __CPUMInternal_h__
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/x86.h>
28
29
30#if !defined(IN_CPUM_R3) && !defined(IN_CPUM_R0) && !defined(IN_CPUM_GC)
31# error "Not in CPUM! This is an internal header!"
32#endif
33
34
35/** @defgroup grp_cpum_int Internals
36 * @ingroup grp_cpum
37 * @internal
38 * @{
39 */
40
41/** Flags and types for CPUM fault handlers
42 * @{ */
43/** Type: Load DS */
44#define CPUM_HANDLER_DS 1
45/** Type: Load ES */
46#define CPUM_HANDLER_ES 2
47/** Type: Load FS */
48#define CPUM_HANDLER_FS 3
49/** Type: Load GS */
50#define CPUM_HANDLER_GS 4
51/** Type: IRET */
52#define CPUM_HANDLER_IRET 5
53/** Type mask. */
54#define CPUM_HANDLER_TYPEMASK 0xff
55/** If set EBP points to the CPUMCTXCORE that's being used. */
56#define CPUM_HANDLER_CTXCORE_IN_EBP BIT(31)
57/** @} */
58
59
60/** Use flags (CPUM::fUseFlags).
61 * (Don't forget to sync this with CPUMInternal.mac!)
62 * @{ */
63/** Used the FPU, SSE or such stuff. */
64#define CPUM_USED_FPU BIT(0)
65/** Used the FPU, SSE or such stuff since last we were in REM.
66 * REM syncing is clearing this, lazy FPU is setting it. */
67#define CPUM_USED_FPU_SINCE_REM BIT(1)
68/** Host OS is using SYSENTER and we must NULL the CS. */
69#define CPUM_USE_SYSENTER BIT(2)
70/** Host OS is using SYSENTER and we must NULL the CS. */
71#define CPUM_USE_SYSCALL BIT(3)
72/** Debug registers are used by host and must be disabled. */
73#define CPUM_USE_DEBUG_REGS_HOST BIT(4)
74/** Enabled use of debug registers in guest context. */
75#define CPUM_USE_DEBUG_REGS BIT(5)
76/** @} */
77
78
79/**
80 * The save host CPU state.
81 */
82typedef struct CPUMHOSTCTX
83{
84 /** FPU state. (16-byte alignment)
85 * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
86 X86FXSTATE fpu;
87
88#if HC_ARCH_BITS == 32
89 /** General purpose register, selectors, flags and more
90 * @{ */
91 //uint32_t eax; - scratch
92 uint32_t ebx;
93 //uint32_t ecx; - scratch
94 //uint32_t edx; - scratch
95 uint32_t edi;
96 uint32_t esi;
97 uint32_t ebp;
98 /* lss pair */
99 uint32_t esp;
100 RTSEL ss;
101 RTSEL ssPadding;
102 RTSEL gs;
103 RTSEL gsPadding;
104 RTSEL fs;
105 RTSEL fsPadding;
106 RTSEL es;
107 RTSEL esPadding;
108 RTSEL ds;
109 RTSEL dsPadding;
110 RTSEL cs;
111 RTSEL csPadding;
112 X86EFLAGS eflags;
113 //uint32_t eip; - scratch
114 /** @} */
115
116 /** Control registers.
117 * @{ */
118 uint32_t cr0;
119 //uint32_t cr2; - scratch
120 uint32_t cr3;
121 uint32_t cr4;
122 /** @} */
123
124 /** Debug registers.
125 * @{ */
126 uint32_t dr0;
127 uint32_t dr1;
128 uint32_t dr2;
129 uint32_t dr3;
130 uint32_t dr6;
131 uint32_t dr7;
132 /** @} */
133
134 /** Global Descriptor Table register. */
135 VBOXGDTR gdtr;
136 uint16_t gdtrPadding;
137 /** Interrupt Descriptor Table register. */
138 VBOXIDTR idtr;
139 uint16_t idtrPadding;
140 /** The task register. */
141 RTSEL ldtr;
142 RTSEL ldtrPadding;
143 /** The task register. */
144 RTSEL tr;
145 RTSEL trPadding;
146 uint32_t SysEnterPadding;
147
148 /** The sysenter msr registers.
149 * This member is not used by the hypervisor context. */
150 CPUMSYSENTER SysEnter;
151
152 /* padding to get 32byte aligned size */
153 uint8_t auPadding[24];
154
155#elif HC_ARCH_BITS == 64
156 /** General purpose register ++
157 * { */
158 //uint64_t rax; - scratch
159 uint64_t rbx;
160 //uint64_t rcx; - scratch
161 //uint64_t rdx; - scratch
162 uint64_t rdi;
163 uint64_t rsi;
164 uint64_t rbp;
165 uint64_t rsp;
166 //uint64_t r8; - scratch
167 //uint64_t r9; - scratch
168 uint64_t r10;
169 uint64_t r11;
170 uint64_t r12;
171 uint64_t r13;
172 uint64_t r14;
173 uint64_t r15;
174 //uint64_t rip; - scratch
175 uint64_t rflags;
176 /** @} */
177
178 /** Selector registers
179 * @{ */
180 RTSEL ss;
181 RTSEL ssPadding;
182 RTSEL gs;
183 RTSEL gsPadding;
184 RTSEL fs;
185 RTSEL fsPadding;
186 RTSEL es;
187 RTSEL esPadding;
188 RTSEL ds;
189 RTSEL dsPadding;
190 RTSEL cs;
191 RTSEL csPadding;
192 /** @} */
193
194 /** Control registers.
195 * @{ */
196 uint64_t cr0;
197 //uint64_t cr2; - scratch
198 uint64_t cr3;
199 uint64_t cr4;
200 uint64_t cr8;
201 /** @} */
202
203 /** Debug registers.
204 * @{ */
205 uint64_t dr0;
206 uint64_t dr1;
207 uint64_t dr2;
208 uint64_t dr3;
209 uint64_t dr6;
210 uint64_t dr7;
211 /** @} */
212
213 /** Global Descriptor Table register. */
214 uint8_t gdtr[10]; //X86GDTR64
215 uint16_t gdtrPadding;
216 /** Interrupt Descriptor Table register. */
217 uint8_t idtr[10]; //X86IDTR64
218 uint16_t idtrPadding;
219 /** The task register. */
220 RTSEL ldtr;
221 RTSEL ldtrPadding;
222 /** The task register. */
223 RTSEL tr;
224 RTSEL trPadding;
225
226 /** MSRs
227 * @{ */
228 CPUMSYSENTER SysEnter;
229 uint64_t FSbase;
230 uint64_t GSbase;
231 uint64_t efer;
232 /** @} */
233
234 /* padding to get 32byte aligned size */
235 uint8_t auPadding[8];
236#else
237# error HC_ARCH_BITS not defined
238#endif
239} CPUMHOSTCTX, *PCPUMHOSTCTX;
240
241
242/**
243 * Converts a CPUM pointer into a VM pointer.
244 * @returns Pointer to the VM structure the CPUM is part of.
245 * @param pCPUM Pointer to CPUM instance data.
246 */
247#define CPUM2VM(pCPUM) ( (PVM)((char*)pCPUM - pCPUM->offVM) )
248
249
250/**
251 * CPUM Data (part of VM)
252 */
253#pragma pack(1)
254typedef struct CPUM
255{
256 /** Offset to the VM structure. */
257 RTUINT offVM;
258 /** Pointer to CPU structure in GC. */
259 GCPTRTYPE(struct CPUM *) pCPUMGC;
260 /** Pointer to CPU structure in HC. */
261 HCPTRTYPE(struct CPUM *) pCPUMHC;
262
263 /** Force 32byte alignment of the next member. */
264 uint32_t padding[4 + (HC_ARCH_BITS == 32)];
265
266 /**
267 * Saved host context. Only valid while inside GC.
268 * Must be aligned on 16 byte boundrary.
269 */
270 CPUMHOSTCTX Host;
271
272 /**
273 * Hypervisor context.
274 * Must be aligned on 16 byte boundrary.
275 */
276 CPUMCTX Hyper;
277
278 /**
279 * Guest context.
280 * Must be aligned on 16 byte boundrary.
281 */
282 CPUMCTX Guest;
283
284
285 /** Pointer to the current hypervisor core context - HCPtr. */
286 HCPTRTYPE(PCPUMCTXCORE) pHyperCoreHC;
287 /** Pointer to the current hypervisor core context - GCPtr. */
288 GCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
289
290 /** Use flags.
291 * These flags indicates both what is to be used and what have been used.
292 */
293 uint32_t fUseFlags;
294
295 /** Changed flags.
296 * These flags indicates to REM (and others) which important guest
297 * registers which has been changed since last time the flags were cleared.
298 * See the CPUM_CHANGED_* defines for what we keep track of.
299 */
300 uint32_t fChanged;
301
302 /** Hidden selector registers state.
303 * Valid (hw accelerated raw mode) or not (normal raw mode)
304 */
305 uint32_t fValidHiddenSelRegs;
306
307 /** Host CPU Features - ECX */
308 struct
309 {
310 /** edx part */
311 X86CPUIDFEATEDX edx;
312 /** ecx part */
313 X86CPUIDFEATECX ecx;
314 } CPUFeatures;
315
316 /** CR4 mask */
317 struct
318 {
319 uint32_t Mask;
320 uint32_t OSFSXR;
321 } CR4;
322
323 /** Have we entered rawmode? */
324 bool fRawEntered;
325 uint8_t abPadding[3 + (HC_ARCH_BITS == 32) * 4];
326
327 /** The standard set of CpuId leafs. */
328 CPUMCPUID aGuestCpuIdStd[5];
329 /** The extended set of CpuId leafs. */
330 CPUMCPUID aGuestCpuIdExt[10];
331 /** The default set of CpuId leafs. */
332 CPUMCPUID GuestCpuIdDef;
333
334 /**
335 * Guest context on raw mode entry.
336 * This a debug feature.
337 */
338 CPUMCTX GuestEntry;
339} CPUM, *PCPUM;
340#pragma pack()
341
342#ifdef IN_RING3
343
344#endif
345
346__BEGIN_DECLS
347
348DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
349DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
350
351__END_DECLS
352
353/** @} */
354
355#endif
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