CPUMInternal.h@ 1283

Last change on this file since 1283 was 1283, checked in by vboxsync, 18 years ago
Added support for the hybrid darwin setup where the kernel is 32-bit but the cpu might be running in 64-bit mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 9.3 KB

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1	/* $Id: CPUMInternal.h 1283 2007-03-07 00:02:11Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22	#ifndef __CPUMInternal_h__
23	#define __CPUMInternal_h__
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/x86.h>
28
29
30	#if !defined(IN_CPUM_R3) && !defined(IN_CPUM_R0) && !defined(IN_CPUM_GC)
31	# error "Not in CPUM! This is an internal header!"
32	#endif
33
34
35	/** @defgroup grp_cpum_int Internals
36	* @ingroup grp_cpum
37	* @internal
38	* @{
39	*/
40
41	/** Flags and types for CPUM fault handlers
42	* @{ */
43	/** Type: Load DS */
44	#define CPUM_HANDLER_DS 1
45	/** Type: Load ES */
46	#define CPUM_HANDLER_ES 2
47	/** Type: Load FS */
48	#define CPUM_HANDLER_FS 3
49	/** Type: Load GS */
50	#define CPUM_HANDLER_GS 4
51	/** Type: IRET */
52	#define CPUM_HANDLER_IRET 5
53	/** Type mask. */
54	#define CPUM_HANDLER_TYPEMASK 0xff
55	/** If set EBP points to the CPUMCTXCORE that's being used. */
56	#define CPUM_HANDLER_CTXCORE_IN_EBP BIT(31)
57	/** @} */
58
59
60	/** Use flags (CPUM::fUseFlags).
61	* (Don't forget to sync this with CPUMInternal.mac!)
62	* @{ */
63	/** Used the FPU, SSE or such stuff. */
64	#define CPUM_USED_FPU BIT(0)
65	/** Used the FPU, SSE or such stuff since last we were in REM.
66	* REM syncing is clearing this, lazy FPU is setting it. */
67	#define CPUM_USED_FPU_SINCE_REM BIT(1)
68	/** Host OS is using SYSENTER and we must NULL the CS. */
69	#define CPUM_USE_SYSENTER BIT(2)
70	/** Host OS is using SYSENTER and we must NULL the CS. */
71	#define CPUM_USE_SYSCALL BIT(3)
72	/** Debug registers are used by host and must be disabled. */
73	#define CPUM_USE_DEBUG_REGS_HOST BIT(4)
74	/** Enabled use of debug registers in guest context. */
75	#define CPUM_USE_DEBUG_REGS BIT(5)
76	/** @} */
77
78
79	/**
80	* The save host CPU state.
81	*
82	* @remark The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
83	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
84	*/
85	typedef struct CPUMHOSTCTX
86	{
87	/** FPU state. (16-byte alignment)
88	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
89	X86FXSTATE fpu;
90
91	/** General purpose register, selectors, flags and more
92	* @{ */
93	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
94	/** General purpose register ++
95	* { */
96	//uint64_t rax; - scratch
97	uint64_t rbx;
98	//uint64_t rcx; - scratch
99	//uint64_t rdx; - scratch
100	uint64_t rdi;
101	uint64_t rsi;
102	uint64_t rbp;
103	uint64_t rsp;
104	//uint64_t r8; - scratch
105	//uint64_t r9; - scratch
106	uint64_t r10;
107	uint64_t r11;
108	uint64_t r12;
109	uint64_t r13;
110	uint64_t r14;
111	uint64_t r15;
112	//uint64_t rip; - scratch
113	uint64_t rflags;
114	#endif
115
116	#if HC_ARCH_BITS == 32
117	//uint32_t eax; - scratch
118	uint32_t ebx;
119	//uint32_t ecx; - scratch
120	//uint32_t edx; - scratch
121	uint32_t edi;
122	uint32_t esi;
123	uint32_t ebp;
124	X86EFLAGS eflags;
125	//uint32_t eip; - scratch
126	/* lss pair! */
127	uint32_t esp;
128	#endif
129	/** @} */
130
131	/** Selector registers
132	* @{ */
133	RTSEL ss;
134	RTSEL ssPadding;
135	RTSEL gs;
136	RTSEL gsPadding;
137	RTSEL fs;
138	RTSEL fsPadding;
139	RTSEL es;
140	RTSEL esPadding;
141	RTSEL ds;
142	RTSEL dsPadding;
143	RTSEL cs;
144	RTSEL csPadding;
145	/** @} */
146
147	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
148	/** Control registers.
149	* @{ */
150	uint32_t cr0;
151	//uint32_t cr2; - scratch
152	uint32_t cr3;
153	uint32_t cr4;
154	/** @} */
155
156	/** Debug registers.
157	* @{ */
158	uint32_t dr0;
159	uint32_t dr1;
160	uint32_t dr2;
161	uint32_t dr3;
162	uint32_t dr6;
163	uint32_t dr7;
164	/** @} */
165
166	/** Global Descriptor Table register. */
167	X86XDTR32 gdtr;
168	uint16_t gdtrPadding;
169	/** Interrupt Descriptor Table register. */
170	X86XDTR32 idtr;
171	uint16_t idtrPadding;
172	/** The task register. */
173	RTSEL ldtr;
174	RTSEL ldtrPadding;
175	/** The task register. */
176	RTSEL tr;
177	RTSEL trPadding;
178	uint32_t SysEnterPadding;
179
180	/** The sysenter msr registers.
181	* This member is not used by the hypervisor context. */
182	CPUMSYSENTER SysEnter;
183
184	/* padding to get 32byte aligned size */
185	uint8_t auPadding[24];
186
187	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
188
189	/** Control registers.
190	* @{ */
191	uint64_t cr0;
192	//uint64_t cr2; - scratch
193	uint64_t cr3;
194	uint64_t cr4;
195	uint64_t cr8;
196	/** @} */
197
198	/** Debug registers.
199	* @{ */
200	uint64_t dr0;
201	uint64_t dr1;
202	uint64_t dr2;
203	uint64_t dr3;
204	uint64_t dr6;
205	uint64_t dr7;
206	/** @} */
207
208	/** Global Descriptor Table register. */
209	X86XDTR64 gdtr;
210	uint16_t gdtrPadding;
211	/** Interrupt Descriptor Table register. */
212	X86XDTR64 idtr;
213	uint16_t idtrPadding;
214	/** The task register. */
215	RTSEL ldtr;
216	RTSEL ldtrPadding;
217	/** The task register. */
218	RTSEL tr;
219	RTSEL trPadding;
220
221	/** MSRs
222	* @{ */
223	CPUMSYSENTER SysEnter;
224	uint64_t FSbase;
225	uint64_t GSbase;
226	uint64_t efer;
227	/** @} */
228
229	/* padding to get 32byte aligned size */
230	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
231	uint8_t auPadding[16];
232	# else
233	uint8_t auPadding[24];
234	# endif
235
236	#else
237	# error HC_ARCH_BITS not defined
238	#endif
239	} CPUMHOSTCTX, *PCPUMHOSTCTX;
240
241
242	/**
243	* Converts a CPUM pointer into a VM pointer.
244	* @returns Pointer to the VM structure the CPUM is part of.
245	* @param pCPUM Pointer to CPUM instance data.
246	*/
247	#define CPUM2VM(pCPUM) ( (PVM)((char*)pCPUM - pCPUM->offVM) )
248
249
250	/**
251	* CPUM Data (part of VM)
252	*/
253	#pragma pack(1)
254	typedef struct CPUM
255	{
256	/** Offset to the VM structure. */
257	RTUINT offVM;
258	/** Pointer to CPU structure in GC. */
259	GCPTRTYPE(struct CPUM *) pCPUMGC;
260	/** Pointer to CPU structure in HC. */
261	HCPTRTYPE(struct CPUM *) pCPUMHC;
262
263	/** Force 32byte alignment of the next member. */
264	uint32_t padding[4 + (HC_ARCH_BITS == 32)];
265
266	/**
267	* Saved host context. Only valid while inside GC.
268	* Must be aligned on 16 byte boundrary.
269	*/
270	CPUMHOSTCTX Host;
271
272	/**
273	* Hypervisor context.
274	* Must be aligned on 16 byte boundrary.
275	*/
276	CPUMCTX Hyper;
277
278	/**
279	* Guest context.
280	* Must be aligned on 16 byte boundrary.
281	*/
282	CPUMCTX Guest;
283
284
285	/** Pointer to the current hypervisor core context - HCPtr. */
286	HCPTRTYPE(PCPUMCTXCORE) pHyperCoreHC;
287	/** Pointer to the current hypervisor core context - GCPtr. */
288	GCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
289
290	/** Use flags.
291	* These flags indicates both what is to be used and what have been used.
292	*/
293	uint32_t fUseFlags;
294
295	/** Changed flags.
296	* These flags indicates to REM (and others) which important guest
297	* registers which has been changed since last time the flags were cleared.
298	* See the CPUM_CHANGED_* defines for what we keep track of.
299	*/
300	uint32_t fChanged;
301
302	/** Hidden selector registers state.
303	* Valid (hw accelerated raw mode) or not (normal raw mode)
304	*/
305	uint32_t fValidHiddenSelRegs;
306
307	/** Host CPU Features - ECX */
308	struct
309	{
310	/** edx part */
311	X86CPUIDFEATEDX edx;
312	/** ecx part */
313	X86CPUIDFEATECX ecx;
314	} CPUFeatures;
315
316	/** CR4 mask */
317	struct
318	{
319	uint32_t AndMask;
320	uint32_t OrMask;
321	} CR4;
322
323	/** Have we entered rawmode? */
324	bool fRawEntered;
325	uint8_t abPadding[3 + (HC_ARCH_BITS == 32) * 4];
326
327	/** The standard set of CpuId leafs. */
328	CPUMCPUID aGuestCpuIdStd[5];
329	/** The extended set of CpuId leafs. */
330	CPUMCPUID aGuestCpuIdExt[10];
331	/** The default set of CpuId leafs. */
332	CPUMCPUID GuestCpuIdDef;
333
334	/**
335	* Guest context on raw mode entry.
336	* This a debug feature.
337	*/
338	CPUMCTX GuestEntry;
339	} CPUM, *PCPUM;
340	#pragma pack()
341
342	#ifdef IN_RING3
343
344	#endif
345
346	__BEGIN_DECLS
347
348	DECLASM(int) CPUMHandleLazyFPUAsm(PCPUM pCPUM);
349	DECLASM(int) CPUMRestoreHostFPUStateAsm(PCPUM pCPUM);
350
351	__END_DECLS
352
353	/** @} */
354
355	#endif

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source: vbox/trunk/src/VBox/VMM/CPUMInternal.h@ 1283

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