VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 8129

Last change on this file since 8129 was 8129, checked in by vboxsync, 17 years ago

Removed inactive PGM_WITH_BROKEN_32PAE_SWITCHER code
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 86.0 KB
Line 
1/* $Id: CPUM.cpp 8129 2008-04-18 09:13:04Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/cpum.h>
24#include <VBox/cpumdis.h>
25#include <VBox/pgm.h>
26#include <VBox/mm.h>
27#include <VBox/selm.h>
28#include <VBox/dbgf.h>
29#include <VBox/patm.h>
30#include <VBox/ssm.h>
31#include "CPUMInternal.h"
32#include <VBox/vm.h>
33
34#include <VBox/param.h>
35#include <VBox/dis.h>
36#include <VBox/err.h>
37#include <VBox/log.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/string.h>
41#include <iprt/system.h>
42
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47/** The saved state version. */
48#define CPUM_SAVED_STATE_VERSION 6
49
50
51/*******************************************************************************
52* Structures and Typedefs *
53*******************************************************************************/
54
55/**
56 * What kind of cpu info dump to performe.
57 */
58typedef enum CPUMDUMPTYPE
59{
60 CPUMDUMPTYPE_TERSE,
61 CPUMDUMPTYPE_DEFAULT,
62 CPUMDUMPTYPE_VERBOSE
63
64} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
65
66
67/*******************************************************************************
68* Internal Functions *
69*******************************************************************************/
70static int cpumR3CpuIdInit(PVM pVM);
71static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
72static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
73static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
74static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
75static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
76static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
77static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78
79
80/**
81 * Initializes the CPUM.
82 *
83 * @returns VBox status code.
84 * @param pVM The VM to operate on.
85 */
86CPUMR3DECL(int) CPUMR3Init(PVM pVM)
87{
88 LogFlow(("CPUMR3Init\n"));
89
90 /*
91 * Assert alignment and sizes.
92 */
93 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
94 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
95
96 /*
97 * Setup any fixed pointers and offsets.
98 */
99 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
100 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
101 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
102 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
103
104 /* Hidden selector registers are invalid by default. */
105 pVM->cpum.s.fValidHiddenSelRegs = false;
106
107 /*
108 * Check that the CPU supports the minimum features we require.
109 */
110 /** @todo check the contract! */
111 if (!ASMHasCpuId())
112 {
113 Log(("The CPU doesn't support CPUID!\n"));
114 return VERR_UNSUPPORTED_CPU;
115 }
116 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
117
118 /* Setup the CR4 AND and OR masks used in the switcher */
119 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
120 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
121 {
122 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
123 /* No FXSAVE implies no SSE */
124 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
125 pVM->cpum.s.CR4.OrMask = 0;
126 }
127 else
128 {
129 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
130 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
131 }
132
133 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
134 {
135 Log(("The CPU doesn't support MMX!\n"));
136 return VERR_UNSUPPORTED_CPU;
137 }
138 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
139 {
140 Log(("The CPU doesn't support TSC!\n"));
141 return VERR_UNSUPPORTED_CPU;
142 }
143 /* Bogus on AMD? */
144 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
145 {
146 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
147 }
148
149 /*
150 * Setup hypervisor startup values.
151 */
152
153 /*
154 * Register saved state data item.
155 */
156 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
157 NULL, cpumR3Save, NULL,
158 NULL, cpumR3Load, NULL);
159 if (VBOX_FAILURE(rc))
160 return rc;
161
162 /*
163 * Register info handlers.
164 */
165 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
166 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
167 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
168 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
169 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
170
171 /*
172 * Initialize the Guest CPU state.
173 */
174 rc = cpumR3CpuIdInit(pVM);
175 if (VBOX_FAILURE(rc))
176 return rc;
177 CPUMR3Reset(pVM);
178 return VINF_SUCCESS;
179}
180
181
182/**
183 * Initializes the emulated CPU's cpuid information.
184 *
185 * @returns VBox status code.
186 * @param pVM The VM to operate on.
187 */
188static int cpumR3CpuIdInit(PVM pVM)
189{
190 PCPUM pCPUM = &pVM->cpum.s;
191 uint32_t i;
192
193 /*
194 * Get the host CPUIDs.
195 */
196 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
197 ASMCpuId_Idx_ECX(i, 0,
198 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
199 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
200 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
201 ASMCpuId(0x80000000 + i,
202 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
203 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
204 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
205 ASMCpuId(0xc0000000 + i,
206 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
207 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
208
209
210 /*
211 * Only report features we can support.
212 */
213 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
214 | X86_CPUID_FEATURE_EDX_VME
215 | X86_CPUID_FEATURE_EDX_DE
216 | X86_CPUID_FEATURE_EDX_PSE
217 | X86_CPUID_FEATURE_EDX_TSC
218 | X86_CPUID_FEATURE_EDX_MSR
219 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
220 | X86_CPUID_FEATURE_EDX_MCE
221 | X86_CPUID_FEATURE_EDX_CX8
222 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
223 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
224 //| X86_CPUID_FEATURE_EDX_SEP
225 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
226 | X86_CPUID_FEATURE_EDX_PGE
227 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
228 | X86_CPUID_FEATURE_EDX_CMOV
229 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
230 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
231 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
232 | X86_CPUID_FEATURE_EDX_CLFSH
233 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
234 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
235 | X86_CPUID_FEATURE_EDX_MMX
236 | X86_CPUID_FEATURE_EDX_FXSR
237 | X86_CPUID_FEATURE_EDX_SSE
238 | X86_CPUID_FEATURE_EDX_SSE2
239 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
240 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
241 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
242 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
243 | 0;
244 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
245 | X86_CPUID_FEATURE_ECX_MONITOR
246 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
247 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
248 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
249 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
250 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
251 | 0;
252
253 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
254 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
255 | X86_CPUID_AMD_FEATURE_EDX_VME
256 | X86_CPUID_AMD_FEATURE_EDX_DE
257 | X86_CPUID_AMD_FEATURE_EDX_PSE
258 | X86_CPUID_AMD_FEATURE_EDX_TSC
259 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
260 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
261 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
262 | X86_CPUID_AMD_FEATURE_EDX_CX8
263 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
264 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
265 //| X86_CPUID_AMD_FEATURE_EDX_SEP
266 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
267 | X86_CPUID_AMD_FEATURE_EDX_PGE
268 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
269 | X86_CPUID_AMD_FEATURE_EDX_CMOV
270 | X86_CPUID_AMD_FEATURE_EDX_PAT
271 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
272 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
273 | X86_CPUID_AMD_FEATURE_EDX_MMX
274 | X86_CPUID_AMD_FEATURE_EDX_FXSR
275 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
276 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
277 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
278 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
279 | 0;
280 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
281 | 0;
282
283 /*
284 * Hide HTT, multicode, SMP, whatever.
285 * (APIC-ID := 0 and #LogCpus := 0)
286 */
287 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
288
289 /*
290 * Determin the default.
291 *
292 * Intel returns values of the highest standard function, while AMD
293 * returns zeros. VIA on the other hand seems to returning nothing or
294 * perhaps some random garbage, we don't try duplicate this behavior.
295 */
296 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
297 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
298 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
299
300 /*
301 * Limit it the number of entries and fill the remaining with the defaults.
302 *
303 * The limits are masking off stuff about power saving and similar, this
304 * is perhaps a bit crudely done as there is probably some relatively harmless
305 * info too in these leaves (like words about having a constant TSC).
306 */
307 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
308 pCPUM->aGuestCpuIdStd[0].eax = 2;
309 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
310 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
311
312 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
313 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
314 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
315 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
316 : 0;
317 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
318 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
319
320 /*
321 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
322 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
323 * We don't support more than 1 processor.
324 */
325 pCPUM->aGuestCpuIdStd[4].eax = 0;
326
327 /*
328 * Centaur stuff (VIA).
329 *
330 * The important part here (we think) is to make sure the 0xc0000000
331 * function returns 0xc0000001. As for the features, we don't currently
332 * let on about any of those... 0xc0000002 seems to be some
333 * temperature/hz/++ stuff, include it as well (static).
334 */
335 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
336 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
337 {
338 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
339 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
340 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
341 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
342 i++)
343 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
344 }
345 else
346 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
347 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
348
349
350 /*
351 * Load CPUID overrides from configuration.
352 */
353 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
354 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
355 for (i=0;; )
356 {
357 while (cElements-- > 0)
358 {
359 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
360 if (pNode)
361 {
362 uint32_t u32;
363 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
364 if (VBOX_SUCCESS(rc))
365 pCpuId->eax = u32;
366 else
367 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
368
369 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
370 if (VBOX_SUCCESS(rc))
371 pCpuId->ebx = u32;
372 else
373 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
374
375 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
376 if (VBOX_SUCCESS(rc))
377 pCpuId->ecx = u32;
378 else
379 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
380
381 rc = CFGMR3QueryU32(pNode, "edx", &u32);
382 if (VBOX_SUCCESS(rc))
383 pCpuId->edx = u32;
384 else
385 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
386 }
387 pCpuId++;
388 i++;
389 }
390
391 /* next */
392 if ((i & UINT32_C(0xc0000000)) == 0)
393 {
394 pCpuId = &pCPUM->aGuestCpuIdExt[0];
395 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
396 i = UINT32_C(0x80000000);
397 }
398 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
399 {
400 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
401 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
402 i = UINT32_C(0xc0000000);
403 }
404 else
405 break;
406 }
407
408 /* Check if PAE was explicitely enabled by the user. */
409 bool fEnable = false;
410 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
411 if (VBOX_SUCCESS(rc) && fEnable)
412 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
413
414 /*
415 * Log the cpuid and we're good.
416 */
417 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
418 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
419 LogRel(("************************* CPUID dump ************************\n"));
420 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
421 LogRel(("\n"));
422 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
423 LogRel(("******************** End of CPUID dump **********************\n"));
424 return VINF_SUCCESS;
425}
426
427
428
429
430/**
431 * Applies relocations to data and code managed by this
432 * component. This function will be called at init and
433 * whenever the VMM need to relocate it self inside the GC.
434 *
435 * The CPUM will update the addresses used by the switcher.
436 *
437 * @param pVM The VM.
438 */
439CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
440{
441 LogFlow(("CPUMR3Relocate\n"));
442 /*
443 * Switcher pointers.
444 */
445 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
446 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
447 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
448}
449
450
451/**
452 * Queries the pointer to the internal CPUMCTX structure
453 *
454 * @returns VBox status code.
455 * @param pVM Handle to the virtual machine.
456 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
457 */
458CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
459{
460 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
461 /*
462 * Store the address. (Later we might check how's calling, thus the RC.)
463 */
464 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
465 return VINF_SUCCESS;
466}
467
468
469/**
470 * Terminates the CPUM.
471 *
472 * Termination means cleaning up and freeing all resources,
473 * the VM it self is at this point powered off or suspended.
474 *
475 * @returns VBox status code.
476 * @param pVM The VM to operate on.
477 */
478CPUMR3DECL(int) CPUMR3Term(PVM pVM)
479{
480 /** @todo */
481 return 0;
482}
483
484
485/**
486 * Resets the CPU.
487 *
488 * @returns VINF_SUCCESS.
489 * @param pVM The VM handle.
490 */
491CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
492{
493 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
494
495 /*
496 * Initialize everything to ZERO first.
497 */
498 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
499 memset(pCtx, 0, sizeof(*pCtx));
500 pVM->cpum.s.fUseFlags = fUseFlags;
501
502 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
503 pCtx->eip = 0x0000fff0;
504 pCtx->edx = 0x00000600; /* P6 processor */
505 pCtx->eflags.Bits.u1Reserved0 = 1;
506
507 pCtx->cs = 0xf000;
508 pCtx->csHid.u32Base = 0xffff0000;
509 pCtx->csHid.u32Limit = 0x0000ffff;
510 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
511 pCtx->csHid.Attr.n.u1Present = 1;
512 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
513
514 pCtx->dsHid.u32Limit = 0x0000ffff;
515 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
516 pCtx->dsHid.Attr.n.u1Present = 1;
517 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
518
519 pCtx->esHid.u32Limit = 0x0000ffff;
520 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
521 pCtx->esHid.Attr.n.u1Present = 1;
522 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
523
524 pCtx->fsHid.u32Limit = 0x0000ffff;
525 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
526 pCtx->fsHid.Attr.n.u1Present = 1;
527 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
528
529 pCtx->gsHid.u32Limit = 0x0000ffff;
530 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
531 pCtx->gsHid.Attr.n.u1Present = 1;
532 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
533
534 pCtx->ssHid.u32Limit = 0x0000ffff;
535 pCtx->ssHid.Attr.n.u1Present = 1;
536 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
537 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
538
539 pCtx->idtr.cbIdt = 0xffff;
540 pCtx->gdtr.cbGdt = 0xffff;
541
542 pCtx->ldtrHid.u32Limit = 0xffff;
543 pCtx->ldtrHid.Attr.n.u1Present = 1;
544 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
545
546 pCtx->trHid.u32Limit = 0xffff;
547 pCtx->trHid.Attr.n.u1Present = 1;
548 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
549
550 pCtx->dr6 = 0xFFFF0FF0;
551 pCtx->dr7 = 0x400;
552
553 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
554 pCtx->fpu.FCW = 0x37f;
555
556 /* Init PAT MSR */
557 pCtx->msrPAT = 0x0007040600070406ULL; /* @todo correct? */
558}
559
560
561
562/**
563 * Execute state save operation.
564 *
565 * @returns VBox status code.
566 * @param pVM VM Handle.
567 * @param pSSM SSM operation handle.
568 */
569static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
570{
571 /*
572 * Save.
573 */
574 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
575 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
576 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
577 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
578
579 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
580 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
581
582 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
583 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
584
585 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
586 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
587
588 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
589
590 /* Add the cpuid for checking that the cpu is unchanged. */
591 uint32_t au32CpuId[8] = {0};
592 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
593 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
594 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
595}
596
597
598/**
599 * Execute state load operation.
600 *
601 * @returns VBox status code.
602 * @param pVM VM Handle.
603 * @param pSSM SSM operation handle.
604 * @param u32Version Data layout version.
605 */
606static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
607{
608 /*
609 * Validate version.
610 */
611 if (u32Version != CPUM_SAVED_STATE_VERSION)
612 {
613 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
614 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
615 }
616
617 /*
618 * Restore.
619 */
620 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
621 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
622 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
623 pVM->cpum.s.Hyper.cr3 = uCR3;
624 pVM->cpum.s.Hyper.esp = uESP;
625 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
626 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
627 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
628
629 uint32_t cElements;
630 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
631 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
632 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
633 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
634
635 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
636 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
637 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
638 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
639
640 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
641 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
642 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
643 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
644
645 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
646
647 /*
648 * Check that the basic cpuid id information is unchanged.
649 */
650 uint32_t au32CpuId[8] = {0};
651 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
652 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
653 uint32_t au32CpuIdSaved[8];
654 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
655 if (VBOX_SUCCESS(rc))
656 {
657 /* Ignore APIC ID (AMD specs). */
658 au32CpuId[5] &= ~0xff000000;
659 au32CpuIdSaved[5] &= ~0xff000000;
660 /* Ignore the number of Logical CPUs (AMD specs). */
661 au32CpuId[5] &= ~0x00ff0000;
662 au32CpuIdSaved[5] &= ~0x00ff0000;
663
664 /* do the compare */
665 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
666 {
667 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
668 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
669 "Saved=%.*Vhxs\n"
670 "Real =%.*Vhxs\n",
671 sizeof(au32CpuIdSaved), au32CpuIdSaved,
672 sizeof(au32CpuId), au32CpuId));
673 else
674 {
675 LogRel(("cpumR3Load: CpuId mismatch!\n"
676 "Saved=%.*Vhxs\n"
677 "Real =%.*Vhxs\n",
678 sizeof(au32CpuIdSaved), au32CpuIdSaved,
679 sizeof(au32CpuId), au32CpuId));
680 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
681 }
682 }
683 }
684
685 return rc;
686}
687
688
689/**
690 * Formats the EFLAGS value into mnemonics.
691 *
692 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
693 * @param efl The EFLAGS value.
694 */
695static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
696{
697 /*
698 * Format the flags.
699 */
700 static struct
701 {
702 const char *pszSet; const char *pszClear; uint32_t fFlag;
703 } s_aFlags[] =
704 {
705 { "vip",NULL, X86_EFL_VIP },
706 { "vif",NULL, X86_EFL_VIF },
707 { "ac", NULL, X86_EFL_AC },
708 { "vm", NULL, X86_EFL_VM },
709 { "rf", NULL, X86_EFL_RF },
710 { "nt", NULL, X86_EFL_NT },
711 { "ov", "nv", X86_EFL_OF },
712 { "dn", "up", X86_EFL_DF },
713 { "ei", "di", X86_EFL_IF },
714 { "tf", NULL, X86_EFL_TF },
715 { "nt", "pl", X86_EFL_SF },
716 { "nz", "zr", X86_EFL_ZF },
717 { "ac", "na", X86_EFL_AF },
718 { "po", "pe", X86_EFL_PF },
719 { "cy", "nc", X86_EFL_CF },
720 };
721 char *psz = pszEFlags;
722 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
723 {
724 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
725 if (pszAdd)
726 {
727 strcpy(psz, pszAdd);
728 psz += strlen(pszAdd);
729 *psz++ = ' ';
730 }
731 }
732 psz[-1] = '\0';
733}
734
735
736/**
737 * Formats a full register dump.
738 *
739 * @param pCtx The context to format.
740 * @param pCtxCore The context core to format.
741 * @param pHlp Output functions.
742 * @param enmType The dump type.
743 * @param pszPrefix Register name prefix.
744 */
745static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
746{
747 /*
748 * Format the EFLAGS.
749 */
750 uint32_t efl = pCtxCore->eflags.u32;
751 char szEFlags[80];
752 cpumR3InfoFormatFlags(&szEFlags[0], efl);
753
754 /*
755 * Format the registers.
756 */
757 switch (enmType)
758 {
759 case CPUMDUMPTYPE_TERSE:
760 pHlp->pfnPrintf(pHlp,
761 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
762 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
763 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
764 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
765 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
766 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
767 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
768 break;
769
770 case CPUMDUMPTYPE_DEFAULT:
771 pHlp->pfnPrintf(pHlp,
772 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
773 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
774 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
775 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08x:%04x %sldtr=%04x\n"
776 ,
777 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
778 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
779 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
780 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
781 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
782 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
783 break;
784
785 case CPUMDUMPTYPE_VERBOSE:
786 pHlp->pfnPrintf(pHlp,
787 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
788 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
789 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
790 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
791 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
792 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
793 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
794 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
795 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
796 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
797 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
798 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
799 ,
800 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
801 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
802 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
803 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
804 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
805 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
806 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
807 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
808 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
809 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
810 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
811 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
812
813 pHlp->pfnPrintf(pHlp,
814 "FPU:\n"
815 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
816 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
817 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
818 ,
819 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
820 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
821 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
822 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
823
824
825 break;
826 }
827}
828
829
830/**
831 * Display all cpu states and any other cpum info.
832 *
833 * @param pVM VM Handle.
834 * @param pHlp The info helper functions.
835 * @param pszArgs Arguments, ignored.
836 */
837static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
838{
839 cpumR3InfoGuest(pVM, pHlp, pszArgs);
840 cpumR3InfoHyper(pVM, pHlp, pszArgs);
841 cpumR3InfoHost(pVM, pHlp, pszArgs);
842}
843
844
845/**
846 * Parses the info argument.
847 *
848 * The argument starts with 'verbose', 'terse' or 'default' and then
849 * continues with the comment string.
850 *
851 * @param pszArgs The pointer to the argument string.
852 * @param penmType Where to store the dump type request.
853 * @param ppszComment Where to store the pointer to the comment string.
854 */
855static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
856{
857 if (!pszArgs)
858 {
859 *penmType = CPUMDUMPTYPE_DEFAULT;
860 *ppszComment = "";
861 }
862 else
863 {
864 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
865 {
866 pszArgs += 5;
867 *penmType = CPUMDUMPTYPE_VERBOSE;
868 }
869 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
870 {
871 pszArgs += 5;
872 *penmType = CPUMDUMPTYPE_TERSE;
873 }
874 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
875 {
876 pszArgs += 7;
877 *penmType = CPUMDUMPTYPE_DEFAULT;
878 }
879 else
880 *penmType = CPUMDUMPTYPE_DEFAULT;
881 *ppszComment = RTStrStripL(pszArgs);
882 }
883}
884
885
886/**
887 * Display the guest cpu state.
888 *
889 * @param pVM VM Handle.
890 * @param pHlp The info helper functions.
891 * @param pszArgs Arguments, ignored.
892 */
893static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
894{
895 CPUMDUMPTYPE enmType;
896 const char *pszComment;
897 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
898 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
899 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
900}
901
902
903/**
904 * Display the hypervisor cpu state.
905 *
906 * @param pVM VM Handle.
907 * @param pHlp The info helper functions.
908 * @param pszArgs Arguments, ignored.
909 */
910static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
911{
912 CPUMDUMPTYPE enmType;
913 const char *pszComment;
914 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
915 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
916 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
917 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
918}
919
920
921/**
922 * Display the host cpu state.
923 *
924 * @param pVM VM Handle.
925 * @param pHlp The info helper functions.
926 * @param pszArgs Arguments, ignored.
927 */
928static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
929{
930 CPUMDUMPTYPE enmType;
931 const char *pszComment;
932 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
933 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
934
935 /*
936 * Format the EFLAGS.
937 */
938 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
939#if HC_ARCH_BITS == 32
940 uint32_t efl = pCtx->eflags.u32;
941#else
942 uint64_t efl = pCtx->rflags;
943#endif
944 char szEFlags[80];
945 cpumR3InfoFormatFlags(&szEFlags[0], efl);
946
947 /*
948 * Format the registers.
949 */
950#if HC_ARCH_BITS == 32
951# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
952 if (!(pCtx->efer & MSR_K6_EFER_LMA))
953# endif
954 {
955 pHlp->pfnPrintf(pHlp,
956 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
957 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
958 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
959 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
960 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
961 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
962 ,
963 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
964 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
965 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
966 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
967 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
968 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
969 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
970 }
971# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
972 else
973# endif
974#endif
975#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
976 {
977 pHlp->pfnPrintf(pHlp,
978 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
979 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
980 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
981 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
982 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
983 "r14=%016RX64 r15=%016RX64\n"
984 "iopl=%d %31s\n"
985 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
986 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
987 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
988 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
989 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
990 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
991 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
992 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
993 ,
994 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
995 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
996 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
997 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
998 pCtx->r11, pCtx->r12, pCtx->r13,
999 pCtx->r14, pCtx->r15,
1000 X86_EFL_GET_IOPL(efl), szEFlags,
1001 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1002 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1003 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
1004 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1005 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1006 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1007 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1008 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1009 }
1010#endif
1011}
1012
1013/**
1014 * Get L1 cache / TLS associativity.
1015 */
1016static const char *getCacheAss(unsigned u, char *pszBuf)
1017{
1018 if (u == 0)
1019 return "res0 ";
1020 if (u == 1)
1021 return "direct";
1022 if (u >= 256)
1023 return "???";
1024
1025 RTStrPrintf(pszBuf, 16, "%d way", u);
1026 return pszBuf;
1027}
1028
1029
1030/**
1031 * Get L2 cache soociativity.
1032 */
1033const char *getL2CacheAss(unsigned u)
1034{
1035 switch (u)
1036 {
1037 case 0: return "off ";
1038 case 1: return "direct";
1039 case 2: return "2 way ";
1040 case 3: return "res3 ";
1041 case 4: return "4 way ";
1042 case 5: return "res5 ";
1043 case 6: return "8 way ";
1044 case 7: return "res7 ";
1045 case 8: return "16 way";
1046 case 9: return "res9 ";
1047 case 10: return "res10 ";
1048 case 11: return "res11 ";
1049 case 12: return "res12 ";
1050 case 13: return "res13 ";
1051 case 14: return "res14 ";
1052 case 15: return "fully ";
1053 default:
1054 return "????";
1055 }
1056}
1057
1058
1059/**
1060 * Display the guest CpuId leaves.
1061 *
1062 * @param pVM VM Handle.
1063 * @param pHlp The info helper functions.
1064 * @param pszArgs "terse", "default" or "verbose".
1065 */
1066static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1067{
1068 /*
1069 * Parse the argument.
1070 */
1071 unsigned iVerbosity = 1;
1072 if (pszArgs)
1073 {
1074 pszArgs = RTStrStripL(pszArgs);
1075 if (!strcmp(pszArgs, "terse"))
1076 iVerbosity--;
1077 else if (!strcmp(pszArgs, "verbose"))
1078 iVerbosity++;
1079 }
1080
1081 /*
1082 * Start cracking.
1083 */
1084 CPUMCPUID Host;
1085 CPUMCPUID Guest;
1086 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1087
1088 pHlp->pfnPrintf(pHlp,
1089 " RAW Standard CPUIDs\n"
1090 " Function eax ebx ecx edx\n");
1091 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1092 {
1093 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1094 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1095
1096 pHlp->pfnPrintf(pHlp,
1097 "Gst: %08x %08x %08x %08x %08x%s\n"
1098 "Hst: %08x %08x %08x %08x\n",
1099 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1100 i <= cStdMax ? "" : "*",
1101 Host.eax, Host.ebx, Host.ecx, Host.edx);
1102 }
1103
1104 /*
1105 * If verbose, decode it.
1106 */
1107 if (iVerbosity)
1108 {
1109 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1110 pHlp->pfnPrintf(pHlp,
1111 "Name: %.04s%.04s%.04s\n"
1112 "Supports: 0-%x\n",
1113 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1114 }
1115
1116 /*
1117 * Get Features.
1118 */
1119 if (cStdMax >= 1 && iVerbosity)
1120 {
1121 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1122 uint32_t uEAX = Guest.eax;
1123
1124 pHlp->pfnPrintf(pHlp,
1125 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1126 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1127 "Stepping: %d\n"
1128 "APIC ID: %#04x\n"
1129 "Logical CPUs: %d\n"
1130 "CLFLUSH Size: %d\n"
1131 "Brand ID: %#04x\n",
1132 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1133 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1134 (uEAX >> 0) & 0xf,
1135 (Guest.ebx >> 24) & 0xff,
1136 (Guest.ebx >> 16) & 0xff,
1137 (Guest.ebx >> 8) & 0xff,
1138 (Guest.ebx >> 0) & 0xff);
1139 if (iVerbosity == 1)
1140 {
1141 uint32_t uEDX = Guest.edx;
1142 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1143 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1144 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1145 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1146 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1147 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1148 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1149 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1150 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1151 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1152 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1153 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1154 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1155 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1156 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1157 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1158 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1159 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1160 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1161 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1162 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1163 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1164 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1165 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1166 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1167 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1168 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1169 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1170 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1171 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1172 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1173 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1174 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1175 pHlp->pfnPrintf(pHlp, "\n");
1176
1177 uint32_t uECX = Guest.ecx;
1178 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1179 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1180 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1181 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1182 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1183 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1184 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1185 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1186 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1187 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1188 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1189 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1190 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1191 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1192 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1193 for (unsigned iBit = 14; iBit < 32; iBit++)
1194 if (uECX & RT_BIT(iBit))
1195 pHlp->pfnPrintf(pHlp, " %d", iBit);
1196 pHlp->pfnPrintf(pHlp, "\n");
1197 }
1198 else
1199 {
1200 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1201
1202 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1203 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1204 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1205 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1206
1207 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1208 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1209 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1210 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1211 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1212 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1213 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1214 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1215 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1216 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1217 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1218 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1219 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1220 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1221 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1222 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1223 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1224 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1225 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1226 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1227 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1228 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1229 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1230 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1231 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1232 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1233 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1234 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1235 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1236 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1237 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1238 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1239 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1240
1241 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1242 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1243 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1244 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1245 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1246 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1247 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1248 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1249 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1250 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1251 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1252 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1253 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1254 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1255 }
1256 }
1257 if (cStdMax >= 2 && iVerbosity)
1258 {
1259 /** @todo */
1260 }
1261
1262 /*
1263 * Extended.
1264 * Implemented after AMD specs.
1265 */
1266 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1267
1268 pHlp->pfnPrintf(pHlp,
1269 "\n"
1270 " RAW Extended CPUIDs\n"
1271 " Function eax ebx ecx edx\n");
1272 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1273 {
1274 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1275 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1276
1277 pHlp->pfnPrintf(pHlp,
1278 "Gst: %08x %08x %08x %08x %08x%s\n"
1279 "Hst: %08x %08x %08x %08x\n",
1280 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1281 i <= cExtMax ? "" : "*",
1282 Host.eax, Host.ebx, Host.ecx, Host.edx);
1283 }
1284
1285 /*
1286 * Understandable output
1287 */
1288 if (iVerbosity && cExtMax >= 0)
1289 {
1290 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1291 pHlp->pfnPrintf(pHlp,
1292 "Ext Name: %.4s%.4s%.4s\n"
1293 "Ext Supports: 0x80000000-%#010x\n",
1294 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1295 }
1296
1297 if (iVerbosity && cExtMax >= 1)
1298 {
1299 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1300 uint32_t uEAX = Guest.eax;
1301 pHlp->pfnPrintf(pHlp,
1302 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1303 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1304 "Stepping: %d\n"
1305 "Brand ID: %#05x\n",
1306 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1307 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1308 (uEAX >> 0) & 0xf,
1309 Guest.ebx & 0xfff);
1310
1311 if (iVerbosity == 1)
1312 {
1313 uint32_t uEDX = Guest.edx;
1314 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1315 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1316 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1317 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1318 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1319 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1320 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1321 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1322 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1323 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1324 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1325 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1326 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1327 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1328 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1329 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1330 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1331 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1332 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1333 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1334 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1335 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1336 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1337 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1338 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1339 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1340 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1341 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1342 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1343 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1344 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1345 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1346 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1347 pHlp->pfnPrintf(pHlp, "\n");
1348
1349 uint32_t uECX = Guest.ecx;
1350 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1351 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1352 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1353 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1354 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1355 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1356 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1357 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1358 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1359 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1360 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1361 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1362 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1363 for (unsigned iBit = 5; iBit < 32; iBit++)
1364 if (uECX & RT_BIT(iBit))
1365 pHlp->pfnPrintf(pHlp, " %d", iBit);
1366 pHlp->pfnPrintf(pHlp, "\n");
1367 }
1368 else
1369 {
1370 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1371
1372 uint32_t uEdxGst = Guest.edx;
1373 uint32_t uEdxHst = Host.edx;
1374 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1375 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1376 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1377 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1378 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1379 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1380 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1381 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1382 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1383 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1384 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1385 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1386 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1387 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1388 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1389 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1390 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1391 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1392 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1393 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1394 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1395 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1396 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1397 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1398 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1399 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1400 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1401 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1402 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1403 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1404 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1405 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1406 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1407
1408 uint32_t uEcxGst = Guest.ecx;
1409 uint32_t uEcxHst = Host.ecx;
1410 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1411 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1412 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1413 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1414 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1415 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1416 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1417 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1418 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1419 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1420 pHlp->pfnPrintf(pHlp, "11:10 - Reserved = %#x (%#x)\n", (uEcxGst >> 10) & 3, (uEcxHst >> 10) & 3);
1421 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1422 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1423 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1424 }
1425 }
1426
1427 if (iVerbosity && cExtMax >= 2)
1428 {
1429 char szString[4*4*3+1] = {0};
1430 uint32_t *pu32 = (uint32_t *)szString;
1431 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1432 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1433 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1434 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1435 if (cExtMax >= 3)
1436 {
1437 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1438 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1439 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1440 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1441 }
1442 if (cExtMax >= 4)
1443 {
1444 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1445 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1446 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1447 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1448 }
1449 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1450 }
1451
1452 if (iVerbosity && cExtMax >= 5)
1453 {
1454 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1455 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1456 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1457 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1458 char sz1[32];
1459 char sz2[32];
1460
1461 pHlp->pfnPrintf(pHlp,
1462 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1463 "TLB 2/4M Data: %s %3d entries\n",
1464 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1465 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1466 pHlp->pfnPrintf(pHlp,
1467 "TLB 4K Instr/Uni: %s %3d entries\n"
1468 "TLB 4K Data: %s %3d entries\n",
1469 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1470 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1471 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1472 "L1 Instr Cache Lines Per Tag: %d\n"
1473 "L1 Instr Cache Associativity: %s\n"
1474 "L1 Instr Cache Size: %d KB\n",
1475 (uEDX >> 0) & 0xff,
1476 (uEDX >> 8) & 0xff,
1477 getCacheAss((uEDX >> 16) & 0xff, sz1),
1478 (uEDX >> 24) & 0xff);
1479 pHlp->pfnPrintf(pHlp,
1480 "L1 Data Cache Line Size: %d bytes\n"
1481 "L1 Data Cache Lines Per Tag: %d\n"
1482 "L1 Data Cache Associativity: %s\n"
1483 "L1 Data Cache Size: %d KB\n",
1484 (uECX >> 0) & 0xff,
1485 (uECX >> 8) & 0xff,
1486 getCacheAss((uECX >> 16) & 0xff, sz1),
1487 (uECX >> 24) & 0xff);
1488 }
1489
1490 if (iVerbosity && cExtMax >= 6)
1491 {
1492 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1493 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1494 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1495
1496 pHlp->pfnPrintf(pHlp,
1497 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1498 "L2 TLB 2/4M Data: %s %4d entries\n",
1499 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1500 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1501 pHlp->pfnPrintf(pHlp,
1502 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1503 "L2 TLB 4K Data: %s %4d entries\n",
1504 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1505 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1506 pHlp->pfnPrintf(pHlp,
1507 "L2 Cache Line Size: %d bytes\n"
1508 "L2 Cache Lines Per Tag: %d\n"
1509 "L2 Cache Associativity: %s\n"
1510 "L2 Cache Size: %d KB\n",
1511 (uEDX >> 0) & 0xff,
1512 (uEDX >> 8) & 0xf,
1513 getL2CacheAss((uEDX >> 12) & 0xf),
1514 (uEDX >> 16) & 0xffff);
1515 }
1516
1517 if (iVerbosity && cExtMax >= 7)
1518 {
1519 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1520
1521 pHlp->pfnPrintf(pHlp, "APM Features: ");
1522 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1523 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1524 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1525 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1526 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1527 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1528 for (unsigned iBit = 6; iBit < 32; iBit++)
1529 if (uEDX & RT_BIT(iBit))
1530 pHlp->pfnPrintf(pHlp, " %d", iBit);
1531 pHlp->pfnPrintf(pHlp, "\n");
1532 }
1533
1534 if (iVerbosity && cExtMax >= 8)
1535 {
1536 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1537 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1538
1539 pHlp->pfnPrintf(pHlp,
1540 "Physical Address Width: %d bits\n"
1541 "Virtual Address Width: %d bits\n",
1542 (uEAX >> 0) & 0xff,
1543 (uEAX >> 8) & 0xff);
1544 pHlp->pfnPrintf(pHlp,
1545 "Physical Core Count: %d\n",
1546 (uECX >> 0) & 0xff);
1547 }
1548
1549
1550 /*
1551 * Centaur.
1552 */
1553 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1554
1555 pHlp->pfnPrintf(pHlp,
1556 "\n"
1557 " RAW Centaur CPUIDs\n"
1558 " Function eax ebx ecx edx\n");
1559 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1560 {
1561 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1562 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1563
1564 pHlp->pfnPrintf(pHlp,
1565 "Gst: %08x %08x %08x %08x %08x%s\n"
1566 "Hst: %08x %08x %08x %08x\n",
1567 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1568 i <= cCentaurMax ? "" : "*",
1569 Host.eax, Host.ebx, Host.ecx, Host.edx);
1570 }
1571
1572 /*
1573 * Understandable output
1574 */
1575 if (iVerbosity && cCentaurMax >= 0)
1576 {
1577 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1578 pHlp->pfnPrintf(pHlp,
1579 "Centaur Supports: 0xc0000000-%#010x\n",
1580 Guest.eax);
1581 }
1582
1583 if (iVerbosity && cCentaurMax >= 1)
1584 {
1585 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1586 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1587 uint32_t uEdxHst = Host.edx;
1588
1589 if (iVerbosity == 1)
1590 {
1591 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1592 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1593 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1594 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1595 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1596 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1597 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1598 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1599 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1600 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1601 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1602 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1603 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1604 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1605 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1606 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1607 for (unsigned iBit = 14; iBit < 32; iBit++)
1608 if (uEdxGst & RT_BIT(iBit))
1609 pHlp->pfnPrintf(pHlp, " %d", iBit);
1610 pHlp->pfnPrintf(pHlp, "\n");
1611 }
1612 else
1613 {
1614 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1615 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1616 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1617 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1618 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1619 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1620 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1621 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1622 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1623 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1624 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1625 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1626 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1627 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1628 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1629 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1630 for (unsigned iBit = 14; iBit < 32; iBit++)
1631 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1632 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1633 pHlp->pfnPrintf(pHlp, "\n");
1634 }
1635 }
1636}
1637
1638
1639/**
1640 * Structure used when disassembling and instructions in DBGF.
1641 * This is used so the reader function can get the stuff it needs.
1642 */
1643typedef struct CPUMDISASSTATE
1644{
1645 /** Pointer to the CPU structure. */
1646 PDISCPUSTATE pCpu;
1647 /** The VM handle. */
1648 PVM pVM;
1649 /** Pointer to the first byte in the segemnt. */
1650 RTGCUINTPTR GCPtrSegBase;
1651 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1652 RTGCUINTPTR GCPtrSegEnd;
1653 /** The size of the segment minus 1. */
1654 RTGCUINTPTR cbSegLimit;
1655 /** Pointer to the current page - HC Ptr. */
1656 void const *pvPageHC;
1657 /** Pointer to the current page - GC Ptr. */
1658 RTGCPTR pvPageGC;
1659 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1660 PGMPAGEMAPLOCK PageMapLock;
1661 /** Whether the PageMapLock is valid or not. */
1662 bool fLocked;
1663} CPUMDISASSTATE, *PCPUMDISASSTATE;
1664
1665
1666/**
1667 * Instruction reader.
1668 *
1669 * @returns VBox status code.
1670 * @param PtrSrc Address to read from.
1671 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1672 * @param pu8Dst Where to store the bytes.
1673 * @param cbRead Number of bytes to read.
1674 * @param uDisCpu Pointer to the disassembler cpu state.
1675 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1676 */
1677static DECLCALLBACK(int) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, void *uDisCpu)
1678{
1679 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1680 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1681 Assert(cbRead > 0);
1682 for (;;)
1683 {
1684 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1685
1686 /* Need to update the page translation? */
1687 if ( !pState->pvPageHC
1688 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1689 {
1690 int rc = VINF_SUCCESS;
1691
1692 /* translate the address */
1693 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1694 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1695 {
1696 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1697 if (!pState->pvPageHC)
1698 rc = VERR_INVALID_POINTER;
1699 }
1700 else
1701 {
1702 /* Release mapping lock previously acquired. */
1703 if (pState->fLocked)
1704 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1705 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1706 pState->fLocked = RT_SUCCESS_NP(rc);
1707 }
1708 if (VBOX_FAILURE(rc))
1709 {
1710 pState->pvPageHC = NULL;
1711 return rc;
1712 }
1713 }
1714
1715 /* check the segemnt limit */
1716 if (PtrSrc > pState->cbSegLimit)
1717 return VERR_OUT_OF_SELECTOR_BOUNDS;
1718
1719 /* calc how much we can read */
1720 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1721 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1722 if (cb > cbSeg && !cbSeg)
1723 cb = cbSeg;
1724 if (cb > cbRead)
1725 cb = cbRead;
1726
1727 /* read and advance */
1728 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1729 cbRead -= cb;
1730 if (!cbRead)
1731 return VINF_SUCCESS;
1732 pu8Dst += cb;
1733 PtrSrc += cb;
1734 }
1735}
1736
1737
1738/**
1739 * Disassemble an instruction and return the information in the provided structure.
1740 *
1741 * @returns VBox status code.
1742 * @param pVM VM Handle
1743 * @param pCtx CPU context
1744 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1745 * @param pCpu Disassembly state
1746 * @param pszPrefix String prefix for logging (debug only)
1747 *
1748 */
1749CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1750{
1751 CPUMDISASSTATE State;
1752 int rc;
1753
1754 State.pCpu = pCpu;
1755 State.pvPageGC = 0;
1756 State.pvPageHC = NULL;
1757 State.pVM = pVM;
1758 State.fLocked = false;
1759
1760 /*
1761 * Get selector information.
1762 */
1763 if ( (pCtx->cr0 & X86_CR0_PE)
1764 && pCtx->eflags.Bits.u1VM == 0)
1765 {
1766 if (CPUMAreHiddenSelRegsValid(pVM))
1767 {
1768 State.GCPtrSegBase = pCtx->csHid.u32Base;
1769 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1770 State.cbSegLimit = pCtx->csHid.u32Limit;
1771 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1772 }
1773 else
1774 {
1775 SELMSELINFO SelInfo;
1776
1777 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1778 if (!VBOX_SUCCESS(rc))
1779 {
1780 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1781 return rc;
1782 }
1783
1784 /*
1785 * Validate the selector.
1786 */
1787 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1788 if (!VBOX_SUCCESS(rc))
1789 {
1790 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1791 return rc;
1792 }
1793 State.GCPtrSegBase = SelInfo.GCPtrBase;
1794 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1795 State.cbSegLimit = SelInfo.cbLimit;
1796 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1797 }
1798 }
1799 else
1800 {
1801 /* real or V86 mode */
1802 pCpu->mode = CPUMODE_16BIT;
1803 State.GCPtrSegBase = pCtx->cs * 16;
1804 State.GCPtrSegEnd = 0xFFFFFFFF;
1805 State.cbSegLimit = 0xFFFFFFFF;
1806 }
1807
1808 /*
1809 * Disassemble the instruction.
1810 */
1811 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1812 pCpu->apvUserData[0] = &State;
1813
1814 uint32_t cbInstr;
1815#ifdef LOG_ENABLED
1816 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
1817 if (VBOX_SUCCESS(rc))
1818 {
1819#else
1820 char szOutput[160];
1821 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
1822 if (VBOX_SUCCESS(rc))
1823 {
1824 /* log it */
1825 if (pszPrefix)
1826 Log(("%s: %s", pszPrefix, szOutput));
1827 else
1828 Log(("%s", szOutput));
1829#endif
1830 rc = VINF_SUCCESS;
1831 }
1832 else
1833 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
1834
1835 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
1836 if (State.fLocked)
1837 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
1838
1839 return rc;
1840}
1841
1842
1843#ifdef DEBUG
1844/**
1845 * Disassemble an instruction and dump it to the log
1846 *
1847 * @returns VBox status code.
1848 * @param pVM VM Handle
1849 * @param pCtx CPU context
1850 * @param pc GC instruction pointer
1851 * @param prefix String prefix for logging
1852 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1853 *
1854 */
1855CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1856{
1857 DISCPUSTATE cpu;
1858
1859 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1860}
1861
1862/**
1863 * Disassemble an instruction and dump it to the log
1864 *
1865 * @returns VBox status code.
1866 * @param pVM VM Handle
1867 * @param pCtx CPU context
1868 * @param pc GC instruction pointer
1869 * @param prefix String prefix for logging
1870 * @param nrInstructions
1871 *
1872 */
1873CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1874{
1875 for(int i=0;i<nrInstructions;i++)
1876 {
1877 DISCPUSTATE cpu;
1878
1879 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1880 pc += cpu.opsize;
1881 }
1882}
1883
1884#endif
1885
1886#ifdef DEBUG
1887/**
1888 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1889 *
1890 * @internal
1891 */
1892CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1893{
1894 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1895}
1896#endif
1897
1898
1899/**
1900 * API for controlling a few of the CPU features found in CR4.
1901 *
1902 * Currently only X86_CR4_TSD is accepted as input.
1903 *
1904 * @returns VBox status code.
1905 *
1906 * @param pVM The VM handle.
1907 * @param fOr The CR4 OR mask.
1908 * @param fAnd The CR4 AND mask.
1909 */
1910CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1911{
1912 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1913 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1914
1915 pVM->cpum.s.CR4.OrMask &= fAnd;
1916 pVM->cpum.s.CR4.OrMask |= fOr;
1917
1918 return VINF_SUCCESS;
1919}
1920
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