VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 400

Last change on this file since 400 was 186, checked in by vboxsync, 18 years ago

Turn off sysenter/sysexit support due to IOPL problems. (#1782)
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File size: 72.7 KB
Line 
1/* $Id: CPUM.cpp 186 2007-01-19 17:04:07Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006 InnoTek Systemberatung GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46#include "x86context.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 3
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107 /* Hidden selector registers are invalid by default. */
108 pVM->cpum.s.fValidHiddenSelRegs = false;
109
110 /*
111 * Check that the CPU supports the minimum features we require.
112 */
113 /** @todo check the contract! */
114 if (!ASMHasCpuId())
115 {
116 Log(("The CPU doesn't support CPUID!\n"));
117 return VERR_UNSUPPORTED_CPU;
118 }
119 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121 /* Setup the CR4 AND and OR masks used in the switcher */
122 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124 {
125 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126 /* No FXSAVE implies no SSE */
127 pVM->cpum.s.CR4.Mask = X86_CR4_PVI | X86_CR4_VME;
128 pVM->cpum.s.CR4.OSFSXR = 0;
129 }
130 else
131 {
132 pVM->cpum.s.CR4.Mask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
133 pVM->cpum.s.CR4.OSFSXR = X86_CR4_OSFSXR;
134 }
135
136 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
137 {
138 Log(("The CPU doesn't support MMX!\n"));
139 return VERR_UNSUPPORTED_CPU;
140 }
141 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
142 {
143 Log(("The CPU doesn't support TSC!\n"));
144 return VERR_UNSUPPORTED_CPU;
145 }
146 /* Bogus on AMD? */
147 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
148 {
149 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
150 }
151
152 /*
153 * Setup hypervisor startup values.
154 */
155
156 /*
157 * Register saved state data item.
158 */
159 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
160 NULL, cpumR3Save, NULL,
161 NULL, cpumR3Load, NULL);
162 if (VBOX_FAILURE(rc))
163 return rc;
164
165 /*
166 * Register info handlers.
167 */
168 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
169 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
170 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
171 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
172 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
173
174 /*
175 * Initialize the Guest CPU state.
176 */
177 rc = cpumR3CpuIdInit(pVM);
178 if (VBOX_FAILURE(rc))
179 return rc;
180 CPUMR3Reset(pVM);
181 return VINF_SUCCESS;
182}
183
184
185/**
186 * Initializes the emulated CPU's cpuid information.
187 *
188 * @returns VBox status code.
189 * @param pVM The VM to operate on.
190 */
191static int cpumR3CpuIdInit(PVM pVM)
192{
193 PCPUM pCPUM = &pVM->cpum.s;
194 uint32_t i;
195
196 /*
197 * Get the host CPUIDs.
198 */
199 for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
200 ASMCpuId(i,
201 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
202 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
203 for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
204 ASMCpuId(0x80000000 + i,
205 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
206 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
207
208 /*
209 * Only report features we can support.
210 */
211 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
212 //| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
213 | X86_CPUID_FEATURE_EDX_DE
214 | X86_CPUID_FEATURE_EDX_PSE
215 | X86_CPUID_FEATURE_EDX_TSC
216 | X86_CPUID_FEATURE_EDX_MSR
217 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
218 | X86_CPUID_FEATURE_EDX_MCE
219 | X86_CPUID_FEATURE_EDX_CX8
220 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
221 | X86_CPUID_FEATURE_EDX_SEP
222 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
223 | X86_CPUID_FEATURE_EDX_PGE
224 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
225 | X86_CPUID_FEATURE_EDX_CMOV
226 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
227 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
228 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
229 //| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
230 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
231 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
232 | X86_CPUID_FEATURE_EDX_MMX
233 | X86_CPUID_FEATURE_EDX_FXSR
234 | X86_CPUID_FEATURE_EDX_SSE
235 | X86_CPUID_FEATURE_EDX_SSE2
236 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
237 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
238 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
239 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
240 | 0;
241 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
242 | X86_CPUID_FEATURE_ECX_MONITOR
243 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
244 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
245 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
246 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
247 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
248 | 0;
249
250#if 1 /* we didn't used to do this, but I guess we should */
251 /* ASSUMES that this is ALLWAYS the AMD define feature set if present. */
252 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
253 //| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
254 | X86_CPUID_AMD_FEATURE_EDX_DE
255 | X86_CPUID_AMD_FEATURE_EDX_PSE
256 | X86_CPUID_AMD_FEATURE_EDX_TSC
257 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
258 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
259 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
260 | X86_CPUID_AMD_FEATURE_EDX_CX8
261 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
262 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
263 //| X86_CPUID_AMD_FEATURE_EDX_SEP
264 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
265 | X86_CPUID_AMD_FEATURE_EDX_PGE
266 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
267 | X86_CPUID_AMD_FEATURE_EDX_CMOV
268 | X86_CPUID_AMD_FEATURE_EDX_PAT
269 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
270 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
271 | X86_CPUID_AMD_FEATURE_EDX_MMX
272 | X86_CPUID_AMD_FEATURE_EDX_FXSR
273 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
274 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
275 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
276 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
277 | 0;
278 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
279 | 0;
280#endif
281
282#if 0 /* this is what we used to do. */
283 /*
284 * Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
285 */
286 pCPUM->aGuestCpuIdStd[1].ebx = 0;
287
288 /*
289 * Set the max standard index to 2.
290 */
291 pCPUM->aGuestCpuIdStd[0].eax = 2;
292 pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
293
294#else /* this is what we probably should do */
295 /*
296 * Hide HTT, multicode, SMP, whatever.
297 * (APIC-ID := 0 and #LogCpus := 0)
298 */
299 pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
300
301 /*
302 * Determin the default value and limit it the number of entries.
303 * Intel returns values of the highest standard function, while AMD returns zeros.
304 */
305 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
306 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
307 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
308
309 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
310 pCPUM->aGuestCpuIdStd[0].eax = 2;
311
312 if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
313 pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
314
315#endif
316
317 /*
318 * Assign defaults to the entries we chopped off.
319 */
320 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
321 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
322 for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
323 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
324
325 /*
326 * Load CPUID overrides from configuration.
327 */
328 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
329 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
330 for (;;)
331 {
332 while (cElements-- < 0)
333 {
334 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
335 if (pNode)
336 {
337 uint32_t u32;
338 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
339 if (VBOX_SUCCESS(rc))
340 pCpuId->eax = u32;
341 else
342 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
343
344 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
345 if (VBOX_SUCCESS(rc))
346 pCpuId->ebx = u32;
347 else
348 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
349
350 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
351 if (VBOX_SUCCESS(rc))
352 pCpuId->ecx = u32;
353 else
354 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
355
356 rc = CFGMR3QueryU32(pNode, "edx", &u32);
357 if (VBOX_SUCCESS(rc))
358 pCpuId->edx = u32;
359 else
360 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
361 }
362 }
363
364 /* next */
365 if (i & 0x80000000)
366 break;
367 pCpuId = &pCPUM->aGuestCpuIdExt[0];
368 cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
369 i = 0x80000000;
370 }
371
372 /*
373 * Log the cpuid and we're good.
374 */
375 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
376 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
377 LogRel(("************************* CPUID dump ************************\n"));
378 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
379 LogRel(("\n"));
380 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
381 LogRel(("******************** End of CPUID dump **********************\n"));
382 return VINF_SUCCESS;
383}
384
385
386
387
388/**
389 * Applies relocations to data and code managed by this
390 * component. This function will be called at init and
391 * whenever the VMM need to relocate it self inside the GC.
392 *
393 * The CPUM will update the addresses used by the switcher.
394 *
395 * @param pVM The VM.
396 */
397CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
398{
399 LogFlow(("CPUMR3Relocate\n"));
400 /*
401 * Switcher pointers.
402 */
403 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
404 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
405}
406
407
408/**
409 * Queries the pointer to the internal CPUMCTX structure
410 *
411 * @returns VBox status code.
412 * @param pVM Handle to the virtual machine.
413 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
414 */
415CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
416{
417 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
418 /*
419 * Store the address. (Later we might check how's calling, thus the RC.)
420 */
421 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
422 return VINF_SUCCESS;
423}
424
425
426/**
427 * Terminates the CPUM.
428 *
429 * Termination means cleaning up and freeing all resources,
430 * the VM it self is at this point powered off or suspended.
431 *
432 * @returns VBox status code.
433 * @param pVM The VM to operate on.
434 */
435CPUMR3DECL(int) CPUMR3Term(PVM pVM)
436{
437 /** @todo */
438 return 0;
439}
440
441
442/**
443 * Resets the CPU.
444 *
445 * @returns VINF_SUCCESS.
446 * @param pVM The VM handle.
447 */
448CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
449{
450 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
451
452 /*
453 * Initialize everything to ZERO first.
454 */
455 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
456 memset(pCtx, 0, sizeof(*pCtx));
457 pVM->cpum.s.fUseFlags = fUseFlags;
458
459 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
460 pCtx->eip = 0x0000fff0;
461 pCtx->edx = 0x00000600; /* P6 processor */
462 pCtx->eflags.Bits.u1Reserved0 = 1;
463
464 pCtx->cs = 0xf000;
465 pCtx->csHid.u32Base = 0xffff0000;
466 pCtx->csHid.u32Limit = 0x0000ffff;
467 pCtx->dsHid.u32Limit = 0x0000ffff;
468 pCtx->esHid.u32Limit = 0x0000ffff;
469 pCtx->fsHid.u32Limit = 0x0000ffff;
470 pCtx->gsHid.u32Limit = 0x0000ffff;
471 pCtx->ssHid.u32Limit = 0x0000ffff;
472 pCtx->idtr.cbIdt = 0xffff;
473 pCtx->gdtr.cbGdt = 0xffff;
474 pCtx->ldtrHid.u32Limit = 0xffff;
475 pCtx->ldtrHid.Attr.u = X86_DESC_P;
476 pCtx->trHid.u32Limit = 0xffff;
477 pCtx->trHid.Attr.u = X86_DESC_P;
478
479 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
480 pCtx->fpu.FCW = 0x37f;
481}
482
483
484
485/**
486 * Execute state save operation.
487 *
488 * @returns VBox status code.
489 * @param pVM VM Handle.
490 * @param pSSM SSM operation handle.
491 */
492static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
493{
494 /*
495 * Save.
496 */
497 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
498 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
499 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
500 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
501
502 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
503 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
504
505 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
506 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
507
508 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
509
510 /* Add the cpuid for checking that the cpu is unchanged. */
511 uint32_t au32CpuId[8] = {0};
512 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
513 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
514 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
515}
516
517
518/**
519 * Execute state load operation.
520 *
521 * @returns VBox status code.
522 * @param pVM VM Handle.
523 * @param pSSM SSM operation handle.
524 * @param u32Version Data layout version.
525 */
526static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
527{
528 /*
529 * Validate version.
530 */
531 if (u32Version != CPUM_SAVED_STATE_VERSION)
532 {
533 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
534 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
535 }
536
537 /*
538 * Restore.
539 */
540 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
541 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
542 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
543 pVM->cpum.s.Hyper.cr3 = uCR3;
544 pVM->cpum.s.Hyper.esp = uESP;
545 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
546 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
547 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
548
549 uint32_t cElements;
550 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
551 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
552 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
553 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
554
555 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
556 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
557 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
558 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
559
560 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
561
562 /*
563 * Check that the basic cpuid id information is unchanged.
564 */
565 uint32_t au32CpuId[8] = {0};
566 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
567 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
568 uint32_t au32CpuIdSaved[8];
569 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
570 if (VBOX_SUCCESS(rc))
571 {
572 /* Ignore APIC ID (AMD specs). */
573 au32CpuId[5] &= ~0xff000000;
574 au32CpuIdSaved[5] &= ~0xff000000;
575 /* Ignore the number of Logical CPUs (AMD specs). */
576 au32CpuId[5] &= ~0x00ff0000;
577 au32CpuIdSaved[5] &= ~0x00ff0000;
578
579 /* do the compare */
580 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
581 {
582 Log(("cpumR3Load: CpuId mismatch!\n"
583 "Saved=%.*Vhxs\n"
584 "Real =%.*Vhxs\n",
585 sizeof(au32CpuIdSaved), au32CpuIdSaved,
586 sizeof(au32CpuId), au32CpuId));
587 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
588 }
589 }
590
591 return rc;
592}
593
594
595/**
596 * Formats the EFLAGS value into mnemonics.
597 *
598 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
599 * @param efl The EFLAGS value.
600 */
601static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
602{
603 /*
604 * Format the flags.
605 */
606 static struct
607 {
608 const char *pszSet; const char *pszClear; uint32_t fFlag;
609 } s_aFlags[] =
610 {
611 { "vip",NULL, X86_EFL_VIP },
612 { "vif",NULL, X86_EFL_VIF },
613 { "ac", NULL, X86_EFL_AC },
614 { "vm", NULL, X86_EFL_VM },
615 { "rf", NULL, X86_EFL_RF },
616 { "nt", NULL, X86_EFL_NT },
617 { "ov", "nv", X86_EFL_OF },
618 { "dn", "up", X86_EFL_DF },
619 { "ei", "di", X86_EFL_IF },
620 { "tf", NULL, X86_EFL_TF },
621 { "nt", "pl", X86_EFL_SF },
622 { "nz", "zr", X86_EFL_ZF },
623 { "ac", "na", X86_EFL_AF },
624 { "po", "pe", X86_EFL_PF },
625 { "cy", "nc", X86_EFL_CF },
626 };
627 char *psz = pszEFlags;
628 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
629 {
630 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
631 if (pszAdd)
632 {
633 strcpy(psz, pszAdd);
634 psz += strlen(pszAdd);
635 *psz++ = ' ';
636 }
637 }
638 psz[-1] = '\0';
639}
640
641
642/**
643 * Formats a full register dump.
644 *
645 * @param pCtx The context to format.
646 * @param pCtxCore The context core to format.
647 * @param pHlp Output functions.
648 * @param enmType The dump type.
649 * @param pszPrefix Register name prefix.
650 */
651static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
652{
653 /*
654 * Format the EFLAGS.
655 */
656 uint32_t efl = pCtxCore->eflags.u32;
657 char szEFlags[80];
658 cpumR3InfoFormatFlags(&szEFlags[0], efl);
659
660 /*
661 * Format the registers.
662 */
663 switch (enmType)
664 {
665 case CPUMDUMPTYPE_TERSE:
666 pHlp->pfnPrintf(pHlp,
667 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
668 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
669 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
670 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
671 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
672 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
673 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
674 break;
675
676 case CPUMDUMPTYPE_DEFAULT:
677 pHlp->pfnPrintf(pHlp,
678 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
679 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
680 "%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
681 "%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
682 ,
683 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
684 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
685 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
686 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl,
687 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
688 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
689 break;
690
691 case CPUMDUMPTYPE_VERBOSE:
692 pHlp->pfnPrintf(pHlp,
693 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
694 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
695 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
696 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
697 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
698 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
699 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
700 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
701 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
702 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
703 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
704 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
705 "%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
706 ,
707 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
708 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
709 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
710 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
711 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
712 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
713 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
714 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
715 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
716 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
717 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
718 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
719 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
720 break;
721 }
722}
723
724
725/**
726 * Display all cpu states and any other cpum info.
727 *
728 * @param pVM VM Handle.
729 * @param pHlp The info helper functions.
730 * @param pszArgs Arguments, ignored.
731 */
732static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
733{
734 cpumR3InfoGuest(pVM, pHlp, pszArgs);
735 cpumR3InfoHyper(pVM, pHlp, pszArgs);
736 cpumR3InfoHost(pVM, pHlp, pszArgs);
737}
738
739
740/**
741 * Parses the info argument.
742 *
743 * The argument starts with 'verbose', 'terse' or 'default' and then
744 * continues with the comment string.
745 *
746 * @param pszArgs The pointer to the argument string.
747 * @param penmType Where to store the dump type request.
748 * @param ppszComment Where to store the pointer to the comment string.
749 */
750static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
751{
752 if (!pszArgs)
753 {
754 *penmType = CPUMDUMPTYPE_DEFAULT;
755 *ppszComment = "";
756 }
757 else
758 {
759 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
760 {
761 pszArgs += 5;
762 *penmType = CPUMDUMPTYPE_VERBOSE;
763 }
764 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
765 {
766 pszArgs += 5;
767 *penmType = CPUMDUMPTYPE_TERSE;
768 }
769 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
770 {
771 pszArgs += 7;
772 *penmType = CPUMDUMPTYPE_DEFAULT;
773 }
774 else
775 *penmType = CPUMDUMPTYPE_DEFAULT;
776 *ppszComment = RTStrStripL(pszArgs);
777 }
778}
779
780
781/**
782 * Display the guest cpu state.
783 *
784 * @param pVM VM Handle.
785 * @param pHlp The info helper functions.
786 * @param pszArgs Arguments, ignored.
787 */
788static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
789{
790 CPUMDUMPTYPE enmType;
791 const char *pszComment;
792 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
793 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
794 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
795}
796
797
798/**
799 * Display the hypervisor cpu state.
800 *
801 * @param pVM VM Handle.
802 * @param pHlp The info helper functions.
803 * @param pszArgs Arguments, ignored.
804 */
805static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
806{
807 CPUMDUMPTYPE enmType;
808 const char *pszComment;
809 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
810 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
811 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
812}
813
814
815/**
816 * Display the host cpu state.
817 *
818 * @param pVM VM Handle.
819 * @param pHlp The info helper functions.
820 * @param pszArgs Arguments, ignored.
821 */
822static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
823{
824 CPUMDUMPTYPE enmType;
825 const char *pszComment;
826 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
827 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
828
829 /*
830 * Format the EFLAGS.
831 */
832 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
833#if HC_ARCH_BITS == 32
834 uint32_t efl = pCtx->eflags.u32;
835#else
836 uint64_t efl = pCtx->rflags;
837#endif
838 char szEFlags[80];
839 cpumR3InfoFormatFlags(&szEFlags[0], efl);
840
841 /*
842 * Format the registers.
843 */
844#if HC_ARCH_BITS == 32
845 pHlp->pfnPrintf(pHlp,
846 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
847 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
848 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
849 "cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
850 "dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
851 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
852 ,
853 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
854 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
855 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
856 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
857 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
858 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, (RTSEL)pCtx->ldtr,
859 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
860#else /* 64-bit */
861 pHlp->pfnPrintf(pHlp,
862 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
863 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
864 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
865 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
866 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
867 "r14=%016RX64 r15=%016RX64\n"
868 "iopl=%d %31s\n"
869 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
870 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
871 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
872 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
873 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
874 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
875 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
876 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
877 ,
878 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
879 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
880 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
881 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
882 pCtx->r11, pCtx->r12, pCtx->r13,
883 pCtx->r14, pCtx->r15,
884 X86_EFL_GET_IOPL(efl), szEFlags,
885 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
886 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
887 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
888 pCtx->dr0, pCtx->dr1, pCtx->dr2,
889 pCtx->dr3, pCtx->dr6, pCtx->dr7,
890 *(uint64_t *)&pCtx->gdtr[2], *(uint16_t *)&pCtx->gdtr[0], *(uint64_t *)&pCtx->idtr[2], *(uint16_t *)&pCtx->idtr[0],
891 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
892 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
893#endif
894}
895
896/**
897 * Get L1 cache / TLS associativity.
898 */
899static const char *getCacheAss(unsigned u, char *pszBuf)
900{
901 if (u == 0)
902 return "res0 ";
903 if (u == 1)
904 return "direct";
905 if (u >= 256)
906 return "???";
907
908 RTStrPrintf(pszBuf, 16, "%d way", u);
909 return pszBuf;
910}
911
912
913/**
914 * Get L2 cache soociativity.
915 */
916const char *getL2CacheAss(unsigned u)
917{
918 switch (u)
919 {
920 case 0: return "off ";
921 case 1: return "direct";
922 case 2: return "2 way ";
923 case 3: return "res3 ";
924 case 4: return "4 way ";
925 case 5: return "res5 ";
926 case 6: return "8 way ";
927 case 7: return "res7 ";
928 case 8: return "16 way";
929 case 9: return "res9 ";
930 case 10: return "res10 ";
931 case 11: return "res11 ";
932 case 12: return "res12 ";
933 case 13: return "res13 ";
934 case 14: return "res14 ";
935 case 15: return "fully ";
936 default:
937 return "????";
938 }
939}
940
941
942/**
943 * Display the guest CpuId leafs.
944 *
945 * @param pVM VM Handle.
946 * @param pHlp The info helper functions.
947 * @param pszArgs "terse", "default" or "verbose".
948 */
949static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
950{
951 /*
952 * Parse the argument.
953 */
954 unsigned iVerbosity = 1;
955 if (pszArgs)
956 {
957 pszArgs = RTStrStripL(pszArgs);
958 if (!strcmp(pszArgs, "terse"))
959 iVerbosity--;
960 else if (!strcmp(pszArgs, "verbose"))
961 iVerbosity++;
962 }
963
964 /*
965 * Start cracking.
966 */
967 CPUMCPUID Host;
968 CPUMCPUID Guest;
969 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
970
971 pHlp->pfnPrintf(pHlp,
972 " RAW Standard CPUIDs\n"
973 " Function eax ebx ecx edx\n");
974 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
975 {
976 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
977 ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
978
979 pHlp->pfnPrintf(pHlp,
980 "Gst: %08x %08x %08x %08x %08x%s\n"
981 "Hst: %08x %08x %08x %08x\n",
982 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
983 i <= cStdMax ? "" : "*",
984 Host.eax, Host.ebx, Host.ecx, Host.edx);
985 }
986
987 /*
988 * If verbose, decode it.
989 */
990 if (iVerbosity)
991 {
992 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
993 pHlp->pfnPrintf(pHlp,
994 "Name: %.04s%.04s%.04s\n"
995 "Supports: 0-%x\n",
996 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
997 }
998
999 /*
1000 * Get Features.
1001 */
1002 if (cStdMax >= 1 && iVerbosity)
1003 {
1004 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1005 uint32_t uEAX = Guest.eax;
1006
1007 pHlp->pfnPrintf(pHlp,
1008 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1009 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1010 "Stepping: %d\n"
1011 "APIC ID: %#04x\n"
1012 "Logical CPUs: %d\n"
1013 "CLFLUSH Size: %d\n"
1014 "Brand ID: %#04x\n",
1015 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1016 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1017 (uEAX >> 0) & 0xf,
1018 (Guest.ebx >> 24) & 0xff,
1019 (Guest.ebx >> 16) & 0xff,
1020 (Guest.ebx >> 8) & 0xff,
1021 (Guest.ebx >> 0) & 0xff);
1022 if (iVerbosity == 1)
1023 {
1024 uint32_t uEDX = Guest.edx;
1025 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1026 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1027 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1028 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1029 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1030 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1031 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1032 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1033 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1034 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1035 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1036 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1037 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1038 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1039 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1040 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1041 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1042 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1043 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1044 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1045 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1046 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1047 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1048 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1049 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1050 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1051 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1052 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1053 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1054 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1055 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1056 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1057 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1058 pHlp->pfnPrintf(pHlp, "\n");
1059
1060 uint32_t uECX = Guest.ecx;
1061 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1062 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1063 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1064 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1065 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1066 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1067 if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1068 if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1069 if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1070 if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1071 if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1072 if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1073 if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1074 if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1075 if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1076 for (unsigned iBit = 14; iBit < 32; iBit++)
1077 if (uECX & BIT(iBit))
1078 pHlp->pfnPrintf(pHlp, " %d", iBit);
1079 pHlp->pfnPrintf(pHlp, "\n");
1080 }
1081 else
1082 {
1083 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1084
1085 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1086 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1087 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1088 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1089
1090 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1091 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1092 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1093 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1094 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1095 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1096 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1097 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1098 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1099 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1100 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1101 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1102 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1103 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1104 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1105 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1106 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1107 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1108 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1109 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1110 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1111 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1112 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1113 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1114 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1115 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1116 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1117 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1118 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1119 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1120 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1121 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1122 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1123
1124 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1125 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1126 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1127 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1128 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1129 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1130 pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1131 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1132 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1133 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1134 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1135 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1136 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1137 }
1138 }
1139 if (cStdMax >= 2 && iVerbosity)
1140 {
1141 /** @todo */
1142 }
1143
1144 /*
1145 * Extended.
1146 * Implemented after AMD specs.
1147 */
1148 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1149
1150 pHlp->pfnPrintf(pHlp,
1151 "\n"
1152 " RAW Extended CPUIDs\n"
1153 " Function eax ebx ecx edx\n");
1154 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1155 {
1156 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1157 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1158
1159 pHlp->pfnPrintf(pHlp,
1160 "Gst: %08x %08x %08x %08x %08x%s\n"
1161 "Hst: %08x %08x %08x %08x\n",
1162 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1163 i <= cExtMax ? "" : "*",
1164 Host.eax, Host.ebx, Host.ecx, Host.edx);
1165 }
1166
1167 /*
1168 * Understandable output
1169 */
1170 if (iVerbosity && cExtMax >= 0)
1171 {
1172 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1173 pHlp->pfnPrintf(pHlp,
1174 "Ext Name: %.4s%.4s%.4s\n"
1175 "Ext Supports: 0x80000000-%#010x\n",
1176 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1177 }
1178
1179 if (iVerbosity && cExtMax >= 1)
1180 {
1181 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1182 uint32_t uEAX = Guest.eax;
1183 pHlp->pfnPrintf(pHlp,
1184 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1185 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1186 "Stepping: %d\n"
1187 "Brand ID: %#05x\n",
1188 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1189 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1190 (uEAX >> 0) & 0xf,
1191 Guest.ebx & 0xfff);
1192
1193 if (iVerbosity == 1)
1194 {
1195 uint32_t uEDX = Guest.edx;
1196 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1197 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1198 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1199 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1200 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1201 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1202 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1203 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1204 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1205 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1206 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1207 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1208 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1209 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1210 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1211 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1212 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1213 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1214 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1215 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1216 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1217 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1218 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1219 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1220 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1221 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1222 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1223 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1224 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1225 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1226 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1227 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1228 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1229 pHlp->pfnPrintf(pHlp, "\n");
1230
1231 uint32_t uECX = Guest.ecx;
1232 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1233 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1234 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1235 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1236 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1237 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1238 for (unsigned iBit = 5; iBit < 32; iBit++)
1239 if (uECX & BIT(iBit))
1240 pHlp->pfnPrintf(pHlp, " %d", iBit);
1241 pHlp->pfnPrintf(pHlp, "\n");
1242 }
1243 else
1244 {
1245 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1246
1247 uint32_t uEdxGst = Guest.edx;
1248 uint32_t uEdxHst = Host.edx;
1249 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1250 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1251 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1252 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1253 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1254 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1255 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1256 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1257 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1258 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1259 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1260 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1261 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1262 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1263 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1264 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1265 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1266 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1267 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1268 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1269 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1270 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1271 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1272 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1273 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1274 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1275 pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1276 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1277 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1278 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1279 pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1280 pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1281 pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1282
1283 uint32_t uEcxGst = Guest.ecx;
1284 uint32_t uEcxHst = Host.ecx;
1285 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1286 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1287 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1288 pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1289 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1290 pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1291 }
1292 }
1293
1294 if (iVerbosity && cExtMax >= 2)
1295 {
1296 char szString[4*4*3+1] = {0};
1297 uint32_t *pu32 = (uint32_t *)szString;
1298 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1299 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1300 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1301 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1302 if (cExtMax >= 3)
1303 {
1304 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1305 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1306 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1307 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1308 }
1309 if (cExtMax >= 4)
1310 {
1311 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1312 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1313 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1314 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1315 }
1316 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1317 }
1318
1319 if (iVerbosity && cExtMax >= 5)
1320 {
1321 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1322 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1323 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1324 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1325 char sz1[32];
1326 char sz2[32];
1327
1328 pHlp->pfnPrintf(pHlp,
1329 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1330 "TLB 2/4M Data: %s %3d entries\n",
1331 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1332 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1333 pHlp->pfnPrintf(pHlp,
1334 "TLB 4K Instr/Uni: %s %3d entries\n"
1335 "TLB 4K Data: %s %3d entries\n",
1336 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1337 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1338 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1339 "L1 Instr Cache Lines Per Tag: %d\n"
1340 "L1 Instr Cache Associativity: %s\n"
1341 "L1 Instr Cache Size: %d KB\n",
1342 (uEDX >> 0) & 0xff,
1343 (uEDX >> 8) & 0xff,
1344 getCacheAss((uEDX >> 16) & 0xff, sz1),
1345 (uEDX >> 24) & 0xff);
1346 pHlp->pfnPrintf(pHlp,
1347 "L1 Data Cache Line Size: %d bytes\n"
1348 "L1 Data Cache Lines Per Tag: %d\n"
1349 "L1 Data Cache Associativity: %s\n"
1350 "L1 Data Cache Size: %d KB\n",
1351 (uECX >> 0) & 0xff,
1352 (uECX >> 8) & 0xff,
1353 getCacheAss((uECX >> 16) & 0xff, sz1),
1354 (uECX >> 24) & 0xff);
1355 }
1356
1357 if (iVerbosity && cExtMax >= 6)
1358 {
1359 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1360 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1361 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1362
1363 pHlp->pfnPrintf(pHlp,
1364 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1365 "L2 TLB 2/4M Data: %s %4d entries\n",
1366 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1367 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1368 pHlp->pfnPrintf(pHlp,
1369 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1370 "L2 TLB 4K Data: %s %4d entries\n",
1371 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1372 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1373 pHlp->pfnPrintf(pHlp,
1374 "L2 Cache Line Size: %d bytes\n"
1375 "L2 Cache Lines Per Tag: %d\n"
1376 "L2 Cache Associativity: %s\n"
1377 "L2 Cache Size: %d KB\n",
1378 (uEDX >> 0) & 0xff,
1379 (uEDX >> 8) & 0xf,
1380 getL2CacheAss((uEDX >> 12) & 0xf),
1381 (uEDX >> 16) & 0xffff);
1382 }
1383
1384 if (iVerbosity && cExtMax >= 7)
1385 {
1386 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1387
1388 pHlp->pfnPrintf(pHlp, "APM Features: ");
1389 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1390 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1391 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1392 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1393 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1394 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1395 for (unsigned iBit = 6; iBit < 32; iBit++)
1396 if (uEDX & BIT(iBit))
1397 pHlp->pfnPrintf(pHlp, " %d", iBit);
1398 pHlp->pfnPrintf(pHlp, "\n");
1399 }
1400
1401 if (iVerbosity && cExtMax >= 8)
1402 {
1403 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1404 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1405
1406 pHlp->pfnPrintf(pHlp,
1407 "Physical Address Width: %d bits\n"
1408 "Virtual Address Width: %d bits\n",
1409 (uEAX >> 0) & 0xff,
1410 (uEAX >> 8) & 0xff);
1411 pHlp->pfnPrintf(pHlp,
1412 "Physical Core Count: %d\n",
1413 (uECX >> 0) & 0xff);
1414 }
1415}
1416
1417
1418/**
1419 * Structure used when disassembling and instructions in DBGF.
1420 * This is used so the reader function can get the stuff it needs.
1421 */
1422typedef struct CPUMDISASSTATE
1423{
1424 /** Pointer to the CPU structure. */
1425 PDISCPUSTATE pCpu;
1426 /** The VM handle. */
1427 PVM pVM;
1428 /** Pointer to the first byte in the segemnt. */
1429 RTGCUINTPTR GCPtrSegBase;
1430 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1431 RTGCUINTPTR GCPtrSegEnd;
1432 /** The size of the segment minus 1. */
1433 RTGCUINTPTR cbSegLimit;
1434 /** Pointer to the current page - HC Ptr. */
1435 void *pvPageHC;
1436 /** Pointer to the current page - GC Ptr. */
1437 RTGCPTR pvPageGC;
1438 /** The rc of the operation.
1439 *
1440 * @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1441 * When we've got time we should adjust the disassembler to use VBox status codes and not
1442 * boolean returns.
1443 */
1444 int rc;
1445} CPUMDISASSTATE, *PCPUMDISASSTATE;
1446
1447
1448/**
1449 * Instruction reader.
1450 *
1451 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1452 * @param PtrSrc Address to read from.
1453 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1454 * @param pu8Dst Where to store the bytes.
1455 * @param cbRead Number of bytes to read.
1456 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1457 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1458 * @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
1459 * declared as what it actually is a PDISCPUSTATE.
1460 */
1461static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1462{
1463 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1464 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1465 Assert(cbRead > 0);
1466 for (;;)
1467 {
1468 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1469
1470 /* Need to update the page translation? */
1471 if ( !pState->pvPageHC
1472 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1473 {
1474 /* translate the address */
1475 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1476 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1477 {
1478 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1479 if (!pState->pvPageHC)
1480 pState->rc = VERR_INVALID_POINTER;
1481 }
1482 else
1483 pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1484 if (VBOX_FAILURE(pState->rc))
1485 {
1486 pState->pvPageHC = NULL;
1487 return pState->rc;
1488 }
1489 }
1490
1491 /* check the segemnt limit */
1492 if (PtrSrc > pState->cbSegLimit)
1493 return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1494
1495 /* calc how much we can read */
1496 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1497 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1498 if (cb > cbSeg && !cbSeg)
1499 cb = cbSeg;
1500 if (cb > cbRead)
1501 cb = cbRead;
1502
1503 /* read and advance */
1504 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1505 cbRead -= cb;
1506 if (!cbRead)
1507 return VINF_SUCCESS;
1508 pu8Dst += cb;
1509 PtrSrc += cb;
1510 }
1511}
1512
1513
1514/**
1515 * Disassemble an instruction and return the information in the provided structure.
1516 *
1517 * @returns VBox status code.
1518 * @param pVM VM Handle
1519 * @param pCtx CPU context
1520 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1521 * @param pCpu Disassembly state
1522 * @param pszPrefix String prefix for logging (debug only)
1523 *
1524 */
1525CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1526{
1527 CPUMDISASSTATE State;
1528 int rc;
1529
1530 State.pCpu = pCpu;
1531 State.pvPageGC = 0;
1532 State.pvPageHC = NULL;
1533 State.rc = VINF_SUCCESS;
1534 State.pVM = pVM;
1535 /*
1536 * Get selector information.
1537 */
1538 if (pCtx->eflags.Bits.u1VM == 0)
1539 {
1540 if (CPUMAreHiddenSelRegsValid(pVM))
1541 {
1542 State.GCPtrSegBase = pCtx->csHid.u32Base;
1543 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1544 State.cbSegLimit = pCtx->csHid.u32Limit;
1545 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1546 }
1547 else
1548 {
1549 SELMSELINFO SelInfo;
1550
1551 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1552 if (!VBOX_SUCCESS(rc))
1553 {
1554 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1555 return rc;
1556 }
1557
1558 /*
1559 * Validate the selector.
1560 */
1561 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1562 if (!VBOX_SUCCESS(rc))
1563 {
1564 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1565 return rc;
1566 }
1567 State.GCPtrSegBase = SelInfo.GCPtrBase;
1568 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1569 State.cbSegLimit = SelInfo.cbLimit;
1570 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1571 }
1572 }
1573 else
1574 {
1575 /* V86 mode */
1576 pCpu->mode = CPUMODE_16BIT; /* @todo */
1577 State.GCPtrSegBase = pCtx->cs * 16;
1578 State.GCPtrSegEnd = 0xFFFFFFFF;
1579 State.cbSegLimit = 0xFFFFFFFF;
1580 }
1581
1582 /*
1583 * Disassemble the instruction.
1584 */
1585 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1586 pCpu->dwUserData[0] = (uintptr_t)&State;
1587
1588 uint32_t cbInstr;
1589#ifdef LOG_ENABLED
1590 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1591 {
1592#else
1593 char szOutput[160];
1594 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1595 {
1596 /* log it */
1597 if (pszPrefix)
1598 Log(("%s: %s", pszPrefix, szOutput));
1599 else
1600 Log(("%s", szOutput));
1601#endif
1602 return VINF_SUCCESS;
1603 }
1604
1605 /* DISInstr failure */
1606 if (VBOX_FAILURE(State.rc))
1607 {
1608 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1609 return State.rc;
1610 }
1611 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1612 rc = VERR_GENERAL_FAILURE;
1613 return rc;
1614}
1615
1616
1617#ifdef DEBUG
1618/**
1619 * Disassemble an instruction and dump it to the log
1620 *
1621 * @returns VBox status code.
1622 * @param pVM VM Handle
1623 * @param pCtx CPU context
1624 * @param pc GC instruction pointer
1625 * @param prefix String prefix for logging
1626 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1627 *
1628 */
1629CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1630{
1631 DISCPUSTATE cpu;
1632
1633 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1634}
1635
1636/**
1637 * Disassemble an instruction and dump it to the log
1638 *
1639 * @returns VBox status code.
1640 * @param pVM VM Handle
1641 * @param pCtx CPU context
1642 * @param pc GC instruction pointer
1643 * @param prefix String prefix for logging
1644 * @param nrInstructions
1645 *
1646 */
1647CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1648{
1649 for(int i=0;i<nrInstructions;i++)
1650 {
1651 DISCPUSTATE cpu;
1652
1653 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1654 pc += cpu.opsize;
1655 }
1656}
1657
1658#endif
1659
1660#ifdef DEBUG
1661/**
1662 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1663 *
1664 * @internal
1665 */
1666CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1667{
1668 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1669}
1670#endif
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