VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 2981

Last change on this file since 2981 was 2981, checked in by vboxsync, 17 years ago

InnoTek -> innotek: all the headers and comments.
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File size: 75.3 KB
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1/* $Id: CPUM.cpp 2981 2007-06-01 16:01:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager)
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * If you received this file as part of a commercial VirtualBox
18 * distribution, then only the terms of your commercial VirtualBox
19 * license agreement apply instead of the previous paragraph.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include <VBox/cpumdis.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/selm.h>
32#include <VBox/dbgf.h>
33#include <VBox/patm.h>
34#include <VBox/ssm.h>
35#include "CPUMInternal.h"
36#include <VBox/vm.h>
37
38#include <VBox/param.h>
39#include <VBox/dis.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/string.h>
45#include <iprt/system.h>
46#include "x86context.h"
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The saved state version. */
52#define CPUM_SAVED_STATE_VERSION 3
53
54
55/*******************************************************************************
56* Structures and Typedefs *
57*******************************************************************************/
58
59/**
60 * What kind of cpu info dump to performe.
61 */
62typedef enum CPUMDUMPTYPE
63{
64 CPUMDUMPTYPE_TERSE,
65 CPUMDUMPTYPE_DEFAULT,
66 CPUMDUMPTYPE_VERBOSE
67
68} CPUMDUMPTYPE, *PCPUMDUMPTYPE;
69
70
71/*******************************************************************************
72* Internal Functions *
73*******************************************************************************/
74static int cpumR3CpuIdInit(PVM pVM);
75static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
76static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
77static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
78static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
79static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
80static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
81static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
82
83
84/**
85 * Initializes the CPUM.
86 *
87 * @returns VBox status code.
88 * @param pVM The VM to operate on.
89 */
90CPUMR3DECL(int) CPUMR3Init(PVM pVM)
91{
92 LogFlow(("CPUMR3Init\n"));
93
94 /*
95 * Assert alignment and sizes.
96 */
97 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
98 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
99
100 /*
101 * Setup any fixed pointers and offsets.
102 */
103 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
104 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
105 pVM->cpum.s.pHyperCoreHC = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
106
107 /* Hidden selector registers are invalid by default. */
108 pVM->cpum.s.fValidHiddenSelRegs = false;
109
110 /*
111 * Check that the CPU supports the minimum features we require.
112 */
113 /** @todo check the contract! */
114 if (!ASMHasCpuId())
115 {
116 Log(("The CPU doesn't support CPUID!\n"));
117 return VERR_UNSUPPORTED_CPU;
118 }
119 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
120
121 /* Setup the CR4 AND and OR masks used in the switcher */
122 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
123 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
124 {
125 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
126 /* No FXSAVE implies no SSE */
127 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
128 pVM->cpum.s.CR4.OrMask = 0;
129 }
130 else
131 {
132 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
133 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
134 }
135
136 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
137 {
138 Log(("The CPU doesn't support MMX!\n"));
139 return VERR_UNSUPPORTED_CPU;
140 }
141 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
142 {
143 Log(("The CPU doesn't support TSC!\n"));
144 return VERR_UNSUPPORTED_CPU;
145 }
146 /* Bogus on AMD? */
147 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
148 {
149 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
150 }
151
152 /*
153 * Setup hypervisor startup values.
154 */
155
156 /*
157 * Register saved state data item.
158 */
159 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
160 NULL, cpumR3Save, NULL,
161 NULL, cpumR3Load, NULL);
162 if (VBOX_FAILURE(rc))
163 return rc;
164
165 /*
166 * Register info handlers.
167 */
168 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
169 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
170 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
171 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
172 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leafs.", &cpumR3CpuIdInfo);
173
174 /*
175 * Initialize the Guest CPU state.
176 */
177 rc = cpumR3CpuIdInit(pVM);
178 if (VBOX_FAILURE(rc))
179 return rc;
180 CPUMR3Reset(pVM);
181 return VINF_SUCCESS;
182}
183
184
185/**
186 * Initializes the emulated CPU's cpuid information.
187 *
188 * @returns VBox status code.
189 * @param pVM The VM to operate on.
190 */
191static int cpumR3CpuIdInit(PVM pVM)
192{
193 PCPUM pCPUM = &pVM->cpum.s;
194 uint32_t i;
195
196 /*
197 * Get the host CPUIDs.
198 */
199 for (i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
200 ASMCpuId(i,
201 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
202 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
203 for (i = 0; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
204 ASMCpuId(0x80000000 + i,
205 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
206 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
207
208 /*
209 * Only report features we can support.
210 */
211 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
212 | X86_CPUID_FEATURE_EDX_VME
213 | X86_CPUID_FEATURE_EDX_DE
214 | X86_CPUID_FEATURE_EDX_PSE
215 | X86_CPUID_FEATURE_EDX_TSC
216 | X86_CPUID_FEATURE_EDX_MSR
217 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
218 | X86_CPUID_FEATURE_EDX_MCE
219 | X86_CPUID_FEATURE_EDX_CX8
220 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
221 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
222 //| X86_CPUID_FEATURE_EDX_SEP
223 //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
224 | X86_CPUID_FEATURE_EDX_PGE
225 //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
226 | X86_CPUID_FEATURE_EDX_CMOV
227 //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
228 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
229 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
230 //| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
231 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
232 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
233 | X86_CPUID_FEATURE_EDX_MMX
234 | X86_CPUID_FEATURE_EDX_FXSR
235 | X86_CPUID_FEATURE_EDX_SSE
236 | X86_CPUID_FEATURE_EDX_SSE2
237 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
238 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
239 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
240 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
241 | 0;
242 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
243 | X86_CPUID_FEATURE_ECX_MONITOR
244 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
245 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
246 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
247 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
248 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
249 | 0;
250
251#if 1 /* we didn't used to do this, but I guess we should */
252 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
253 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
254 | X86_CPUID_AMD_FEATURE_EDX_VME
255 | X86_CPUID_AMD_FEATURE_EDX_DE
256 | X86_CPUID_AMD_FEATURE_EDX_PSE
257 | X86_CPUID_AMD_FEATURE_EDX_TSC
258 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
259 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
260 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
261 | X86_CPUID_AMD_FEATURE_EDX_CX8
262 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
263 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
264 //| X86_CPUID_AMD_FEATURE_EDX_SEP
265 //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
266 | X86_CPUID_AMD_FEATURE_EDX_PGE
267 //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
268 | X86_CPUID_AMD_FEATURE_EDX_CMOV
269 | X86_CPUID_AMD_FEATURE_EDX_PAT
270 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
271 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
272 | X86_CPUID_AMD_FEATURE_EDX_MMX
273 | X86_CPUID_AMD_FEATURE_EDX_FXSR
274 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
275 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
276 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
277 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
278 | 0;
279 pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
280 | 0;
281#endif
282
283#if 0 /* this is what we used to do. */
284 /*
285 * Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
286 */
287 pCPUM->aGuestCpuIdStd[1].ebx = 0;
288
289 /*
290 * Set the max standard index to 2.
291 */
292 pCPUM->aGuestCpuIdStd[0].eax = 2;
293 pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
294
295#else /* this is what we probably should do */
296 /*
297 * Hide HTT, multicode, SMP, whatever.
298 * (APIC-ID := 0 and #LogCpus := 0)
299 */
300 pCPUM->aGuestCpuIdStd[1].ebx = 0x0000ffff;
301
302 /*
303 * Determin the default value and limit it the number of entries.
304 * Intel returns values of the highest standard function, while AMD returns zeros.
305 */
306 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
307 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
308 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
309
310 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
311 pCPUM->aGuestCpuIdStd[0].eax = 2;
312
313 if (pCPUM->aGuestCpuIdExt[0].eax > 0x80000004)
314 pCPUM->aGuestCpuIdExt[0].eax = 0x80000004;
315
316#endif
317
318 /*
319 * Assign defaults to the entries we chopped off.
320 */
321 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
322 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
323 for (i = pCPUM->aGuestCpuIdExt[0].eax - 0x80000000 + 1; i < ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
324 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
325
326 /*
327 * Load CPUID overrides from configuration.
328 */
329 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
330 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
331 for (;;)
332 {
333 while (cElements-- < 0)
334 {
335 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
336 if (pNode)
337 {
338 uint32_t u32;
339 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
340 if (VBOX_SUCCESS(rc))
341 pCpuId->eax = u32;
342 else
343 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
344
345 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
346 if (VBOX_SUCCESS(rc))
347 pCpuId->ebx = u32;
348 else
349 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
350
351 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
352 if (VBOX_SUCCESS(rc))
353 pCpuId->ecx = u32;
354 else
355 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
356
357 rc = CFGMR3QueryU32(pNode, "edx", &u32);
358 if (VBOX_SUCCESS(rc))
359 pCpuId->edx = u32;
360 else
361 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
362 }
363 }
364
365 /* next */
366 if (i & 0x80000000)
367 break;
368 pCpuId = &pCPUM->aGuestCpuIdExt[0];
369 cElements = ELEMENTS(pCPUM->aGuestCpuIdExt);
370 i = 0x80000000;
371 }
372
373 /*
374 * Log the cpuid and we're good.
375 */
376 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
377 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
378 LogRel(("************************* CPUID dump ************************\n"));
379 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
380 LogRel(("\n"));
381 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
382 LogRel(("******************** End of CPUID dump **********************\n"));
383 return VINF_SUCCESS;
384}
385
386
387
388
389/**
390 * Applies relocations to data and code managed by this
391 * component. This function will be called at init and
392 * whenever the VMM need to relocate it self inside the GC.
393 *
394 * The CPUM will update the addresses used by the switcher.
395 *
396 * @param pVM The VM.
397 */
398CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
399{
400 LogFlow(("CPUMR3Relocate\n"));
401 /*
402 * Switcher pointers.
403 */
404 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
405 pVM->cpum.s.pHyperCoreGC = MMHyperHC2GC(pVM, pVM->cpum.s.pHyperCoreHC);
406}
407
408
409/**
410 * Queries the pointer to the internal CPUMCTX structure
411 *
412 * @returns VBox status code.
413 * @param pVM Handle to the virtual machine.
414 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
415 */
416CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx)
417{
418 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
419 /*
420 * Store the address. (Later we might check how's calling, thus the RC.)
421 */
422 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
423 return VINF_SUCCESS;
424}
425
426
427/**
428 * Terminates the CPUM.
429 *
430 * Termination means cleaning up and freeing all resources,
431 * the VM it self is at this point powered off or suspended.
432 *
433 * @returns VBox status code.
434 * @param pVM The VM to operate on.
435 */
436CPUMR3DECL(int) CPUMR3Term(PVM pVM)
437{
438 /** @todo */
439 return 0;
440}
441
442
443/**
444 * Resets the CPU.
445 *
446 * @returns VINF_SUCCESS.
447 * @param pVM The VM handle.
448 */
449CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
450{
451 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
452
453 /*
454 * Initialize everything to ZERO first.
455 */
456 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
457 memset(pCtx, 0, sizeof(*pCtx));
458 pVM->cpum.s.fUseFlags = fUseFlags;
459
460 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
461 pCtx->eip = 0x0000fff0;
462 pCtx->edx = 0x00000600; /* P6 processor */
463 pCtx->eflags.Bits.u1Reserved0 = 1;
464
465 pCtx->cs = 0xf000;
466 pCtx->csHid.u32Base = 0xffff0000;
467 pCtx->csHid.u32Limit = 0x0000ffff;
468 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
469 pCtx->csHid.Attr.n.u1Present = 1;
470 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
471
472 pCtx->dsHid.u32Limit = 0x0000ffff;
473 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
474 pCtx->dsHid.Attr.n.u1Present = 1;
475 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
476
477 pCtx->esHid.u32Limit = 0x0000ffff;
478 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
479 pCtx->esHid.Attr.n.u1Present = 1;
480 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
481
482 pCtx->fsHid.u32Limit = 0x0000ffff;
483 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
484 pCtx->fsHid.Attr.n.u1Present = 1;
485 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
486
487 pCtx->gsHid.u32Limit = 0x0000ffff;
488 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
489 pCtx->gsHid.Attr.n.u1Present = 1;
490 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
491
492 pCtx->ssHid.u32Limit = 0x0000ffff;
493 pCtx->ssHid.Attr.n.u1Present = 1;
494 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
495 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
496
497 pCtx->idtr.cbIdt = 0xffff;
498 pCtx->gdtr.cbGdt = 0xffff;
499
500 pCtx->ldtrHid.u32Limit = 0xffff;
501 pCtx->ldtrHid.Attr.n.u1Present = 1;
502 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
503
504 pCtx->trHid.u32Limit = 0xffff;
505 pCtx->trHid.Attr.n.u1Present = 1;
506 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
507
508 pCtx->dr6 = 0xFFFF0FF0;
509 pCtx->dr7 = 0x400;
510
511 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
512 pCtx->fpu.FCW = 0x37f;
513}
514
515
516
517/**
518 * Execute state save operation.
519 *
520 * @returns VBox status code.
521 * @param pVM VM Handle.
522 * @param pSSM SSM operation handle.
523 */
524static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
525{
526 /*
527 * Save.
528 */
529 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
530 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
531 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
532 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
533
534 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
535 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
536
537 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
538 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
539
540 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
541
542 /* Add the cpuid for checking that the cpu is unchanged. */
543 uint32_t au32CpuId[8] = {0};
544 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
545 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
546 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
547}
548
549
550/**
551 * Execute state load operation.
552 *
553 * @returns VBox status code.
554 * @param pVM VM Handle.
555 * @param pSSM SSM operation handle.
556 * @param u32Version Data layout version.
557 */
558static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
559{
560 /*
561 * Validate version.
562 */
563 if (u32Version != CPUM_SAVED_STATE_VERSION)
564 {
565 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
566 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
567 }
568
569 /*
570 * Restore.
571 */
572 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
573 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
574 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
575 pVM->cpum.s.Hyper.cr3 = uCR3;
576 pVM->cpum.s.Hyper.esp = uESP;
577 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
578 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
579 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
580
581 uint32_t cElements;
582 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
583 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
584 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
585 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
586
587 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
588 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
589 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
590 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
591
592 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
593
594 /*
595 * Check that the basic cpuid id information is unchanged.
596 */
597 uint32_t au32CpuId[8] = {0};
598 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
599 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
600 uint32_t au32CpuIdSaved[8];
601 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
602 if (VBOX_SUCCESS(rc))
603 {
604 /* Ignore APIC ID (AMD specs). */
605 au32CpuId[5] &= ~0xff000000;
606 au32CpuIdSaved[5] &= ~0xff000000;
607 /* Ignore the number of Logical CPUs (AMD specs). */
608 au32CpuId[5] &= ~0x00ff0000;
609 au32CpuIdSaved[5] &= ~0x00ff0000;
610
611 /* do the compare */
612 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
613 {
614 Log(("cpumR3Load: CpuId mismatch!\n"
615 "Saved=%.*Vhxs\n"
616 "Real =%.*Vhxs\n",
617 sizeof(au32CpuIdSaved), au32CpuIdSaved,
618 sizeof(au32CpuId), au32CpuId));
619 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
620 }
621 }
622
623 return rc;
624}
625
626
627/**
628 * Formats the EFLAGS value into mnemonics.
629 *
630 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
631 * @param efl The EFLAGS value.
632 */
633static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
634{
635 /*
636 * Format the flags.
637 */
638 static struct
639 {
640 const char *pszSet; const char *pszClear; uint32_t fFlag;
641 } s_aFlags[] =
642 {
643 { "vip",NULL, X86_EFL_VIP },
644 { "vif",NULL, X86_EFL_VIF },
645 { "ac", NULL, X86_EFL_AC },
646 { "vm", NULL, X86_EFL_VM },
647 { "rf", NULL, X86_EFL_RF },
648 { "nt", NULL, X86_EFL_NT },
649 { "ov", "nv", X86_EFL_OF },
650 { "dn", "up", X86_EFL_DF },
651 { "ei", "di", X86_EFL_IF },
652 { "tf", NULL, X86_EFL_TF },
653 { "nt", "pl", X86_EFL_SF },
654 { "nz", "zr", X86_EFL_ZF },
655 { "ac", "na", X86_EFL_AF },
656 { "po", "pe", X86_EFL_PF },
657 { "cy", "nc", X86_EFL_CF },
658 };
659 char *psz = pszEFlags;
660 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
661 {
662 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
663 if (pszAdd)
664 {
665 strcpy(psz, pszAdd);
666 psz += strlen(pszAdd);
667 *psz++ = ' ';
668 }
669 }
670 psz[-1] = '\0';
671}
672
673
674/**
675 * Formats a full register dump.
676 *
677 * @param pCtx The context to format.
678 * @param pCtxCore The context core to format.
679 * @param pHlp Output functions.
680 * @param enmType The dump type.
681 * @param pszPrefix Register name prefix.
682 */
683static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
684{
685 /*
686 * Format the EFLAGS.
687 */
688 uint32_t efl = pCtxCore->eflags.u32;
689 char szEFlags[80];
690 cpumR3InfoFormatFlags(&szEFlags[0], efl);
691
692 /*
693 * Format the registers.
694 */
695 switch (enmType)
696 {
697 case CPUMDUMPTYPE_TERSE:
698 pHlp->pfnPrintf(pHlp,
699 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
700 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
701 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
702 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
703 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
704 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
705 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
706 break;
707
708 case CPUMDUMPTYPE_DEFAULT:
709 pHlp->pfnPrintf(pHlp,
710 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
711 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
712 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
713 "%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
714 ,
715 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
716 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
717 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
718 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
719 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
720 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
721 break;
722
723 case CPUMDUMPTYPE_VERBOSE:
724 pHlp->pfnPrintf(pHlp,
725 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
726 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
727 "%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
728 "%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
729 "%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
730 "%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
731 "%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
732 "%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
733 "%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
734 "%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
735 "%str ={%04x base=%08x limit=%08x flags=%08x}\n"
736 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
737 "%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
738 ,
739 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
740 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
741 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
742 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
743 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
744 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
745 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
746 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
747 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
748 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u32Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
749 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u32Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
750 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
751 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW);
752 break;
753 }
754}
755
756
757/**
758 * Display all cpu states and any other cpum info.
759 *
760 * @param pVM VM Handle.
761 * @param pHlp The info helper functions.
762 * @param pszArgs Arguments, ignored.
763 */
764static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
765{
766 cpumR3InfoGuest(pVM, pHlp, pszArgs);
767 cpumR3InfoHyper(pVM, pHlp, pszArgs);
768 cpumR3InfoHost(pVM, pHlp, pszArgs);
769}
770
771
772/**
773 * Parses the info argument.
774 *
775 * The argument starts with 'verbose', 'terse' or 'default' and then
776 * continues with the comment string.
777 *
778 * @param pszArgs The pointer to the argument string.
779 * @param penmType Where to store the dump type request.
780 * @param ppszComment Where to store the pointer to the comment string.
781 */
782static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
783{
784 if (!pszArgs)
785 {
786 *penmType = CPUMDUMPTYPE_DEFAULT;
787 *ppszComment = "";
788 }
789 else
790 {
791 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
792 {
793 pszArgs += 5;
794 *penmType = CPUMDUMPTYPE_VERBOSE;
795 }
796 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
797 {
798 pszArgs += 5;
799 *penmType = CPUMDUMPTYPE_TERSE;
800 }
801 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
802 {
803 pszArgs += 7;
804 *penmType = CPUMDUMPTYPE_DEFAULT;
805 }
806 else
807 *penmType = CPUMDUMPTYPE_DEFAULT;
808 *ppszComment = RTStrStripL(pszArgs);
809 }
810}
811
812
813/**
814 * Display the guest cpu state.
815 *
816 * @param pVM VM Handle.
817 * @param pHlp The info helper functions.
818 * @param pszArgs Arguments, ignored.
819 */
820static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
821{
822 CPUMDUMPTYPE enmType;
823 const char *pszComment;
824 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
825 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
826 cpumR3InfoOne(&pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
827}
828
829
830/**
831 * Display the hypervisor cpu state.
832 *
833 * @param pVM VM Handle.
834 * @param pHlp The info helper functions.
835 * @param pszArgs Arguments, ignored.
836 */
837static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
838{
839 CPUMDUMPTYPE enmType;
840 const char *pszComment;
841 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
842 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
843 cpumR3InfoOne(&pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreHC, pHlp, enmType, ".");
844 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
845}
846
847
848/**
849 * Display the host cpu state.
850 *
851 * @param pVM VM Handle.
852 * @param pHlp The info helper functions.
853 * @param pszArgs Arguments, ignored.
854 */
855static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
856{
857 CPUMDUMPTYPE enmType;
858 const char *pszComment;
859 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
860 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
861
862 /*
863 * Format the EFLAGS.
864 */
865 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
866#if HC_ARCH_BITS == 32
867 uint32_t efl = pCtx->eflags.u32;
868#else
869 uint64_t efl = pCtx->rflags;
870#endif
871 char szEFlags[80];
872 cpumR3InfoFormatFlags(&szEFlags[0], efl);
873
874 /*
875 * Format the registers.
876 */
877#if HC_ARCH_BITS == 32
878# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
879 if (!(pCtx->efer & MSR_K6_EFER_LMA))
880# endif
881 {
882 pHlp->pfnPrintf(pHlp,
883 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
884 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
885 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
886 "cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
887 "dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
888 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
889 ,
890 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
891 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
892 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
893 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
894 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
895 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
896 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
897 }
898# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
899 else
900# endif
901#endif
902#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
903 {
904 pHlp->pfnPrintf(pHlp,
905 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
906 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
907 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
908 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
909 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
910 "r14=%016RX64 r15=%016RX64\n"
911 "iopl=%d %31s\n"
912 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
913 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
914 "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
915 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
916 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
917 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
918 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
919 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
920 ,
921 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
922 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
923 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
924 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
925 pCtx->r11, pCtx->r12, pCtx->r13,
926 pCtx->r14, pCtx->r15,
927 X86_EFL_GET_IOPL(efl), szEFlags,
928 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
929 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
930 pCtx->cr4, pCtx->cr8, pCtx->ldtr, pCtx->tr,
931 pCtx->dr0, pCtx->dr1, pCtx->dr2,
932 pCtx->dr3, pCtx->dr6, pCtx->dr7,
933 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
934 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
935 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
936 }
937#endif
938}
939
940/**
941 * Get L1 cache / TLS associativity.
942 */
943static const char *getCacheAss(unsigned u, char *pszBuf)
944{
945 if (u == 0)
946 return "res0 ";
947 if (u == 1)
948 return "direct";
949 if (u >= 256)
950 return "???";
951
952 RTStrPrintf(pszBuf, 16, "%d way", u);
953 return pszBuf;
954}
955
956
957/**
958 * Get L2 cache soociativity.
959 */
960const char *getL2CacheAss(unsigned u)
961{
962 switch (u)
963 {
964 case 0: return "off ";
965 case 1: return "direct";
966 case 2: return "2 way ";
967 case 3: return "res3 ";
968 case 4: return "4 way ";
969 case 5: return "res5 ";
970 case 6: return "8 way ";
971 case 7: return "res7 ";
972 case 8: return "16 way";
973 case 9: return "res9 ";
974 case 10: return "res10 ";
975 case 11: return "res11 ";
976 case 12: return "res12 ";
977 case 13: return "res13 ";
978 case 14: return "res14 ";
979 case 15: return "fully ";
980 default:
981 return "????";
982 }
983}
984
985
986/**
987 * Display the guest CpuId leafs.
988 *
989 * @param pVM VM Handle.
990 * @param pHlp The info helper functions.
991 * @param pszArgs "terse", "default" or "verbose".
992 */
993static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
994{
995 /*
996 * Parse the argument.
997 */
998 unsigned iVerbosity = 1;
999 if (pszArgs)
1000 {
1001 pszArgs = RTStrStripL(pszArgs);
1002 if (!strcmp(pszArgs, "terse"))
1003 iVerbosity--;
1004 else if (!strcmp(pszArgs, "verbose"))
1005 iVerbosity++;
1006 }
1007
1008 /*
1009 * Start cracking.
1010 */
1011 CPUMCPUID Host;
1012 CPUMCPUID Guest;
1013 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1014
1015 pHlp->pfnPrintf(pHlp,
1016 " RAW Standard CPUIDs\n"
1017 " Function eax ebx ecx edx\n");
1018 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1019 {
1020 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1021 ASMCpuId(i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1022
1023 pHlp->pfnPrintf(pHlp,
1024 "Gst: %08x %08x %08x %08x %08x%s\n"
1025 "Hst: %08x %08x %08x %08x\n",
1026 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1027 i <= cStdMax ? "" : "*",
1028 Host.eax, Host.ebx, Host.ecx, Host.edx);
1029 }
1030
1031 /*
1032 * If verbose, decode it.
1033 */
1034 if (iVerbosity)
1035 {
1036 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1037 pHlp->pfnPrintf(pHlp,
1038 "Name: %.04s%.04s%.04s\n"
1039 "Supports: 0-%x\n",
1040 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1041 }
1042
1043 /*
1044 * Get Features.
1045 */
1046 if (cStdMax >= 1 && iVerbosity)
1047 {
1048 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1049 uint32_t uEAX = Guest.eax;
1050
1051 pHlp->pfnPrintf(pHlp,
1052 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1053 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1054 "Stepping: %d\n"
1055 "APIC ID: %#04x\n"
1056 "Logical CPUs: %d\n"
1057 "CLFLUSH Size: %d\n"
1058 "Brand ID: %#04x\n",
1059 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1060 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1061 (uEAX >> 0) & 0xf,
1062 (Guest.ebx >> 24) & 0xff,
1063 (Guest.ebx >> 16) & 0xff,
1064 (Guest.ebx >> 8) & 0xff,
1065 (Guest.ebx >> 0) & 0xff);
1066 if (iVerbosity == 1)
1067 {
1068 uint32_t uEDX = Guest.edx;
1069 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1070 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1071 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1072 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1073 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1074 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1075 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1076 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1077 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1078 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1079 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1080 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1081 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1082 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1083 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1084 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1085 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1086 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1087 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1088 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1089 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1090 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1091 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1092 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1093 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1094 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1095 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1096 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1097 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1098 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1099 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1100 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1101 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1102 pHlp->pfnPrintf(pHlp, "\n");
1103
1104 uint32_t uECX = Guest.ecx;
1105 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1106 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1107 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1108 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1109 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1110 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1111 if (uECX & BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1112 if (uECX & BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1113 if (uECX & BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1114 if (uECX & BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1115 if (uECX & BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1116 if (uECX & BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1117 if (uECX & BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1118 if (uECX & BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1119 if (uECX & BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1120 for (unsigned iBit = 14; iBit < 32; iBit++)
1121 if (uECX & BIT(iBit))
1122 pHlp->pfnPrintf(pHlp, " %d", iBit);
1123 pHlp->pfnPrintf(pHlp, "\n");
1124 }
1125 else
1126 {
1127 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1128
1129 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1130 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1131 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1132 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1133
1134 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1135 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1136 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1137 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1138 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1139 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1140 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1141 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1142 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1143 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1144 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1145 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1146 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1147 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1148 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1149 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1150 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1151 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1152 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1153 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1154 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1155 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1156 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1157 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1158 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1159 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1160 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1161 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1162 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1163 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1164 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1165 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1166 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1167
1168 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1169 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1170 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1171 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1172 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1173 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1174 pHlp->pfnPrintf(pHlp, "Enh. SpeedStep Tech = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1175 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1176 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved3, EcxHost.u1Reserved3);
1177 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1178 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1179 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1180 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u18Reserved5, EcxHost.u18Reserved5);
1181 }
1182 }
1183 if (cStdMax >= 2 && iVerbosity)
1184 {
1185 /** @todo */
1186 }
1187
1188 /*
1189 * Extended.
1190 * Implemented after AMD specs.
1191 */
1192 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1193
1194 pHlp->pfnPrintf(pHlp,
1195 "\n"
1196 " RAW Extended CPUIDs\n"
1197 " Function eax ebx ecx edx\n");
1198 for (unsigned i = 0; i <= ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1199 {
1200 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1201 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1202
1203 pHlp->pfnPrintf(pHlp,
1204 "Gst: %08x %08x %08x %08x %08x%s\n"
1205 "Hst: %08x %08x %08x %08x\n",
1206 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1207 i <= cExtMax ? "" : "*",
1208 Host.eax, Host.ebx, Host.ecx, Host.edx);
1209 }
1210
1211 /*
1212 * Understandable output
1213 */
1214 if (iVerbosity && cExtMax >= 0)
1215 {
1216 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1217 pHlp->pfnPrintf(pHlp,
1218 "Ext Name: %.4s%.4s%.4s\n"
1219 "Ext Supports: 0x80000000-%#010x\n",
1220 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1221 }
1222
1223 if (iVerbosity && cExtMax >= 1)
1224 {
1225 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1226 uint32_t uEAX = Guest.eax;
1227 pHlp->pfnPrintf(pHlp,
1228 "Family: %d \tExtended: %d \tEffectiv: %d\n"
1229 "Model: %d \tExtended: %d \tEffectiv: %d\n"
1230 "Stepping: %d\n"
1231 "Brand ID: %#05x\n",
1232 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
1233 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
1234 (uEAX >> 0) & 0xf,
1235 Guest.ebx & 0xfff);
1236
1237 if (iVerbosity == 1)
1238 {
1239 uint32_t uEDX = Guest.edx;
1240 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1241 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1242 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1243 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1244 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1245 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1246 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1247 if (uEDX & BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1248 if (uEDX & BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1249 if (uEDX & BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1250 if (uEDX & BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1251 if (uEDX & BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1252 if (uEDX & BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1253 if (uEDX & BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1254 if (uEDX & BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1255 if (uEDX & BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1256 if (uEDX & BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1257 if (uEDX & BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1258 if (uEDX & BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1259 if (uEDX & BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1260 if (uEDX & BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1261 if (uEDX & BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1262 if (uEDX & BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1263 if (uEDX & BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1264 if (uEDX & BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1265 if (uEDX & BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1266 if (uEDX & BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1267 if (uEDX & BIT(26)) pHlp->pfnPrintf(pHlp, " 26");
1268 if (uEDX & BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1269 if (uEDX & BIT(28)) pHlp->pfnPrintf(pHlp, " 29");
1270 if (uEDX & BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1271 if (uEDX & BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1272 if (uEDX & BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1273 pHlp->pfnPrintf(pHlp, "\n");
1274
1275 uint32_t uECX = Guest.ecx;
1276 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1277 if (uECX & BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1278 if (uECX & BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1279 if (uECX & BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1280 if (uECX & BIT(3)) pHlp->pfnPrintf(pHlp, " SVM");
1281 if (uECX & BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1282 for (unsigned iBit = 5; iBit < 32; iBit++)
1283 if (uECX & BIT(iBit))
1284 pHlp->pfnPrintf(pHlp, " %d", iBit);
1285 pHlp->pfnPrintf(pHlp, "\n");
1286 }
1287 else
1288 {
1289 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1290
1291 uint32_t uEdxGst = Guest.edx;
1292 uint32_t uEdxHst = Host.edx;
1293 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1294 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
1295 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
1296 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
1297 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
1298 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
1299 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
1300 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
1301 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
1302 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
1303 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
1304 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(10)), !!(uEdxHst & BIT(10)));
1305 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
1306 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
1307 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
1308 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
1309 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
1310 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
1311 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
1312 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(18)), !!(uEdxHst & BIT(18)));
1313 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(19)), !!(uEdxHst & BIT(19)));
1314 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
1315 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
1316 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
1317 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
1318 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
1319 pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
1320 pHlp->pfnPrintf(pHlp, "26 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(26)), !!(uEdxHst & BIT(26)));
1321 pHlp->pfnPrintf(pHlp, "27 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(27)), !!(uEdxHst & BIT(27)));
1322 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & BIT(28)), !!(uEdxHst & BIT(28)));
1323 pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
1324 pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
1325 pHlp->pfnPrintf(pHlp, "?? - AMD 3DNow = %d (%d)\n", !!(uEdxGst & BIT(31)), !!(uEdxHst & BIT(31)));
1326
1327 uint32_t uEcxGst = Guest.ecx;
1328 uint32_t uEcxHst = Host.ecx;
1329 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
1330 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
1331 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
1332 pHlp->pfnPrintf(pHlp, "3 - Reserved = %d (%d)\n", !!(uEcxGst & BIT( 3)), !!(uEcxHst & BIT( 3)));
1333 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
1334 pHlp->pfnPrintf(pHlp, "31:5 - Reserved = %#x (%#x)\n", uEcxGst >> 5, uEcxHst >> 5);
1335 }
1336 }
1337
1338 if (iVerbosity && cExtMax >= 2)
1339 {
1340 char szString[4*4*3+1] = {0};
1341 uint32_t *pu32 = (uint32_t *)szString;
1342 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1343 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1344 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1345 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1346 if (cExtMax >= 3)
1347 {
1348 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1349 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1350 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1351 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1352 }
1353 if (cExtMax >= 4)
1354 {
1355 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1356 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1357 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1358 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1359 }
1360 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1361 }
1362
1363 if (iVerbosity && cExtMax >= 5)
1364 {
1365 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1366 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1367 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1368 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1369 char sz1[32];
1370 char sz2[32];
1371
1372 pHlp->pfnPrintf(pHlp,
1373 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1374 "TLB 2/4M Data: %s %3d entries\n",
1375 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1376 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1377 pHlp->pfnPrintf(pHlp,
1378 "TLB 4K Instr/Uni: %s %3d entries\n"
1379 "TLB 4K Data: %s %3d entries\n",
1380 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1381 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1382 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1383 "L1 Instr Cache Lines Per Tag: %d\n"
1384 "L1 Instr Cache Associativity: %s\n"
1385 "L1 Instr Cache Size: %d KB\n",
1386 (uEDX >> 0) & 0xff,
1387 (uEDX >> 8) & 0xff,
1388 getCacheAss((uEDX >> 16) & 0xff, sz1),
1389 (uEDX >> 24) & 0xff);
1390 pHlp->pfnPrintf(pHlp,
1391 "L1 Data Cache Line Size: %d bytes\n"
1392 "L1 Data Cache Lines Per Tag: %d\n"
1393 "L1 Data Cache Associativity: %s\n"
1394 "L1 Data Cache Size: %d KB\n",
1395 (uECX >> 0) & 0xff,
1396 (uECX >> 8) & 0xff,
1397 getCacheAss((uECX >> 16) & 0xff, sz1),
1398 (uECX >> 24) & 0xff);
1399 }
1400
1401 if (iVerbosity && cExtMax >= 6)
1402 {
1403 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1404 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1405 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1406
1407 pHlp->pfnPrintf(pHlp,
1408 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1409 "L2 TLB 2/4M Data: %s %4d entries\n",
1410 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1411 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1412 pHlp->pfnPrintf(pHlp,
1413 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1414 "L2 TLB 4K Data: %s %4d entries\n",
1415 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1416 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1417 pHlp->pfnPrintf(pHlp,
1418 "L2 Cache Line Size: %d bytes\n"
1419 "L2 Cache Lines Per Tag: %d\n"
1420 "L2 Cache Associativity: %s\n"
1421 "L2 Cache Size: %d KB\n",
1422 (uEDX >> 0) & 0xff,
1423 (uEDX >> 8) & 0xf,
1424 getL2CacheAss((uEDX >> 12) & 0xf),
1425 (uEDX >> 16) & 0xffff);
1426 }
1427
1428 if (iVerbosity && cExtMax >= 7)
1429 {
1430 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1431
1432 pHlp->pfnPrintf(pHlp, "APM Features: ");
1433 if (uEDX & BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1434 if (uEDX & BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1435 if (uEDX & BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1436 if (uEDX & BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1437 if (uEDX & BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1438 if (uEDX & BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1439 for (unsigned iBit = 6; iBit < 32; iBit++)
1440 if (uEDX & BIT(iBit))
1441 pHlp->pfnPrintf(pHlp, " %d", iBit);
1442 pHlp->pfnPrintf(pHlp, "\n");
1443 }
1444
1445 if (iVerbosity && cExtMax >= 8)
1446 {
1447 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1448 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1449
1450 pHlp->pfnPrintf(pHlp,
1451 "Physical Address Width: %d bits\n"
1452 "Virtual Address Width: %d bits\n",
1453 (uEAX >> 0) & 0xff,
1454 (uEAX >> 8) & 0xff);
1455 pHlp->pfnPrintf(pHlp,
1456 "Physical Core Count: %d\n",
1457 (uECX >> 0) & 0xff);
1458 }
1459}
1460
1461
1462/**
1463 * Structure used when disassembling and instructions in DBGF.
1464 * This is used so the reader function can get the stuff it needs.
1465 */
1466typedef struct CPUMDISASSTATE
1467{
1468 /** Pointer to the CPU structure. */
1469 PDISCPUSTATE pCpu;
1470 /** The VM handle. */
1471 PVM pVM;
1472 /** Pointer to the first byte in the segemnt. */
1473 RTGCUINTPTR GCPtrSegBase;
1474 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1475 RTGCUINTPTR GCPtrSegEnd;
1476 /** The size of the segment minus 1. */
1477 RTGCUINTPTR cbSegLimit;
1478 /** Pointer to the current page - HC Ptr. */
1479 void *pvPageHC;
1480 /** Pointer to the current page - GC Ptr. */
1481 RTGCPTR pvPageGC;
1482 /** The rc of the operation.
1483 *
1484 * @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
1485 * When we've got time we should adjust the disassembler to use VBox status codes and not
1486 * boolean returns.
1487 */
1488 int rc;
1489} CPUMDISASSTATE, *PCPUMDISASSTATE;
1490
1491
1492/**
1493 * Instruction reader.
1494 *
1495 * @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
1496 * @param PtrSrc Address to read from.
1497 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1498 * @param pu8Dst Where to store the bytes.
1499 * @param cbRead Number of bytes to read.
1500 * @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
1501 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1502 * @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
1503 * declared as what it actually is a PDISCPUSTATE.
1504 */
1505static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
1506{
1507 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1508 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
1509 Assert(cbRead > 0);
1510 for (;;)
1511 {
1512 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1513
1514 /* Need to update the page translation? */
1515 if ( !pState->pvPageHC
1516 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1517 {
1518 /* translate the address */
1519 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1520 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1521 {
1522 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1523 if (!pState->pvPageHC)
1524 pState->rc = VERR_INVALID_POINTER;
1525 }
1526 else
1527 pState->rc = PGMPhysGCPtr2HCPtr(pState->pVM, pState->pvPageGC, &pState->pvPageHC);
1528 if (VBOX_FAILURE(pState->rc))
1529 {
1530 pState->pvPageHC = NULL;
1531 return pState->rc;
1532 }
1533 }
1534
1535 /* check the segemnt limit */
1536 if (PtrSrc > pState->cbSegLimit)
1537 return pState->rc = VERR_OUT_OF_SELECTOR_BOUNDS;
1538
1539 /* calc how much we can read */
1540 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1541 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1542 if (cb > cbSeg && !cbSeg)
1543 cb = cbSeg;
1544 if (cb > cbRead)
1545 cb = cbRead;
1546
1547 /* read and advance */
1548 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1549 cbRead -= cb;
1550 if (!cbRead)
1551 return VINF_SUCCESS;
1552 pu8Dst += cb;
1553 PtrSrc += cb;
1554 }
1555}
1556
1557
1558/**
1559 * Disassemble an instruction and return the information in the provided structure.
1560 *
1561 * @returns VBox status code.
1562 * @param pVM VM Handle
1563 * @param pCtx CPU context
1564 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1565 * @param pCpu Disassembly state
1566 * @param pszPrefix String prefix for logging (debug only)
1567 *
1568 */
1569CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1570{
1571 CPUMDISASSTATE State;
1572 int rc;
1573
1574 State.pCpu = pCpu;
1575 State.pvPageGC = 0;
1576 State.pvPageHC = NULL;
1577 State.rc = VINF_SUCCESS;
1578 State.pVM = pVM;
1579
1580 /*
1581 * Get selector information.
1582 */
1583 if ( (pCtx->cr0 & X86_CR0_PE)
1584 && pCtx->eflags.Bits.u1VM == 0)
1585 {
1586 if (CPUMAreHiddenSelRegsValid(pVM))
1587 {
1588 State.GCPtrSegBase = pCtx->csHid.u32Base;
1589 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u32Base;
1590 State.cbSegLimit = pCtx->csHid.u32Limit;
1591 pCpu->mode = pCtx->csHid.Attr.n.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1592 }
1593 else
1594 {
1595 SELMSELINFO SelInfo;
1596
1597 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1598 if (!VBOX_SUCCESS(rc))
1599 {
1600 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1601 return rc;
1602 }
1603
1604 /*
1605 * Validate the selector.
1606 */
1607 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1608 if (!VBOX_SUCCESS(rc))
1609 {
1610 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1611 return rc;
1612 }
1613 State.GCPtrSegBase = SelInfo.GCPtrBase;
1614 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1615 State.cbSegLimit = SelInfo.cbLimit;
1616 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1617 }
1618 }
1619 else
1620 {
1621 /* real or V86 mode */
1622 pCpu->mode = CPUMODE_16BIT;
1623 State.GCPtrSegBase = pCtx->cs * 16;
1624 State.GCPtrSegEnd = 0xFFFFFFFF;
1625 State.cbSegLimit = 0xFFFFFFFF;
1626 }
1627
1628 /*
1629 * Disassemble the instruction.
1630 */
1631 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
1632 pCpu->dwUserData[0] = (uintptr_t)&State;
1633
1634 uint32_t cbInstr;
1635#ifdef LOG_ENABLED
1636 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL))
1637 {
1638#else
1639 char szOutput[160];
1640 if (DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]))
1641 {
1642 /* log it */
1643 if (pszPrefix)
1644 Log(("%s: %s", pszPrefix, szOutput));
1645 else
1646 Log(("%s", szOutput));
1647#endif
1648 return VINF_SUCCESS;
1649 }
1650
1651 /* DISInstr failure */
1652 if (VBOX_FAILURE(State.rc))
1653 {
1654 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
1655 return State.rc;
1656 }
1657 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv\n", pCtx->cs, GCPtrPC));
1658 rc = VERR_GENERAL_FAILURE;
1659 return rc;
1660}
1661
1662
1663#ifdef DEBUG
1664/**
1665 * Disassemble an instruction and dump it to the log
1666 *
1667 * @returns VBox status code.
1668 * @param pVM VM Handle
1669 * @param pCtx CPU context
1670 * @param pc GC instruction pointer
1671 * @param prefix String prefix for logging
1672 * @deprecated Use DBGFR3DisasInstrCurrentLog().
1673 *
1674 */
1675CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
1676{
1677 DISCPUSTATE cpu;
1678
1679 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1680}
1681
1682/**
1683 * Disassemble an instruction and dump it to the log
1684 *
1685 * @returns VBox status code.
1686 * @param pVM VM Handle
1687 * @param pCtx CPU context
1688 * @param pc GC instruction pointer
1689 * @param prefix String prefix for logging
1690 * @param nrInstructions
1691 *
1692 */
1693CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
1694{
1695 for(int i=0;i<nrInstructions;i++)
1696 {
1697 DISCPUSTATE cpu;
1698
1699 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
1700 pc += cpu.opsize;
1701 }
1702}
1703
1704#endif
1705
1706#ifdef DEBUG
1707/**
1708 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
1709 *
1710 * @internal
1711 */
1712CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
1713{
1714 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
1715}
1716#endif
1717
1718
1719/**
1720 * API for controlling a few of the CPU features found in CR4.
1721 *
1722 * Currently only X86_CR4_TSD is accepted as input.
1723 *
1724 * @returns VBox status code.
1725 *
1726 * @param pVM The VM handle.
1727 * @param fOr The CR4 OR mask.
1728 * @param fAnd The CR4 AND mask.
1729 */
1730CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
1731{
1732 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
1733 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
1734
1735 pVM->cpum.s.CR4.OrMask &= fAnd;
1736 pVM->cpum.s.CR4.OrMask |= fOr;
1737
1738 return VINF_SUCCESS;
1739}
1740
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