CPUM.cpp@ 26295

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1	/* $Id: CPUM.cpp 26263 2010-02-05 02:24:13Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/mm.h>
46	#include <VBox/selm.h>
47	#include <VBox/dbgf.h>
48	#include <VBox/patm.h>
49	#include <VBox/hwaccm.h>
50	#include <VBox/ssm.h>
51	#include "CPUMInternal.h"
52	#include <VBox/vm.h>
53
54	#include <VBox/param.h>
55	#include <VBox/dis.h>
56	#include <VBox/err.h>
57	#include <VBox/log.h>
58	#include <iprt/assert.h>
59	#include <iprt/asm.h>
60	#include <iprt/string.h>
61	#include <iprt/mp.h>
62	#include <iprt/cpuset.h>
63
64
65	/*******************************************************************************
66	* Defined Constants And Macros *
67	*******************************************************************************/
68	/** The current saved state version. */
69	#define CPUM_SAVED_STATE_VERSION 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatability. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detech the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Initializes the per-VCPU CPUM.
244	*
245	* @returns VBox status code.
246	* @param pVM The VM to operate on.
247	*/
248	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
249	{
250	LogFlow(("CPUMR3InitCPU\n"));
251	return VINF_SUCCESS;
252	}
253
254
255	/**
256	* Detect the CPU vendor give n the
257	*
258	* @returns The vendor.
259	* @param uEAX EAX from CPUID(0).
260	* @param uEBX EBX from CPUID(0).
261	* @param uECX ECX from CPUID(0).
262	* @param uEDX EDX from CPUID(0).
263	*/
264	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
265	{
266	if ( uEAX >= 1
267	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
268	&& uECX == X86_CPUID_VENDOR_AMD_ECX
269	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
270	return CPUMCPUVENDOR_AMD;
271
272	if ( uEAX >= 1
273	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
274	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
275	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
276	return CPUMCPUVENDOR_INTEL;
277
278	/** @todo detect the other buggers... */
279	return CPUMCPUVENDOR_UNKNOWN;
280	}
281
282
283	/**
284	* Fetches overrides for a CPUID leaf.
285	*
286	* @returns VBox status code.
287	* @param pLeaf The leaf to load the overrides into.
288	* @param pCfgNode The CFGM node containing the overrides
289	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
290	* @param iLeaf The CPUID leaf number.
291	*/
292	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
293	{
294	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
295	if (pLeafNode)
296	{
297	uint32_t u32;
298	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
299	if (RT_SUCCESS(rc))
300	pLeaf->eax = u32;
301	else
302	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
303
304	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
305	if (RT_SUCCESS(rc))
306	pLeaf->ebx = u32;
307	else
308	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
309
310	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
311	if (RT_SUCCESS(rc))
312	pLeaf->ecx = u32;
313	else
314	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
315
316	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
317	if (RT_SUCCESS(rc))
318	pLeaf->edx = u32;
319	else
320	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
321
322	}
323	return VINF_SUCCESS;
324	}
325
326
327	/**
328	* Load the overrides for a set of CPUID leafs.
329	*
330	* @returns VBox status code.
331	* @param paLeafs The leaf array.
332	* @param cLeafs The number of leafs.
333	* @param uStart The start leaf number.
334	* @param pCfgNode The CFGM node containing the overrides
335	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
336	*/
337	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
338	{
339	for (uint32_t i = 0; i < cLeafs; i++)
340	{
341	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
342	if (RT_FAILURE(rc))
343	return rc;
344	}
345
346	return VINF_SUCCESS;
347	}
348
349	/**
350	* Init a set of host CPUID leafs.
351	*
352	* @returns VBox status code.
353	* @param paLeafs The leaf array.
354	* @param cLeafs The number of leafs.
355	* @param uStart The start leaf number.
356	* @param pCfgNode The /CPUM/HostCPUID/ node.
357	*/
358	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
359	{
360	/* Using the ECX variant for all of them can't hurt... */
361	for (uint32_t i = 0; i < cLeafs; i++)
362	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
363
364	/* Load CPUID leaf override; we currently don't care if the caller
365	specifies features the host CPU doesn't support. */
366	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
367	}
368
369
370	/**
371	* Initializes the emulated CPU's cpuid information.
372	*
373	* @returns VBox status code.
374	* @param pVM The VM to operate on.
375	*/
376	static int cpumR3CpuIdInit(PVM pVM)
377	{
378	PCPUM pCPUM = &pVM->cpum.s;
379	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
380	uint32_t i;
381	int rc;
382
383	/*
384	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
385	*/
386	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
387	* Overrides the host CPUID leaf values used for calculating the guest CPUID
388	* leafs. This can be used to preserve the CPUID values when moving a VM to
389	* a different machine. Another use is restricting (or extending) the
390	* feature set exposed to the guest. */
391	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
392	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
393	AssertRCReturn(rc, rc);
394	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
395	AssertRCReturn(rc, rc);
396	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
397	AssertRCReturn(rc, rc);
398
399	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
400	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
401
402	/*
403	* Only report features we can support.
404	*/
405	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
406	\| X86_CPUID_FEATURE_EDX_VME
407	\| X86_CPUID_FEATURE_EDX_DE
408	\| X86_CPUID_FEATURE_EDX_PSE
409	\| X86_CPUID_FEATURE_EDX_TSC
410	\| X86_CPUID_FEATURE_EDX_MSR
411	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
412	\| X86_CPUID_FEATURE_EDX_MCE
413	\| X86_CPUID_FEATURE_EDX_CX8
414	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
415	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
416	//\| X86_CPUID_FEATURE_EDX_SEP
417	\| X86_CPUID_FEATURE_EDX_MTRR
418	\| X86_CPUID_FEATURE_EDX_PGE
419	\| X86_CPUID_FEATURE_EDX_MCA
420	\| X86_CPUID_FEATURE_EDX_CMOV
421	\| X86_CPUID_FEATURE_EDX_PAT
422	\| X86_CPUID_FEATURE_EDX_PSE36
423	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
424	\| X86_CPUID_FEATURE_EDX_CLFSH
425	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
426	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
427	\| X86_CPUID_FEATURE_EDX_MMX
428	\| X86_CPUID_FEATURE_EDX_FXSR
429	\| X86_CPUID_FEATURE_EDX_SSE
430	\| X86_CPUID_FEATURE_EDX_SSE2
431	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
432	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
433	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
434	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
435	\| 0;
436	pCPUM->aGuestCpuIdStd[1].ecx &= 0
437	\| X86_CPUID_FEATURE_ECX_SSE3
438	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
439	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
440	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
441	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
442	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
443	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
444	\| X86_CPUID_FEATURE_ECX_SSSE3
445	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
446	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
447	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
448	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
449	/* ECX Bit 21 - x2APIC support - not yet. */
450	// \| X86_CPUID_FEATURE_ECX_X2APIC
451	/* ECX Bit 23 - POPCNT instruction. */
452	//\| X86_CPUID_FEATURE_ECX_POPCNT
453	\| 0;
454
455	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
456	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
457	\| X86_CPUID_AMD_FEATURE_EDX_VME
458	\| X86_CPUID_AMD_FEATURE_EDX_DE
459	\| X86_CPUID_AMD_FEATURE_EDX_PSE
460	\| X86_CPUID_AMD_FEATURE_EDX_TSC
461	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
462	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
463	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
464	\| X86_CPUID_AMD_FEATURE_EDX_CX8
465	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
466	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
467	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
468	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
469	\| X86_CPUID_AMD_FEATURE_EDX_PGE
470	\| X86_CPUID_AMD_FEATURE_EDX_MCA
471	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
472	\| X86_CPUID_AMD_FEATURE_EDX_PAT
473	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
474	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
475	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
476	\| X86_CPUID_AMD_FEATURE_EDX_MMX
477	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
478	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
479	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
480	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
481	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
482	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
484	\| 0;
485	pCPUM->aGuestCpuIdExt[1].ecx &= 0
486	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
487	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
488	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
489	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
490	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
491	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
492	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
493	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
494	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
495	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
496	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
497	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
498	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
499	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
500	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
501	\| 0;
502
503	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
504	if (pCPUM->fSyntheticCpu)
505	{
506	const char szVendor[13] = "VirtualBox ";
507	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
508
509	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
510
511	/* Limit the nr of standard leaves; 5 for monitor/mwait */
512	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
513
514	/* 0: Vendor */
515	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
516	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
517	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
518
519	/* 1.eax: Version information. family : model : stepping */
520	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
521
522	/* Leaves 2 - 4 are Intel only - zero them out */
523	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
524	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
525	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
526
527	/* Leaf 5 = monitor/mwait */
528
529	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
530	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
531	/* AMD only - set to zero. */
532	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
533
534	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
535	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
536
537	/* 0x800000002-4: Processor Name String Identifier. */
538	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
539	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
540	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
541	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
542	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
543	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
544	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
545	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
546	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
547	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
548	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
549	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
550
551	/* 0x800000005-7 - reserved -> zero */
552	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
553	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
554	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
555
556	/* 0x800000008: only the max virtual and physical address size. */
557	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
558	}
559
560	/*
561	* Hide HTT, multicode, SMP, whatever.
562	* (APIC-ID := 0 and #LogCpus := 0)
563	*/
564	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
565	#ifdef VBOX_WITH_MULTI_CORE
566	if ( pVM->cCpus > 1
567	&& pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
568	{
569	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
570	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
571	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
572	}
573	#endif
574
575	/* Cpuid 2:
576	* Intel: Cache and TLB information
577	* AMD: Reserved
578	* Safe to expose
579	*/
580
581	/* Cpuid 3:
582	* Intel: EAX, EBX - reserved
583	* ECX, EDX - Processor Serial Number if available, otherwise reserved
584	* AMD: Reserved
585	* Safe to expose
586	*/
587	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
588	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
589
590	/* Cpuid 4:
591	* Intel: Deterministic Cache Parameters Leaf
592	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
593	* AMD: Reserved
594	* Safe to expose, except for EAX:
595	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
596	* Bits 31-26: Maximum number of processor cores in this physical package**
597	* Note: These SMP values are constant regardless of ECX
598	*/
599	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
600	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
601	#ifdef VBOX_WITH_MULTI_CORE
602	if ( pVM->cCpus > 1
603	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
604	{
605	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
606	/* One logical processor with possibly multiple cores. */
607	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
608	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
609	}
610	#endif
611
612	/* Cpuid 5: Monitor/mwait Leaf
613	* Intel: ECX, EDX - reserved
614	* EAX, EBX - Smallest and largest monitor line size
615	* AMD: EDX - reserved
616	* EAX, EBX - Smallest and largest monitor line size
617	* ECX - extensions (ignored for now)
618	* Safe to expose
619	*/
620	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
621	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
622
623	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
624
625	/*
626	* Determine the default.
627	*
628	* Intel returns values of the highest standard function, while AMD
629	* returns zeros. VIA on the other hand seems to returning nothing or
630	* perhaps some random garbage, we don't try to duplicate this behavior.
631	*/
632	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
633	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
634	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
635
636	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
637	* Safe to pass on to the guest.
638	*
639	* Intel: 0x800000005 reserved
640	* 0x800000006 L2 cache information
641	* AMD: 0x800000005 L1 cache information
642	* 0x800000006 L2/L3 cache information
643	*/
644
645	/* Cpuid 0x800000007:
646	* AMD: EAX, EBX, ECX - reserved
647	* EDX: Advanced Power Management Information
648	* Intel: Reserved
649	*/
650	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
651	{
652	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
653
654	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
655
656	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
657	{
658	/* Only expose the TSC invariant capability bit to the guest. */
659	pCPUM->aGuestCpuIdExt[7].edx &= 0
660	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
661	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
662	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
663	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
664	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
665	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
666	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
667	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
668	#if 1
669	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
670	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
671	*/
672	#else
673	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
674	#endif
675	\| 0;
676	}
677	else
678	pCPUM->aGuestCpuIdExt[7].edx = 0;
679	}
680
681	/* Cpuid 0x800000008:
682	* AMD: EBX, EDX - reserved
683	* EAX: Virtual/Physical address Size
684	* ECX: Number of cores + APICIdCoreIdSize
685	* Intel: EAX: Virtual/Physical address Size
686	* EBX, ECX, EDX - reserved
687	*/
688	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
689	{
690	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
691	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
692	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
693	* NC (0-7) Number of cores; 0 equals 1 core */
694	pCPUM->aGuestCpuIdExt[8].ecx = 0;
695	#ifdef VBOX_WITH_MULTI_CORE
696	if ( pVM->cCpus > 1
697	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
698	{
699	/* Legacy method to determine the number of cores. */
700	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
701	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
702
703	}
704	#endif
705	}
706
707	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
708	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
709	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
710	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
711	*/
712	bool fNt4LeafLimit;
713	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
714	if (fNt4LeafLimit)
715	pCPUM->aGuestCpuIdStd[0].eax = 3;
716
717	/*
718	* Limit it the number of entries and fill the remaining with the defaults.
719	*
720	* The limits are masking off stuff about power saving and similar, this
721	* is perhaps a bit crudely done as there is probably some relatively harmless
722	* info too in these leaves (like words about having a constant TSC).
723	*/
724	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
725	pCPUM->aGuestCpuIdStd[0].eax = 5;
726
727	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
728	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
729
730	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
731	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
732	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
733	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
734	: 0;
735	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
736	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
737
738	/*
739	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
740	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
741	* of processors from (cpuid(4).eax >> 26) + 1.
742	*/
743	if (pVM->cCpus == 1)
744	pCPUM->aGuestCpuIdStd[4].eax = 0;
745
746	/*
747	* Centaur stuff (VIA).
748	*
749	* The important part here (we think) is to make sure the 0xc0000000
750	* function returns 0xc0000001. As for the features, we don't currently
751	* let on about any of those... 0xc0000002 seems to be some
752	* temperature/hz/++ stuff, include it as well (static).
753	*/
754	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
755	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
756	{
757	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
758	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
759	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
760	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
761	i++)
762	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
763	}
764	else
765	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
766	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
767
768
769	/*
770	* Load CPUID overrides from configuration.
771	* Note: Kind of redundant now, but allows unchanged overrides
772	*/
773	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
774	* Overrides the CPUID leaf values. */
775	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
776	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
777	AssertRCReturn(rc, rc);
778	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
779	AssertRCReturn(rc, rc);
780	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
781	AssertRCReturn(rc, rc);
782
783	/*
784	* Check if PAE was explicitely enabled by the user.
785	*/
786	bool fEnable;
787	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
788	if (fEnable)
789	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
790
791	/*
792	* Log the cpuid and we're good.
793	*/
794	RTCPUSET OnlineSet;
795	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
796	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
797	LogRel(("*********************** CPUID dump **********************\n"));
798	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
799	LogRel(("\n"));
800	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
801	LogRel(("****************** End of CPUID dump ********************\n"));
802	return VINF_SUCCESS;
803	}
804
805
806
807
808	/**
809	* Applies relocations to data and code managed by this
810	* component. This function will be called at init and
811	* whenever the VMM need to relocate it self inside the GC.
812	*
813	* The CPUM will update the addresses used by the switcher.
814	*
815	* @param pVM The VM.
816	*/
817	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
818	{
819	LogFlow(("CPUMR3Relocate\n"));
820	for (VMCPUID i = 0; i < pVM->cCpus; i++)
821	{
822	/*
823	* Switcher pointers.
824	*/
825	PVMCPU pVCpu = &pVM->aCpus[i];
826	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
827	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
828	}
829	}
830
831
832	/**
833	* Terminates the CPUM.
834	*
835	* Termination means cleaning up and freeing all resources,
836	* the VM it self is at this point powered off or suspended.
837	*
838	* @returns VBox status code.
839	* @param pVM The VM to operate on.
840	*/
841	VMMR3DECL(int) CPUMR3Term(PVM pVM)
842	{
843	CPUMR3TermCPU(pVM);
844	return 0;
845	}
846
847
848	/**
849	* Terminates the per-VCPU CPUM.
850	*
851	* Termination means cleaning up and freeing all resources,
852	* the VM it self is at this point powered off or suspended.
853	*
854	* @returns VBox status code.
855	* @param pVM The VM to operate on.
856	*/
857	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
858	{
859	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
860	for (VMCPUID i = 0; i < pVM->cCpus; i++)
861	{
862	PVMCPU pVCpu = &pVM->aCpus[i];
863	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
864
865	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
866	pVCpu->cpum.s.uMagic = 0;
867	pCtx->dr[5] = 0;
868	}
869	#endif
870	return 0;
871	}
872
873
874	/**
875	* Resets a virtual CPU.
876	*
877	* Used by CPUMR3Reset and CPU hot plugging.
878	*
879	* @param pVCpu The virtual CPU handle.
880	*/
881	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
882	{
883	/** @todo anything different for VCPU > 0? */
884	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
885
886	/*
887	* Initialize everything to ZERO first.
888	*/
889	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
890	memset(pCtx, 0, sizeof(*pCtx));
891	pVCpu->cpum.s.fUseFlags = fUseFlags;
892
893	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
894	pCtx->eip = 0x0000fff0;
895	pCtx->edx = 0x00000600; /* P6 processor */
896	pCtx->eflags.Bits.u1Reserved0 = 1;
897
898	pCtx->cs = 0xf000;
899	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
900	pCtx->csHid.u32Limit = 0x0000ffff;
901	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
902	pCtx->csHid.Attr.n.u1Present = 1;
903	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
904
905	pCtx->dsHid.u32Limit = 0x0000ffff;
906	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
907	pCtx->dsHid.Attr.n.u1Present = 1;
908	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
909
910	pCtx->esHid.u32Limit = 0x0000ffff;
911	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
912	pCtx->esHid.Attr.n.u1Present = 1;
913	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
914
915	pCtx->fsHid.u32Limit = 0x0000ffff;
916	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
917	pCtx->fsHid.Attr.n.u1Present = 1;
918	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
919
920	pCtx->gsHid.u32Limit = 0x0000ffff;
921	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
922	pCtx->gsHid.Attr.n.u1Present = 1;
923	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
924
925	pCtx->ssHid.u32Limit = 0x0000ffff;
926	pCtx->ssHid.Attr.n.u1Present = 1;
927	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
928	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
929
930	pCtx->idtr.cbIdt = 0xffff;
931	pCtx->gdtr.cbGdt = 0xffff;
932
933	pCtx->ldtrHid.u32Limit = 0xffff;
934	pCtx->ldtrHid.Attr.n.u1Present = 1;
935	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
936
937	pCtx->trHid.u32Limit = 0xffff;
938	pCtx->trHid.Attr.n.u1Present = 1;
939	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
940
941	pCtx->dr[6] = X86_DR6_INIT_VAL;
942	pCtx->dr[7] = X86_DR7_INIT_VAL;
943
944	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
945	pCtx->fpu.FCW = 0x37f;
946
947	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
948	pCtx->fpu.MXCSR = 0x1F80;
949
950	/* Init PAT MSR */
951	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
952
953	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
954	* The Intel docs don't mention it.
955	*/
956	pCtx->msrEFER = 0;
957	}
958
959
960	/**
961	* Resets the CPU.
962	*
963	* @returns VINF_SUCCESS.
964	* @param pVM The VM handle.
965	*/
966	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
967	{
968	for (VMCPUID i = 0; i < pVM->cCpus; i++)
969	{
970	CPUMR3ResetCpu(&pVM->aCpus[i]);
971
972	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
973	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
974
975	/* Magic marker for searching in crash dumps. */
976	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
977	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
978	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
979	#endif
980	}
981	}
982
983
984	/**
985	* Called both in pass 0 and the final pass.
986	*
987	* @param pVM The VM handle.
988	* @param pSSM The saved state handle.
989	*/
990	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
991	{
992	/*
993	* Save all the CPU ID leaves here so we can check them for compatability
994	* upon loading.
995	*/
996	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
997	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
998
999	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1000	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1001
1002	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1003	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1004
1005	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1006
1007	/*
1008	* Save a good portion of the raw CPU IDs as well as they may come in
1009	* handy when validating features for raw mode.
1010	*/
1011	CPUMCPUID aRawStd[16];
1012	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1013	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1014	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1015	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1016
1017	CPUMCPUID aRawExt[32];
1018	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1019	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1020	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1021	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1022	}
1023
1024
1025	/**
1026	* Loads the CPU ID leaves saved by pass 0.
1027	*
1028	* @returns VBox status code.
1029	* @param pVM The VM handle.
1030	* @param pSSM The saved state handle.
1031	* @param uVersion The format version.
1032	*/
1033	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1034	{
1035	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1036
1037	/*
1038	* Define a bunch of macros for simplifying the code.
1039	*/
1040	/* Generic expression + failure message. */
1041	#define CPUID_CHECK_RET(expr, fmt) \
1042	do { \
1043	if (!(expr)) \
1044	{ \
1045	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1046	if (fStrictCpuIdChecks) \
1047	{ \
1048	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1049	RTStrFree(pszMsg); \
1050	return rcCpuid; \
1051	} \
1052	LogRel(("CPUM: %s\n", pszMsg)); \
1053	RTStrFree(pszMsg); \
1054	} \
1055	} while (0)
1056	#define CPUID_CHECK_WRN(expr, fmt) \
1057	do { \
1058	if (!(expr)) \
1059	LogRel(fmt); \
1060	} while (0)
1061
1062	/* For comparing two values and bitch if they differs. */
1063	#define CPUID_CHECK2_RET(what, host, saved) \
1064	do { \
1065	if ((host) != (saved)) \
1066	{ \
1067	if (fStrictCpuIdChecks) \
1068	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1069	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1070	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1071	} \
1072	} while (0)
1073	#define CPUID_CHECK2_WRN(what, host, saved) \
1074	do { \
1075	if ((host) != (saved)) \
1076	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1077	} while (0)
1078
1079	/* For checking raw cpu features (raw mode). */
1080	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1081	do { \
1082	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1083	{ \
1084	if (fStrictCpuIdChecks) \
1085	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1086	N_(#bit " mismatch: host=%d saved=%d"), \
1087	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1088	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1089	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1090	} \
1091	} while (0)
1092	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1093	do { \
1094	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1095	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1096	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1097	} while (0)
1098	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1099
1100	/* For checking guest features. */
1101	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1102	do { \
1103	if ( (aGuestCpuId##set [1].reg & bit) \
1104	&& !(aHostRaw##set [1].reg & bit) \
1105	&& !(aHostOverride##set [1].reg & bit) \
1106	&& !(aGuestOverride##set [1].reg & bit) \
1107	) \
1108	{ \
1109	if (fStrictCpuIdChecks) \
1110	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1111	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1112	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1113	} \
1114	} while (0)
1115	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1116	do { \
1117	if ( (aGuestCpuId##set [1].reg & bit) \
1118	&& !(aHostRaw##set [1].reg & bit) \
1119	&& !(aHostOverride##set [1].reg & bit) \
1120	&& !(aGuestOverride##set [1].reg & bit) \
1121	) \
1122	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1123	} while (0)
1124	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1125	do { \
1126	if ( (aGuestCpuId##set [1].reg & bit) \
1127	&& !(aHostRaw##set [1].reg & bit) \
1128	&& !(aHostOverride##set [1].reg & bit) \
1129	&& !(aGuestOverride##set [1].reg & bit) \
1130	) \
1131	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1132	} while (0)
1133	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1134
1135	/* For checking guest features if AMD guest CPU. */
1136	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1137	do { \
1138	if ( (aGuestCpuId##set [1].reg & bit) \
1139	&& fGuestAmd \
1140	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1141	&& !(aHostOverride##set [1].reg & bit) \
1142	&& !(aGuestOverride##set [1].reg & bit) \
1143	) \
1144	{ \
1145	if (fStrictCpuIdChecks) \
1146	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1147	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1148	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1149	} \
1150	} while (0)
1151	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1152	do { \
1153	if ( (aGuestCpuId##set [1].reg & bit) \
1154	&& fGuestAmd \
1155	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1156	&& !(aHostOverride##set [1].reg & bit) \
1157	&& !(aGuestOverride##set [1].reg & bit) \
1158	) \
1159	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1160	} while (0)
1161	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1162	do { \
1163	if ( (aGuestCpuId##set [1].reg & bit) \
1164	&& fGuestAmd \
1165	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1166	&& !(aHostOverride##set [1].reg & bit) \
1167	&& !(aGuestOverride##set [1].reg & bit) \
1168	) \
1169	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1170	} while (0)
1171	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1172
1173	/* For checking AMD features which have a corresponding bit in the standard
1174	range. (Intel defines very few bits in the extended feature sets.) */
1175	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1176	do { \
1177	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1178	&& !(fHostAmd \
1179	? aHostRawExt[1].reg & (ExtBit) \
1180	: aHostRawStd[1].reg & (StdBit)) \
1181	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1182	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1183	) \
1184	{ \
1185	if (fStrictCpuIdChecks) \
1186	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1187	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1188	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1189	} \
1190	} while (0)
1191	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1192	do { \
1193	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1194	&& !(fHostAmd \
1195	? aHostRawExt[1].reg & (ExtBit) \
1196	: aHostRawStd[1].reg & (StdBit)) \
1197	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1198	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1199	) \
1200	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1201	} while (0)
1202	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1203	do { \
1204	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1205	&& !(fHostAmd \
1206	? aHostRawExt[1].reg & (ExtBit) \
1207	: aHostRawStd[1].reg & (StdBit)) \
1208	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1209	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1210	) \
1211	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1212	} while (0)
1213	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1214
1215	/*
1216	* Load them into stack buffers first.
1217	*/
1218	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1219	uint32_t cGuestCpuIdStd;
1220	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1221	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1222	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1223	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1224
1225	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1226	uint32_t cGuestCpuIdExt;
1227	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1228	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1229	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1230	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1231
1232	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1233	uint32_t cGuestCpuIdCentaur;
1234	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1235	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1236	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1237	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1238
1239	CPUMCPUID GuestCpuIdDef;
1240	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1241	AssertRCReturn(rc, rc);
1242
1243	CPUMCPUID aRawStd[16];
1244	uint32_t cRawStd;
1245	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1246	if (cRawStd > RT_ELEMENTS(aRawStd))
1247	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1248	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1249
1250	CPUMCPUID aRawExt[32];
1251	uint32_t cRawExt;
1252	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1253	if (cRawExt > RT_ELEMENTS(aRawExt))
1254	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1255	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1256	AssertRCReturn(rc, rc);
1257
1258	/*
1259	* Note that we support restoring less than the current amount of standard
1260	* leaves because we've been allowed more is newer version of VBox.
1261	*
1262	* So, pad new entries with the default.
1263	*/
1264	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1265	aGuestCpuIdStd[i] = GuestCpuIdDef;
1266
1267	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1268	aGuestCpuIdExt[i] = GuestCpuIdDef;
1269
1270	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1271	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1272
1273	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1274	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1275
1276	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1277	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1278
1279	/*
1280	* Get the raw CPU IDs for the current host.
1281	*/
1282	CPUMCPUID aHostRawStd[16];
1283	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1284	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1285
1286	CPUMCPUID aHostRawExt[32];
1287	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1288	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1289
1290	/*
1291	* Get the host and guest overrides so we don't reject the state because
1292	* some feature was enabled thru these interfaces.
1293	* Note! We currently only need the feature leafs, so skip rest.
1294	*/
1295	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1296	CPUMCPUID aGuestOverrideStd[2];
1297	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1298	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1299
1300	CPUMCPUID aGuestOverrideExt[2];
1301	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1302	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1303
1304	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1305	CPUMCPUID aHostOverrideStd[2];
1306	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1307	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1308
1309	CPUMCPUID aHostOverrideExt[2];
1310	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1311	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1312
1313	/*
1314	* This can be skipped.
1315	*/
1316	bool fStrictCpuIdChecks;
1317	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1318
1319
1320
1321	/*
1322	* For raw-mode we'll require that the CPUs are very similar since we don't
1323	* intercept CPUID instructions for user mode applications.
1324	*/
1325	if (!HWACCMIsEnabled(pVM))
1326	{
1327	/* CPUID(0) */
1328	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1329	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1330	&& aHostRawStd[0].edx == aRawStd[0].edx,
1331	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1332	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1333	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1334	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1335	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1336	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1337
1338	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1339
1340	/* CPUID(1).eax */
1341	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1342	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1343	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1344
1345	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1346	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1347	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1348
1349	/* CPUID(1).ecx */
1350	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1351	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1352	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1353	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1354	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1355	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1356	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1357	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1358	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1359	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1360	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1361	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1362	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1363	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1364	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1365	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1366	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1367	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1368	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1369	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1370	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1371	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1372	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1373	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1374	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1375	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1376	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1377	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1378	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1379	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1380	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1381	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1382
1383	/* CPUID(1).edx */
1384	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1385	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1386	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1387	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1388	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1389	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1390	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1391	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1392	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1393	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1394	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1395	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1396	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1397	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1398	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1399	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1400	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1401	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1402	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1403	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1404	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1405	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1406	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1407	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1408	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1409	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1410	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1411	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1412	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1413	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1414	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1415	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1416
1417	/* CPUID(2) - config, mostly about caches. ignore. */
1418	/* CPUID(3) - processor serial number. ignore. */
1419	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1420	/* CPUID(5) - mwait/monitor config. ignore. */
1421	/* CPUID(6) - power management. ignore. */
1422	/* CPUID(7) - ???. ignore. */
1423	/* CPUID(8) - ???. ignore. */
1424	/* CPUID(9) - DCA. ignore for now. */
1425	/* CPUID(a) - PeMo info. ignore for now. */
1426	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1427
1428	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1429	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1430	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1431	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1432	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1433	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1434	{
1435	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1436	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1437	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1438	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1439	}
1440
1441	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1442	Note! Intel have/is marking many of the fields here as reserved. We
1443	will verify them as if it's an AMD CPU. */
1444	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1445	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1446	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1447	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1448	{
1449	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1450	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1451	&& aHostRawExt[0].edx == aRawExt[0].edx,
1452	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1453	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1454	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1455	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1456
1457	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1458	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1459	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1460	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1461	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1462	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1463
1464	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1465	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1466	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1467	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1468
1469	/* CPUID(0x80000001).ecx */
1470	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1471	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1472	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1473	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1474	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1475	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1476	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1477	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1478	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1479	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1480	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1481	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1482	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1483	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1484	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1485	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1486	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1487	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1488	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1489	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1490	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1491	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1492	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1493	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1494	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1495	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1496	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1497	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1498	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1499	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1500	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1501	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1502
1503	/* CPUID(0x80000001).edx */
1504	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1505	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1506	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1507	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1508	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1509	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1510	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1511	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1512	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1513	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1514	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1515	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1516	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1517	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1518	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1519	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1520	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1521	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1522	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1523	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1524	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1525	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1526	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1527	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1528	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1529	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1530	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1531	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1532	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1533	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1534	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1535	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1536
1537	/** @todo verify the rest as well. */
1538	}
1539	}
1540
1541
1542
1543	/*
1544	* Verify that we can support the features already exposed to the guest on
1545	* this host.
1546	*
1547	* Most of the features we're emulating requires intercepting instruction
1548	* and doing it the slow way, so there is no need to warn when they aren't
1549	* present in the host CPU. Thus we use IGN instead of EMU on these.
1550	*
1551	* Trailing comments:
1552	* "EMU" - Possible to emulate, could be lots of work and very slow.
1553	* "EMU?" - Can this be emulated?
1554	*/
1555	/* CPUID(1).ecx */
1556	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1557	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1558	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1559	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1560	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1561	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1562	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1563	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1564	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1565	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1566	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1567	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1568	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1569	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1570	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1571	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1572	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1573	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1574	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1575	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1576	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1577	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1578	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1579	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1580	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1581	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1582	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1583	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1584	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1585	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1586	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1587	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1588
1589	/* CPUID(1).edx */
1590	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1591	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1592	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1593	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1594	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1595	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1596	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1597	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1598	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1599	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1600	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1601	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1602	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1603	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1604	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1605	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1606	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1607	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1608	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1609	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1610	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1611	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1612	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1613	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1614	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1615	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1616	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1617	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1618	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1619	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1620	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1621	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1622
1623	/* CPUID(0x80000000). */
1624	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1625	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1626	{
1627	/** @todo deal with no 0x80000001 on the host. */
1628	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1629	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1630
1631	/* CPUID(0x80000001).ecx */
1632	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1633	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1634	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1635	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1636	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1637	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1638	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1639	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1640	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1641	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1642	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1643	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1644	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1645	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1646	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1647	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1648	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1649	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1650	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1651	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1652	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1653	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1654	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1655	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1656	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1657	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1658	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1659	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1660	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1661	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1662	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1663	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1664
1665	/* CPUID(0x80000001).edx */
1666	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1667	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1668	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1669	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1670	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1671	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1672	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1673	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1674	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1675	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1676	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1677	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1678	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1679	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1680	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1681	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1682	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1683	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1684	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1685	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1686	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1687	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1688	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1689	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1690	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1691	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1692	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1693	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1694	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1695	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1696	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1697	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1698	}
1699
1700	/*
1701	* We're good, commit the CPU ID leaves.
1702	*/
1703	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1704	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1705	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1706	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1707
1708	#undef CPUID_CHECK_RET
1709	#undef CPUID_CHECK_WRN
1710	#undef CPUID_CHECK2_RET
1711	#undef CPUID_CHECK2_WRN
1712	#undef CPUID_RAW_FEATURE_RET
1713	#undef CPUID_RAW_FEATURE_WRN
1714	#undef CPUID_RAW_FEATURE_IGN
1715	#undef CPUID_GST_FEATURE_RET
1716	#undef CPUID_GST_FEATURE_WRN
1717	#undef CPUID_GST_FEATURE_EMU
1718	#undef CPUID_GST_FEATURE_IGN
1719	#undef CPUID_GST_FEATURE2_RET
1720	#undef CPUID_GST_FEATURE2_WRN
1721	#undef CPUID_GST_FEATURE2_EMU
1722	#undef CPUID_GST_FEATURE2_IGN
1723	#undef CPUID_GST_AMD_FEATURE_RET
1724	#undef CPUID_GST_AMD_FEATURE_WRN
1725	#undef CPUID_GST_AMD_FEATURE_EMU
1726	#undef CPUID_GST_AMD_FEATURE_IGN
1727
1728	return VINF_SUCCESS;
1729	}
1730
1731
1732	/**
1733	* Pass 0 live exec callback.
1734	*
1735	* @returns VINF_SSM_DONT_CALL_AGAIN.
1736	* @param pVM The VM handle.
1737	* @param pSSM The saved state handle.
1738	* @param uPass The pass (0).
1739	*/
1740	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1741	{
1742	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1743	cpumR3SaveCpuId(pVM, pSSM);
1744	return VINF_SSM_DONT_CALL_AGAIN;
1745	}
1746
1747
1748	/**
1749	* Execute state save operation.
1750	*
1751	* @returns VBox status code.
1752	* @param pVM VM Handle.
1753	* @param pSSM SSM operation handle.
1754	*/
1755	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1756	{
1757	/*
1758	* Save.
1759	*/
1760	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1761	{
1762	PVMCPU pVCpu = &pVM->aCpus[i];
1763
1764	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1765	}
1766
1767	SSMR3PutU32(pSSM, pVM->cCpus);
1768	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1769	{
1770	PVMCPU pVCpu = &pVM->aCpus[i];
1771
1772	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1773	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1774	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1775	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1776	}
1777
1778	cpumR3SaveCpuId(pVM, pSSM);
1779	return VINF_SUCCESS;
1780	}
1781
1782
1783	/**
1784	* Load a version 1.6 CPUMCTX structure.
1785	*
1786	* @returns VBox status code.
1787	* @param pVM VM Handle.
1788	* @param pCpumctx16 Version 1.6 CPUMCTX
1789	*/
1790	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1791	{
1792	#define CPUMCTX16_LOADREG(RegName) \
1793	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1794
1795	#define CPUMCTX16_LOADDRXREG(RegName) \
1796	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1797
1798	#define CPUMCTX16_LOADHIDREG(RegName) \
1799	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1800	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1801	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1802
1803	#define CPUMCTX16_LOADSEGREG(RegName) \
1804	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1805	CPUMCTX16_LOADHIDREG(RegName);
1806
1807	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1808
1809	CPUMCTX16_LOADREG(rax);
1810	CPUMCTX16_LOADREG(rbx);
1811	CPUMCTX16_LOADREG(rcx);
1812	CPUMCTX16_LOADREG(rdx);
1813	CPUMCTX16_LOADREG(rdi);
1814	CPUMCTX16_LOADREG(rsi);
1815	CPUMCTX16_LOADREG(rbp);
1816	CPUMCTX16_LOADREG(esp);
1817	CPUMCTX16_LOADREG(rip);
1818	CPUMCTX16_LOADREG(rflags);
1819
1820	CPUMCTX16_LOADSEGREG(cs);
1821	CPUMCTX16_LOADSEGREG(ds);
1822	CPUMCTX16_LOADSEGREG(es);
1823	CPUMCTX16_LOADSEGREG(fs);
1824	CPUMCTX16_LOADSEGREG(gs);
1825	CPUMCTX16_LOADSEGREG(ss);
1826
1827	CPUMCTX16_LOADREG(r8);
1828	CPUMCTX16_LOADREG(r9);
1829	CPUMCTX16_LOADREG(r10);
1830	CPUMCTX16_LOADREG(r11);
1831	CPUMCTX16_LOADREG(r12);
1832	CPUMCTX16_LOADREG(r13);
1833	CPUMCTX16_LOADREG(r14);
1834	CPUMCTX16_LOADREG(r15);
1835
1836	CPUMCTX16_LOADREG(cr0);
1837	CPUMCTX16_LOADREG(cr2);
1838	CPUMCTX16_LOADREG(cr3);
1839	CPUMCTX16_LOADREG(cr4);
1840
1841	CPUMCTX16_LOADDRXREG(0);
1842	CPUMCTX16_LOADDRXREG(1);
1843	CPUMCTX16_LOADDRXREG(2);
1844	CPUMCTX16_LOADDRXREG(3);
1845	CPUMCTX16_LOADDRXREG(4);
1846	CPUMCTX16_LOADDRXREG(5);
1847	CPUMCTX16_LOADDRXREG(6);
1848	CPUMCTX16_LOADDRXREG(7);
1849
1850	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1851	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1852	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1853	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1854
1855	CPUMCTX16_LOADREG(ldtr);
1856	CPUMCTX16_LOADREG(tr);
1857
1858	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1859
1860	CPUMCTX16_LOADREG(msrEFER);
1861	CPUMCTX16_LOADREG(msrSTAR);
1862	CPUMCTX16_LOADREG(msrPAT);
1863	CPUMCTX16_LOADREG(msrLSTAR);
1864	CPUMCTX16_LOADREG(msrCSTAR);
1865	CPUMCTX16_LOADREG(msrSFMASK);
1866	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1867
1868	CPUMCTX16_LOADHIDREG(ldtr);
1869	CPUMCTX16_LOADHIDREG(tr);
1870
1871	#undef CPUMCTX16_LOADSEGREG
1872	#undef CPUMCTX16_LOADHIDREG
1873	#undef CPUMCTX16_LOADDRXREG
1874	#undef CPUMCTX16_LOADREG
1875	}
1876
1877
1878	/**
1879	* @copydoc FNSSMINTLOADPREP
1880	*/
1881	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1882	{
1883	pVM->cpum.s.fPendingRestore = true;
1884	return VINF_SUCCESS;
1885	}
1886
1887
1888	/**
1889	* @copydoc FNSSMINTLOADEXEC
1890	*/
1891	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1892	{
1893	/*
1894	* Validate version.
1895	*/
1896	if ( uVersion != CPUM_SAVED_STATE_VERSION
1897	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1898	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1899	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1900	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1901	{
1902	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1903	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1904	}
1905
1906	if (uPass == SSM_PASS_FINAL)
1907	{
1908	/*
1909	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1910	* really old SSM file versions.)
1911	*/
1912	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1913	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1914	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1915	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1916
1917	/*
1918	* Restore.
1919	*/
1920	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1921	{
1922	PVMCPU pVCpu = &pVM->aCpus[i];
1923	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1924	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1925
1926	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1927	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1928	pVCpu->cpum.s.Hyper.esp = uESP;
1929	}
1930
1931	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1932	{
1933	CPUMCTX_VER1_6 cpumctx16;
1934	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1935	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1936
1937	/* Save the old cpumctx state into the new one. */
1938	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1939
1940	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1941	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1942	}
1943	else
1944	{
1945	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1946	{
1947	uint32_t cCpus;
1948	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1949	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1950	VERR_SSM_UNEXPECTED_DATA);
1951	}
1952	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1953	\|\| pVM->cCpus == 1,
1954	("cCpus=%u\n", pVM->cCpus),
1955	VERR_SSM_UNEXPECTED_DATA);
1956
1957	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1958	{
1959	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1960	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1961	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1962	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1963	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1964	}
1965	}
1966	}
1967
1968	pVM->cpum.s.fPendingRestore = false;
1969
1970	/*
1971	* Guest CPUIDs.
1972	*/
1973	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1974	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1975
1976	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1977	* actually required. */
1978
1979	/*
1980	* Restore the CPUID leaves.
1981	*
1982	* Note that we support restoring less than the current amount of standard
1983	* leaves because we've been allowed more is newer version of VBox.
1984	*/
1985	uint32_t cElements;
1986	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1987	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1988	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1989	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1990
1991	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1992	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1993	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1994	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1995
1996	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1997	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1998	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1999	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2000
2001	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2002
2003	/*
2004	* Check that the basic cpuid id information is unchanged.
2005	*/
2006	/** @todo we should check the 64 bits capabilities too! */
2007	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2008	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2009	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2010	uint32_t au32CpuIdSaved[8];
2011	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2012	if (RT_SUCCESS(rc))
2013	{
2014	/* Ignore CPU stepping. */
2015	au32CpuId[4] &= 0xfffffff0;
2016	au32CpuIdSaved[4] &= 0xfffffff0;
2017
2018	/* Ignore APIC ID (AMD specs). */
2019	au32CpuId[5] &= ~0xff000000;
2020	au32CpuIdSaved[5] &= ~0xff000000;
2021
2022	/* Ignore the number of Logical CPUs (AMD specs). */
2023	au32CpuId[5] &= ~0x00ff0000;
2024	au32CpuIdSaved[5] &= ~0x00ff0000;
2025
2026	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2027	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2028	\| X86_CPUID_FEATURE_ECX_VMX
2029	\| X86_CPUID_FEATURE_ECX_SMX
2030	\| X86_CPUID_FEATURE_ECX_EST
2031	\| X86_CPUID_FEATURE_ECX_TM2
2032	\| X86_CPUID_FEATURE_ECX_CNTXID
2033	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2034	\| X86_CPUID_FEATURE_ECX_PDCM
2035	\| X86_CPUID_FEATURE_ECX_DCA
2036	\| X86_CPUID_FEATURE_ECX_X2APIC
2037	);
2038	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2039	\| X86_CPUID_FEATURE_ECX_VMX
2040	\| X86_CPUID_FEATURE_ECX_SMX
2041	\| X86_CPUID_FEATURE_ECX_EST
2042	\| X86_CPUID_FEATURE_ECX_TM2
2043	\| X86_CPUID_FEATURE_ECX_CNTXID
2044	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2045	\| X86_CPUID_FEATURE_ECX_PDCM
2046	\| X86_CPUID_FEATURE_ECX_DCA
2047	\| X86_CPUID_FEATURE_ECX_X2APIC
2048	);
2049
2050	/* Make sure we don't forget to update the masks when enabling
2051	* features in the future.
2052	*/
2053	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2054	( X86_CPUID_FEATURE_ECX_DTES64
2055	\| X86_CPUID_FEATURE_ECX_VMX
2056	\| X86_CPUID_FEATURE_ECX_SMX
2057	\| X86_CPUID_FEATURE_ECX_EST
2058	\| X86_CPUID_FEATURE_ECX_TM2
2059	\| X86_CPUID_FEATURE_ECX_CNTXID
2060	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2061	\| X86_CPUID_FEATURE_ECX_PDCM
2062	\| X86_CPUID_FEATURE_ECX_DCA
2063	\| X86_CPUID_FEATURE_ECX_X2APIC
2064	)));
2065	/* do the compare */
2066	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2067	{
2068	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2069	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2070	"Saved=%.*Rhxs\n"
2071	"Real =%.*Rhxs\n",
2072	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2073	sizeof(au32CpuId), au32CpuId));
2074	else
2075	{
2076	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2077	"Saved=%.*Rhxs\n"
2078	"Real =%.*Rhxs\n",
2079	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2080	sizeof(au32CpuId), au32CpuId));
2081	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2082	}
2083	}
2084	}
2085
2086	return rc;
2087	}
2088
2089
2090	/**
2091	* @copydoc FNSSMINTLOADPREP
2092	*/
2093	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2094	{
2095	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2096	return VINF_SUCCESS;
2097
2098	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2099	if (pVM->cpum.s.fPendingRestore)
2100	{
2101	LogRel(("CPUM: Missing state!\n"));
2102	return VERR_INTERNAL_ERROR_2;
2103	}
2104
2105	return VINF_SUCCESS;
2106	}
2107
2108
2109	/**
2110	* Checks if the CPUM state restore is still pending.
2111	*
2112	* @returns true / false.
2113	* @param pVM The VM handle.
2114	*/
2115	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2116	{
2117	return pVM->cpum.s.fPendingRestore;
2118	}
2119
2120
2121	/**
2122	* Formats the EFLAGS value into mnemonics.
2123	*
2124	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2125	* @param efl The EFLAGS value.
2126	*/
2127	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2128	{
2129	/*
2130	* Format the flags.
2131	*/
2132	static const struct
2133	{
2134	const char pszSet; const char pszClear; uint32_t fFlag;
2135	} s_aFlags[] =
2136	{
2137	{ "vip",NULL, X86_EFL_VIP },
2138	{ "vif",NULL, X86_EFL_VIF },
2139	{ "ac", NULL, X86_EFL_AC },
2140	{ "vm", NULL, X86_EFL_VM },
2141	{ "rf", NULL, X86_EFL_RF },
2142	{ "nt", NULL, X86_EFL_NT },
2143	{ "ov", "nv", X86_EFL_OF },
2144	{ "dn", "up", X86_EFL_DF },
2145	{ "ei", "di", X86_EFL_IF },
2146	{ "tf", NULL, X86_EFL_TF },
2147	{ "nt", "pl", X86_EFL_SF },
2148	{ "nz", "zr", X86_EFL_ZF },
2149	{ "ac", "na", X86_EFL_AF },
2150	{ "po", "pe", X86_EFL_PF },
2151	{ "cy", "nc", X86_EFL_CF },
2152	};
2153	char *psz = pszEFlags;
2154	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2155	{
2156	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2157	if (pszAdd)
2158	{
2159	strcpy(psz, pszAdd);
2160	psz += strlen(pszAdd);
2161	*psz++ = ' ';
2162	}
2163	}
2164	psz[-1] = '\0';
2165	}
2166
2167
2168	/**
2169	* Formats a full register dump.
2170	*
2171	* @param pVM VM Handle.
2172	* @param pCtx The context to format.
2173	* @param pCtxCore The context core to format.
2174	* @param pHlp Output functions.
2175	* @param enmType The dump type.
2176	* @param pszPrefix Register name prefix.
2177	*/
2178	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2179	{
2180	/*
2181	* Format the EFLAGS.
2182	*/
2183	uint32_t efl = pCtxCore->eflags.u32;
2184	char szEFlags[80];
2185	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2186
2187	/*
2188	* Format the registers.
2189	*/
2190	switch (enmType)
2191	{
2192	case CPUMDUMPTYPE_TERSE:
2193	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2194	pHlp->pfnPrintf(pHlp,
2195	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2196	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2197	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2198	"%sr14=%016RX64 %sr15=%016RX64\n"
2199	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2200	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2201	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2202	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2203	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2204	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2205	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2206	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2207	else
2208	pHlp->pfnPrintf(pHlp,
2209	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2210	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2211	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2212	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2213	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2214	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2215	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2216	break;
2217
2218	case CPUMDUMPTYPE_DEFAULT:
2219	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2220	pHlp->pfnPrintf(pHlp,
2221	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2222	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2223	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2224	"%sr14=%016RX64 %sr15=%016RX64\n"
2225	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2226	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2227	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2228	,
2229	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2230	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2231	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2232	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2233	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2234	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2235	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2236	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2237	else
2238	pHlp->pfnPrintf(pHlp,
2239	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2240	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2241	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2242	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2243	,
2244	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2245	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2246	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2247	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2248	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2249	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2250	break;
2251
2252	case CPUMDUMPTYPE_VERBOSE:
2253	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2254	pHlp->pfnPrintf(pHlp,
2255	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2256	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2257	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2258	"%sr14=%016RX64 %sr15=%016RX64\n"
2259	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2260	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2261	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2262	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2263	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2264	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2265	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2266	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2267	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2268	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2269	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2270	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2271	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2272	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2273	,
2274	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2275	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2276	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2277	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2278	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2279	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2280	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2281	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2282	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2283	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2284	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2285	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2286	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2287	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2288	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2289	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2290	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2291	else
2292	pHlp->pfnPrintf(pHlp,
2293	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2294	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2295	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2296	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2297	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2298	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2299	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2300	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2301	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2302	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2303	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2304	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2305	,
2306	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2307	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2308	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2309	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2310	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2311	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2312	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2313	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2314	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2315	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2316	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2317	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2318
2319	pHlp->pfnPrintf(pHlp,
2320	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2321	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2322	,
2323	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2324	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2325	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2326	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2327	);
2328	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2329	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2330	{
2331	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2332	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2333	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2334	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2335	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2336	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2337	/** @todo This isn't entirenly correct and needs more work! */
2338	pHlp->pfnPrintf(pHlp,
2339	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2340	pszPrefix, iST, pszPrefix, iFPR,
2341	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2342	uTag, chSign, iInteger, u64Fraction, uExponent);
2343	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2344	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2345	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2346	else
2347	pHlp->pfnPrintf(pHlp, "\n");
2348	}
2349	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2350	pHlp->pfnPrintf(pHlp,
2351	iXMM & 1
2352	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2353	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2354	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2355	pCtx->fpu.aXMM[iXMM].au32[3],
2356	pCtx->fpu.aXMM[iXMM].au32[2],
2357	pCtx->fpu.aXMM[iXMM].au32[1],
2358	pCtx->fpu.aXMM[iXMM].au32[0]);
2359	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2360	if (pCtx->fpu.au32RsrvdRest[i])
2361	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2362	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2363
2364	pHlp->pfnPrintf(pHlp,
2365	"%sEFER =%016RX64\n"
2366	"%sPAT =%016RX64\n"
2367	"%sSTAR =%016RX64\n"
2368	"%sCSTAR =%016RX64\n"
2369	"%sLSTAR =%016RX64\n"
2370	"%sSFMASK =%016RX64\n"
2371	"%sKERNELGSBASE =%016RX64\n",
2372	pszPrefix, pCtx->msrEFER,
2373	pszPrefix, pCtx->msrPAT,
2374	pszPrefix, pCtx->msrSTAR,
2375	pszPrefix, pCtx->msrCSTAR,
2376	pszPrefix, pCtx->msrLSTAR,
2377	pszPrefix, pCtx->msrSFMASK,
2378	pszPrefix, pCtx->msrKERNELGSBASE);
2379	break;
2380	}
2381	}
2382
2383
2384	/**
2385	* Display all cpu states and any other cpum info.
2386	*
2387	* @param pVM VM Handle.
2388	* @param pHlp The info helper functions.
2389	* @param pszArgs Arguments, ignored.
2390	*/
2391	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2392	{
2393	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2394	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2395	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2396	cpumR3InfoHost(pVM, pHlp, pszArgs);
2397	}
2398
2399
2400	/**
2401	* Parses the info argument.
2402	*
2403	* The argument starts with 'verbose', 'terse' or 'default' and then
2404	* continues with the comment string.
2405	*
2406	* @param pszArgs The pointer to the argument string.
2407	* @param penmType Where to store the dump type request.
2408	* @param ppszComment Where to store the pointer to the comment string.
2409	*/
2410	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2411	{
2412	if (!pszArgs)
2413	{
2414	*penmType = CPUMDUMPTYPE_DEFAULT;
2415	*ppszComment = "";
2416	}
2417	else
2418	{
2419	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2420	{
2421	pszArgs += 5;
2422	*penmType = CPUMDUMPTYPE_VERBOSE;
2423	}
2424	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2425	{
2426	pszArgs += 5;
2427	*penmType = CPUMDUMPTYPE_TERSE;
2428	}
2429	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2430	{
2431	pszArgs += 7;
2432	*penmType = CPUMDUMPTYPE_DEFAULT;
2433	}
2434	else
2435	*penmType = CPUMDUMPTYPE_DEFAULT;
2436	*ppszComment = RTStrStripL(pszArgs);
2437	}
2438	}
2439
2440
2441	/**
2442	* Display the guest cpu state.
2443	*
2444	* @param pVM VM Handle.
2445	* @param pHlp The info helper functions.
2446	* @param pszArgs Arguments, ignored.
2447	*/
2448	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2449	{
2450	CPUMDUMPTYPE enmType;
2451	const char *pszComment;
2452	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2453
2454	/* @todo SMP support! */
2455	PVMCPU pVCpu = VMMGetCpu(pVM);
2456	if (!pVCpu)
2457	pVCpu = &pVM->aCpus[0];
2458
2459	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2460
2461	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2462	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2463	}
2464
2465
2466	/**
2467	* Display the current guest instruction
2468	*
2469	* @param pVM VM Handle.
2470	* @param pHlp The info helper functions.
2471	* @param pszArgs Arguments, ignored.
2472	*/
2473	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2474	{
2475	char szInstruction[256];
2476	/* @todo SMP support! */
2477	PVMCPU pVCpu = VMMGetCpu(pVM);
2478	if (!pVCpu)
2479	pVCpu = &pVM->aCpus[0];
2480
2481	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2482	if (RT_SUCCESS(rc))
2483	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2484	}
2485
2486
2487	/**
2488	* Display the hypervisor cpu state.
2489	*
2490	* @param pVM VM Handle.
2491	* @param pHlp The info helper functions.
2492	* @param pszArgs Arguments, ignored.
2493	*/
2494	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2495	{
2496	CPUMDUMPTYPE enmType;
2497	const char *pszComment;
2498	/* @todo SMP */
2499	PVMCPU pVCpu = &pVM->aCpus[0];
2500
2501	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2502	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2503	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2504	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2505	}
2506
2507
2508	/**
2509	* Display the host cpu state.
2510	*
2511	* @param pVM VM Handle.
2512	* @param pHlp The info helper functions.
2513	* @param pszArgs Arguments, ignored.
2514	*/
2515	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2516	{
2517	CPUMDUMPTYPE enmType;
2518	const char *pszComment;
2519	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2520	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2521
2522	/*
2523	* Format the EFLAGS.
2524	*/
2525	/* @todo SMP */
2526	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2527	#if HC_ARCH_BITS == 32
2528	uint32_t efl = pCtx->eflags.u32;
2529	#else
2530	uint64_t efl = pCtx->rflags;
2531	#endif
2532	char szEFlags[80];
2533	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2534
2535	/*
2536	* Format the registers.
2537	*/
2538	#if HC_ARCH_BITS == 32
2539	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2540	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2541	# endif
2542	{
2543	pHlp->pfnPrintf(pHlp,
2544	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2545	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2546	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2547	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2548	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2549	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2550	,
2551	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2552	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2553	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2554	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2555	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2556	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2557	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2558	}
2559	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2560	else
2561	# endif
2562	#endif
2563	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2564	{
2565	pHlp->pfnPrintf(pHlp,
2566	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2567	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2568	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2569	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2570	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2571	"r14=%016RX64 r15=%016RX64\n"
2572	"iopl=%d %31s\n"
2573	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2574	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2575	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2576	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2577	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2578	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2579	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2580	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2581	,
2582	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2583	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2584	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2585	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2586	pCtx->r11, pCtx->r12, pCtx->r13,
2587	pCtx->r14, pCtx->r15,
2588	X86_EFL_GET_IOPL(efl), szEFlags,
2589	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2590	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2591	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2592	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2593	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2594	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2595	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2596	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2597	}
2598	#endif
2599	}
2600
2601
2602	/**
2603	* Get L1 cache / TLS associativity.
2604	*/
2605	static const char getCacheAss(unsigned u, char pszBuf)
2606	{
2607	if (u == 0)
2608	return "res0 ";
2609	if (u == 1)
2610	return "direct";
2611	if (u >= 256)
2612	return "???";
2613
2614	RTStrPrintf(pszBuf, 16, "%d way", u);
2615	return pszBuf;
2616	}
2617
2618
2619	/**
2620	* Get L2 cache soociativity.
2621	*/
2622	const char *getL2CacheAss(unsigned u)
2623	{
2624	switch (u)
2625	{
2626	case 0: return "off ";
2627	case 1: return "direct";
2628	case 2: return "2 way ";
2629	case 3: return "res3 ";
2630	case 4: return "4 way ";
2631	case 5: return "res5 ";
2632	case 6: return "8 way "; case 7: return "res7 ";
2633	case 8: return "16 way";
2634	case 9: return "res9 ";
2635	case 10: return "res10 ";
2636	case 11: return "res11 ";
2637	case 12: return "res12 ";
2638	case 13: return "res13 ";
2639	case 14: return "res14 ";
2640	case 15: return "fully ";
2641	default:
2642	return "????";
2643	}
2644	}
2645
2646
2647	/**
2648	* Display the guest CpuId leaves.
2649	*
2650	* @param pVM VM Handle.
2651	* @param pHlp The info helper functions.
2652	* @param pszArgs "terse", "default" or "verbose".
2653	*/
2654	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2655	{
2656	/*
2657	* Parse the argument.
2658	*/
2659	unsigned iVerbosity = 1;
2660	if (pszArgs)
2661	{
2662	pszArgs = RTStrStripL(pszArgs);
2663	if (!strcmp(pszArgs, "terse"))
2664	iVerbosity--;
2665	else if (!strcmp(pszArgs, "verbose"))
2666	iVerbosity++;
2667	}
2668
2669	/*
2670	* Start cracking.
2671	*/
2672	CPUMCPUID Host;
2673	CPUMCPUID Guest;
2674	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2675
2676	pHlp->pfnPrintf(pHlp,
2677	" RAW Standard CPUIDs\n"
2678	" Function eax ebx ecx edx\n");
2679	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2680	{
2681	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2682	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2683
2684	pHlp->pfnPrintf(pHlp,
2685	"Gst: %08x %08x %08x %08x %08x%s\n"
2686	"Hst: %08x %08x %08x %08x\n",
2687	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2688	i <= cStdMax ? "" : "*",
2689	Host.eax, Host.ebx, Host.ecx, Host.edx);
2690	}
2691
2692	/*
2693	* If verbose, decode it.
2694	*/
2695	if (iVerbosity)
2696	{
2697	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2698	pHlp->pfnPrintf(pHlp,
2699	"Name: %.04s%.04s%.04s\n"
2700	"Supports: 0-%x\n",
2701	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2702	}
2703
2704	/*
2705	* Get Features.
2706	*/
2707	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2708	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2709	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2710	if (cStdMax >= 1 && iVerbosity)
2711	{
2712	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2713	uint32_t uEAX = Guest.eax;
2714
2715	pHlp->pfnPrintf(pHlp,
2716	"Family: %d \tExtended: %d \tEffective: %d\n"
2717	"Model: %d \tExtended: %d \tEffective: %d\n"
2718	"Stepping: %d\n"
2719	"Type: %d\n"
2720	"APIC ID: %#04x\n"
2721	"Logical CPUs: %d\n"
2722	"CLFLUSH Size: %d\n"
2723	"Brand ID: %#04x\n",
2724	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2725	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2726	ASMGetCpuStepping(uEAX),
2727	(uEAX >> 12) & 3,
2728	(Guest.ebx >> 24) & 0xff,
2729	(Guest.ebx >> 16) & 0xff,
2730	(Guest.ebx >> 8) & 0xff,
2731	(Guest.ebx >> 0) & 0xff);
2732	if (iVerbosity == 1)
2733	{
2734	uint32_t uEDX = Guest.edx;
2735	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2736	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2737	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2738	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2739	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2740	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2741	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2742	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2743	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2744	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2745	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2746	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2747	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2748	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2749	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2750	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2751	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2752	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2753	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2754	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2755	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2756	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2757	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2758	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2759	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2760	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2761	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2762	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2763	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2764	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2765	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2766	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2767	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2768	pHlp->pfnPrintf(pHlp, "\n");
2769
2770	uint32_t uECX = Guest.ecx;
2771	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2772	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2773	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2774	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2775	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2776	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2777	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2778	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2779	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2780	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2781	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2782	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2783	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2784	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2785	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2786	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2787	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2788	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2789	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2790	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2791	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2792	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2793	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2794	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2795	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2796	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2797	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2798	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2799	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2800	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2801	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2802	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2803	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2804	pHlp->pfnPrintf(pHlp, "\n");
2805	}
2806	else
2807	{
2808	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2809
2810	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2811	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2812	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2813	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2814
2815	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2816	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2817	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2818	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2819	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2820	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2821	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2822	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2823	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2824	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2825	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2826	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2827	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2828	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2829	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2830	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2831	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2832	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2833	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2834	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2835	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2836	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2837	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2838	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2839	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2840	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2841	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2842	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2843	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2844	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2845	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2846	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2847	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2848
2849	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2850	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2851	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2852	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2853	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2854	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2855	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2856	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2857	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2858	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2859	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2860	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2861	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2862	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2863	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2864	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2865	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2866	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2867	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2868	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2869	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2870	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2871	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2872	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2873	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2874	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2875	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2876	}
2877	}
2878	if (cStdMax >= 2 && iVerbosity)
2879	{
2880	/** @todo */
2881	}
2882
2883	/*
2884	* Extended.
2885	* Implemented after AMD specs.
2886	*/
2887	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2888
2889	pHlp->pfnPrintf(pHlp,
2890	"\n"
2891	" RAW Extended CPUIDs\n"
2892	" Function eax ebx ecx edx\n");
2893	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2894	{
2895	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2896	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2897
2898	pHlp->pfnPrintf(pHlp,
2899	"Gst: %08x %08x %08x %08x %08x%s\n"
2900	"Hst: %08x %08x %08x %08x\n",
2901	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2902	i <= cExtMax ? "" : "*",
2903	Host.eax, Host.ebx, Host.ecx, Host.edx);
2904	}
2905
2906	/*
2907	* Understandable output
2908	*/
2909	if (iVerbosity)
2910	{
2911	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2912	pHlp->pfnPrintf(pHlp,
2913	"Ext Name: %.4s%.4s%.4s\n"
2914	"Ext Supports: 0x80000000-%#010x\n",
2915	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2916	}
2917
2918	if (iVerbosity && cExtMax >= 1)
2919	{
2920	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2921	uint32_t uEAX = Guest.eax;
2922	pHlp->pfnPrintf(pHlp,
2923	"Family: %d \tExtended: %d \tEffective: %d\n"
2924	"Model: %d \tExtended: %d \tEffective: %d\n"
2925	"Stepping: %d\n"
2926	"Brand ID: %#05x\n",
2927	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2928	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2929	ASMGetCpuStepping(uEAX),
2930	Guest.ebx & 0xfff);
2931
2932	if (iVerbosity == 1)
2933	{
2934	uint32_t uEDX = Guest.edx;
2935	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2936	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2937	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2938	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2939	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2940	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2941	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2942	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2943	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2944	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2945	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2946	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2947	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2948	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2949	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2950	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2951	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2952	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2953	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2954	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2955	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2956	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2957	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2958	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2959	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2960	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2961	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2962	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2963	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2964	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2965	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2966	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2967	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2968	pHlp->pfnPrintf(pHlp, "\n");
2969
2970	uint32_t uECX = Guest.ecx;
2971	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2972	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2973	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2974	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2975	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2976	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2977	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2978	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2979	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2980	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2981	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2982	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2983	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2984	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2985	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2986	for (unsigned iBit = 5; iBit < 32; iBit++)
2987	if (uECX & RT_BIT(iBit))
2988	pHlp->pfnPrintf(pHlp, " %d", iBit);
2989	pHlp->pfnPrintf(pHlp, "\n");
2990	}
2991	else
2992	{
2993	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2994
2995	uint32_t uEdxGst = Guest.edx;
2996	uint32_t uEdxHst = Host.edx;
2997	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2998	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2999	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3000	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3001	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3002	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3003	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3004	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3005	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3006	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3007	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3008	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3009	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3010	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3011	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3012	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3013	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3014	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3015	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3016	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3017	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3018	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3019	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3020	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3021	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3022	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3023	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3024	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3025	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3026	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3027	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3028	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3029	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3030
3031	uint32_t uEcxGst = Guest.ecx;
3032	uint32_t uEcxHst = Host.ecx;
3033	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3034	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3035	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3036	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3037	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3038	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3039	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3040	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3041	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3042	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3043	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3044	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3045	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3046	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3047	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3048	}
3049	}
3050
3051	if (iVerbosity && cExtMax >= 2)
3052	{
3053	char szString[443+1] = {0};
3054	uint32_t pu32 = (uint32_t )szString;
3055	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3056	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3057	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3058	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3059	if (cExtMax >= 3)
3060	{
3061	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3062	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3063	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3064	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3065	}
3066	if (cExtMax >= 4)
3067	{
3068	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3069	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3070	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3071	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3072	}
3073	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3074	}
3075
3076	if (iVerbosity && cExtMax >= 5)
3077	{
3078	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3079	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3080	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3081	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3082	char sz1[32];
3083	char sz2[32];
3084
3085	pHlp->pfnPrintf(pHlp,
3086	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3087	"TLB 2/4M Data: %s %3d entries\n",
3088	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3089	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3090	pHlp->pfnPrintf(pHlp,
3091	"TLB 4K Instr/Uni: %s %3d entries\n"
3092	"TLB 4K Data: %s %3d entries\n",
3093	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3094	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3095	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3096	"L1 Instr Cache Lines Per Tag: %d\n"
3097	"L1 Instr Cache Associativity: %s\n"
3098	"L1 Instr Cache Size: %d KB\n",
3099	(uEDX >> 0) & 0xff,
3100	(uEDX >> 8) & 0xff,
3101	getCacheAss((uEDX >> 16) & 0xff, sz1),
3102	(uEDX >> 24) & 0xff);
3103	pHlp->pfnPrintf(pHlp,
3104	"L1 Data Cache Line Size: %d bytes\n"
3105	"L1 Data Cache Lines Per Tag: %d\n"
3106	"L1 Data Cache Associativity: %s\n"
3107	"L1 Data Cache Size: %d KB\n",
3108	(uECX >> 0) & 0xff,
3109	(uECX >> 8) & 0xff,
3110	getCacheAss((uECX >> 16) & 0xff, sz1),
3111	(uECX >> 24) & 0xff);
3112	}
3113
3114	if (iVerbosity && cExtMax >= 6)
3115	{
3116	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3117	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3118	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3119
3120	pHlp->pfnPrintf(pHlp,
3121	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3122	"L2 TLB 2/4M Data: %s %4d entries\n",
3123	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3124	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3125	pHlp->pfnPrintf(pHlp,
3126	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3127	"L2 TLB 4K Data: %s %4d entries\n",
3128	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3129	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3130	pHlp->pfnPrintf(pHlp,
3131	"L2 Cache Line Size: %d bytes\n"
3132	"L2 Cache Lines Per Tag: %d\n"
3133	"L2 Cache Associativity: %s\n"
3134	"L2 Cache Size: %d KB\n",
3135	(uEDX >> 0) & 0xff,
3136	(uEDX >> 8) & 0xf,
3137	getL2CacheAss((uEDX >> 12) & 0xf),
3138	(uEDX >> 16) & 0xffff);
3139	}
3140
3141	if (iVerbosity && cExtMax >= 7)
3142	{
3143	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3144
3145	pHlp->pfnPrintf(pHlp, "APM Features: ");
3146	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3147	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3148	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3149	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3150	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3151	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3152	for (unsigned iBit = 6; iBit < 32; iBit++)
3153	if (uEDX & RT_BIT(iBit))
3154	pHlp->pfnPrintf(pHlp, " %d", iBit);
3155	pHlp->pfnPrintf(pHlp, "\n");
3156	}
3157
3158	if (iVerbosity && cExtMax >= 8)
3159	{
3160	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3161	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3162
3163	pHlp->pfnPrintf(pHlp,
3164	"Physical Address Width: %d bits\n"
3165	"Virtual Address Width: %d bits\n",
3166	(uEAX >> 0) & 0xff,
3167	(uEAX >> 8) & 0xff);
3168	pHlp->pfnPrintf(pHlp,
3169	"Physical Core Count: %d\n",
3170	(uECX >> 0) & 0xff);
3171	}
3172
3173
3174	/*
3175	* Centaur.
3176	*/
3177	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3178
3179	pHlp->pfnPrintf(pHlp,
3180	"\n"
3181	" RAW Centaur CPUIDs\n"
3182	" Function eax ebx ecx edx\n");
3183	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3184	{
3185	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3186	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3187
3188	pHlp->pfnPrintf(pHlp,
3189	"Gst: %08x %08x %08x %08x %08x%s\n"
3190	"Hst: %08x %08x %08x %08x\n",
3191	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3192	i <= cCentaurMax ? "" : "*",
3193	Host.eax, Host.ebx, Host.ecx, Host.edx);
3194	}
3195
3196	/*
3197	* Understandable output
3198	*/
3199	if (iVerbosity)
3200	{
3201	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3202	pHlp->pfnPrintf(pHlp,
3203	"Centaur Supports: 0xc0000000-%#010x\n",
3204	Guest.eax);
3205	}
3206
3207	if (iVerbosity && cCentaurMax >= 1)
3208	{
3209	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3210	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3211	uint32_t uEdxHst = Host.edx;
3212
3213	if (iVerbosity == 1)
3214	{
3215	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3216	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3217	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3218	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3219	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3220	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3221	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3222	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3223	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3224	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3225	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3226	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3227	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3228	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3229	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3230	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3231	for (unsigned iBit = 14; iBit < 32; iBit++)
3232	if (uEdxGst & RT_BIT(iBit))
3233	pHlp->pfnPrintf(pHlp, " %d", iBit);
3234	pHlp->pfnPrintf(pHlp, "\n");
3235	}
3236	else
3237	{
3238	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3239	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3240	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3241	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3242	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3243	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3244	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3245	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3246	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3247	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3248	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3249	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3250	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3251	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3252	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3253	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3254	for (unsigned iBit = 14; iBit < 32; iBit++)
3255	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3256	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3257	pHlp->pfnPrintf(pHlp, "\n");
3258	}
3259	}
3260	}
3261
3262
3263	/**
3264	* Structure used when disassembling and instructions in DBGF.
3265	* This is used so the reader function can get the stuff it needs.
3266	*/
3267	typedef struct CPUMDISASSTATE
3268	{
3269	/** Pointer to the CPU structure. */
3270	PDISCPUSTATE pCpu;
3271	/** The VM handle. */
3272	PVM pVM;
3273	/** The VMCPU handle. */
3274	PVMCPU pVCpu;
3275	/** Pointer to the first byte in the segemnt. */
3276	RTGCUINTPTR GCPtrSegBase;
3277	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3278	RTGCUINTPTR GCPtrSegEnd;
3279	/** The size of the segment minus 1. */
3280	RTGCUINTPTR cbSegLimit;
3281	/** Pointer to the current page - R3 Ptr. */
3282	void const *pvPageR3;
3283	/** Pointer to the current page - GC Ptr. */
3284	RTGCPTR pvPageGC;
3285	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3286	PGMPAGEMAPLOCK PageMapLock;
3287	/** Whether the PageMapLock is valid or not. */
3288	bool fLocked;
3289	/** 64 bits mode or not. */
3290	bool f64Bits;
3291	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3292
3293
3294	/**
3295	* Instruction reader.
3296	*
3297	* @returns VBox status code.
3298	* @param PtrSrc Address to read from.
3299	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3300	* @param pu8Dst Where to store the bytes.
3301	* @param cbRead Number of bytes to read.
3302	* @param uDisCpu Pointer to the disassembler cpu state.
3303	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3304	*/
3305	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3306	{
3307	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3308	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3309	Assert(cbRead > 0);
3310	for (;;)
3311	{
3312	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3313
3314	/* Need to update the page translation? */
3315	if ( !pState->pvPageR3
3316	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3317	{
3318	int rc = VINF_SUCCESS;
3319
3320	/* translate the address */
3321	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3322	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3323	&& !HWACCMIsEnabled(pState->pVM))
3324	{
3325	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3326	if (!pState->pvPageR3)
3327	rc = VERR_INVALID_POINTER;
3328	}
3329	else
3330	{
3331	/* Release mapping lock previously acquired. */
3332	if (pState->fLocked)
3333	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3334	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3335	pState->fLocked = RT_SUCCESS_NP(rc);
3336	}
3337	if (RT_FAILURE(rc))
3338	{
3339	pState->pvPageR3 = NULL;
3340	return rc;
3341	}
3342	}
3343
3344	/* check the segemnt limit */
3345	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3346	return VERR_OUT_OF_SELECTOR_BOUNDS;
3347
3348	/* calc how much we can read */
3349	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3350	if (!pState->f64Bits)
3351	{
3352	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3353	if (cb > cbSeg && cbSeg)
3354	cb = cbSeg;
3355	}
3356	if (cb > cbRead)
3357	cb = cbRead;
3358
3359	/* read and advance */
3360	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3361	cbRead -= cb;
3362	if (!cbRead)
3363	return VINF_SUCCESS;
3364	pu8Dst += cb;
3365	PtrSrc += cb;
3366	}
3367	}
3368
3369
3370	/**
3371	* Disassemble an instruction and return the information in the provided structure.
3372	*
3373	* @returns VBox status code.
3374	* @param pVM VM Handle
3375	* @param pVCpu VMCPU Handle
3376	* @param pCtx CPU context
3377	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3378	* @param pCpu Disassembly state
3379	* @param pszPrefix String prefix for logging (debug only)
3380	*
3381	*/
3382	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3383	{
3384	CPUMDISASSTATE State;
3385	int rc;
3386
3387	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3388	State.pCpu = pCpu;
3389	State.pvPageGC = 0;
3390	State.pvPageR3 = NULL;
3391	State.pVM = pVM;
3392	State.pVCpu = pVCpu;
3393	State.fLocked = false;
3394	State.f64Bits = false;
3395
3396	/*
3397	* Get selector information.
3398	*/
3399	if ( (pCtx->cr0 & X86_CR0_PE)
3400	&& pCtx->eflags.Bits.u1VM == 0)
3401	{
3402	if (CPUMAreHiddenSelRegsValid(pVM))
3403	{
3404	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3405	State.GCPtrSegBase = pCtx->csHid.u64Base;
3406	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3407	State.cbSegLimit = pCtx->csHid.u32Limit;
3408	pCpu->mode = (State.f64Bits)
3409	? CPUMODE_64BIT
3410	: pCtx->csHid.Attr.n.u1DefBig
3411	? CPUMODE_32BIT
3412	: CPUMODE_16BIT;
3413	}
3414	else
3415	{
3416	DBGFSELINFO SelInfo;
3417
3418	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3419	if (RT_FAILURE(rc))
3420	{
3421	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3422	return rc;
3423	}
3424
3425	/*
3426	* Validate the selector.
3427	*/
3428	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3429	if (RT_FAILURE(rc))
3430	{
3431	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3432	return rc;
3433	}
3434	State.GCPtrSegBase = SelInfo.GCPtrBase;
3435	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3436	State.cbSegLimit = SelInfo.cbLimit;
3437	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3438	}
3439	}
3440	else
3441	{
3442	/* real or V86 mode */
3443	pCpu->mode = CPUMODE_16BIT;
3444	State.GCPtrSegBase = pCtx->cs * 16;
3445	State.GCPtrSegEnd = 0xFFFFFFFF;
3446	State.cbSegLimit = 0xFFFFFFFF;
3447	}
3448
3449	/*
3450	* Disassemble the instruction.
3451	*/
3452	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3453	pCpu->apvUserData[0] = &State;
3454
3455	uint32_t cbInstr;
3456	#ifndef LOG_ENABLED
3457	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3458	if (RT_SUCCESS(rc))
3459	{
3460	#else
3461	char szOutput[160];
3462	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3463	if (RT_SUCCESS(rc))
3464	{
3465	/* log it */
3466	if (pszPrefix)
3467	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3468	else
3469	Log(("%s", szOutput));
3470	#endif
3471	rc = VINF_SUCCESS;
3472	}
3473	else
3474	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3475
3476	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3477	if (State.fLocked)
3478	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3479
3480	return rc;
3481	}
3482
3483	#ifdef DEBUG
3484
3485	/**
3486	* Disassemble an instruction and dump it to the log
3487	*
3488	* @returns VBox status code.
3489	* @param pVM VM Handle
3490	* @param pVCpu VMCPU Handle
3491	* @param pCtx CPU context
3492	* @param pc GC instruction pointer
3493	* @param pszPrefix String prefix for logging
3494	*
3495	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3496	*/
3497	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3498	{
3499	DISCPUSTATE Cpu;
3500	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3501	}
3502
3503
3504	/**
3505	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3506	*
3507	* @internal
3508	*/
3509	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3510	{
3511	/** @todo SMP support!! */
3512	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3513	}
3514
3515	#endif /* DEBUG */
3516
3517	/**
3518	* API for controlling a few of the CPU features found in CR4.
3519	*
3520	* Currently only X86_CR4_TSD is accepted as input.
3521	*
3522	* @returns VBox status code.
3523	*
3524	* @param pVM The VM handle.
3525	* @param fOr The CR4 OR mask.
3526	* @param fAnd The CR4 AND mask.
3527	*/
3528	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3529	{
3530	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3531	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3532
3533	pVM->cpum.s.CR4.OrMask &= fAnd;
3534	pVM->cpum.s.CR4.OrMask \|= fOr;
3535
3536	return VINF_SUCCESS;
3537	}
3538
3539
3540	/**
3541	* Gets a pointer to the array of standard CPUID leaves.
3542	*
3543	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3544	*
3545	* @returns Pointer to the standard CPUID leaves (read-only).
3546	* @param pVM The VM handle.
3547	* @remark Intended for PATM.
3548	*/
3549	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3550	{
3551	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3552	}
3553
3554
3555	/**
3556	* Gets a pointer to the array of extended CPUID leaves.
3557	*
3558	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3559	*
3560	* @returns Pointer to the extended CPUID leaves (read-only).
3561	* @param pVM The VM handle.
3562	* @remark Intended for PATM.
3563	*/
3564	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3565	{
3566	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3567	}
3568
3569
3570	/**
3571	* Gets a pointer to the array of centaur CPUID leaves.
3572	*
3573	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3574	*
3575	* @returns Pointer to the centaur CPUID leaves (read-only).
3576	* @param pVM The VM handle.
3577	* @remark Intended for PATM.
3578	*/
3579	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3580	{
3581	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3582	}
3583
3584
3585	/**
3586	* Gets a pointer to the default CPUID leaf.
3587	*
3588	* @returns Pointer to the default CPUID leaf (read-only).
3589	* @param pVM The VM handle.
3590	* @remark Intended for PATM.
3591	*/
3592	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3593	{
3594	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3595	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 26295

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