CPUM.cpp@ 25957

Last change on this file since 25957 was 25957, checked in by vboxsync, 15 years ago
CPUM: StrictCpuIdChecks should default to true instead of false (to override: VBoxInternal/CPUM/StrictCpuIdChecks 0). Fixed log messages about bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 171.0 KB

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1	/* $Id: CPUM.cpp 25957 2010-01-21 13:33:58Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/pdm.h>
46	#include <VBox/mm.h>
47	#include <VBox/selm.h>
48	#include <VBox/dbgf.h>
49	#include <VBox/patm.h>
50	#include <VBox/hwaccm.h>
51	#include <VBox/ssm.h>
52	#include "CPUMInternal.h"
53	#include <VBox/vm.h>
54
55	#include <VBox/param.h>
56	#include <VBox/dis.h>
57	#include <VBox/err.h>
58	#include <VBox/log.h>
59	#include <iprt/assert.h>
60	#include <iprt/asm.h>
61	#include <iprt/string.h>
62	#include <iprt/mp.h>
63	#include <iprt/cpuset.h>
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The current saved state version. */
70	#define CPUM_SAVED_STATE_VERSION 11
71	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
72	* changes. */
73	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
74	/** The saved state version for the 2.1 trunk before the MSR changes. */
75	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
76	/** The saved state version of 2.0, used for backwards compatibility. */
77	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
78	/** The saved state version of 1.6, used for backwards compatability. */
79	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
80
81
82	/*******************************************************************************
83	* Structures and Typedefs *
84	*******************************************************************************/
85
86	/**
87	* What kind of cpu info dump to perform.
88	*/
89	typedef enum CPUMDUMPTYPE
90	{
91	CPUMDUMPTYPE_TERSE,
92	CPUMDUMPTYPE_DEFAULT,
93	CPUMDUMPTYPE_VERBOSE
94	} CPUMDUMPTYPE;
95	/** Pointer to a cpu info dump type. */
96	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
97
98
99	/*******************************************************************************
100	* Internal Functions *
101	*******************************************************************************/
102	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
103	static int cpumR3CpuIdInit(PVM pVM);
104	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
105	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
107	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
108	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
109	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115
116
117	/**
118	* Initializes the CPUM.
119	*
120	* @returns VBox status code.
121	* @param pVM The VM to operate on.
122	*/
123	VMMR3DECL(int) CPUMR3Init(PVM pVM)
124	{
125	LogFlow(("CPUMR3Init\n"));
126
127	/*
128	* Assert alignment and sizes.
129	*/
130	AssertCompileMemberAlignment(VM, cpum.s, 32);
131	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
132	AssertCompileSizeAlignment(CPUMCTX, 64);
133	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
134	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
135	AssertCompileMemberAlignment(VM, cpum, 64);
136	AssertCompileMemberAlignment(VM, aCpus, 64);
137	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
138	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
139
140	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
141	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
142	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
143
144	/* Calculate the offset from CPUMCPU to CPUM. */
145	for (VMCPUID i = 0; i < pVM->cCpus; i++)
146	{
147	PVMCPU pVCpu = &pVM->aCpus[i];
148
149	/*
150	* Setup any fixed pointers and offsets.
151	*/
152	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
153	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
154
155	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
156	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
157	}
158
159	/*
160	* Check that the CPU supports the minimum features we require.
161	*/
162	if (!ASMHasCpuId())
163	{
164	Log(("The CPU doesn't support CPUID!\n"));
165	return VERR_UNSUPPORTED_CPU;
166	}
167	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
168	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
169
170	/* Setup the CR4 AND and OR masks used in the switcher */
171	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
172	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
173	{
174	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
175	/* No FXSAVE implies no SSE */
176	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
177	pVM->cpum.s.CR4.OrMask = 0;
178	}
179	else
180	{
181	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
182	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
183	}
184
185	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
186	{
187	Log(("The CPU doesn't support MMX!\n"));
188	return VERR_UNSUPPORTED_CPU;
189	}
190	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
191	{
192	Log(("The CPU doesn't support TSC!\n"));
193	return VERR_UNSUPPORTED_CPU;
194	}
195	/* Bogus on AMD? */
196	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
197	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
198
199	/*
200	* Detech the host CPU vendor.
201	* (The guest CPU vendor is re-detected later on.)
202	*/
203	uint32_t uEAX, uEBX, uECX, uEDX;
204	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
205	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
206	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
207
208	/*
209	* Setup hypervisor startup values.
210	*/
211
212	/*
213	* Register saved state data item.
214	*/
215	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
216	NULL, cpumR3LiveExec, NULL,
217	NULL, cpumR3SaveExec, NULL,
218	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
219	if (RT_FAILURE(rc))
220	return rc;
221
222	/*
223	* Register info handlers.
224	*/
225	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232	/*
233	* Initialize the Guest CPUID state.
234	*/
235	rc = cpumR3CpuIdInit(pVM);
236	if (RT_FAILURE(rc))
237	return rc;
238	CPUMR3Reset(pVM);
239	return VINF_SUCCESS;
240	}
241
242
243	/**
244	* Initializes the per-VCPU CPUM.
245	*
246	* @returns VBox status code.
247	* @param pVM The VM to operate on.
248	*/
249	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250	{
251	LogFlow(("CPUMR3InitCPU\n"));
252	return VINF_SUCCESS;
253	}
254
255
256	/**
257	* Detect the CPU vendor give n the
258	*
259	* @returns The vendor.
260	* @param uEAX EAX from CPUID(0).
261	* @param uEBX EBX from CPUID(0).
262	* @param uECX ECX from CPUID(0).
263	* @param uEDX EDX from CPUID(0).
264	*/
265	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
266	{
267	if ( uEAX >= 1
268	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
269	&& uECX == X86_CPUID_VENDOR_AMD_ECX
270	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
271	return CPUMCPUVENDOR_AMD;
272
273	if ( uEAX >= 1
274	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
275	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
276	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
277	return CPUMCPUVENDOR_INTEL;
278
279	/** @todo detect the other buggers... */
280	return CPUMCPUVENDOR_UNKNOWN;
281	}
282
283
284	/**
285	* Fetches overrides for a CPUID leaf.
286	*
287	* @returns VBox status code.
288	* @param pLeaf The leaf to load the overrides into.
289	* @param pCfgNode The CFGM node containing the overrides
290	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
291	* @param iLeaf The CPUID leaf number.
292	*/
293	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
294	{
295	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
296	if (pLeafNode)
297	{
298	uint32_t u32;
299	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
300	if (RT_SUCCESS(rc))
301	pLeaf->eax = u32;
302	else
303	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
304
305	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
306	if (RT_SUCCESS(rc))
307	pLeaf->ebx = u32;
308	else
309	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
310
311	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
312	if (RT_SUCCESS(rc))
313	pLeaf->ecx = u32;
314	else
315	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
316
317	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
318	if (RT_SUCCESS(rc))
319	pLeaf->edx = u32;
320	else
321	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
322
323	}
324	return VINF_SUCCESS;
325	}
326
327
328	/**
329	* Load the overrides for a set of CPUID leafs.
330	*
331	* @returns VBox status code.
332	* @param paLeafs The leaf array.
333	* @param cLeafs The number of leafs.
334	* @param uStart The start leaf number.
335	* @param pCfgNode The CFGM node containing the overrides
336	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
337	*/
338	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
339	{
340	for (uint32_t i = 0; i < cLeafs; i++)
341	{
342	int rc = cpumR3CpuIdFetchLeafOverride(&paLeafs[i], pCfgNode, uStart + i);
343	if (RT_FAILURE(rc))
344	return rc;
345	}
346
347	return VINF_SUCCESS;
348	}
349
350	/**
351	* Init a set of host CPUID leafs.
352	*
353	* @returns VBox status code.
354	* @param paLeafs The leaf array.
355	* @param cLeafs The number of leafs.
356	* @param uStart The start leaf number.
357	* @param pCfgNode The /CPUM/HostCPUID/ node.
358	*/
359	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeafs, uint32_t cLeafs, PCFGMNODE pCfgNode)
360	{
361	/* Using the ECX variant for all of them can't hurt... */
362	for (uint32_t i = 0; i < cLeafs; i++)
363	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeafs[i].eax, &paLeafs[i].ebx, &paLeafs[i].ecx, &paLeafs[i].edx);
364
365	/* Load CPUID leaf override; we currently don't care if the caller
366	specifies features the host CPU doesn't support. */
367	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeafs, cLeafs, pCfgNode);
368	}
369
370
371	/**
372	* Initializes the emulated CPU's cpuid information.
373	*
374	* @returns VBox status code.
375	* @param pVM The VM to operate on.
376	*/
377	static int cpumR3CpuIdInit(PVM pVM)
378	{
379	PCPUM pCPUM = &pVM->cpum.s;
380	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
381	uint32_t i;
382	int rc;
383
384	/*
385	* Get the host CPUIDs and redetect the guest CPU vendor (could've been overridden).
386	*/
387	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
388	* Overrides the host CPUID leaf values used for calculating the guest CPUID
389	* leafs. This can be used to preserve the CPUID values when moving a VM to
390	* a different machine. Another use is restricting (or extending) the
391	* feature set exposed to the guest. */
392	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
393	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
394	AssertRCReturn(rc, rc);
395	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
396	AssertRCReturn(rc, rc);
397	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
398	AssertRCReturn(rc, rc);
399
400	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
401	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
402
403	/*
404	* Only report features we can support.
405	*/
406	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
407	\| X86_CPUID_FEATURE_EDX_VME
408	\| X86_CPUID_FEATURE_EDX_DE
409	\| X86_CPUID_FEATURE_EDX_PSE
410	\| X86_CPUID_FEATURE_EDX_TSC
411	\| X86_CPUID_FEATURE_EDX_MSR
412	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
413	\| X86_CPUID_FEATURE_EDX_MCE
414	\| X86_CPUID_FEATURE_EDX_CX8
415	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
416	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
417	//\| X86_CPUID_FEATURE_EDX_SEP
418	\| X86_CPUID_FEATURE_EDX_MTRR
419	\| X86_CPUID_FEATURE_EDX_PGE
420	\| X86_CPUID_FEATURE_EDX_MCA
421	\| X86_CPUID_FEATURE_EDX_CMOV
422	\| X86_CPUID_FEATURE_EDX_PAT
423	\| X86_CPUID_FEATURE_EDX_PSE36
424	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
425	\| X86_CPUID_FEATURE_EDX_CLFSH
426	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
427	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
428	\| X86_CPUID_FEATURE_EDX_MMX
429	\| X86_CPUID_FEATURE_EDX_FXSR
430	\| X86_CPUID_FEATURE_EDX_SSE
431	\| X86_CPUID_FEATURE_EDX_SSE2
432	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
433	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
434	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
435	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
436	\| 0;
437	pCPUM->aGuestCpuIdStd[1].ecx &= 0
438	\| X86_CPUID_FEATURE_ECX_SSE3
439	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
440	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
441	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
442	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
443	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
444	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
445	\| X86_CPUID_FEATURE_ECX_SSSE3
446	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
447	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
448	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
449	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
450	/* ECX Bit 21 - x2APIC support - not yet. */
451	// \| X86_CPUID_FEATURE_ECX_X2APIC
452	/* ECX Bit 23 - POPCNT instruction. */
453	//\| X86_CPUID_FEATURE_ECX_POPCNT
454	\| 0;
455
456	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
457	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
458	\| X86_CPUID_AMD_FEATURE_EDX_VME
459	\| X86_CPUID_AMD_FEATURE_EDX_DE
460	\| X86_CPUID_AMD_FEATURE_EDX_PSE
461	\| X86_CPUID_AMD_FEATURE_EDX_TSC
462	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
463	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
464	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
465	\| X86_CPUID_AMD_FEATURE_EDX_CX8
466	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
467	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
468	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
469	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
470	\| X86_CPUID_AMD_FEATURE_EDX_PGE
471	\| X86_CPUID_AMD_FEATURE_EDX_MCA
472	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
473	\| X86_CPUID_AMD_FEATURE_EDX_PAT
474	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
475	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
476	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
477	\| X86_CPUID_AMD_FEATURE_EDX_MMX
478	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
479	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
480	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
481	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
482	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
483	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
484	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
485	\| 0;
486	pCPUM->aGuestCpuIdExt[1].ecx &= 0
487	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
488	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
489	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
490	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
491	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
492	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
493	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
494	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
495	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
496	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
497	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
498	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
499	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
500	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
501	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
502	\| 0;
503
504	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false); AssertRCReturn(rc, rc);
505	if (pCPUM->fSyntheticCpu)
506	{
507	const char szVendor[13] = "VirtualBox ";
508	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
509
510	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
511
512	/* Limit the nr of standard leaves; 5 for monitor/mwait */
513	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
514
515	/* 0: Vendor */
516	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
517	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
518	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
519
520	/* 1.eax: Version information. family : model : stepping */
521	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
522
523	/* Leaves 2 - 4 are Intel only - zero them out */
524	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
525	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
526	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
527
528	/* Leaf 5 = monitor/mwait */
529
530	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
531	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
532	/* AMD only - set to zero. */
533	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
534
535	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
536	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
537
538	/* 0x800000002-4: Processor Name String Identifier. */
539	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
540	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
541	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
542	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
543	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
544	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
545	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
546	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
547	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
548	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
549	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
550	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
551
552	/* 0x800000005-7 - reserved -> zero */
553	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
554	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
555	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
556
557	/* 0x800000008: only the max virtual and physical address size. */
558	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
559	}
560
561	/*
562	* Hide HTT, multicode, SMP, whatever.
563	* (APIC-ID := 0 and #LogCpus := 0)
564	*/
565	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
566	#ifdef VBOX_WITH_MULTI_CORE
567	if ( pVM->cCpus > 1
568	&& pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
569	{
570	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
571	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
572	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
573	}
574	#endif
575
576	/* Cpuid 2:
577	* Intel: Cache and TLB information
578	* AMD: Reserved
579	* Safe to expose
580	*/
581
582	/* Cpuid 3:
583	* Intel: EAX, EBX - reserved
584	* ECX, EDX - Processor Serial Number if available, otherwise reserved
585	* AMD: Reserved
586	* Safe to expose
587	*/
588	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
589	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
590
591	/* Cpuid 4:
592	* Intel: Deterministic Cache Parameters Leaf
593	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
594	* AMD: Reserved
595	* Safe to expose, except for EAX:
596	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
597	* Bits 31-26: Maximum number of processor cores in this physical package**
598	* Note: These SMP values are constant regardless of ECX
599	*/
600	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
601	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
602	#ifdef VBOX_WITH_MULTI_CORE
603	if ( pVM->cCpus > 1
604	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
605	{
606	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
607	/* One logical processor with possibly multiple cores. */
608	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
609	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
610	}
611	#endif
612
613	/* Cpuid 5: Monitor/mwait Leaf
614	* Intel: ECX, EDX - reserved
615	* EAX, EBX - Smallest and largest monitor line size
616	* AMD: EDX - reserved
617	* EAX, EBX - Smallest and largest monitor line size
618	* ECX - extensions (ignored for now)
619	* Safe to expose
620	*/
621	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
622	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
623
624	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
625
626	/*
627	* Determine the default.
628	*
629	* Intel returns values of the highest standard function, while AMD
630	* returns zeros. VIA on the other hand seems to returning nothing or
631	* perhaps some random garbage, we don't try to duplicate this behavior.
632	*/
633	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
634	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
635	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
636
637	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
638	* Safe to pass on to the guest.
639	*
640	* Intel: 0x800000005 reserved
641	* 0x800000006 L2 cache information
642	* AMD: 0x800000005 L1 cache information
643	* 0x800000006 L2/L3 cache information
644	*/
645
646	/* Cpuid 0x800000007:
647	* AMD: EAX, EBX, ECX - reserved
648	* EDX: Advanced Power Management Information
649	* Intel: Reserved
650	*/
651	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
652	{
653	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
654
655	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
656
657	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
658	{
659	/* Only expose the TSC invariant capability bit to the guest. */
660	pCPUM->aGuestCpuIdExt[7].edx &= 0
661	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
662	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
663	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
664	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
665	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
666	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
667	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
668	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
669	#if 1
670	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
671	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
672	*/
673	#else
674	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
675	#endif
676	\| 0;
677	}
678	else
679	pCPUM->aGuestCpuIdExt[7].edx = 0;
680	}
681
682	/* Cpuid 0x800000008:
683	* AMD: EBX, EDX - reserved
684	* EAX: Virtual/Physical address Size
685	* ECX: Number of cores + APICIdCoreIdSize
686	* Intel: EAX: Virtual/Physical address Size
687	* EBX, ECX, EDX - reserved
688	*/
689	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
690	{
691	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
692	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
693	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
694	* NC (0-7) Number of cores; 0 equals 1 core */
695	pCPUM->aGuestCpuIdExt[8].ecx = 0;
696	#ifdef VBOX_WITH_MULTI_CORE
697	if ( pVM->cCpus > 1
698	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
699	{
700	/* Legacy method to determine the number of cores. */
701	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
702	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
703
704	}
705	#endif
706	}
707
708	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
709	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
710	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
711	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
712	*/
713	bool fNt4LeafLimit;
714	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
715	if (fNt4LeafLimit)
716	pCPUM->aGuestCpuIdStd[0].eax = 3;
717
718	/*
719	* Limit it the number of entries and fill the remaining with the defaults.
720	*
721	* The limits are masking off stuff about power saving and similar, this
722	* is perhaps a bit crudely done as there is probably some relatively harmless
723	* info too in these leaves (like words about having a constant TSC).
724	*/
725	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
726	pCPUM->aGuestCpuIdStd[0].eax = 5;
727
728	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
729	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
730
731	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
732	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
733	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
734	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
735	: 0;
736	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
737	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
738
739	/*
740	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
741	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
742	* of processors from (cpuid(4).eax >> 26) + 1.
743	*/
744	if (pVM->cCpus == 1)
745	pCPUM->aGuestCpuIdStd[4].eax = 0;
746
747	/*
748	* Centaur stuff (VIA).
749	*
750	* The important part here (we think) is to make sure the 0xc0000000
751	* function returns 0xc0000001. As for the features, we don't currently
752	* let on about any of those... 0xc0000002 seems to be some
753	* temperature/hz/++ stuff, include it as well (static).
754	*/
755	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
756	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
757	{
758	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
759	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
760	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
761	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
762	i++)
763	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
764	}
765	else
766	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
767	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
768
769
770	/*
771	* Load CPUID overrides from configuration.
772	* Note: Kind of redundant now, but allows unchanged overrides
773	*/
774	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
775	* Overrides the CPUID leaf values. */
776	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
777	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
778	AssertRCReturn(rc, rc);
779	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
780	AssertRCReturn(rc, rc);
781	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
782	AssertRCReturn(rc, rc);
783
784	/*
785	* Check if PAE was explicitely enabled by the user.
786	*/
787	bool fEnable;
788	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
789	if (fEnable)
790	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
791
792	/*
793	* Log the cpuid and we're good.
794	*/
795	RTCPUSET OnlineSet;
796	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
797	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
798	LogRel(("*********************** CPUID dump **********************\n"));
799	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
800	LogRel(("\n"));
801	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
802	LogRel(("****************** End of CPUID dump ********************\n"));
803	return VINF_SUCCESS;
804	}
805
806
807
808
809	/**
810	* Applies relocations to data and code managed by this
811	* component. This function will be called at init and
812	* whenever the VMM need to relocate it self inside the GC.
813	*
814	* The CPUM will update the addresses used by the switcher.
815	*
816	* @param pVM The VM.
817	*/
818	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
819	{
820	LogFlow(("CPUMR3Relocate\n"));
821	for (VMCPUID i = 0; i < pVM->cCpus; i++)
822	{
823	/*
824	* Switcher pointers.
825	*/
826	PVMCPU pVCpu = &pVM->aCpus[i];
827	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
828	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
829	}
830	}
831
832
833	/**
834	* Terminates the CPUM.
835	*
836	* Termination means cleaning up and freeing all resources,
837	* the VM it self is at this point powered off or suspended.
838	*
839	* @returns VBox status code.
840	* @param pVM The VM to operate on.
841	*/
842	VMMR3DECL(int) CPUMR3Term(PVM pVM)
843	{
844	CPUMR3TermCPU(pVM);
845	return 0;
846	}
847
848
849	/**
850	* Terminates the per-VCPU CPUM.
851	*
852	* Termination means cleaning up and freeing all resources,
853	* the VM it self is at this point powered off or suspended.
854	*
855	* @returns VBox status code.
856	* @param pVM The VM to operate on.
857	*/
858	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
859	{
860	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
861	for (VMCPUID i = 0; i < pVM->cCpus; i++)
862	{
863	PVMCPU pVCpu = &pVM->aCpus[i];
864	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
865
866	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
867	pVCpu->cpum.s.uMagic = 0;
868	pCtx->dr[5] = 0;
869	}
870	#endif
871	return 0;
872	}
873
874
875	/**
876	* Resets a virtual CPU.
877	*
878	* Used by CPUMR3Reset and CPU hot plugging.
879	*
880	* @param pVCpu The virtual CPU handle.
881	*/
882	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
883	{
884	/** @todo anything different for VCPU > 0? */
885	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
886
887	/*
888	* Initialize everything to ZERO first.
889	*/
890	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
891	memset(pCtx, 0, sizeof(*pCtx));
892	pVCpu->cpum.s.fUseFlags = fUseFlags;
893
894	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
895	pCtx->eip = 0x0000fff0;
896	pCtx->edx = 0x00000600; /* P6 processor */
897	pCtx->eflags.Bits.u1Reserved0 = 1;
898
899	pCtx->cs = 0xf000;
900	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
901	pCtx->csHid.u32Limit = 0x0000ffff;
902	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
903	pCtx->csHid.Attr.n.u1Present = 1;
904	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
905
906	pCtx->dsHid.u32Limit = 0x0000ffff;
907	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
908	pCtx->dsHid.Attr.n.u1Present = 1;
909	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
910
911	pCtx->esHid.u32Limit = 0x0000ffff;
912	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
913	pCtx->esHid.Attr.n.u1Present = 1;
914	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
915
916	pCtx->fsHid.u32Limit = 0x0000ffff;
917	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
918	pCtx->fsHid.Attr.n.u1Present = 1;
919	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
920
921	pCtx->gsHid.u32Limit = 0x0000ffff;
922	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
923	pCtx->gsHid.Attr.n.u1Present = 1;
924	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
925
926	pCtx->ssHid.u32Limit = 0x0000ffff;
927	pCtx->ssHid.Attr.n.u1Present = 1;
928	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
929	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
930
931	pCtx->idtr.cbIdt = 0xffff;
932	pCtx->gdtr.cbGdt = 0xffff;
933
934	pCtx->ldtrHid.u32Limit = 0xffff;
935	pCtx->ldtrHid.Attr.n.u1Present = 1;
936	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
937
938	pCtx->trHid.u32Limit = 0xffff;
939	pCtx->trHid.Attr.n.u1Present = 1;
940	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
941
942	pCtx->dr[6] = X86_DR6_INIT_VAL;
943	pCtx->dr[7] = X86_DR7_INIT_VAL;
944
945	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
946	pCtx->fpu.FCW = 0x37f;
947
948	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
949	pCtx->fpu.MXCSR = 0x1F80;
950
951	/* Init PAT MSR */
952	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
953
954	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
955	* The Intel docs don't mention it.
956	*/
957	pCtx->msrEFER = 0;
958	}
959
960
961	/**
962	* Resets the CPU.
963	*
964	* @returns VINF_SUCCESS.
965	* @param pVM The VM handle.
966	*/
967	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
968	{
969	for (VMCPUID i = 0; i < pVM->cCpus; i++)
970	{
971	CPUMR3ResetCpu(&pVM->aCpus[i]);
972
973	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
974	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
975
976	/* Magic marker for searching in crash dumps. */
977	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
978	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
979	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
980	#endif
981	}
982	}
983
984
985	/**
986	* Called both in pass 0 and the final pass.
987	*
988	* @param pVM The VM handle.
989	* @param pSSM The saved state handle.
990	*/
991	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
992	{
993	/*
994	* Save all the CPU ID leaves here so we can check them for compatability
995	* upon loading.
996	*/
997	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
998	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
999
1000	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1001	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1002
1003	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1004	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1005
1006	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1007
1008	/*
1009	* Save a good portion of the raw CPU IDs as well as they may come in
1010	* handy when validating features for raw mode.
1011	*/
1012	CPUMCPUID aRawStd[16];
1013	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1014	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1015	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1016	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1017
1018	CPUMCPUID aRawExt[32];
1019	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1020	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1021	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1022	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1023	}
1024
1025
1026	/**
1027	* Loads the CPU ID leaves saved by pass 0.
1028	*
1029	* @returns VBox status code.
1030	* @param pVM The VM handle.
1031	* @param pSSM The saved state handle.
1032	* @param uVersion The format version.
1033	*/
1034	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1035	{
1036	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1037
1038	/*
1039	* Define a bunch of macros for simplifying the code.
1040	*/
1041	/* Generic expression + failure message. */
1042	#define CPUID_CHECK_RET(expr, fmt) \
1043	do { \
1044	if (!(expr)) \
1045	{ \
1046	char pszMsg = RTStrAPrintf2 fmt; / lack of variadict macros sucks */ \
1047	if (fStrictCpuIdChecks) \
1048	{ \
1049	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1050	RTStrFree(pszMsg); \
1051	return rcCpuid; \
1052	} \
1053	LogRel(("CPUM: %s\n", pszMsg)); \
1054	RTStrFree(pszMsg); \
1055	} \
1056	} while (0)
1057	#define CPUID_CHECK_WRN(expr, fmt) \
1058	do { \
1059	if (!(expr)) \
1060	LogRel(fmt); \
1061	} while (0)
1062
1063	/* For comparing two values and bitch if they differs. */
1064	#define CPUID_CHECK2_RET(what, host, saved) \
1065	do { \
1066	if ((host) != (saved)) \
1067	{ \
1068	if (fStrictCpuIdChecks) \
1069	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1070	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1071	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1072	} \
1073	} while (0)
1074	#define CPUID_CHECK2_WRN(what, host, saved) \
1075	do { \
1076	if ((host) != (saved)) \
1077	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1078	} while (0)
1079
1080	/* For checking raw cpu features (raw mode). */
1081	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1082	do { \
1083	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1084	{ \
1085	if (fStrictCpuIdChecks) \
1086	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1087	N_(#bit " mismatch: host=%d saved=%d"), \
1088	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1089	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1090	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1091	} \
1092	} while (0)
1093	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1094	do { \
1095	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1096	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1097	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1098	} while (0)
1099	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1100
1101	/* For checking guest features. */
1102	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1103	do { \
1104	if ( (aGuestCpuId##set [1].reg & bit) \
1105	&& !(aHostRaw##set [1].reg & bit) \
1106	&& !(aHostOverride##set [1].reg & bit) \
1107	&& !(aGuestOverride##set [1].reg & bit) \
1108	) \
1109	{ \
1110	if (fStrictCpuIdChecks) \
1111	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1112	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1113	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1114	} \
1115	} while (0)
1116	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1117	do { \
1118	if ( (aGuestCpuId##set [1].reg & bit) \
1119	&& !(aHostRaw##set [1].reg & bit) \
1120	&& !(aHostOverride##set [1].reg & bit) \
1121	&& !(aGuestOverride##set [1].reg & bit) \
1122	) \
1123	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1124	} while (0)
1125	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1126	do { \
1127	if ( (aGuestCpuId##set [1].reg & bit) \
1128	&& !(aHostRaw##set [1].reg & bit) \
1129	&& !(aHostOverride##set [1].reg & bit) \
1130	&& !(aGuestOverride##set [1].reg & bit) \
1131	) \
1132	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1133	} while (0)
1134	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1135
1136	/* For checking guest features if AMD guest CPU. */
1137	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1138	do { \
1139	if ( (aGuestCpuId##set [1].reg & bit) \
1140	&& fGuestAmd \
1141	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1142	&& !(aHostOverride##set [1].reg & bit) \
1143	&& !(aGuestOverride##set [1].reg & bit) \
1144	) \
1145	{ \
1146	if (fStrictCpuIdChecks) \
1147	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1148	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1149	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1150	} \
1151	} while (0)
1152	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1153	do { \
1154	if ( (aGuestCpuId##set [1].reg & bit) \
1155	&& fGuestAmd \
1156	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1157	&& !(aHostOverride##set [1].reg & bit) \
1158	&& !(aGuestOverride##set [1].reg & bit) \
1159	) \
1160	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1161	} while (0)
1162	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1163	do { \
1164	if ( (aGuestCpuId##set [1].reg & bit) \
1165	&& fGuestAmd \
1166	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1167	&& !(aHostOverride##set [1].reg & bit) \
1168	&& !(aGuestOverride##set [1].reg & bit) \
1169	) \
1170	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1171	} while (0)
1172	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1173
1174	/* For checking AMD features which have a corresponding bit in the standard
1175	range. (Intel defines very few bits in the extended feature sets.) */
1176	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1177	do { \
1178	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1179	&& !(fHostAmd \
1180	? aHostRawExt[1].reg & (ExtBit) \
1181	: aHostRawStd[1].reg & (StdBit)) \
1182	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1183	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1184	) \
1185	{ \
1186	if (fStrictCpuIdChecks) \
1187	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1188	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1189	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1190	} \
1191	} while (0)
1192	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1193	do { \
1194	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1195	&& !(fHostAmd \
1196	? aHostRawExt[1].reg & (ExtBit) \
1197	: aHostRawStd[1].reg & (StdBit)) \
1198	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1199	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1200	) \
1201	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1202	} while (0)
1203	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1204	do { \
1205	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1206	&& !(fHostAmd \
1207	? aHostRawExt[1].reg & (ExtBit) \
1208	: aHostRawStd[1].reg & (StdBit)) \
1209	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1210	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1211	) \
1212	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1213	} while (0)
1214	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1215
1216	/*
1217	* Load them into stack buffers first.
1218	*/
1219	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1220	uint32_t cGuestCpuIdStd;
1221	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1222	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1223	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1224	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1225
1226	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1227	uint32_t cGuestCpuIdExt;
1228	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1229	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1230	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1231	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1232
1233	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1234	uint32_t cGuestCpuIdCentaur;
1235	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1236	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1237	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1238	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1239
1240	CPUMCPUID GuestCpuIdDef;
1241	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1242	AssertRCReturn(rc, rc);
1243
1244	CPUMCPUID aRawStd[16];
1245	uint32_t cRawStd;
1246	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1247	if (cRawStd > RT_ELEMENTS(aRawStd))
1248	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1249	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1250
1251	CPUMCPUID aRawExt[32];
1252	uint32_t cRawExt;
1253	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1254	if (cRawExt > RT_ELEMENTS(aRawExt))
1255	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1256	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1257	AssertRCReturn(rc, rc);
1258
1259	/*
1260	* Note that we support restoring less than the current amount of standard
1261	* leaves because we've been allowed more is newer version of VBox.
1262	*
1263	* So, pad new entries with the default.
1264	*/
1265	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1266	aGuestCpuIdStd[i] = GuestCpuIdDef;
1267
1268	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1269	aGuestCpuIdExt[i] = GuestCpuIdDef;
1270
1271	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1272	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1273
1274	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1275	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1276
1277	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1278	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1279
1280	/*
1281	* Get the raw CPU IDs for the current host.
1282	*/
1283	CPUMCPUID aHostRawStd[16];
1284	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1285	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1286
1287	CPUMCPUID aHostRawExt[32];
1288	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1289	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1290
1291	/*
1292	* Get the host and guest overrides so we don't reject the state because
1293	* some feature was enabled thru these interfaces.
1294	* Note! We currently only need the feature leafs, so skip rest.
1295	*/
1296	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1297	CPUMCPUID aGuestOverrideStd[2];
1298	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1299	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1300
1301	CPUMCPUID aGuestOverrideExt[2];
1302	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1303	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1304
1305	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1306	CPUMCPUID aHostOverrideStd[2];
1307	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1308	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1309
1310	CPUMCPUID aHostOverrideExt[2];
1311	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1312	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1313
1314	/*
1315	* This can be skipped.
1316	*/
1317	bool fStrictCpuIdChecks;
1318	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1319
1320
1321
1322	/*
1323	* For raw-mode we'll require that the CPUs are very similar since we don't
1324	* intercept CPUID instructions for user mode applications.
1325	*/
1326	if (!HWACCMIsEnabled(pVM))
1327	{
1328	/* CPUID(0) */
1329	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1330	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1331	&& aHostRawStd[0].edx == aRawStd[0].edx,
1332	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1333	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1334	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1335	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1336	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1337	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1338
1339	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1340
1341	/* CPUID(1).eax */
1342	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1343	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1344	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1345
1346	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1347	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1348	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1349
1350	/* CPUID(1).ecx */
1351	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1352	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1353	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1354	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1355	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1356	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1357	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1358	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1359	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1360	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1361	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1362	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1363	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1364	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1365	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1366	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1367	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1368	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1369	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1370	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1371	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1372	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1373	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1374	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1375	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1376	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1377	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1378	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1379	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1380	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1381	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1382	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1383
1384	/* CPUID(1).edx */
1385	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1386	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1387	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1388	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1389	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1390	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1391	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1392	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1393	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1394	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1395	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1396	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1397	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1398	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1399	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1400	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1401	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1402	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1403	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1404	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1405	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1406	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1407	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1408	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1409	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1410	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1411	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1412	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1413	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1414	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1415	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1416	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1417
1418	/* CPUID(2) - config, mostly about caches. ignore. */
1419	/* CPUID(3) - processor serial number. ignore. */
1420	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1421	/* CPUID(5) - mwait/monitor config. ignore. */
1422	/* CPUID(6) - power management. ignore. */
1423	/* CPUID(7) - ???. ignore. */
1424	/* CPUID(8) - ???. ignore. */
1425	/* CPUID(9) - DCA. ignore for now. */
1426	/* CPUID(a) - PeMo info. ignore for now. */
1427	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1428
1429	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1430	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1431	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1432	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1433	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1434	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1435	{
1436	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1437	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1438	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1439	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1440	}
1441
1442	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1443	Note! Intel have/is marking many of the fields here as reserved. We
1444	will verify them as if it's an AMD CPU. */
1445	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1446	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1447	(N_("Extended leafs was present on saved state host, but is missing on the current\n")));
1448	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1449	{
1450	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1451	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1452	&& aHostRawExt[0].edx == aRawExt[0].edx,
1453	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1454	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1455	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1456	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1457
1458	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1459	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1460	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1461	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1462	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1463	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1464
1465	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1466	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1467	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1468	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1469
1470	/* CPUID(0x80000001).ecx */
1471	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1472	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1473	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1474	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1475	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1476	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1477	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1478	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1479	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1480	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1481	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1482	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1483	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1484	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1485	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1486	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1487	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1488	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1489	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1490	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1491	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1492	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1493	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1494	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1495	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1496	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1497	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1498	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1499	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1500	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1501	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1502	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1503
1504	/* CPUID(0x80000001).edx */
1505	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1506	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1507	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1508	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1509	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1510	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1511	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1512	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1513	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1514	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1515	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1516	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1517	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1518	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1519	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1520	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1521	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1522	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1523	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1524	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1525	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1526	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1527	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1528	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1529	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1530	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1531	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1532	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1533	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1534	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1535	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1536	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1537
1538	/** @todo verify the rest as well. */
1539	}
1540	}
1541
1542
1543
1544	/*
1545	* Verify that we can support the features already exposed to the guest on
1546	* this host.
1547	*
1548	* Most of the features we're emulating requires intercepting instruction
1549	* and doing it the slow way, so there is no need to warn when they aren't
1550	* present in the host CPU. Thus we use IGN instead of EMU on these.
1551	*
1552	* Trailing comments:
1553	* "EMU" - Possible to emulate, could be lots of work and very slow.
1554	* "EMU?" - Can this be emulated?
1555	*/
1556	/* CPUID(1).ecx */
1557	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1558	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1559	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1560	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1561	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1562	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1563	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1564	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1565	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1566	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1567	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1568	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1569	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1570	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1571	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1572	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1573	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1574	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1575	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1576	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1577	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1578	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1579	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1580	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1581	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1582	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1583	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1584	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1585	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1586	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1587	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1588	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1589
1590	/* CPUID(1).edx */
1591	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1592	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1593	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1594	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1595	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1596	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1597	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1598	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1599	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1600	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1601	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1602	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1603	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1604	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1605	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1606	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1607	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1608	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1609	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1610	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1611	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1612	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1613	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1614	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1615	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1616	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1617	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1618	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1619	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1620	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1621	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1622	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1623
1624	/* CPUID(0x80000000). */
1625	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1626	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1627	{
1628	/** @todo deal with no 0x80000001 on the host. */
1629	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1630	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1631
1632	/* CPUID(0x80000001).ecx */
1633	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1634	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1635	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1636	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1637	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1638	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1639	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1640	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1641	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1642	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1643	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1644	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1645	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1646	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1647	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1648	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1649	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1650	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1651	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1652	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1653	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1654	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1655	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1656	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1657	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1658	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1659	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1660	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1661	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1662	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1663	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1664	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1665
1666	/* CPUID(0x80000001).edx */
1667	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1668	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1669	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1670	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1671	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1672	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1673	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1674	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1675	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1676	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1677	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1678	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1679	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1680	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1681	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1682	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1683	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1684	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1685	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1686	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1687	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1688	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1689	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1690	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1691	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1692	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1693	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1694	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1695	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1696	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1697	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1698	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1699	}
1700
1701	/*
1702	* We're good, commit the CPU ID leaves.
1703	*/
1704	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1705	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1706	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1707	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1708
1709	#undef CPUID_CHECK_RET
1710	#undef CPUID_CHECK_WRN
1711	#undef CPUID_CHECK2_RET
1712	#undef CPUID_CHECK2_WRN
1713	#undef CPUID_RAW_FEATURE_RET
1714	#undef CPUID_RAW_FEATURE_WRN
1715	#undef CPUID_RAW_FEATURE_IGN
1716	#undef CPUID_GST_FEATURE_RET
1717	#undef CPUID_GST_FEATURE_WRN
1718	#undef CPUID_GST_FEATURE_EMU
1719	#undef CPUID_GST_FEATURE_IGN
1720	#undef CPUID_GST_FEATURE2_RET
1721	#undef CPUID_GST_FEATURE2_WRN
1722	#undef CPUID_GST_FEATURE2_EMU
1723	#undef CPUID_GST_FEATURE2_IGN
1724	#undef CPUID_GST_AMD_FEATURE_RET
1725	#undef CPUID_GST_AMD_FEATURE_WRN
1726	#undef CPUID_GST_AMD_FEATURE_EMU
1727	#undef CPUID_GST_AMD_FEATURE_IGN
1728
1729	return VINF_SUCCESS;
1730	}
1731
1732
1733	/**
1734	* Pass 0 live exec callback.
1735	*
1736	* @returns VINF_SSM_DONT_CALL_AGAIN.
1737	* @param pVM The VM handle.
1738	* @param pSSM The saved state handle.
1739	* @param uPass The pass (0).
1740	*/
1741	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1742	{
1743	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1744	cpumR3SaveCpuId(pVM, pSSM);
1745	return VINF_SSM_DONT_CALL_AGAIN;
1746	}
1747
1748
1749	/**
1750	* Execute state save operation.
1751	*
1752	* @returns VBox status code.
1753	* @param pVM VM Handle.
1754	* @param pSSM SSM operation handle.
1755	*/
1756	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1757	{
1758	/*
1759	* Save.
1760	*/
1761	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1762	{
1763	PVMCPU pVCpu = &pVM->aCpus[i];
1764
1765	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1766	}
1767
1768	SSMR3PutU32(pSSM, pVM->cCpus);
1769	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1770	{
1771	PVMCPU pVCpu = &pVM->aCpus[i];
1772
1773	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1774	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1775	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1776	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1777	}
1778
1779	cpumR3SaveCpuId(pVM, pSSM);
1780	return VINF_SUCCESS;
1781	}
1782
1783
1784	/**
1785	* Load a version 1.6 CPUMCTX structure.
1786	*
1787	* @returns VBox status code.
1788	* @param pVM VM Handle.
1789	* @param pCpumctx16 Version 1.6 CPUMCTX
1790	*/
1791	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1792	{
1793	#define CPUMCTX16_LOADREG(RegName) \
1794	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1795
1796	#define CPUMCTX16_LOADDRXREG(RegName) \
1797	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1798
1799	#define CPUMCTX16_LOADHIDREG(RegName) \
1800	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1801	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1802	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1803
1804	#define CPUMCTX16_LOADSEGREG(RegName) \
1805	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1806	CPUMCTX16_LOADHIDREG(RegName);
1807
1808	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1809
1810	CPUMCTX16_LOADREG(rax);
1811	CPUMCTX16_LOADREG(rbx);
1812	CPUMCTX16_LOADREG(rcx);
1813	CPUMCTX16_LOADREG(rdx);
1814	CPUMCTX16_LOADREG(rdi);
1815	CPUMCTX16_LOADREG(rsi);
1816	CPUMCTX16_LOADREG(rbp);
1817	CPUMCTX16_LOADREG(esp);
1818	CPUMCTX16_LOADREG(rip);
1819	CPUMCTX16_LOADREG(rflags);
1820
1821	CPUMCTX16_LOADSEGREG(cs);
1822	CPUMCTX16_LOADSEGREG(ds);
1823	CPUMCTX16_LOADSEGREG(es);
1824	CPUMCTX16_LOADSEGREG(fs);
1825	CPUMCTX16_LOADSEGREG(gs);
1826	CPUMCTX16_LOADSEGREG(ss);
1827
1828	CPUMCTX16_LOADREG(r8);
1829	CPUMCTX16_LOADREG(r9);
1830	CPUMCTX16_LOADREG(r10);
1831	CPUMCTX16_LOADREG(r11);
1832	CPUMCTX16_LOADREG(r12);
1833	CPUMCTX16_LOADREG(r13);
1834	CPUMCTX16_LOADREG(r14);
1835	CPUMCTX16_LOADREG(r15);
1836
1837	CPUMCTX16_LOADREG(cr0);
1838	CPUMCTX16_LOADREG(cr2);
1839	CPUMCTX16_LOADREG(cr3);
1840	CPUMCTX16_LOADREG(cr4);
1841
1842	CPUMCTX16_LOADDRXREG(0);
1843	CPUMCTX16_LOADDRXREG(1);
1844	CPUMCTX16_LOADDRXREG(2);
1845	CPUMCTX16_LOADDRXREG(3);
1846	CPUMCTX16_LOADDRXREG(4);
1847	CPUMCTX16_LOADDRXREG(5);
1848	CPUMCTX16_LOADDRXREG(6);
1849	CPUMCTX16_LOADDRXREG(7);
1850
1851	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1852	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1853	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1854	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1855
1856	CPUMCTX16_LOADREG(ldtr);
1857	CPUMCTX16_LOADREG(tr);
1858
1859	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1860
1861	CPUMCTX16_LOADREG(msrEFER);
1862	CPUMCTX16_LOADREG(msrSTAR);
1863	CPUMCTX16_LOADREG(msrPAT);
1864	CPUMCTX16_LOADREG(msrLSTAR);
1865	CPUMCTX16_LOADREG(msrCSTAR);
1866	CPUMCTX16_LOADREG(msrSFMASK);
1867	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1868
1869	CPUMCTX16_LOADHIDREG(ldtr);
1870	CPUMCTX16_LOADHIDREG(tr);
1871
1872	#undef CPUMCTX16_LOADSEGREG
1873	#undef CPUMCTX16_LOADHIDREG
1874	#undef CPUMCTX16_LOADDRXREG
1875	#undef CPUMCTX16_LOADREG
1876	}
1877
1878
1879	/**
1880	* @copydoc FNSSMINTLOADPREP
1881	*/
1882	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1883	{
1884	pVM->cpum.s.fPendingRestore = true;
1885	return VINF_SUCCESS;
1886	}
1887
1888
1889	/**
1890	* @copydoc FNSSMINTLOADEXEC
1891	*/
1892	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1893	{
1894	/*
1895	* Validate version.
1896	*/
1897	if ( uVersion != CPUM_SAVED_STATE_VERSION
1898	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1899	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1900	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1901	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1902	{
1903	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1904	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1905	}
1906
1907	if (uPass == SSM_PASS_FINAL)
1908	{
1909	/*
1910	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1911	* really old SSM file versions.)
1912	*/
1913	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1914	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1915	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1916	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1917
1918	/*
1919	* Restore.
1920	*/
1921	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1922	{
1923	PVMCPU pVCpu = &pVM->aCpus[i];
1924	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1925	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1926
1927	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1928	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1929	pVCpu->cpum.s.Hyper.esp = uESP;
1930	}
1931
1932	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1933	{
1934	CPUMCTX_VER1_6 cpumctx16;
1935	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1936	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1937
1938	/* Save the old cpumctx state into the new one. */
1939	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1940
1941	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1942	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1943	}
1944	else
1945	{
1946	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1947	{
1948	uint32_t cCpus;
1949	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1950	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1951	VERR_SSM_UNEXPECTED_DATA);
1952	}
1953	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1954	\|\| pVM->cCpus == 1,
1955	("cCpus=%u\n", pVM->cCpus),
1956	VERR_SSM_UNEXPECTED_DATA);
1957
1958	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1959	{
1960	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1961	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1962	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1963	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1964	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1965	}
1966	}
1967	}
1968
1969	pVM->cpum.s.fPendingRestore = false;
1970
1971	/*
1972	* Guest CPUIDs.
1973	*/
1974	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1975	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1976
1977	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1978	* actually required. */
1979
1980	/*
1981	* Restore the CPUID leaves.
1982	*
1983	* Note that we support restoring less than the current amount of standard
1984	* leaves because we've been allowed more is newer version of VBox.
1985	*/
1986	uint32_t cElements;
1987	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1988	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1989	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1990	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1991
1992	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1993	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1994	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1995	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1996
1997	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1998	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1999	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2000	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2001
2002	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2003
2004	/*
2005	* Check that the basic cpuid id information is unchanged.
2006	*/
2007	/** @todo we should check the 64 bits capabilities too! */
2008	uint32_t au32CpuId[8] = {0};
2009	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2010	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2011	uint32_t au32CpuIdSaved[8];
2012	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2013	if (RT_SUCCESS(rc))
2014	{
2015	/* Ignore CPU stepping. */
2016	au32CpuId[4] &= 0xfffffff0;
2017	au32CpuIdSaved[4] &= 0xfffffff0;
2018
2019	/* Ignore APIC ID (AMD specs). */
2020	au32CpuId[5] &= ~0xff000000;
2021	au32CpuIdSaved[5] &= ~0xff000000;
2022
2023	/* Ignore the number of Logical CPUs (AMD specs). */
2024	au32CpuId[5] &= ~0x00ff0000;
2025	au32CpuIdSaved[5] &= ~0x00ff0000;
2026
2027	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2028	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2029	\| X86_CPUID_FEATURE_ECX_VMX
2030	\| X86_CPUID_FEATURE_ECX_SMX
2031	\| X86_CPUID_FEATURE_ECX_EST
2032	\| X86_CPUID_FEATURE_ECX_TM2
2033	\| X86_CPUID_FEATURE_ECX_CNTXID
2034	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2035	\| X86_CPUID_FEATURE_ECX_PDCM
2036	\| X86_CPUID_FEATURE_ECX_DCA
2037	\| X86_CPUID_FEATURE_ECX_X2APIC
2038	);
2039	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2040	\| X86_CPUID_FEATURE_ECX_VMX
2041	\| X86_CPUID_FEATURE_ECX_SMX
2042	\| X86_CPUID_FEATURE_ECX_EST
2043	\| X86_CPUID_FEATURE_ECX_TM2
2044	\| X86_CPUID_FEATURE_ECX_CNTXID
2045	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2046	\| X86_CPUID_FEATURE_ECX_PDCM
2047	\| X86_CPUID_FEATURE_ECX_DCA
2048	\| X86_CPUID_FEATURE_ECX_X2APIC
2049	);
2050
2051	/* Make sure we don't forget to update the masks when enabling
2052	* features in the future.
2053	*/
2054	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2055	( X86_CPUID_FEATURE_ECX_DTES64
2056	\| X86_CPUID_FEATURE_ECX_VMX
2057	\| X86_CPUID_FEATURE_ECX_SMX
2058	\| X86_CPUID_FEATURE_ECX_EST
2059	\| X86_CPUID_FEATURE_ECX_TM2
2060	\| X86_CPUID_FEATURE_ECX_CNTXID
2061	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2062	\| X86_CPUID_FEATURE_ECX_PDCM
2063	\| X86_CPUID_FEATURE_ECX_DCA
2064	\| X86_CPUID_FEATURE_ECX_X2APIC
2065	)));
2066	/* do the compare */
2067	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2068	{
2069	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2070	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2071	"Saved=%.*Rhxs\n"
2072	"Real =%.*Rhxs\n",
2073	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2074	sizeof(au32CpuId), au32CpuId));
2075	else
2076	{
2077	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2078	"Saved=%.*Rhxs\n"
2079	"Real =%.*Rhxs\n",
2080	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2081	sizeof(au32CpuId), au32CpuId));
2082	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2083	}
2084	}
2085	}
2086
2087	return rc;
2088	}
2089
2090
2091	/**
2092	* @copydoc FNSSMINTLOADPREP
2093	*/
2094	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2095	{
2096	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2097	return VINF_SUCCESS;
2098
2099	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2100	if (pVM->cpum.s.fPendingRestore)
2101	{
2102	LogRel(("CPUM: Missing state!\n"));
2103	return VERR_INTERNAL_ERROR_2;
2104	}
2105
2106	return VINF_SUCCESS;
2107	}
2108
2109
2110	/**
2111	* Checks if the CPUM state restore is still pending.
2112	*
2113	* @returns true / false.
2114	* @param pVM The VM handle.
2115	*/
2116	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2117	{
2118	return pVM->cpum.s.fPendingRestore;
2119	}
2120
2121
2122	/**
2123	* Formats the EFLAGS value into mnemonics.
2124	*
2125	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2126	* @param efl The EFLAGS value.
2127	*/
2128	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2129	{
2130	/*
2131	* Format the flags.
2132	*/
2133	static const struct
2134	{
2135	const char pszSet; const char pszClear; uint32_t fFlag;
2136	} s_aFlags[] =
2137	{
2138	{ "vip",NULL, X86_EFL_VIP },
2139	{ "vif",NULL, X86_EFL_VIF },
2140	{ "ac", NULL, X86_EFL_AC },
2141	{ "vm", NULL, X86_EFL_VM },
2142	{ "rf", NULL, X86_EFL_RF },
2143	{ "nt", NULL, X86_EFL_NT },
2144	{ "ov", "nv", X86_EFL_OF },
2145	{ "dn", "up", X86_EFL_DF },
2146	{ "ei", "di", X86_EFL_IF },
2147	{ "tf", NULL, X86_EFL_TF },
2148	{ "nt", "pl", X86_EFL_SF },
2149	{ "nz", "zr", X86_EFL_ZF },
2150	{ "ac", "na", X86_EFL_AF },
2151	{ "po", "pe", X86_EFL_PF },
2152	{ "cy", "nc", X86_EFL_CF },
2153	};
2154	char *psz = pszEFlags;
2155	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2156	{
2157	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2158	if (pszAdd)
2159	{
2160	strcpy(psz, pszAdd);
2161	psz += strlen(pszAdd);
2162	*psz++ = ' ';
2163	}
2164	}
2165	psz[-1] = '\0';
2166	}
2167
2168
2169	/**
2170	* Formats a full register dump.
2171	*
2172	* @param pVM VM Handle.
2173	* @param pCtx The context to format.
2174	* @param pCtxCore The context core to format.
2175	* @param pHlp Output functions.
2176	* @param enmType The dump type.
2177	* @param pszPrefix Register name prefix.
2178	*/
2179	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2180	{
2181	/*
2182	* Format the EFLAGS.
2183	*/
2184	uint32_t efl = pCtxCore->eflags.u32;
2185	char szEFlags[80];
2186	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2187
2188	/*
2189	* Format the registers.
2190	*/
2191	switch (enmType)
2192	{
2193	case CPUMDUMPTYPE_TERSE:
2194	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2195	pHlp->pfnPrintf(pHlp,
2196	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2197	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2198	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2199	"%sr14=%016RX64 %sr15=%016RX64\n"
2200	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2201	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2202	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2203	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2204	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2205	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2206	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2207	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2208	else
2209	pHlp->pfnPrintf(pHlp,
2210	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2211	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2212	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2213	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2214	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2215	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2216	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2217	break;
2218
2219	case CPUMDUMPTYPE_DEFAULT:
2220	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2221	pHlp->pfnPrintf(pHlp,
2222	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2223	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2224	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2225	"%sr14=%016RX64 %sr15=%016RX64\n"
2226	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2227	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2228	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2229	,
2230	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2231	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2232	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2233	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2234	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2235	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2236	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2237	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2238	else
2239	pHlp->pfnPrintf(pHlp,
2240	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2241	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2242	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2243	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2244	,
2245	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2246	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2247	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2248	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2249	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2250	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2251	break;
2252
2253	case CPUMDUMPTYPE_VERBOSE:
2254	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2255	pHlp->pfnPrintf(pHlp,
2256	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2257	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2258	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2259	"%sr14=%016RX64 %sr15=%016RX64\n"
2260	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2261	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2262	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2263	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2264	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2265	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2266	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2267	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2268	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2269	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2270	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2271	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2272	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2273	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2274	,
2275	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2276	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2277	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2278	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2279	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2280	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2281	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2282	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2283	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2284	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2285	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2286	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2287	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2288	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2289	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2290	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2291	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2292	else
2293	pHlp->pfnPrintf(pHlp,
2294	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2295	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2296	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2297	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2298	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2299	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2300	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2301	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2302	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2303	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2304	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2305	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2306	,
2307	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2308	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2309	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2310	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2311	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2312	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2313	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2314	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2315	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2316	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2317	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2318	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2319
2320	pHlp->pfnPrintf(pHlp,
2321	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2322	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2323	,
2324	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2325	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2326	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2327	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2328	);
2329	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2330	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2331	{
2332	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2333	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2334	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2335	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2336	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2337	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2338	/** @todo This isn't entirenly correct and needs more work! */
2339	pHlp->pfnPrintf(pHlp,
2340	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2341	pszPrefix, iST, pszPrefix, iFPR,
2342	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2343	uTag, chSign, iInteger, u64Fraction, uExponent);
2344	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2345	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2346	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2347	else
2348	pHlp->pfnPrintf(pHlp, "\n");
2349	}
2350	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2351	pHlp->pfnPrintf(pHlp,
2352	iXMM & 1
2353	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2354	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2355	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2356	pCtx->fpu.aXMM[iXMM].au32[3],
2357	pCtx->fpu.aXMM[iXMM].au32[2],
2358	pCtx->fpu.aXMM[iXMM].au32[1],
2359	pCtx->fpu.aXMM[iXMM].au32[0]);
2360	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2361	if (pCtx->fpu.au32RsrvdRest[i])
2362	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2363	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2364
2365	pHlp->pfnPrintf(pHlp,
2366	"%sEFER =%016RX64\n"
2367	"%sPAT =%016RX64\n"
2368	"%sSTAR =%016RX64\n"
2369	"%sCSTAR =%016RX64\n"
2370	"%sLSTAR =%016RX64\n"
2371	"%sSFMASK =%016RX64\n"
2372	"%sKERNELGSBASE =%016RX64\n",
2373	pszPrefix, pCtx->msrEFER,
2374	pszPrefix, pCtx->msrPAT,
2375	pszPrefix, pCtx->msrSTAR,
2376	pszPrefix, pCtx->msrCSTAR,
2377	pszPrefix, pCtx->msrLSTAR,
2378	pszPrefix, pCtx->msrSFMASK,
2379	pszPrefix, pCtx->msrKERNELGSBASE);
2380	break;
2381	}
2382	}
2383
2384
2385	/**
2386	* Display all cpu states and any other cpum info.
2387	*
2388	* @param pVM VM Handle.
2389	* @param pHlp The info helper functions.
2390	* @param pszArgs Arguments, ignored.
2391	*/
2392	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2393	{
2394	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2395	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2396	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2397	cpumR3InfoHost(pVM, pHlp, pszArgs);
2398	}
2399
2400
2401	/**
2402	* Parses the info argument.
2403	*
2404	* The argument starts with 'verbose', 'terse' or 'default' and then
2405	* continues with the comment string.
2406	*
2407	* @param pszArgs The pointer to the argument string.
2408	* @param penmType Where to store the dump type request.
2409	* @param ppszComment Where to store the pointer to the comment string.
2410	*/
2411	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2412	{
2413	if (!pszArgs)
2414	{
2415	*penmType = CPUMDUMPTYPE_DEFAULT;
2416	*ppszComment = "";
2417	}
2418	else
2419	{
2420	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2421	{
2422	pszArgs += 5;
2423	*penmType = CPUMDUMPTYPE_VERBOSE;
2424	}
2425	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2426	{
2427	pszArgs += 5;
2428	*penmType = CPUMDUMPTYPE_TERSE;
2429	}
2430	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2431	{
2432	pszArgs += 7;
2433	*penmType = CPUMDUMPTYPE_DEFAULT;
2434	}
2435	else
2436	*penmType = CPUMDUMPTYPE_DEFAULT;
2437	*ppszComment = RTStrStripL(pszArgs);
2438	}
2439	}
2440
2441
2442	/**
2443	* Display the guest cpu state.
2444	*
2445	* @param pVM VM Handle.
2446	* @param pHlp The info helper functions.
2447	* @param pszArgs Arguments, ignored.
2448	*/
2449	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2450	{
2451	CPUMDUMPTYPE enmType;
2452	const char *pszComment;
2453	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2454
2455	/* @todo SMP support! */
2456	PVMCPU pVCpu = VMMGetCpu(pVM);
2457	if (!pVCpu)
2458	pVCpu = &pVM->aCpus[0];
2459
2460	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2461
2462	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2463	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2464	}
2465
2466
2467	/**
2468	* Display the current guest instruction
2469	*
2470	* @param pVM VM Handle.
2471	* @param pHlp The info helper functions.
2472	* @param pszArgs Arguments, ignored.
2473	*/
2474	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2475	{
2476	char szInstruction[256];
2477	/* @todo SMP support! */
2478	PVMCPU pVCpu = VMMGetCpu(pVM);
2479	if (!pVCpu)
2480	pVCpu = &pVM->aCpus[0];
2481
2482	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2483	if (RT_SUCCESS(rc))
2484	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2485	}
2486
2487
2488	/**
2489	* Display the hypervisor cpu state.
2490	*
2491	* @param pVM VM Handle.
2492	* @param pHlp The info helper functions.
2493	* @param pszArgs Arguments, ignored.
2494	*/
2495	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2496	{
2497	CPUMDUMPTYPE enmType;
2498	const char *pszComment;
2499	/* @todo SMP */
2500	PVMCPU pVCpu = &pVM->aCpus[0];
2501
2502	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2503	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2504	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2505	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2506	}
2507
2508
2509	/**
2510	* Display the host cpu state.
2511	*
2512	* @param pVM VM Handle.
2513	* @param pHlp The info helper functions.
2514	* @param pszArgs Arguments, ignored.
2515	*/
2516	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2517	{
2518	CPUMDUMPTYPE enmType;
2519	const char *pszComment;
2520	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2521	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2522
2523	/*
2524	* Format the EFLAGS.
2525	*/
2526	/* @todo SMP */
2527	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2528	#if HC_ARCH_BITS == 32
2529	uint32_t efl = pCtx->eflags.u32;
2530	#else
2531	uint64_t efl = pCtx->rflags;
2532	#endif
2533	char szEFlags[80];
2534	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2535
2536	/*
2537	* Format the registers.
2538	*/
2539	#if HC_ARCH_BITS == 32
2540	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2541	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2542	# endif
2543	{
2544	pHlp->pfnPrintf(pHlp,
2545	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2546	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2547	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2548	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2549	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2550	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2551	,
2552	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2553	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2554	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2555	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2556	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2557	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2558	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2559	}
2560	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2561	else
2562	# endif
2563	#endif
2564	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2565	{
2566	pHlp->pfnPrintf(pHlp,
2567	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2568	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2569	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2570	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2571	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2572	"r14=%016RX64 r15=%016RX64\n"
2573	"iopl=%d %31s\n"
2574	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2575	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2576	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2577	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2578	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2579	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2580	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2581	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2582	,
2583	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2584	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2585	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2586	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2587	pCtx->r11, pCtx->r12, pCtx->r13,
2588	pCtx->r14, pCtx->r15,
2589	X86_EFL_GET_IOPL(efl), szEFlags,
2590	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2591	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2592	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2593	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2594	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2595	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2596	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2597	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2598	}
2599	#endif
2600	}
2601
2602
2603	/**
2604	* Get L1 cache / TLS associativity.
2605	*/
2606	static const char getCacheAss(unsigned u, char pszBuf)
2607	{
2608	if (u == 0)
2609	return "res0 ";
2610	if (u == 1)
2611	return "direct";
2612	if (u >= 256)
2613	return "???";
2614
2615	RTStrPrintf(pszBuf, 16, "%d way", u);
2616	return pszBuf;
2617	}
2618
2619
2620	/**
2621	* Get L2 cache soociativity.
2622	*/
2623	const char *getL2CacheAss(unsigned u)
2624	{
2625	switch (u)
2626	{
2627	case 0: return "off ";
2628	case 1: return "direct";
2629	case 2: return "2 way ";
2630	case 3: return "res3 ";
2631	case 4: return "4 way ";
2632	case 5: return "res5 ";
2633	case 6: return "8 way "; case 7: return "res7 ";
2634	case 8: return "16 way";
2635	case 9: return "res9 ";
2636	case 10: return "res10 ";
2637	case 11: return "res11 ";
2638	case 12: return "res12 ";
2639	case 13: return "res13 ";
2640	case 14: return "res14 ";
2641	case 15: return "fully ";
2642	default:
2643	return "????";
2644	}
2645	}
2646
2647
2648	/**
2649	* Display the guest CpuId leaves.
2650	*
2651	* @param pVM VM Handle.
2652	* @param pHlp The info helper functions.
2653	* @param pszArgs "terse", "default" or "verbose".
2654	*/
2655	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2656	{
2657	/*
2658	* Parse the argument.
2659	*/
2660	unsigned iVerbosity = 1;
2661	if (pszArgs)
2662	{
2663	pszArgs = RTStrStripL(pszArgs);
2664	if (!strcmp(pszArgs, "terse"))
2665	iVerbosity--;
2666	else if (!strcmp(pszArgs, "verbose"))
2667	iVerbosity++;
2668	}
2669
2670	/*
2671	* Start cracking.
2672	*/
2673	CPUMCPUID Host;
2674	CPUMCPUID Guest;
2675	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2676
2677	pHlp->pfnPrintf(pHlp,
2678	" RAW Standard CPUIDs\n"
2679	" Function eax ebx ecx edx\n");
2680	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2681	{
2682	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2683	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2684
2685	pHlp->pfnPrintf(pHlp,
2686	"Gst: %08x %08x %08x %08x %08x%s\n"
2687	"Hst: %08x %08x %08x %08x\n",
2688	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2689	i <= cStdMax ? "" : "*",
2690	Host.eax, Host.ebx, Host.ecx, Host.edx);
2691	}
2692
2693	/*
2694	* If verbose, decode it.
2695	*/
2696	if (iVerbosity)
2697	{
2698	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2699	pHlp->pfnPrintf(pHlp,
2700	"Name: %.04s%.04s%.04s\n"
2701	"Supports: 0-%x\n",
2702	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2703	}
2704
2705	/*
2706	* Get Features.
2707	*/
2708	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2709	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2710	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2711	if (cStdMax >= 1 && iVerbosity)
2712	{
2713	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2714	uint32_t uEAX = Guest.eax;
2715
2716	pHlp->pfnPrintf(pHlp,
2717	"Family: %d \tExtended: %d \tEffective: %d\n"
2718	"Model: %d \tExtended: %d \tEffective: %d\n"
2719	"Stepping: %d\n"
2720	"Type: %d\n"
2721	"APIC ID: %#04x\n"
2722	"Logical CPUs: %d\n"
2723	"CLFLUSH Size: %d\n"
2724	"Brand ID: %#04x\n",
2725	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2726	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2727	ASMGetCpuStepping(uEAX),
2728	(uEAX >> 12) & 3,
2729	(Guest.ebx >> 24) & 0xff,
2730	(Guest.ebx >> 16) & 0xff,
2731	(Guest.ebx >> 8) & 0xff,
2732	(Guest.ebx >> 0) & 0xff);
2733	if (iVerbosity == 1)
2734	{
2735	uint32_t uEDX = Guest.edx;
2736	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2737	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2738	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2739	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2740	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2741	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2742	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2743	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2744	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2745	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2746	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2747	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2748	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2749	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2750	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2751	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2752	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2753	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2754	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2755	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2756	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2757	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2758	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2759	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2760	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2761	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2762	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2763	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2764	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2765	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2766	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2767	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2768	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2769	pHlp->pfnPrintf(pHlp, "\n");
2770
2771	uint32_t uECX = Guest.ecx;
2772	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2773	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2774	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2775	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2776	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2777	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2778	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2779	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2780	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2781	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2782	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2783	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2784	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2785	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2786	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2787	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2788	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2789	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2790	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " 17");
2791	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2792	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4_1");
2793	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4_2");
2794	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2795	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2796	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2797	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " 24");
2798	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2799	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2800	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2801	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2802	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2803	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2804	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2805	pHlp->pfnPrintf(pHlp, "\n");
2806	}
2807	else
2808	{
2809	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2810
2811	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2812	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2813	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2814	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2815
2816	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2817	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2818	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2819	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2820	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2821	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2822	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2823	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2824	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2825	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2826	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2827	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2828	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2829	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2830	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2831	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2832	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2833	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2834	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2835	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2836	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2837	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2838	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2839	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2840	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2841	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2842	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2843	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2844	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2845	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2846	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2847	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2848	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2849
2850	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2851	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2852	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2853	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2854	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2855	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2856	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2857	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2858	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2859	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2860	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2861	pHlp->pfnPrintf(pHlp, "FMA = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
2862	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2863	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2864	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2865	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2866	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2867	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2868	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2869	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2870	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2871	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2872	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2873	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
2874	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2875	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2876	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2877	}
2878	}
2879	if (cStdMax >= 2 && iVerbosity)
2880	{
2881	/** @todo */
2882	}
2883
2884	/*
2885	* Extended.
2886	* Implemented after AMD specs.
2887	*/
2888	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2889
2890	pHlp->pfnPrintf(pHlp,
2891	"\n"
2892	" RAW Extended CPUIDs\n"
2893	" Function eax ebx ecx edx\n");
2894	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2895	{
2896	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2897	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2898
2899	pHlp->pfnPrintf(pHlp,
2900	"Gst: %08x %08x %08x %08x %08x%s\n"
2901	"Hst: %08x %08x %08x %08x\n",
2902	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2903	i <= cExtMax ? "" : "*",
2904	Host.eax, Host.ebx, Host.ecx, Host.edx);
2905	}
2906
2907	/*
2908	* Understandable output
2909	*/
2910	if (iVerbosity)
2911	{
2912	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2913	pHlp->pfnPrintf(pHlp,
2914	"Ext Name: %.4s%.4s%.4s\n"
2915	"Ext Supports: 0x80000000-%#010x\n",
2916	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2917	}
2918
2919	if (iVerbosity && cExtMax >= 1)
2920	{
2921	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2922	uint32_t uEAX = Guest.eax;
2923	pHlp->pfnPrintf(pHlp,
2924	"Family: %d \tExtended: %d \tEffective: %d\n"
2925	"Model: %d \tExtended: %d \tEffective: %d\n"
2926	"Stepping: %d\n"
2927	"Brand ID: %#05x\n",
2928	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2929	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2930	ASMGetCpuStepping(uEAX),
2931	Guest.ebx & 0xfff);
2932
2933	if (iVerbosity == 1)
2934	{
2935	uint32_t uEDX = Guest.edx;
2936	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2937	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2938	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2939	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2940	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2941	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2942	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2943	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2944	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2945	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2946	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2947	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2948	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2949	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2950	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2951	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2952	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2953	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2954	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2955	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2956	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2957	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2958	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2959	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2960	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2961	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2962	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2963	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2964	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2965	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2966	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2967	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2968	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2969	pHlp->pfnPrintf(pHlp, "\n");
2970
2971	uint32_t uECX = Guest.ecx;
2972	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2973	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2974	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2975	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2976	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2977	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2978	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2979	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2980	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2981	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2982	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2983	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2984	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2985	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2986	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2987	for (unsigned iBit = 5; iBit < 32; iBit++)
2988	if (uECX & RT_BIT(iBit))
2989	pHlp->pfnPrintf(pHlp, " %d", iBit);
2990	pHlp->pfnPrintf(pHlp, "\n");
2991	}
2992	else
2993	{
2994	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2995
2996	uint32_t uEdxGst = Guest.edx;
2997	uint32_t uEdxHst = Host.edx;
2998	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2999	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3000	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3001	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3002	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3003	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3004	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3005	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3006	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3007	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3008	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3009	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3010	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3011	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3012	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3013	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3014	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3015	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3016	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3017	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3018	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3019	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3020	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3021	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3022	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3023	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3024	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3025	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3026	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3027	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3028	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3029	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3030	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3031
3032	uint32_t uEcxGst = Guest.ecx;
3033	uint32_t uEcxHst = Host.ecx;
3034	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3035	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3036	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3037	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3038	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3039	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3040	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3041	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3042	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3043	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3044	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3045	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3046	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3047	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3048	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3049	}
3050	}
3051
3052	if (iVerbosity && cExtMax >= 2)
3053	{
3054	char szString[443+1] = {0};
3055	uint32_t pu32 = (uint32_t )szString;
3056	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3057	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3058	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3059	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3060	if (cExtMax >= 3)
3061	{
3062	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3063	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3064	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3065	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3066	}
3067	if (cExtMax >= 4)
3068	{
3069	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3070	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3071	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3072	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3073	}
3074	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3075	}
3076
3077	if (iVerbosity && cExtMax >= 5)
3078	{
3079	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3080	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3081	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3082	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3083	char sz1[32];
3084	char sz2[32];
3085
3086	pHlp->pfnPrintf(pHlp,
3087	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3088	"TLB 2/4M Data: %s %3d entries\n",
3089	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3090	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3091	pHlp->pfnPrintf(pHlp,
3092	"TLB 4K Instr/Uni: %s %3d entries\n"
3093	"TLB 4K Data: %s %3d entries\n",
3094	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3095	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3096	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3097	"L1 Instr Cache Lines Per Tag: %d\n"
3098	"L1 Instr Cache Associativity: %s\n"
3099	"L1 Instr Cache Size: %d KB\n",
3100	(uEDX >> 0) & 0xff,
3101	(uEDX >> 8) & 0xff,
3102	getCacheAss((uEDX >> 16) & 0xff, sz1),
3103	(uEDX >> 24) & 0xff);
3104	pHlp->pfnPrintf(pHlp,
3105	"L1 Data Cache Line Size: %d bytes\n"
3106	"L1 Data Cache Lines Per Tag: %d\n"
3107	"L1 Data Cache Associativity: %s\n"
3108	"L1 Data Cache Size: %d KB\n",
3109	(uECX >> 0) & 0xff,
3110	(uECX >> 8) & 0xff,
3111	getCacheAss((uECX >> 16) & 0xff, sz1),
3112	(uECX >> 24) & 0xff);
3113	}
3114
3115	if (iVerbosity && cExtMax >= 6)
3116	{
3117	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3118	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3119	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3120
3121	pHlp->pfnPrintf(pHlp,
3122	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3123	"L2 TLB 2/4M Data: %s %4d entries\n",
3124	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3125	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3126	pHlp->pfnPrintf(pHlp,
3127	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3128	"L2 TLB 4K Data: %s %4d entries\n",
3129	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3130	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3131	pHlp->pfnPrintf(pHlp,
3132	"L2 Cache Line Size: %d bytes\n"
3133	"L2 Cache Lines Per Tag: %d\n"
3134	"L2 Cache Associativity: %s\n"
3135	"L2 Cache Size: %d KB\n",
3136	(uEDX >> 0) & 0xff,
3137	(uEDX >> 8) & 0xf,
3138	getL2CacheAss((uEDX >> 12) & 0xf),
3139	(uEDX >> 16) & 0xffff);
3140	}
3141
3142	if (iVerbosity && cExtMax >= 7)
3143	{
3144	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3145
3146	pHlp->pfnPrintf(pHlp, "APM Features: ");
3147	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3148	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3149	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3150	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3151	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3152	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3153	for (unsigned iBit = 6; iBit < 32; iBit++)
3154	if (uEDX & RT_BIT(iBit))
3155	pHlp->pfnPrintf(pHlp, " %d", iBit);
3156	pHlp->pfnPrintf(pHlp, "\n");
3157	}
3158
3159	if (iVerbosity && cExtMax >= 8)
3160	{
3161	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3162	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3163
3164	pHlp->pfnPrintf(pHlp,
3165	"Physical Address Width: %d bits\n"
3166	"Virtual Address Width: %d bits\n",
3167	(uEAX >> 0) & 0xff,
3168	(uEAX >> 8) & 0xff);
3169	pHlp->pfnPrintf(pHlp,
3170	"Physical Core Count: %d\n",
3171	(uECX >> 0) & 0xff);
3172	}
3173
3174
3175	/*
3176	* Centaur.
3177	*/
3178	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3179
3180	pHlp->pfnPrintf(pHlp,
3181	"\n"
3182	" RAW Centaur CPUIDs\n"
3183	" Function eax ebx ecx edx\n");
3184	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3185	{
3186	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3187	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3188
3189	pHlp->pfnPrintf(pHlp,
3190	"Gst: %08x %08x %08x %08x %08x%s\n"
3191	"Hst: %08x %08x %08x %08x\n",
3192	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3193	i <= cCentaurMax ? "" : "*",
3194	Host.eax, Host.ebx, Host.ecx, Host.edx);
3195	}
3196
3197	/*
3198	* Understandable output
3199	*/
3200	if (iVerbosity)
3201	{
3202	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3203	pHlp->pfnPrintf(pHlp,
3204	"Centaur Supports: 0xc0000000-%#010x\n",
3205	Guest.eax);
3206	}
3207
3208	if (iVerbosity && cCentaurMax >= 1)
3209	{
3210	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3211	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3212	uint32_t uEdxHst = Host.edx;
3213
3214	if (iVerbosity == 1)
3215	{
3216	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3217	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3218	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3219	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3220	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3221	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3222	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3223	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3224	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3225	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3226	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3227	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3228	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3229	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3230	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3231	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3232	for (unsigned iBit = 14; iBit < 32; iBit++)
3233	if (uEdxGst & RT_BIT(iBit))
3234	pHlp->pfnPrintf(pHlp, " %d", iBit);
3235	pHlp->pfnPrintf(pHlp, "\n");
3236	}
3237	else
3238	{
3239	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3240	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3241	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3242	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3243	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3244	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3245	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3246	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3247	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3248	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3249	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3250	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3251	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3252	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3253	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3254	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3255	for (unsigned iBit = 14; iBit < 32; iBit++)
3256	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3257	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3258	pHlp->pfnPrintf(pHlp, "\n");
3259	}
3260	}
3261	}
3262
3263
3264	/**
3265	* Structure used when disassembling and instructions in DBGF.
3266	* This is used so the reader function can get the stuff it needs.
3267	*/
3268	typedef struct CPUMDISASSTATE
3269	{
3270	/** Pointer to the CPU structure. */
3271	PDISCPUSTATE pCpu;
3272	/** The VM handle. */
3273	PVM pVM;
3274	/** The VMCPU handle. */
3275	PVMCPU pVCpu;
3276	/** Pointer to the first byte in the segemnt. */
3277	RTGCUINTPTR GCPtrSegBase;
3278	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3279	RTGCUINTPTR GCPtrSegEnd;
3280	/** The size of the segment minus 1. */
3281	RTGCUINTPTR cbSegLimit;
3282	/** Pointer to the current page - R3 Ptr. */
3283	void const *pvPageR3;
3284	/** Pointer to the current page - GC Ptr. */
3285	RTGCPTR pvPageGC;
3286	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3287	PGMPAGEMAPLOCK PageMapLock;
3288	/** Whether the PageMapLock is valid or not. */
3289	bool fLocked;
3290	/** 64 bits mode or not. */
3291	bool f64Bits;
3292	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3293
3294
3295	/**
3296	* Instruction reader.
3297	*
3298	* @returns VBox status code.
3299	* @param PtrSrc Address to read from.
3300	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3301	* @param pu8Dst Where to store the bytes.
3302	* @param cbRead Number of bytes to read.
3303	* @param uDisCpu Pointer to the disassembler cpu state.
3304	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3305	*/
3306	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3307	{
3308	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3309	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3310	Assert(cbRead > 0);
3311	for (;;)
3312	{
3313	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3314
3315	/* Need to update the page translation? */
3316	if ( !pState->pvPageR3
3317	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3318	{
3319	int rc = VINF_SUCCESS;
3320
3321	/* translate the address */
3322	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3323	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3324	&& !HWACCMIsEnabled(pState->pVM))
3325	{
3326	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3327	if (!pState->pvPageR3)
3328	rc = VERR_INVALID_POINTER;
3329	}
3330	else
3331	{
3332	/* Release mapping lock previously acquired. */
3333	if (pState->fLocked)
3334	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3335	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3336	pState->fLocked = RT_SUCCESS_NP(rc);
3337	}
3338	if (RT_FAILURE(rc))
3339	{
3340	pState->pvPageR3 = NULL;
3341	return rc;
3342	}
3343	}
3344
3345	/* check the segemnt limit */
3346	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3347	return VERR_OUT_OF_SELECTOR_BOUNDS;
3348
3349	/* calc how much we can read */
3350	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3351	if (!pState->f64Bits)
3352	{
3353	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3354	if (cb > cbSeg && cbSeg)
3355	cb = cbSeg;
3356	}
3357	if (cb > cbRead)
3358	cb = cbRead;
3359
3360	/* read and advance */
3361	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3362	cbRead -= cb;
3363	if (!cbRead)
3364	return VINF_SUCCESS;
3365	pu8Dst += cb;
3366	PtrSrc += cb;
3367	}
3368	}
3369
3370
3371	/**
3372	* Disassemble an instruction and return the information in the provided structure.
3373	*
3374	* @returns VBox status code.
3375	* @param pVM VM Handle
3376	* @param pVCpu VMCPU Handle
3377	* @param pCtx CPU context
3378	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3379	* @param pCpu Disassembly state
3380	* @param pszPrefix String prefix for logging (debug only)
3381	*
3382	*/
3383	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3384	{
3385	CPUMDISASSTATE State;
3386	int rc;
3387
3388	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3389	State.pCpu = pCpu;
3390	State.pvPageGC = 0;
3391	State.pvPageR3 = NULL;
3392	State.pVM = pVM;
3393	State.pVCpu = pVCpu;
3394	State.fLocked = false;
3395	State.f64Bits = false;
3396
3397	/*
3398	* Get selector information.
3399	*/
3400	if ( (pCtx->cr0 & X86_CR0_PE)
3401	&& pCtx->eflags.Bits.u1VM == 0)
3402	{
3403	if (CPUMAreHiddenSelRegsValid(pVM))
3404	{
3405	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3406	State.GCPtrSegBase = pCtx->csHid.u64Base;
3407	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3408	State.cbSegLimit = pCtx->csHid.u32Limit;
3409	pCpu->mode = (State.f64Bits)
3410	? CPUMODE_64BIT
3411	: pCtx->csHid.Attr.n.u1DefBig
3412	? CPUMODE_32BIT
3413	: CPUMODE_16BIT;
3414	}
3415	else
3416	{
3417	DBGFSELINFO SelInfo;
3418
3419	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3420	if (RT_FAILURE(rc))
3421	{
3422	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3423	return rc;
3424	}
3425
3426	/*
3427	* Validate the selector.
3428	*/
3429	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3430	if (RT_FAILURE(rc))
3431	{
3432	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3433	return rc;
3434	}
3435	State.GCPtrSegBase = SelInfo.GCPtrBase;
3436	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3437	State.cbSegLimit = SelInfo.cbLimit;
3438	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3439	}
3440	}
3441	else
3442	{
3443	/* real or V86 mode */
3444	pCpu->mode = CPUMODE_16BIT;
3445	State.GCPtrSegBase = pCtx->cs * 16;
3446	State.GCPtrSegEnd = 0xFFFFFFFF;
3447	State.cbSegLimit = 0xFFFFFFFF;
3448	}
3449
3450	/*
3451	* Disassemble the instruction.
3452	*/
3453	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3454	pCpu->apvUserData[0] = &State;
3455
3456	uint32_t cbInstr;
3457	#ifndef LOG_ENABLED
3458	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3459	if (RT_SUCCESS(rc))
3460	{
3461	#else
3462	char szOutput[160];
3463	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3464	if (RT_SUCCESS(rc))
3465	{
3466	/* log it */
3467	if (pszPrefix)
3468	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3469	else
3470	Log(("%s", szOutput));
3471	#endif
3472	rc = VINF_SUCCESS;
3473	}
3474	else
3475	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3476
3477	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3478	if (State.fLocked)
3479	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3480
3481	return rc;
3482	}
3483
3484	#ifdef DEBUG
3485
3486	/**
3487	* Disassemble an instruction and dump it to the log
3488	*
3489	* @returns VBox status code.
3490	* @param pVM VM Handle
3491	* @param pVCpu VMCPU Handle
3492	* @param pCtx CPU context
3493	* @param pc GC instruction pointer
3494	* @param pszPrefix String prefix for logging
3495	*
3496	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3497	*/
3498	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3499	{
3500	DISCPUSTATE Cpu;
3501	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3502	}
3503
3504
3505	/**
3506	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3507	*
3508	* @internal
3509	*/
3510	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3511	{
3512	/** @todo SMP support!! */
3513	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3514	}
3515
3516	#endif /* DEBUG */
3517
3518	/**
3519	* API for controlling a few of the CPU features found in CR4.
3520	*
3521	* Currently only X86_CR4_TSD is accepted as input.
3522	*
3523	* @returns VBox status code.
3524	*
3525	* @param pVM The VM handle.
3526	* @param fOr The CR4 OR mask.
3527	* @param fAnd The CR4 AND mask.
3528	*/
3529	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3530	{
3531	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3532	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3533
3534	pVM->cpum.s.CR4.OrMask &= fAnd;
3535	pVM->cpum.s.CR4.OrMask \|= fOr;
3536
3537	return VINF_SUCCESS;
3538	}
3539
3540
3541	/**
3542	* Gets a pointer to the array of standard CPUID leaves.
3543	*
3544	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3545	*
3546	* @returns Pointer to the standard CPUID leaves (read-only).
3547	* @param pVM The VM handle.
3548	* @remark Intended for PATM.
3549	*/
3550	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3551	{
3552	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3553	}
3554
3555
3556	/**
3557	* Gets a pointer to the array of extended CPUID leaves.
3558	*
3559	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3560	*
3561	* @returns Pointer to the extended CPUID leaves (read-only).
3562	* @param pVM The VM handle.
3563	* @remark Intended for PATM.
3564	*/
3565	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3566	{
3567	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3568	}
3569
3570
3571	/**
3572	* Gets a pointer to the array of centaur CPUID leaves.
3573	*
3574	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3575	*
3576	* @returns Pointer to the centaur CPUID leaves (read-only).
3577	* @param pVM The VM handle.
3578	* @remark Intended for PATM.
3579	*/
3580	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3581	{
3582	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3583	}
3584
3585
3586	/**
3587	* Gets a pointer to the default CPUID leaf.
3588	*
3589	* @returns Pointer to the default CPUID leaf (read-only).
3590	* @param pVM The VM handle.
3591	* @remark Intended for PATM.
3592	*/
3593	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3594	{
3595	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3596	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 25957

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