CPUM.cpp@ 24327

Last change on this file since 24327 was 24327, checked in by vboxsync, 15 years ago
Load CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support.
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File size: 131.2 KB

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1	/* $Id: CPUM.cpp 24327 2009-11-04 13:19:32Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	/** @page pg_cpum CPUM - CPU Monitor / Manager
23	*
24	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
25	* also responsible for lazy FPU handling and some of the context loading
26	* in raw mode.
27	*
28	* There are three CPU contexts, the most important one is the guest one (GC).
29	* When running in raw-mode (RC) there is a special hyper context for the VMM
30	* part that floats around inside the guest address space. When running in
31	* raw-mode, CPUM also maintains a host context for saving and restoring
32	* registers accross world switches. This latter is done in cooperation with the
33	* world switcher (@see pg_vmm).
34	*
35	* @see grp_cpum
36	*/
37
38	/*******************************************************************************
39	* Header Files *
40	*******************************************************************************/
41	#define LOG_GROUP LOG_GROUP_CPUM
42	#include <VBox/cpum.h>
43	#include <VBox/cpumdis.h>
44	#include <VBox/pgm.h>
45	#include <VBox/pdm.h>
46	#include <VBox/mm.h>
47	#include <VBox/selm.h>
48	#include <VBox/dbgf.h>
49	#include <VBox/patm.h>
50	#include <VBox/hwaccm.h>
51	#include <VBox/ssm.h>
52	#include "CPUMInternal.h"
53	#include <VBox/vm.h>
54
55	#include <VBox/param.h>
56	#include <VBox/dis.h>
57	#include <VBox/err.h>
58	#include <VBox/log.h>
59	#include <iprt/assert.h>
60	#include <iprt/asm.h>
61	#include <iprt/string.h>
62	#include <iprt/mp.h>
63	#include <iprt/cpuset.h>
64
65
66	/*******************************************************************************
67	* Defined Constants And Macros *
68	*******************************************************************************/
69	/** The current saved state version. */
70	#ifdef VBOX_WITH_LIVE_MIGRATION
71	#define CPUM_SAVED_STATE_VERSION 11
72	#else
73	#define CPUM_SAVED_STATE_VERSION 10
74	#endif
75	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
76	* changes. */
77	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78	/** The saved state version for the 2.1 trunk before the MSR changes. */
79	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80	/** The saved state version of 2.0, used for backwards compatibility. */
81	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82	/** The saved state version of 1.6, used for backwards compatability. */
83	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86	/*******************************************************************************
87	* Structures and Typedefs *
88	*******************************************************************************/
89
90	/**
91	* What kind of cpu info dump to perform.
92	*/
93	typedef enum CPUMDUMPTYPE
94	{
95	CPUMDUMPTYPE_TERSE,
96	CPUMDUMPTYPE_DEFAULT,
97	CPUMDUMPTYPE_VERBOSE
98	} CPUMDUMPTYPE;
99	/** Pointer to a cpu info dump type. */
100	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
101
102
103	/*******************************************************************************
104	* Internal Functions *
105	*******************************************************************************/
106	static int cpumR3CpuIdInit(PVM pVM);
107	#ifdef VBOX_WITH_LIVE_MIGRATION
108	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
109	#endif
110	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
111	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
112	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
116	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
117	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
118
119
120	/**
121	* Initializes the CPUM.
122	*
123	* @returns VBox status code.
124	* @param pVM The VM to operate on.
125	*/
126	VMMR3DECL(int) CPUMR3Init(PVM pVM)
127	{
128	LogFlow(("CPUMR3Init\n"));
129
130	/*
131	* Assert alignment and sizes.
132	*/
133	AssertCompileMemberAlignment(VM, cpum.s, 32);
134	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
135	AssertCompileSizeAlignment(CPUMCTX, 64);
136	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
137	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
138	AssertCompileMemberAlignment(VM, cpum, 64);
139	AssertCompileMemberAlignment(VM, aCpus, 64);
140	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
141	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
142
143	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
144	pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
145	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
146
147	/* Calculate the offset from CPUMCPU to CPUM. */
148	for (VMCPUID i = 0; i < pVM->cCpus; i++)
149	{
150	PVMCPU pVCpu = &pVM->aCpus[i];
151
152	/*
153	* Setup any fixed pointers and offsets.
154	*/
155	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
156	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
157
158	pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
159	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
160	}
161
162	/*
163	* Check that the CPU supports the minimum features we require.
164	*/
165	if (!ASMHasCpuId())
166	{
167	Log(("The CPU doesn't support CPUID!\n"));
168	return VERR_UNSUPPORTED_CPU;
169	}
170	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
171	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
172
173	/* Setup the CR4 AND and OR masks used in the switcher */
174	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
175	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
176	{
177	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
178	/* No FXSAVE implies no SSE */
179	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
180	pVM->cpum.s.CR4.OrMask = 0;
181	}
182	else
183	{
184	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
185	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
186	}
187
188	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
189	{
190	Log(("The CPU doesn't support MMX!\n"));
191	return VERR_UNSUPPORTED_CPU;
192	}
193	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
194	{
195	Log(("The CPU doesn't support TSC!\n"));
196	return VERR_UNSUPPORTED_CPU;
197	}
198	/* Bogus on AMD? */
199	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
200	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
201
202	/*
203	* Setup hypervisor startup values.
204	*/
205
206	/*
207	* Register saved state data item.
208	*/
209	#ifdef VBOX_WITH_LIVE_MIGRATION
210	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
211	NULL, cpumR3LiveExec, NULL,
212	NULL, cpumR3SaveExec, NULL,
213	NULL, cpumR3LoadExec, NULL);
214	#else
215	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
216	NULL, NULL, NULL,
217	NULL, cpumR3SaveExec, NULL,
218	NULL, cpumR3LoadExec, NULL);
219	#endif
220	if (RT_FAILURE(rc))
221	return rc;
222
223	/* Query the CPU manufacturer. */
224	uint32_t uEAX, uEBX, uECX, uEDX;
225	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
226	if ( uEAX >= 1
227	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
228	&& uECX == X86_CPUID_VENDOR_AMD_ECX
229	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
230	{
231	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_AMD;
232	}
233	else if ( uEAX >= 1
234	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
235	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
236	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
237	{
238	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_INTEL;
239	}
240	else /** @todo Via */
241	{
242	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor = CPUMCPUVENDOR_UNKNOWN;
243	}
244
245	/*
246	* Register info handlers.
247	*/
248	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
249	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
250	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
251	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
252	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
253	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
254
255	/*
256	* Initialize the Guest CPU state.
257	*/
258	rc = cpumR3CpuIdInit(pVM);
259	if (RT_FAILURE(rc))
260	return rc;
261	CPUMR3Reset(pVM);
262	return VINF_SUCCESS;
263	}
264
265
266	/**
267	* Initializes the per-VCPU CPUM.
268	*
269	* @returns VBox status code.
270	* @param pVM The VM to operate on.
271	*/
272	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
273	{
274	LogFlow(("CPUMR3InitCPU\n"));
275	return VINF_SUCCESS;
276	}
277
278
279	/**
280	* Initializes the emulated CPU's cpuid information.
281	*
282	* @returns VBox status code.
283	* @param pVM The VM to operate on.
284	*/
285	static int cpumR3CpuIdInit(PVM pVM)
286	{
287	PCPUM pCPUM = &pVM->cpum.s;
288	uint32_t i;
289
290	/*
291	* Get the host CPUIDs.
292	*/
293	for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
294	{
295	ASMCpuId_Idx_ECX(i, 0,
296	&pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
297	&pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
298
299	/* Load standard CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
300	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
301	if (pLeaf)
302	{
303	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdStd[i].eax);
304	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdStd[i].ebx);
305	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdStd[i].ecx);
306	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdStd[i].edx);
307	}
308	}
309	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
310	{
311	ASMCpuId(0x80000000 + i,
312	&pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
313	&pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
314
315	/* Load extended CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
316	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
317	if (pLeaf)
318	{
319	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdExt[i].eax);
320	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdExt[i].ebx);
321	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdExt[i].ecx);
322	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdExt[i].edx);
323	}
324	}
325	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
326	{
327	ASMCpuId(0xc0000000 + i,
328	&pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
329	&pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
330
331	/* Load Centaur CPUID leaf override; we currently don't care if the caller specifies features the host CPU doesn't support. */
332	PCFGMNODE pLeaf = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%x", i);
333	if (pLeaf)
334	{
335	CFGMR3QueryU32(pLeaf, "eax", &pCPUM->aGuestCpuIdCentaur[i].eax);
336	CFGMR3QueryU32(pLeaf, "ebx", &pCPUM->aGuestCpuIdCentaur[i].ebx);
337	CFGMR3QueryU32(pLeaf, "ecx", &pCPUM->aGuestCpuIdCentaur[i].ecx);
338	CFGMR3QueryU32(pLeaf, "edx", &pCPUM->aGuestCpuIdCentaur[i].edx);
339	}
340	}
341
342	/*
343	* Only report features we can support.
344	*/
345	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
346	\| X86_CPUID_FEATURE_EDX_VME
347	\| X86_CPUID_FEATURE_EDX_DE
348	\| X86_CPUID_FEATURE_EDX_PSE
349	\| X86_CPUID_FEATURE_EDX_TSC
350	\| X86_CPUID_FEATURE_EDX_MSR
351	//\| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
352	\| X86_CPUID_FEATURE_EDX_MCE
353	\| X86_CPUID_FEATURE_EDX_CX8
354	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
355	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
356	//\| X86_CPUID_FEATURE_EDX_SEP
357	\| X86_CPUID_FEATURE_EDX_MTRR
358	\| X86_CPUID_FEATURE_EDX_PGE
359	\| X86_CPUID_FEATURE_EDX_MCA
360	\| X86_CPUID_FEATURE_EDX_CMOV
361	\| X86_CPUID_FEATURE_EDX_PAT
362	\| X86_CPUID_FEATURE_EDX_PSE36
363	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
364	\| X86_CPUID_FEATURE_EDX_CLFSH
365	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
366	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
367	\| X86_CPUID_FEATURE_EDX_MMX
368	\| X86_CPUID_FEATURE_EDX_FXSR
369	\| X86_CPUID_FEATURE_EDX_SSE
370	\| X86_CPUID_FEATURE_EDX_SSE2
371	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
372	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
373	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
374	//\| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
375	\| 0;
376	pCPUM->aGuestCpuIdStd[1].ecx &= 0
377	\| X86_CPUID_FEATURE_ECX_SSE3
378	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
379	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
380	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
381	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
382	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
383	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
384	//\| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
385	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
386	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
387	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
388	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
389	/* ECX Bit 21 - x2APIC support - not yet. */
390	// \| X86_CPUID_FEATURE_ECX_X2APIC
391	/* ECX Bit 23 - POPCOUNT instruction. */
392	//\| X86_CPUID_FEATURE_ECX_POPCOUNT
393	\| 0;
394
395	/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
396	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
397	\| X86_CPUID_AMD_FEATURE_EDX_VME
398	\| X86_CPUID_AMD_FEATURE_EDX_DE
399	\| X86_CPUID_AMD_FEATURE_EDX_PSE
400	\| X86_CPUID_AMD_FEATURE_EDX_TSC
401	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
402	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
403	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
404	\| X86_CPUID_AMD_FEATURE_EDX_CX8
405	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
406	/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
407	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
408	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
409	\| X86_CPUID_AMD_FEATURE_EDX_PGE
410	\| X86_CPUID_AMD_FEATURE_EDX_MCA
411	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
412	\| X86_CPUID_AMD_FEATURE_EDX_PAT
413	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
414	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
415	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
416	\| X86_CPUID_AMD_FEATURE_EDX_MMX
417	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
418	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
419	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
420	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
421	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
422	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
423	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
424	\| 0;
425	pCPUM->aGuestCpuIdExt[1].ecx &= 0
426	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
427	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
428	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
429	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
430	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
431	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
432	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
433	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
434	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
435	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
436	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
437	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
438	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
439	\| 0;
440
441	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
442	if (pCPUM->fSyntheticCpu)
443	{
444	const char szVendor[13] = "VirtualBox ";
445	const char szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
446
447	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
448
449	/* Limit the nr of standard leaves; 5 for monitor/mwait */
450	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
451
452	/* 0: Vendor */
453	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)szVendor)[0];
454	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)szVendor)[2];
455	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)szVendor)[1];
456
457	/* 1.eax: Version information. family : model : stepping */
458	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
459
460	/* Leaves 2 - 4 are Intel only - zero them out */
461	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
462	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
463	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
464
465	/* Leaf 5 = monitor/mwait */
466
467	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
468	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
469	/* AMD only - set to zero. */
470	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
471
472	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
473	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
474
475	/* 0x800000002-4: Processor Name String Identifier. */
476	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)szProcessor)[0];
477	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)szProcessor)[1];
478	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)szProcessor)[2];
479	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)szProcessor)[3];
480	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)szProcessor)[4];
481	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)szProcessor)[5];
482	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)szProcessor)[6];
483	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)szProcessor)[7];
484	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)szProcessor)[8];
485	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)szProcessor)[9];
486	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)szProcessor)[10];
487	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)szProcessor)[11];
488
489	/* 0x800000005-7 - reserved -> zero */
490	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
491	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
492	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
493
494	/* 0x800000008: only the max virtual and physical address size. */
495	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
496	}
497
498	/*
499	* Hide HTT, multicode, SMP, whatever.
500	* (APIC-ID := 0 and #LogCpus := 0)
501	*/
502	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
503	#ifdef VBOX_WITH_MULTI_CORE
504	if ( pVM->cCpus > 1
505	&& pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC)
506	{
507	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
508	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
509	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
510	}
511	#endif
512
513	/* Cpuid 2:
514	* Intel: Cache and TLB information
515	* AMD: Reserved
516	* Safe to expose
517	*/
518
519	/* Cpuid 3:
520	* Intel: EAX, EBX - reserved
521	* ECX, EDX - Processor Serial Number if available, otherwise reserved
522	* AMD: Reserved
523	* Safe to expose
524	*/
525	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
526	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
527
528	/* Cpuid 4:
529	* Intel: Deterministic Cache Parameters Leaf
530	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
531	* AMD: Reserved
532	* Safe to expose, except for EAX:
533	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
534	* Bits 31-26: Maximum number of processor cores in this physical package**
535	* @Note These SMP values are constant regardless of ECX
536	*/
537	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
538	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
539	#ifdef VBOX_WITH_MULTI_CORE
540	if ( pVM->cCpus > 1
541	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
542	{
543	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
544	/* One logical processor with possibly multiple cores. */
545	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
546	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
547	}
548	#endif
549
550	/* Cpuid 5: Monitor/mwait Leaf
551	* Intel: ECX, EDX - reserved
552	* EAX, EBX - Smallest and largest monitor line size
553	* AMD: EDX - reserved
554	* EAX, EBX - Smallest and largest monitor line size
555	* ECX - extensions (ignored for now)
556	* Safe to expose
557	*/
558	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
559	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
560
561	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
562
563	/*
564	* Determine the default.
565	*
566	* Intel returns values of the highest standard function, while AMD
567	* returns zeros. VIA on the other hand seems to returning nothing or
568	* perhaps some random garbage, we don't try to duplicate this behavior.
569	*/
570	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
571	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
572	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
573
574	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
575	* Safe to pass on to the guest.
576	*
577	* Intel: 0x800000005 reserved
578	* 0x800000006 L2 cache information
579	* AMD: 0x800000005 L1 cache information
580	* 0x800000006 L2/L3 cache information
581	*/
582
583	/* Cpuid 0x800000007:
584	* AMD: EAX, EBX, ECX - reserved
585	* EDX: Advanced Power Management Information
586	* Intel: Reserved
587	*/
588	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
589	{
590	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
591
592	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
593
594	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
595	{
596	/* Only expose the TSC invariant capability bit to the guest. */
597	pCPUM->aGuestCpuIdExt[7].edx &= 0
598	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
599	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
600	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
601	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
602	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
603	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
604	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
605	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
606	#if 1
607	/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
608	* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
609	*/
610	#else
611	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
612	#endif
613	\| 0;
614	}
615	else
616	pCPUM->aGuestCpuIdExt[7].edx = 0;
617	}
618
619	/* Cpuid 0x800000008:
620	* AMD: EBX, EDX - reserved
621	* EAX: Virtual/Physical address Size
622	* ECX: Number of cores + APICIdCoreIdSize
623	* Intel: EAX: Virtual/Physical address Size
624	* EBX, ECX, EDX - reserved
625	*/
626	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
627	{
628	/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
629	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
630	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
631	* NC (0-7) Number of cores; 0 equals 1 core */
632	pCPUM->aGuestCpuIdExt[8].ecx = 0;
633	#ifdef VBOX_WITH_MULTI_CORE
634	if ( pVM->cCpus > 1
635	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
636	{
637	/* Legacy method to determine the number of cores. */
638	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
639	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
640
641	}
642	#endif
643	}
644
645	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
646	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
647	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
648	* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
649	*/
650	bool fNt4LeafLimit;
651	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
652	if (fNt4LeafLimit)
653	pCPUM->aGuestCpuIdStd[0].eax = 3;
654
655	/*
656	* Limit it the number of entries and fill the remaining with the defaults.
657	*
658	* The limits are masking off stuff about power saving and similar, this
659	* is perhaps a bit crudely done as there is probably some relatively harmless
660	* info too in these leaves (like words about having a constant TSC).
661	*/
662	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
663	pCPUM->aGuestCpuIdStd[0].eax = 5;
664
665	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
666	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
667
668	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
669	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
670	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
671	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
672	: 0;
673	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
674	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
675
676	/*
677	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
678	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
679	* of processors from (cpuid(4).eax >> 26) + 1.
680	*/
681	if (pVM->cCpus == 1)
682	pCPUM->aGuestCpuIdStd[4].eax = 0;
683
684	/*
685	* Centaur stuff (VIA).
686	*
687	* The important part here (we think) is to make sure the 0xc0000000
688	* function returns 0xc0000001. As for the features, we don't currently
689	* let on about any of those... 0xc0000002 seems to be some
690	* temperature/hz/++ stuff, include it as well (static).
691	*/
692	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
693	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
694	{
695	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
696	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
697	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
698	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
699	i++)
700	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
701	}
702	else
703	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
704	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
705
706
707	/*
708	* Load CPUID overrides from configuration.
709	*/
710	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
711	* Overloads the CPUID leaf values. */
712	PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
713	uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
714	for (i=0;; )
715	{
716	while (cElements-- > 0)
717	{
718	PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
719	if (pNode)
720	{
721	uint32_t u32;
722	int rc = CFGMR3QueryU32(pNode, "eax", &u32);
723	if (RT_SUCCESS(rc))
724	pCpuId->eax = u32;
725	else
726	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
727
728	rc = CFGMR3QueryU32(pNode, "ebx", &u32);
729	if (RT_SUCCESS(rc))
730	pCpuId->ebx = u32;
731	else
732	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
733
734	rc = CFGMR3QueryU32(pNode, "ecx", &u32);
735	if (RT_SUCCESS(rc))
736	pCpuId->ecx = u32;
737	else
738	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
739
740	rc = CFGMR3QueryU32(pNode, "edx", &u32);
741	if (RT_SUCCESS(rc))
742	pCpuId->edx = u32;
743	else
744	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
745	}
746	pCpuId++;
747	i++;
748	}
749
750	/* next */
751	if ((i & UINT32_C(0xc0000000)) == 0)
752	{
753	pCpuId = &pCPUM->aGuestCpuIdExt[0];
754	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
755	i = UINT32_C(0x80000000);
756	}
757	else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
758	{
759	pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
760	cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
761	i = UINT32_C(0xc0000000);
762	}
763	else
764	break;
765	}
766
767	/* Check if PAE was explicitely enabled by the user. */
768	bool fEnable = false;
769	int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
770	if (RT_SUCCESS(rc) && fEnable)
771	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
772
773	/*
774	* Log the cpuid and we're good.
775	*/
776	RTCPUSET OnlineSet;
777	LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
778	(int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
779	LogRel(("*********************** CPUID dump **********************\n"));
780	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
781	LogRel(("\n"));
782	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
783	LogRel(("****************** End of CPUID dump ********************\n"));
784	return VINF_SUCCESS;
785	}
786
787
788
789
790	/**
791	* Applies relocations to data and code managed by this
792	* component. This function will be called at init and
793	* whenever the VMM need to relocate it self inside the GC.
794	*
795	* The CPUM will update the addresses used by the switcher.
796	*
797	* @param pVM The VM.
798	*/
799	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
800	{
801	LogFlow(("CPUMR3Relocate\n"));
802	for (VMCPUID i = 0; i < pVM->cCpus; i++)
803	{
804	/*
805	* Switcher pointers.
806	*/
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
809	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
810	}
811	}
812
813
814	/**
815	* Terminates the CPUM.
816	*
817	* Termination means cleaning up and freeing all resources,
818	* the VM it self is at this point powered off or suspended.
819	*
820	* @returns VBox status code.
821	* @param pVM The VM to operate on.
822	*/
823	VMMR3DECL(int) CPUMR3Term(PVM pVM)
824	{
825	CPUMR3TermCPU(pVM);
826	return 0;
827	}
828
829
830	/**
831	* Terminates the per-VCPU CPUM.
832	*
833	* Termination means cleaning up and freeing all resources,
834	* the VM it self is at this point powered off or suspended.
835	*
836	* @returns VBox status code.
837	* @param pVM The VM to operate on.
838	*/
839	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
840	{
841	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
842	for (VMCPUID i = 0; i < pVM->cCpus; i++)
843	{
844	PVMCPU pVCpu = &pVM->aCpus[i];
845	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
846
847	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
848	pVCpu->cpum.s.uMagic = 0;
849	pCtx->dr[5] = 0;
850	}
851	#endif
852	return 0;
853	}
854
855	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
856	{
857	/* @todo anything different for VCPU > 0? */
858	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
859
860	/*
861	* Initialize everything to ZERO first.
862	*/
863	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
864	memset(pCtx, 0, sizeof(*pCtx));
865	pVCpu->cpum.s.fUseFlags = fUseFlags;
866
867	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
868	pCtx->eip = 0x0000fff0;
869	pCtx->edx = 0x00000600; /* P6 processor */
870	pCtx->eflags.Bits.u1Reserved0 = 1;
871
872	pCtx->cs = 0xf000;
873	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
874	pCtx->csHid.u32Limit = 0x0000ffff;
875	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
876	pCtx->csHid.Attr.n.u1Present = 1;
877	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
878
879	pCtx->dsHid.u32Limit = 0x0000ffff;
880	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
881	pCtx->dsHid.Attr.n.u1Present = 1;
882	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
883
884	pCtx->esHid.u32Limit = 0x0000ffff;
885	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
886	pCtx->esHid.Attr.n.u1Present = 1;
887	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
888
889	pCtx->fsHid.u32Limit = 0x0000ffff;
890	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
891	pCtx->fsHid.Attr.n.u1Present = 1;
892	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
893
894	pCtx->gsHid.u32Limit = 0x0000ffff;
895	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
896	pCtx->gsHid.Attr.n.u1Present = 1;
897	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
898
899	pCtx->ssHid.u32Limit = 0x0000ffff;
900	pCtx->ssHid.Attr.n.u1Present = 1;
901	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
902	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
903
904	pCtx->idtr.cbIdt = 0xffff;
905	pCtx->gdtr.cbGdt = 0xffff;
906
907	pCtx->ldtrHid.u32Limit = 0xffff;
908	pCtx->ldtrHid.Attr.n.u1Present = 1;
909	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
910
911	pCtx->trHid.u32Limit = 0xffff;
912	pCtx->trHid.Attr.n.u1Present = 1;
913	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
914
915	pCtx->dr[6] = X86_DR6_INIT_VAL;
916	pCtx->dr[7] = X86_DR7_INIT_VAL;
917
918	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
919	pCtx->fpu.FCW = 0x37f;
920
921	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
922	pCtx->fpu.MXCSR = 0x1F80;
923
924	/* Init PAT MSR */
925	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
926
927	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
928	* The Intel docs don't mention it.
929	*/
930	pCtx->msrEFER = 0;
931	}
932
933	/**
934	* Resets the CPU.
935	*
936	* @returns VINF_SUCCESS.
937	* @param pVM The VM handle.
938	*/
939	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
940	{
941	for (VMCPUID i = 0; i < pVM->cCpus; i++)
942	{
943	CPUMR3ResetCpu(&pVM->aCpus[i]);
944
945	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
946	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
947
948	/* Magic marker for searching in crash dumps. */
949	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
950	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
951	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
952	#endif
953	}
954	}
955
956	#ifdef VBOX_WITH_LIVE_MIGRATION
957
958	/**
959	* Called both in pass 0 and the final pass.
960	*
961	* @param pVM The VM handle.
962	* @param pSSM The saved state handle.
963	*/
964	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
965	{
966	/*
967	* Save all the CPU ID leaves here so we can check them for compatability
968	* upon loading.
969	*/
970	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
971	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
972
973	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
974	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
975
976	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
977	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
978
979	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
980
981	/*
982	* Save a good portion of the raw CPU IDs as well as they may come in
983	* handy when validating features for raw mode.
984	*/
985	CPUMCPUID aRawStd[8];
986	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
987	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
988	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
989	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
990
991	CPUMCPUID aRawExt[16];
992	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
993	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
994	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
995	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
996	}
997
998
999	/**
1000	* Loads the CPU ID leaves saved by pass 0.
1001	*
1002	* @returns VBox status code.
1003	* @param pVM The VM handle.
1004	* @param pSSM The saved state handle.
1005	* @param uVersion The format version.
1006	*/
1007	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1008	{
1009	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1010
1011	/*
1012	* Load them into stack buffers first.
1013	*/
1014	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1015	uint32_t cGuestCpuIdStd;
1016	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1017	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1018	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1019	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1020
1021	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1022	uint32_t cGuestCpuIdExt;
1023	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1024	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1025	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1026	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1027
1028	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1029	uint32_t cGuestCpuIdCentaur;
1030	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1031	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1032	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1033	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1034
1035	CPUMCPUID GuestCpuIdDef;
1036	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1037	AssertRCReturn(rc, rc);
1038
1039	CPUMCPUID aRawStd[8];
1040	uint32_t cRawStd;
1041	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1042	if (cRawStd > RT_ELEMENTS(aRawStd))
1043	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1044	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1045
1046	CPUMCPUID aRawExt[16];
1047	uint32_t cRawExt;
1048	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1049	if (cRawExt > RT_ELEMENTS(aRawExt))
1050	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1051	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1052	AssertRCReturn(rc, rc);
1053
1054	/*
1055	* Note that we support restoring less than the current amount of standard
1056	* leaves because we've been allowed more is newer version of VBox.
1057	*
1058	* So, pad new entries with the default.
1059	*/
1060	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1061	aGuestCpuIdStd[i] = GuestCpuIdDef;
1062
1063	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1064	aGuestCpuIdExt[i] = GuestCpuIdDef;
1065
1066	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1067	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1068
1069	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1070	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1071
1072	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1073	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1074
1075	/*
1076	* Get the raw CPU IDs for the current host.
1077	*/
1078	CPUMCPUID aHostRawStd[8];
1079	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1080	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1081
1082	CPUMCPUID aHostRawExt[16];
1083	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1084	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1085
1086	/*
1087	* Now for the fun part...
1088	*/
1089
1090
1091	/*
1092	* We're good, commit the CPU ID leaves.
1093	*/
1094	memcmp(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1095	memcmp(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1096	memcmp(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1097	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1098
1099	return VINF_SUCCESS;
1100	}
1101
1102
1103	/**
1104	* Pass 0 live exec callback.
1105	*
1106	* @returns VINF_SSM_DONT_CALL_AGAIN.
1107	* @param pVM The VM handle.
1108	* @param pSSM The saved state handle.
1109	* @param uPass The pass (0).
1110	*/
1111	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1112	{
1113	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1114	cpumR3SaveCpuId(pVM, pSSM);
1115	return VINF_SSM_DONT_CALL_AGAIN;
1116	}
1117
1118	#endif /* VBOX_WITH_LIVE_MIGRATION */
1119
1120	/**
1121	* Execute state save operation.
1122	*
1123	* @returns VBox status code.
1124	* @param pVM VM Handle.
1125	* @param pSSM SSM operation handle.
1126	*/
1127	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1128	{
1129	/*
1130	* Save.
1131	*/
1132	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1133	{
1134	PVMCPU pVCpu = &pVM->aCpus[i];
1135
1136	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1137	}
1138
1139	SSMR3PutU32(pSSM, pVM->cCpus);
1140	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1141	{
1142	PVMCPU pVCpu = &pVM->aCpus[i];
1143
1144	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1145	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1146	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1147	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1148	}
1149
1150	#ifdef VBOX_WITH_LIVE_MIGRATION
1151	cpumR3SaveCpuId(pVM, pSSM);
1152	return VINF_SUCCESS;
1153	#else
1154
1155	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1156	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1157
1158	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1159	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1160
1161	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1162	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1163
1164	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1165
1166	/* Add the cpuid for checking that the cpu is unchanged. */
1167	uint32_t au32CpuId[8] = {0};
1168	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1169	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1170	return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
1171	#endif
1172	}
1173
1174
1175	/**
1176	* Load a version 1.6 CPUMCTX structure.
1177	*
1178	* @returns VBox status code.
1179	* @param pVM VM Handle.
1180	* @param pCpumctx16 Version 1.6 CPUMCTX
1181	*/
1182	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1183	{
1184	#define CPUMCTX16_LOADREG(RegName) \
1185	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1186
1187	#define CPUMCTX16_LOADDRXREG(RegName) \
1188	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1189
1190	#define CPUMCTX16_LOADHIDREG(RegName) \
1191	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1192	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1193	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1194
1195	#define CPUMCTX16_LOADSEGREG(RegName) \
1196	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1197	CPUMCTX16_LOADHIDREG(RegName);
1198
1199	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1200
1201	CPUMCTX16_LOADREG(rax);
1202	CPUMCTX16_LOADREG(rbx);
1203	CPUMCTX16_LOADREG(rcx);
1204	CPUMCTX16_LOADREG(rdx);
1205	CPUMCTX16_LOADREG(rdi);
1206	CPUMCTX16_LOADREG(rsi);
1207	CPUMCTX16_LOADREG(rbp);
1208	CPUMCTX16_LOADREG(esp);
1209	CPUMCTX16_LOADREG(rip);
1210	CPUMCTX16_LOADREG(rflags);
1211
1212	CPUMCTX16_LOADSEGREG(cs);
1213	CPUMCTX16_LOADSEGREG(ds);
1214	CPUMCTX16_LOADSEGREG(es);
1215	CPUMCTX16_LOADSEGREG(fs);
1216	CPUMCTX16_LOADSEGREG(gs);
1217	CPUMCTX16_LOADSEGREG(ss);
1218
1219	CPUMCTX16_LOADREG(r8);
1220	CPUMCTX16_LOADREG(r9);
1221	CPUMCTX16_LOADREG(r10);
1222	CPUMCTX16_LOADREG(r11);
1223	CPUMCTX16_LOADREG(r12);
1224	CPUMCTX16_LOADREG(r13);
1225	CPUMCTX16_LOADREG(r14);
1226	CPUMCTX16_LOADREG(r15);
1227
1228	CPUMCTX16_LOADREG(cr0);
1229	CPUMCTX16_LOADREG(cr2);
1230	CPUMCTX16_LOADREG(cr3);
1231	CPUMCTX16_LOADREG(cr4);
1232
1233	CPUMCTX16_LOADDRXREG(0);
1234	CPUMCTX16_LOADDRXREG(1);
1235	CPUMCTX16_LOADDRXREG(2);
1236	CPUMCTX16_LOADDRXREG(3);
1237	CPUMCTX16_LOADDRXREG(4);
1238	CPUMCTX16_LOADDRXREG(5);
1239	CPUMCTX16_LOADDRXREG(6);
1240	CPUMCTX16_LOADDRXREG(7);
1241
1242	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1243	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1244	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1245	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1246
1247	CPUMCTX16_LOADREG(ldtr);
1248	CPUMCTX16_LOADREG(tr);
1249
1250	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1251
1252	CPUMCTX16_LOADREG(msrEFER);
1253	CPUMCTX16_LOADREG(msrSTAR);
1254	CPUMCTX16_LOADREG(msrPAT);
1255	CPUMCTX16_LOADREG(msrLSTAR);
1256	CPUMCTX16_LOADREG(msrCSTAR);
1257	CPUMCTX16_LOADREG(msrSFMASK);
1258	CPUMCTX16_LOADREG(msrKERNELGSBASE);
1259
1260	CPUMCTX16_LOADHIDREG(ldtr);
1261	CPUMCTX16_LOADHIDREG(tr);
1262
1263	#undef CPUMCTX16_LOADSEGREG
1264	#undef CPUMCTX16_LOADHIDREG
1265	#undef CPUMCTX16_LOADDRXREG
1266	#undef CPUMCTX16_LOADREG
1267	}
1268
1269
1270	/**
1271	* Execute state load operation.
1272	*
1273	* @returns VBox status code.
1274	* @param pVM VM Handle.
1275	* @param pSSM SSM operation handle.
1276	* @param uVersion Data layout version.
1277	* @param uPass The data pass.
1278	*/
1279	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1280	{
1281	/*
1282	* Validate version.
1283	*/
1284	if ( uVersion != CPUM_SAVED_STATE_VERSION
1285	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1286	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1287	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1288	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1289	{
1290	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1291	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1292	}
1293
1294	if (uPass == SSM_PASS_FINAL)
1295	{
1296	/*
1297	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1298	* really old SSM file versions.)
1299	*/
1300	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1301	SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1302	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1303	SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1304
1305	/*
1306	* Restore.
1307	*/
1308	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1309	{
1310	PVMCPU pVCpu = &pVM->aCpus[i];
1311	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1312	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1313
1314	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1315	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1316	pVCpu->cpum.s.Hyper.esp = uESP;
1317	}
1318
1319	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1320	{
1321	CPUMCTX_VER1_6 cpumctx16;
1322	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1323	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1324
1325	/* Save the old cpumctx state into the new one. */
1326	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1327
1328	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1329	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1330	}
1331	else
1332	{
1333	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1334	{
1335	uint32_t cCpus;
1336	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1337	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1338	VERR_SSM_UNEXPECTED_DATA);
1339	}
1340	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1341	\|\| pVM->cCpus == 1,
1342	("cCpus=%u\n", pVM->cCpus),
1343	VERR_SSM_UNEXPECTED_DATA);
1344
1345	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1346	{
1347	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1348	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1349	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1350	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1351	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1352	}
1353	}
1354	}
1355
1356	#ifdef VBOX_WITH_LIVE_MIGRATION
1357	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1358	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1359
1360	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1361	* actually required. */
1362	#endif
1363
1364	/*
1365	* Restore the CPUID leaves.
1366	*
1367	* Note that we support restoring less than the current amount of standard
1368	* leaves because we've been allowed more is newer version of VBox.
1369	*/
1370	uint32_t cElements;
1371	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1372	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1373	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1374	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1375
1376	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1377	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1378	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1379	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1380
1381	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1382	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1383	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1384	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1385
1386	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1387
1388	/*
1389	* Check that the basic cpuid id information is unchanged.
1390	*/
1391	/** @todo we should check the 64 bits capabilities too! */
1392	uint32_t au32CpuId[8] = {0};
1393	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1394	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1395	uint32_t au32CpuIdSaved[8];
1396	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1397	if (RT_SUCCESS(rc))
1398	{
1399	/* Ignore CPU stepping. */
1400	au32CpuId[4] &= 0xfffffff0;
1401	au32CpuIdSaved[4] &= 0xfffffff0;
1402
1403	/* Ignore APIC ID (AMD specs). */
1404	au32CpuId[5] &= ~0xff000000;
1405	au32CpuIdSaved[5] &= ~0xff000000;
1406
1407	/* Ignore the number of Logical CPUs (AMD specs). */
1408	au32CpuId[5] &= ~0x00ff0000;
1409	au32CpuIdSaved[5] &= ~0x00ff0000;
1410
1411	/* Ignore some advanced capability bits, that we don't expose to the guest. */
1412	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1413	\| X86_CPUID_FEATURE_ECX_VMX
1414	\| X86_CPUID_FEATURE_ECX_SMX
1415	\| X86_CPUID_FEATURE_ECX_EST
1416	\| X86_CPUID_FEATURE_ECX_TM2
1417	\| X86_CPUID_FEATURE_ECX_CNTXID
1418	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1419	\| X86_CPUID_FEATURE_ECX_PDCM
1420	\| X86_CPUID_FEATURE_ECX_DCA
1421	\| X86_CPUID_FEATURE_ECX_X2APIC
1422	);
1423	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1424	\| X86_CPUID_FEATURE_ECX_VMX
1425	\| X86_CPUID_FEATURE_ECX_SMX
1426	\| X86_CPUID_FEATURE_ECX_EST
1427	\| X86_CPUID_FEATURE_ECX_TM2
1428	\| X86_CPUID_FEATURE_ECX_CNTXID
1429	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1430	\| X86_CPUID_FEATURE_ECX_PDCM
1431	\| X86_CPUID_FEATURE_ECX_DCA
1432	\| X86_CPUID_FEATURE_ECX_X2APIC
1433	);
1434
1435	/* Make sure we don't forget to update the masks when enabling
1436	* features in the future.
1437	*/
1438	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1439	( X86_CPUID_FEATURE_ECX_DTES64
1440	\| X86_CPUID_FEATURE_ECX_VMX
1441	\| X86_CPUID_FEATURE_ECX_SMX
1442	\| X86_CPUID_FEATURE_ECX_EST
1443	\| X86_CPUID_FEATURE_ECX_TM2
1444	\| X86_CPUID_FEATURE_ECX_CNTXID
1445	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1446	\| X86_CPUID_FEATURE_ECX_PDCM
1447	\| X86_CPUID_FEATURE_ECX_DCA
1448	\| X86_CPUID_FEATURE_ECX_X2APIC
1449	)));
1450	/* do the compare */
1451	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1452	{
1453	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1454	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1455	"Saved=%.*Rhxs\n"
1456	"Real =%.*Rhxs\n",
1457	sizeof(au32CpuIdSaved), au32CpuIdSaved,
1458	sizeof(au32CpuId), au32CpuId));
1459	else
1460	{
1461	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1462	"Saved=%.*Rhxs\n"
1463	"Real =%.*Rhxs\n",
1464	sizeof(au32CpuIdSaved), au32CpuIdSaved,
1465	sizeof(au32CpuId), au32CpuId));
1466	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1467	}
1468	}
1469	}
1470
1471	return rc;
1472	}
1473
1474
1475	/**
1476	* Formats the EFLAGS value into mnemonics.
1477	*
1478	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1479	* @param efl The EFLAGS value.
1480	*/
1481	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1482	{
1483	/*
1484	* Format the flags.
1485	*/
1486	static const struct
1487	{
1488	const char pszSet; const char pszClear; uint32_t fFlag;
1489	} s_aFlags[] =
1490	{
1491	{ "vip",NULL, X86_EFL_VIP },
1492	{ "vif",NULL, X86_EFL_VIF },
1493	{ "ac", NULL, X86_EFL_AC },
1494	{ "vm", NULL, X86_EFL_VM },
1495	{ "rf", NULL, X86_EFL_RF },
1496	{ "nt", NULL, X86_EFL_NT },
1497	{ "ov", "nv", X86_EFL_OF },
1498	{ "dn", "up", X86_EFL_DF },
1499	{ "ei", "di", X86_EFL_IF },
1500	{ "tf", NULL, X86_EFL_TF },
1501	{ "nt", "pl", X86_EFL_SF },
1502	{ "nz", "zr", X86_EFL_ZF },
1503	{ "ac", "na", X86_EFL_AF },
1504	{ "po", "pe", X86_EFL_PF },
1505	{ "cy", "nc", X86_EFL_CF },
1506	};
1507	char *psz = pszEFlags;
1508	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1509	{
1510	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1511	if (pszAdd)
1512	{
1513	strcpy(psz, pszAdd);
1514	psz += strlen(pszAdd);
1515	*psz++ = ' ';
1516	}
1517	}
1518	psz[-1] = '\0';
1519	}
1520
1521
1522	/**
1523	* Formats a full register dump.
1524	*
1525	* @param pVM VM Handle.
1526	* @param pCtx The context to format.
1527	* @param pCtxCore The context core to format.
1528	* @param pHlp Output functions.
1529	* @param enmType The dump type.
1530	* @param pszPrefix Register name prefix.
1531	*/
1532	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1533	{
1534	/*
1535	* Format the EFLAGS.
1536	*/
1537	uint32_t efl = pCtxCore->eflags.u32;
1538	char szEFlags[80];
1539	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1540
1541	/*
1542	* Format the registers.
1543	*/
1544	switch (enmType)
1545	{
1546	case CPUMDUMPTYPE_TERSE:
1547	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1548	pHlp->pfnPrintf(pHlp,
1549	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1550	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1551	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1552	"%sr14=%016RX64 %sr15=%016RX64\n"
1553	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1554	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1555	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1556	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1557	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1558	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1559	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1560	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1561	else
1562	pHlp->pfnPrintf(pHlp,
1563	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1564	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1565	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1566	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1567	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1568	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1569	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1570	break;
1571
1572	case CPUMDUMPTYPE_DEFAULT:
1573	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1574	pHlp->pfnPrintf(pHlp,
1575	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1576	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1577	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1578	"%sr14=%016RX64 %sr15=%016RX64\n"
1579	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1580	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1581	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1582	,
1583	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1584	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1585	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1586	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1587	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1588	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1589	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1590	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1591	else
1592	pHlp->pfnPrintf(pHlp,
1593	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1594	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1595	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1596	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1597	,
1598	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1599	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1600	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1601	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1602	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1603	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1604	break;
1605
1606	case CPUMDUMPTYPE_VERBOSE:
1607	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1608	pHlp->pfnPrintf(pHlp,
1609	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1610	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1611	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1612	"%sr14=%016RX64 %sr15=%016RX64\n"
1613	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1614	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1615	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1616	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1617	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1618	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1619	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1620	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1621	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1622	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1623	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1624	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1625	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1626	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1627	,
1628	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1629	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1630	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1631	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1632	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1633	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1634	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1635	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1636	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1637	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1638	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1639	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1640	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1641	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1642	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1643	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1644	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1645	else
1646	pHlp->pfnPrintf(pHlp,
1647	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1648	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1649	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1650	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1651	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1652	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1653	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1654	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1655	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1656	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1657	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1658	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1659	,
1660	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1661	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1662	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1663	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1664	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1665	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1666	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1667	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1668	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1669	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1670	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1671	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1672
1673	pHlp->pfnPrintf(pHlp,
1674	"FPU:\n"
1675	"%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1676	"%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1677	"%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1678	,
1679	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1680	pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1681	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1682	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1683
1684	pHlp->pfnPrintf(pHlp,
1685	"MSR:\n"
1686	"%sEFER =%016RX64\n"
1687	"%sPAT =%016RX64\n"
1688	"%sSTAR =%016RX64\n"
1689	"%sCSTAR =%016RX64\n"
1690	"%sLSTAR =%016RX64\n"
1691	"%sSFMASK =%016RX64\n"
1692	"%sKERNELGSBASE =%016RX64\n",
1693	pszPrefix, pCtx->msrEFER,
1694	pszPrefix, pCtx->msrPAT,
1695	pszPrefix, pCtx->msrSTAR,
1696	pszPrefix, pCtx->msrCSTAR,
1697	pszPrefix, pCtx->msrLSTAR,
1698	pszPrefix, pCtx->msrSFMASK,
1699	pszPrefix, pCtx->msrKERNELGSBASE);
1700	break;
1701	}
1702	}
1703
1704
1705	/**
1706	* Display all cpu states and any other cpum info.
1707	*
1708	* @param pVM VM Handle.
1709	* @param pHlp The info helper functions.
1710	* @param pszArgs Arguments, ignored.
1711	*/
1712	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1713	{
1714	cpumR3InfoGuest(pVM, pHlp, pszArgs);
1715	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1716	cpumR3InfoHyper(pVM, pHlp, pszArgs);
1717	cpumR3InfoHost(pVM, pHlp, pszArgs);
1718	}
1719
1720
1721	/**
1722	* Parses the info argument.
1723	*
1724	* The argument starts with 'verbose', 'terse' or 'default' and then
1725	* continues with the comment string.
1726	*
1727	* @param pszArgs The pointer to the argument string.
1728	* @param penmType Where to store the dump type request.
1729	* @param ppszComment Where to store the pointer to the comment string.
1730	*/
1731	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
1732	{
1733	if (!pszArgs)
1734	{
1735	*penmType = CPUMDUMPTYPE_DEFAULT;
1736	*ppszComment = "";
1737	}
1738	else
1739	{
1740	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1741	{
1742	pszArgs += 5;
1743	*penmType = CPUMDUMPTYPE_VERBOSE;
1744	}
1745	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1746	{
1747	pszArgs += 5;
1748	*penmType = CPUMDUMPTYPE_TERSE;
1749	}
1750	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1751	{
1752	pszArgs += 7;
1753	*penmType = CPUMDUMPTYPE_DEFAULT;
1754	}
1755	else
1756	*penmType = CPUMDUMPTYPE_DEFAULT;
1757	*ppszComment = RTStrStripL(pszArgs);
1758	}
1759	}
1760
1761
1762	/**
1763	* Display the guest cpu state.
1764	*
1765	* @param pVM VM Handle.
1766	* @param pHlp The info helper functions.
1767	* @param pszArgs Arguments, ignored.
1768	*/
1769	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1770	{
1771	CPUMDUMPTYPE enmType;
1772	const char *pszComment;
1773	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1774
1775	/* @todo SMP support! */
1776	PVMCPU pVCpu = VMMGetCpu(pVM);
1777	if (!pVCpu)
1778	pVCpu = &pVM->aCpus[0];
1779
1780	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1781
1782	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1783	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1784	}
1785
1786
1787	/**
1788	* Display the current guest instruction
1789	*
1790	* @param pVM VM Handle.
1791	* @param pHlp The info helper functions.
1792	* @param pszArgs Arguments, ignored.
1793	*/
1794	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1795	{
1796	char szInstruction[256];
1797	/* @todo SMP support! */
1798	PVMCPU pVCpu = VMMGetCpu(pVM);
1799	if (!pVCpu)
1800	pVCpu = &pVM->aCpus[0];
1801
1802	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1803	if (RT_SUCCESS(rc))
1804	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1805	}
1806
1807
1808	/**
1809	* Display the hypervisor cpu state.
1810	*
1811	* @param pVM VM Handle.
1812	* @param pHlp The info helper functions.
1813	* @param pszArgs Arguments, ignored.
1814	*/
1815	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1816	{
1817	CPUMDUMPTYPE enmType;
1818	const char *pszComment;
1819	/* @todo SMP */
1820	PVMCPU pVCpu = &pVM->aCpus[0];
1821
1822	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1823	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1824	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1825	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1826	}
1827
1828
1829	/**
1830	* Display the host cpu state.
1831	*
1832	* @param pVM VM Handle.
1833	* @param pHlp The info helper functions.
1834	* @param pszArgs Arguments, ignored.
1835	*/
1836	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1837	{
1838	CPUMDUMPTYPE enmType;
1839	const char *pszComment;
1840	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1841	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1842
1843	/*
1844	* Format the EFLAGS.
1845	*/
1846	/* @todo SMP */
1847	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1848	#if HC_ARCH_BITS == 32
1849	uint32_t efl = pCtx->eflags.u32;
1850	#else
1851	uint64_t efl = pCtx->rflags;
1852	#endif
1853	char szEFlags[80];
1854	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1855
1856	/*
1857	* Format the registers.
1858	*/
1859	#if HC_ARCH_BITS == 32
1860	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1861	if (!(pCtx->efer & MSR_K6_EFER_LMA))
1862	# endif
1863	{
1864	pHlp->pfnPrintf(pHlp,
1865	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1866	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1867	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1868	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1869	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1870	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1871	,
1872	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
1873	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1874	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1875	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
1876	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1877	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1878	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1879	}
1880	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1881	else
1882	# endif
1883	#endif
1884	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1885	{
1886	pHlp->pfnPrintf(pHlp,
1887	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1888	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1889	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1890	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1891	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1892	"r14=%016RX64 r15=%016RX64\n"
1893	"iopl=%d %31s\n"
1894	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1895	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1896	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
1897	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1898	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1899	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1900	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1901	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1902	,
1903	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
1904	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1905	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
1906	/pCtx->r8, pCtx->r9,/ pCtx->r10,
1907	pCtx->r11, pCtx->r12, pCtx->r13,
1908	pCtx->r14, pCtx->r15,
1909	X86_EFL_GET_IOPL(efl), szEFlags,
1910	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1911	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
1912	pCtx->cr4, pCtx->ldtr, pCtx->tr,
1913	pCtx->dr0, pCtx->dr1, pCtx->dr2,
1914	pCtx->dr3, pCtx->dr6, pCtx->dr7,
1915	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1916	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1917	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1918	}
1919	#endif
1920	}
1921
1922
1923	/**
1924	* Get L1 cache / TLS associativity.
1925	*/
1926	static const char getCacheAss(unsigned u, char pszBuf)
1927	{
1928	if (u == 0)
1929	return "res0 ";
1930	if (u == 1)
1931	return "direct";
1932	if (u >= 256)
1933	return "???";
1934
1935	RTStrPrintf(pszBuf, 16, "%d way", u);
1936	return pszBuf;
1937	}
1938
1939
1940	/**
1941	* Get L2 cache soociativity.
1942	*/
1943	const char *getL2CacheAss(unsigned u)
1944	{
1945	switch (u)
1946	{
1947	case 0: return "off ";
1948	case 1: return "direct";
1949	case 2: return "2 way ";
1950	case 3: return "res3 ";
1951	case 4: return "4 way ";
1952	case 5: return "res5 ";
1953	case 6: return "8 way "; case 7: return "res7 ";
1954	case 8: return "16 way";
1955	case 9: return "res9 ";
1956	case 10: return "res10 ";
1957	case 11: return "res11 ";
1958	case 12: return "res12 ";
1959	case 13: return "res13 ";
1960	case 14: return "res14 ";
1961	case 15: return "fully ";
1962	default:
1963	return "????";
1964	}
1965	}
1966
1967
1968	/**
1969	* Display the guest CpuId leaves.
1970	*
1971	* @param pVM VM Handle.
1972	* @param pHlp The info helper functions.
1973	* @param pszArgs "terse", "default" or "verbose".
1974	*/
1975	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1976	{
1977	/*
1978	* Parse the argument.
1979	*/
1980	unsigned iVerbosity = 1;
1981	if (pszArgs)
1982	{
1983	pszArgs = RTStrStripL(pszArgs);
1984	if (!strcmp(pszArgs, "terse"))
1985	iVerbosity--;
1986	else if (!strcmp(pszArgs, "verbose"))
1987	iVerbosity++;
1988	}
1989
1990	/*
1991	* Start cracking.
1992	*/
1993	CPUMCPUID Host;
1994	CPUMCPUID Guest;
1995	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1996
1997	pHlp->pfnPrintf(pHlp,
1998	" RAW Standard CPUIDs\n"
1999	" Function eax ebx ecx edx\n");
2000	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2001	{
2002	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2003	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2004
2005	pHlp->pfnPrintf(pHlp,
2006	"Gst: %08x %08x %08x %08x %08x%s\n"
2007	"Hst: %08x %08x %08x %08x\n",
2008	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2009	i <= cStdMax ? "" : "*",
2010	Host.eax, Host.ebx, Host.ecx, Host.edx);
2011	}
2012
2013	/*
2014	* If verbose, decode it.
2015	*/
2016	if (iVerbosity)
2017	{
2018	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2019	pHlp->pfnPrintf(pHlp,
2020	"Name: %.04s%.04s%.04s\n"
2021	"Supports: 0-%x\n",
2022	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2023	}
2024
2025	/*
2026	* Get Features.
2027	*/
2028	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2029	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2030	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2031	if (cStdMax >= 1 && iVerbosity)
2032	{
2033	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2034	uint32_t uEAX = Guest.eax;
2035
2036	pHlp->pfnPrintf(pHlp,
2037	"Family: %d \tExtended: %d \tEffective: %d\n"
2038	"Model: %d \tExtended: %d \tEffective: %d\n"
2039	"Stepping: %d\n"
2040	"APIC ID: %#04x\n"
2041	"Logical CPUs: %d\n"
2042	"CLFLUSH Size: %d\n"
2043	"Brand ID: %#04x\n",
2044	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2045	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2046	ASMGetCpuStepping(uEAX),
2047	(Guest.ebx >> 24) & 0xff,
2048	(Guest.ebx >> 16) & 0xff,
2049	(Guest.ebx >> 8) & 0xff,
2050	(Guest.ebx >> 0) & 0xff);
2051	if (iVerbosity == 1)
2052	{
2053	uint32_t uEDX = Guest.edx;
2054	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2055	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2056	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2057	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2058	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2059	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2060	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2061	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2062	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2063	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2064	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2065	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2066	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2067	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2068	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2069	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2070	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2071	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2072	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2073	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2074	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2075	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2076	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2077	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2078	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2079	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2080	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2081	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2082	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2083	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2084	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2085	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2086	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2087	pHlp->pfnPrintf(pHlp, "\n");
2088
2089	uint32_t uECX = Guest.ecx;
2090	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2091	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2092	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
2093	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
2094	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2095	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2096	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2097	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
2098	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2099	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2100	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
2101	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2102	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2103	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
2104	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2105	for (unsigned iBit = 14; iBit < 32; iBit++)
2106	if (uECX & RT_BIT(iBit))
2107	pHlp->pfnPrintf(pHlp, " %d", iBit);
2108	pHlp->pfnPrintf(pHlp, "\n");
2109	}
2110	else
2111	{
2112	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2113
2114	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2115	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2116	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2117	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2118
2119	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2120	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2121	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2122	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2123	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2124	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2125	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2126	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2127	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2128	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2129	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2130	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2131	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2132	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2133	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2134	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2135	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2136	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2137	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2138	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2139	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2140	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2141	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2142	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2143	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2144	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2145	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2146	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2147	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2148	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2149	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2150	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2151	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2152
2153	pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2154	pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2155	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2156	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2157	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2158	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2159	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2160	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2161	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2162	pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2163	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2164	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
2165	pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2166	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2167	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2168	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2169	pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2170	pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2171	pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2172	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2173	pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2174	pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2175	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
2176	pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2177	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2178	pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2179	}
2180	}
2181	if (cStdMax >= 2 && iVerbosity)
2182	{
2183	/** @todo */
2184	}
2185
2186	/*
2187	* Extended.
2188	* Implemented after AMD specs.
2189	*/
2190	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2191
2192	pHlp->pfnPrintf(pHlp,
2193	"\n"
2194	" RAW Extended CPUIDs\n"
2195	" Function eax ebx ecx edx\n");
2196	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2197	{
2198	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2199	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2200
2201	pHlp->pfnPrintf(pHlp,
2202	"Gst: %08x %08x %08x %08x %08x%s\n"
2203	"Hst: %08x %08x %08x %08x\n",
2204	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2205	i <= cExtMax ? "" : "*",
2206	Host.eax, Host.ebx, Host.ecx, Host.edx);
2207	}
2208
2209	/*
2210	* Understandable output
2211	*/
2212	if (iVerbosity)
2213	{
2214	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2215	pHlp->pfnPrintf(pHlp,
2216	"Ext Name: %.4s%.4s%.4s\n"
2217	"Ext Supports: 0x80000000-%#010x\n",
2218	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2219	}
2220
2221	if (iVerbosity && cExtMax >= 1)
2222	{
2223	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2224	uint32_t uEAX = Guest.eax;
2225	pHlp->pfnPrintf(pHlp,
2226	"Family: %d \tExtended: %d \tEffective: %d\n"
2227	"Model: %d \tExtended: %d \tEffective: %d\n"
2228	"Stepping: %d\n"
2229	"Brand ID: %#05x\n",
2230	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2231	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2232	ASMGetCpuStepping(uEAX),
2233	Guest.ebx & 0xfff);
2234
2235	if (iVerbosity == 1)
2236	{
2237	uint32_t uEDX = Guest.edx;
2238	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2239	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2240	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2241	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2242	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2243	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2244	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2245	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2246	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2247	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2248	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2249	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2250	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2251	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2252	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2253	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2254	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2255	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2256	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2257	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2258	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2259	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2260	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2261	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2262	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2263	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2264	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2265	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2266	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2267	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2268	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2269	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2270	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2271	pHlp->pfnPrintf(pHlp, "\n");
2272
2273	uint32_t uECX = Guest.ecx;
2274	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2275	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2276	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2277	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2278	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2279	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2280	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2281	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2282	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2283	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2284	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2285	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2286	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2287	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2288	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2289	for (unsigned iBit = 5; iBit < 32; iBit++)
2290	if (uECX & RT_BIT(iBit))
2291	pHlp->pfnPrintf(pHlp, " %d", iBit);
2292	pHlp->pfnPrintf(pHlp, "\n");
2293	}
2294	else
2295	{
2296	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2297
2298	uint32_t uEdxGst = Guest.edx;
2299	uint32_t uEdxHst = Host.edx;
2300	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2301	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2302	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2303	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2304	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2305	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2306	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2307	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2308	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2309	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2310	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2311	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2312	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2313	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2314	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2315	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2316	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2317	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2318	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2319	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2320	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2321	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2322	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2323	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2324	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2325	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2326	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2327	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2328	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2329	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2330	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2331	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2332	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2333
2334	uint32_t uEcxGst = Guest.ecx;
2335	uint32_t uEcxHst = Host.ecx;
2336	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2337	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2338	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2339	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2340	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2341	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2342	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2343	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2344	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2345	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2346	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2347	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2348	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2349	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2350	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2351	}
2352	}
2353
2354	if (iVerbosity && cExtMax >= 2)
2355	{
2356	char szString[443+1] = {0};
2357	uint32_t pu32 = (uint32_t )szString;
2358	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2359	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2360	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2361	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2362	if (cExtMax >= 3)
2363	{
2364	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2365	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2366	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2367	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2368	}
2369	if (cExtMax >= 4)
2370	{
2371	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2372	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2373	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2374	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2375	}
2376	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2377	}
2378
2379	if (iVerbosity && cExtMax >= 5)
2380	{
2381	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2382	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2383	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2384	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2385	char sz1[32];
2386	char sz2[32];
2387
2388	pHlp->pfnPrintf(pHlp,
2389	"TLB 2/4M Instr/Uni: %s %3d entries\n"
2390	"TLB 2/4M Data: %s %3d entries\n",
2391	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2392	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2393	pHlp->pfnPrintf(pHlp,
2394	"TLB 4K Instr/Uni: %s %3d entries\n"
2395	"TLB 4K Data: %s %3d entries\n",
2396	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2397	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2398	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2399	"L1 Instr Cache Lines Per Tag: %d\n"
2400	"L1 Instr Cache Associativity: %s\n"
2401	"L1 Instr Cache Size: %d KB\n",
2402	(uEDX >> 0) & 0xff,
2403	(uEDX >> 8) & 0xff,
2404	getCacheAss((uEDX >> 16) & 0xff, sz1),
2405	(uEDX >> 24) & 0xff);
2406	pHlp->pfnPrintf(pHlp,
2407	"L1 Data Cache Line Size: %d bytes\n"
2408	"L1 Data Cache Lines Per Tag: %d\n"
2409	"L1 Data Cache Associativity: %s\n"
2410	"L1 Data Cache Size: %d KB\n",
2411	(uECX >> 0) & 0xff,
2412	(uECX >> 8) & 0xff,
2413	getCacheAss((uECX >> 16) & 0xff, sz1),
2414	(uECX >> 24) & 0xff);
2415	}
2416
2417	if (iVerbosity && cExtMax >= 6)
2418	{
2419	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2420	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2421	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2422
2423	pHlp->pfnPrintf(pHlp,
2424	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2425	"L2 TLB 2/4M Data: %s %4d entries\n",
2426	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2427	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2428	pHlp->pfnPrintf(pHlp,
2429	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
2430	"L2 TLB 4K Data: %s %4d entries\n",
2431	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2432	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2433	pHlp->pfnPrintf(pHlp,
2434	"L2 Cache Line Size: %d bytes\n"
2435	"L2 Cache Lines Per Tag: %d\n"
2436	"L2 Cache Associativity: %s\n"
2437	"L2 Cache Size: %d KB\n",
2438	(uEDX >> 0) & 0xff,
2439	(uEDX >> 8) & 0xf,
2440	getL2CacheAss((uEDX >> 12) & 0xf),
2441	(uEDX >> 16) & 0xffff);
2442	}
2443
2444	if (iVerbosity && cExtMax >= 7)
2445	{
2446	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2447
2448	pHlp->pfnPrintf(pHlp, "APM Features: ");
2449	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2450	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2451	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2452	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2453	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2454	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2455	for (unsigned iBit = 6; iBit < 32; iBit++)
2456	if (uEDX & RT_BIT(iBit))
2457	pHlp->pfnPrintf(pHlp, " %d", iBit);
2458	pHlp->pfnPrintf(pHlp, "\n");
2459	}
2460
2461	if (iVerbosity && cExtMax >= 8)
2462	{
2463	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2464	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2465
2466	pHlp->pfnPrintf(pHlp,
2467	"Physical Address Width: %d bits\n"
2468	"Virtual Address Width: %d bits\n",
2469	(uEAX >> 0) & 0xff,
2470	(uEAX >> 8) & 0xff);
2471	pHlp->pfnPrintf(pHlp,
2472	"Physical Core Count: %d\n",
2473	(uECX >> 0) & 0xff);
2474	}
2475
2476
2477	/*
2478	* Centaur.
2479	*/
2480	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2481
2482	pHlp->pfnPrintf(pHlp,
2483	"\n"
2484	" RAW Centaur CPUIDs\n"
2485	" Function eax ebx ecx edx\n");
2486	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2487	{
2488	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2489	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2490
2491	pHlp->pfnPrintf(pHlp,
2492	"Gst: %08x %08x %08x %08x %08x%s\n"
2493	"Hst: %08x %08x %08x %08x\n",
2494	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2495	i <= cCentaurMax ? "" : "*",
2496	Host.eax, Host.ebx, Host.ecx, Host.edx);
2497	}
2498
2499	/*
2500	* Understandable output
2501	*/
2502	if (iVerbosity)
2503	{
2504	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2505	pHlp->pfnPrintf(pHlp,
2506	"Centaur Supports: 0xc0000000-%#010x\n",
2507	Guest.eax);
2508	}
2509
2510	if (iVerbosity && cCentaurMax >= 1)
2511	{
2512	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2513	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2514	uint32_t uEdxHst = Host.edx;
2515
2516	if (iVerbosity == 1)
2517	{
2518	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2519	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2520	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2521	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2522	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2523	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2524	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2525	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2526	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2527	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2528	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2529	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2530	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2531	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2532	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2533	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2534	for (unsigned iBit = 14; iBit < 32; iBit++)
2535	if (uEdxGst & RT_BIT(iBit))
2536	pHlp->pfnPrintf(pHlp, " %d", iBit);
2537	pHlp->pfnPrintf(pHlp, "\n");
2538	}
2539	else
2540	{
2541	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2542	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2543	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2544	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2545	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2546	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2547	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2548	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2549	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2550	/* possibly indicating MM/HE and MM/HE-E on older chips... */
2551	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2552	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2553	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2554	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2555	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2556	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2557	for (unsigned iBit = 14; iBit < 32; iBit++)
2558	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
2559	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2560	pHlp->pfnPrintf(pHlp, "\n");
2561	}
2562	}
2563	}
2564
2565
2566	/**
2567	* Structure used when disassembling and instructions in DBGF.
2568	* This is used so the reader function can get the stuff it needs.
2569	*/
2570	typedef struct CPUMDISASSTATE
2571	{
2572	/** Pointer to the CPU structure. */
2573	PDISCPUSTATE pCpu;
2574	/** The VM handle. */
2575	PVM pVM;
2576	/** The VMCPU handle. */
2577	PVMCPU pVCpu;
2578	/** Pointer to the first byte in the segemnt. */
2579	RTGCUINTPTR GCPtrSegBase;
2580	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2581	RTGCUINTPTR GCPtrSegEnd;
2582	/** The size of the segment minus 1. */
2583	RTGCUINTPTR cbSegLimit;
2584	/** Pointer to the current page - R3 Ptr. */
2585	void const *pvPageR3;
2586	/** Pointer to the current page - GC Ptr. */
2587	RTGCPTR pvPageGC;
2588	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2589	PGMPAGEMAPLOCK PageMapLock;
2590	/** Whether the PageMapLock is valid or not. */
2591	bool fLocked;
2592	/** 64 bits mode or not. */
2593	bool f64Bits;
2594	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2595
2596
2597	/**
2598	* Instruction reader.
2599	*
2600	* @returns VBox status code.
2601	* @param PtrSrc Address to read from.
2602	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2603	* @param pu8Dst Where to store the bytes.
2604	* @param cbRead Number of bytes to read.
2605	* @param uDisCpu Pointer to the disassembler cpu state.
2606	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
2607	*/
2608	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
2609	{
2610	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2611	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2612	Assert(cbRead > 0);
2613	for (;;)
2614	{
2615	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2616
2617	/* Need to update the page translation? */
2618	if ( !pState->pvPageR3
2619	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2620	{
2621	int rc = VINF_SUCCESS;
2622
2623	/* translate the address */
2624	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2625	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2626	&& !HWACCMIsEnabled(pState->pVM))
2627	{
2628	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2629	if (!pState->pvPageR3)
2630	rc = VERR_INVALID_POINTER;
2631	}
2632	else
2633	{
2634	/* Release mapping lock previously acquired. */
2635	if (pState->fLocked)
2636	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2637	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2638	pState->fLocked = RT_SUCCESS_NP(rc);
2639	}
2640	if (RT_FAILURE(rc))
2641	{
2642	pState->pvPageR3 = NULL;
2643	return rc;
2644	}
2645	}
2646
2647	/* check the segemnt limit */
2648	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2649	return VERR_OUT_OF_SELECTOR_BOUNDS;
2650
2651	/* calc how much we can read */
2652	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2653	if (!pState->f64Bits)
2654	{
2655	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2656	if (cb > cbSeg && cbSeg)
2657	cb = cbSeg;
2658	}
2659	if (cb > cbRead)
2660	cb = cbRead;
2661
2662	/* read and advance */
2663	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2664	cbRead -= cb;
2665	if (!cbRead)
2666	return VINF_SUCCESS;
2667	pu8Dst += cb;
2668	PtrSrc += cb;
2669	}
2670	}
2671
2672
2673	/**
2674	* Disassemble an instruction and return the information in the provided structure.
2675	*
2676	* @returns VBox status code.
2677	* @param pVM VM Handle
2678	* @param pVCpu VMCPU Handle
2679	* @param pCtx CPU context
2680	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2681	* @param pCpu Disassembly state
2682	* @param pszPrefix String prefix for logging (debug only)
2683	*
2684	*/
2685	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2686	{
2687	CPUMDISASSTATE State;
2688	int rc;
2689
2690	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2691	State.pCpu = pCpu;
2692	State.pvPageGC = 0;
2693	State.pvPageR3 = NULL;
2694	State.pVM = pVM;
2695	State.pVCpu = pVCpu;
2696	State.fLocked = false;
2697	State.f64Bits = false;
2698
2699	/*
2700	* Get selector information.
2701	*/
2702	if ( (pCtx->cr0 & X86_CR0_PE)
2703	&& pCtx->eflags.Bits.u1VM == 0)
2704	{
2705	if (CPUMAreHiddenSelRegsValid(pVM))
2706	{
2707	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2708	State.GCPtrSegBase = pCtx->csHid.u64Base;
2709	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2710	State.cbSegLimit = pCtx->csHid.u32Limit;
2711	pCpu->mode = (State.f64Bits)
2712	? CPUMODE_64BIT
2713	: pCtx->csHid.Attr.n.u1DefBig
2714	? CPUMODE_32BIT
2715	: CPUMODE_16BIT;
2716	}
2717	else
2718	{
2719	DBGFSELINFO SelInfo;
2720
2721	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2722	if (RT_FAILURE(rc))
2723	{
2724	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2725	return rc;
2726	}
2727
2728	/*
2729	* Validate the selector.
2730	*/
2731	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2732	if (RT_FAILURE(rc))
2733	{
2734	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2735	return rc;
2736	}
2737	State.GCPtrSegBase = SelInfo.GCPtrBase;
2738	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2739	State.cbSegLimit = SelInfo.cbLimit;
2740	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2741	}
2742	}
2743	else
2744	{
2745	/* real or V86 mode */
2746	pCpu->mode = CPUMODE_16BIT;
2747	State.GCPtrSegBase = pCtx->cs * 16;
2748	State.GCPtrSegEnd = 0xFFFFFFFF;
2749	State.cbSegLimit = 0xFFFFFFFF;
2750	}
2751
2752	/*
2753	* Disassemble the instruction.
2754	*/
2755	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2756	pCpu->apvUserData[0] = &State;
2757
2758	uint32_t cbInstr;
2759	#ifndef LOG_ENABLED
2760	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2761	if (RT_SUCCESS(rc))
2762	{
2763	#else
2764	char szOutput[160];
2765	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2766	if (RT_SUCCESS(rc))
2767	{
2768	/* log it */
2769	if (pszPrefix)
2770	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2771	else
2772	Log(("%s", szOutput));
2773	#endif
2774	rc = VINF_SUCCESS;
2775	}
2776	else
2777	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2778
2779	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2780	if (State.fLocked)
2781	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2782
2783	return rc;
2784	}
2785
2786	#ifdef DEBUG
2787
2788	/**
2789	* Disassemble an instruction and dump it to the log
2790	*
2791	* @returns VBox status code.
2792	* @param pVM VM Handle
2793	* @param pVCpu VMCPU Handle
2794	* @param pCtx CPU context
2795	* @param pc GC instruction pointer
2796	* @param pszPrefix String prefix for logging
2797	*
2798	* @deprecated Use DBGFR3DisasInstrCurrentLog().
2799	*/
2800	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2801	{
2802	DISCPUSTATE Cpu;
2803	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2804	}
2805
2806
2807	/**
2808	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
2809	*
2810	* @internal
2811	*/
2812	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2813	{
2814	/* @todo SMP support!! */
2815	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2816	}
2817
2818	#endif /* DEBUG */
2819
2820	/**
2821	* API for controlling a few of the CPU features found in CR4.
2822	*
2823	* Currently only X86_CR4_TSD is accepted as input.
2824	*
2825	* @returns VBox status code.
2826	*
2827	* @param pVM The VM handle.
2828	* @param fOr The CR4 OR mask.
2829	* @param fAnd The CR4 AND mask.
2830	*/
2831	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2832	{
2833	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2834	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2835
2836	pVM->cpum.s.CR4.OrMask &= fAnd;
2837	pVM->cpum.s.CR4.OrMask \|= fOr;
2838
2839	return VINF_SUCCESS;
2840	}
2841
2842
2843	/**
2844	* Gets a pointer to the array of standard CPUID leaves.
2845	*
2846	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2847	*
2848	* @returns Pointer to the standard CPUID leaves (read-only).
2849	* @param pVM The VM handle.
2850	* @remark Intended for PATM.
2851	*/
2852	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2853	{
2854	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2855	}
2856
2857
2858	/**
2859	* Gets a pointer to the array of extended CPUID leaves.
2860	*
2861	* CPUMGetGuestCpuIdExtMax() give the size of the array.
2862	*
2863	* @returns Pointer to the extended CPUID leaves (read-only).
2864	* @param pVM The VM handle.
2865	* @remark Intended for PATM.
2866	*/
2867	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2868	{
2869	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2870	}
2871
2872
2873	/**
2874	* Gets a pointer to the array of centaur CPUID leaves.
2875	*
2876	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2877	*
2878	* @returns Pointer to the centaur CPUID leaves (read-only).
2879	* @param pVM The VM handle.
2880	* @remark Intended for PATM.
2881	*/
2882	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2883	{
2884	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2885	}
2886
2887
2888	/**
2889	* Gets a pointer to the default CPUID leaf.
2890	*
2891	* @returns Pointer to the default CPUID leaf (read-only).
2892	* @param pVM The VM handle.
2893	* @remark Intended for PATM.
2894	*/
2895	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2896	{
2897	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2898	}

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source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 24327

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