VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 23722

Last change on this file since 23722 was 23722, checked in by vboxsync, 15 years ago

CPUM: Live migration coding (incomplete and disabled).
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1/* $Id: CPUM.cpp 23722 2009-10-13 13:05:29Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The current saved state version. */
70#ifdef VBOX_WITH_LIVE_MIGRATION
71#define CPUM_SAVED_STATE_VERSION 11
72#else
73#define CPUM_SAVED_STATE_VERSION 10
74#endif
75/** The saved state version of 3.0 and 3.1 trunk before the live migration
76 * changes. */
77#define CPUM_SAVED_STATE_VERSION_VER3_0 10
78/** The saved state version for the 2.1 trunk before the MSR changes. */
79#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
80/** The saved state version of 2.0, used for backwards compatibility. */
81#define CPUM_SAVED_STATE_VERSION_VER2_0 8
82/** The saved state version of 1.6, used for backwards compatability. */
83#define CPUM_SAVED_STATE_VERSION_VER1_6 6
84
85
86/*******************************************************************************
87* Structures and Typedefs *
88*******************************************************************************/
89
90/**
91 * What kind of cpu info dump to perform.
92 */
93typedef enum CPUMDUMPTYPE
94{
95 CPUMDUMPTYPE_TERSE,
96 CPUMDUMPTYPE_DEFAULT,
97 CPUMDUMPTYPE_VERBOSE
98} CPUMDUMPTYPE;
99/** Pointer to a cpu info dump type. */
100typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
101
102
103/*******************************************************************************
104* Internal Functions *
105*******************************************************************************/
106static int cpumR3CpuIdInit(PVM pVM);
107#ifdef VBOX_WITH_LIVE_MIGRATION
108static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
109#endif
110static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
111static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
112static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
115static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
116static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
117static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
118
119
120/**
121 * Initializes the CPUM.
122 *
123 * @returns VBox status code.
124 * @param pVM The VM to operate on.
125 */
126VMMR3DECL(int) CPUMR3Init(PVM pVM)
127{
128 LogFlow(("CPUMR3Init\n"));
129
130 /*
131 * Assert alignment and sizes.
132 */
133 AssertCompileMemberAlignment(VM, cpum.s, 32);
134 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
135 AssertCompileSizeAlignment(CPUMCTX, 64);
136 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
137 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
138 AssertCompileMemberAlignment(VM, cpum, 64);
139 AssertCompileMemberAlignment(VM, aCpus, 64);
140 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
141 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
142
143 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
144 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
145 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
146
147 /* Calculate the offset from CPUMCPU to CPUM. */
148 for (VMCPUID i = 0; i < pVM->cCpus; i++)
149 {
150 PVMCPU pVCpu = &pVM->aCpus[i];
151
152 /*
153 * Setup any fixed pointers and offsets.
154 */
155 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
156 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
157
158 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
159 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
160 }
161
162 /*
163 * Check that the CPU supports the minimum features we require.
164 */
165 if (!ASMHasCpuId())
166 {
167 Log(("The CPU doesn't support CPUID!\n"));
168 return VERR_UNSUPPORTED_CPU;
169 }
170 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
171 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
172
173 /* Setup the CR4 AND and OR masks used in the switcher */
174 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
175 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
176 {
177 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
178 /* No FXSAVE implies no SSE */
179 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
180 pVM->cpum.s.CR4.OrMask = 0;
181 }
182 else
183 {
184 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
185 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
186 }
187
188 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
189 {
190 Log(("The CPU doesn't support MMX!\n"));
191 return VERR_UNSUPPORTED_CPU;
192 }
193 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
194 {
195 Log(("The CPU doesn't support TSC!\n"));
196 return VERR_UNSUPPORTED_CPU;
197 }
198 /* Bogus on AMD? */
199 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
200 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
201
202 /*
203 * Setup hypervisor startup values.
204 */
205
206 /*
207 * Register saved state data item.
208 */
209#ifdef VBOX_WITH_LIVE_MIGRATION
210 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
211 NULL, cpumR3LiveExec, NULL,
212 NULL, cpumR3SaveExec, NULL,
213 NULL, cpumR3LoadExec, NULL);
214#else
215 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
216 NULL, NULL, NULL,
217 NULL, cpumR3SaveExec, NULL,
218 NULL, cpumR3LoadExec, NULL);
219#endif
220 if (RT_FAILURE(rc))
221 return rc;
222
223 /* Query the CPU manufacturer. */
224 uint32_t uEAX, uEBX, uECX, uEDX;
225 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
226 if ( uEAX >= 1
227 && uEBX == X86_CPUID_VENDOR_AMD_EBX
228 && uECX == X86_CPUID_VENDOR_AMD_ECX
229 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
230 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
231 else if ( uEAX >= 1
232 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
233 && uECX == X86_CPUID_VENDOR_INTEL_ECX
234 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
235 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
236 else /** @todo Via */
237 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
238
239 /*
240 * Register info handlers.
241 */
242 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
243 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
244 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
245 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
246 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
247 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
248
249 /*
250 * Initialize the Guest CPU state.
251 */
252 rc = cpumR3CpuIdInit(pVM);
253 if (RT_FAILURE(rc))
254 return rc;
255 CPUMR3Reset(pVM);
256 return VINF_SUCCESS;
257}
258
259
260/**
261 * Initializes the per-VCPU CPUM.
262 *
263 * @returns VBox status code.
264 * @param pVM The VM to operate on.
265 */
266VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
267{
268 LogFlow(("CPUMR3InitCPU\n"));
269 return VINF_SUCCESS;
270}
271
272
273/**
274 * Initializes the emulated CPU's cpuid information.
275 *
276 * @returns VBox status code.
277 * @param pVM The VM to operate on.
278 */
279static int cpumR3CpuIdInit(PVM pVM)
280{
281 PCPUM pCPUM = &pVM->cpum.s;
282 uint32_t i;
283
284 /*
285 * Get the host CPUIDs.
286 */
287 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
288 ASMCpuId_Idx_ECX(i, 0,
289 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
290 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
291 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
292 ASMCpuId(0x80000000 + i,
293 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
294 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
295 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
296 ASMCpuId(0xc0000000 + i,
297 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
298 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
299
300
301 /*
302 * Only report features we can support.
303 */
304 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
305 | X86_CPUID_FEATURE_EDX_VME
306 | X86_CPUID_FEATURE_EDX_DE
307 | X86_CPUID_FEATURE_EDX_PSE
308 | X86_CPUID_FEATURE_EDX_TSC
309 | X86_CPUID_FEATURE_EDX_MSR
310 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
311 | X86_CPUID_FEATURE_EDX_MCE
312 | X86_CPUID_FEATURE_EDX_CX8
313 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
314 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
315 //| X86_CPUID_FEATURE_EDX_SEP
316 | X86_CPUID_FEATURE_EDX_MTRR
317 | X86_CPUID_FEATURE_EDX_PGE
318 | X86_CPUID_FEATURE_EDX_MCA
319 | X86_CPUID_FEATURE_EDX_CMOV
320 | X86_CPUID_FEATURE_EDX_PAT
321 | X86_CPUID_FEATURE_EDX_PSE36
322 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
323 | X86_CPUID_FEATURE_EDX_CLFSH
324 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
325 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
326 | X86_CPUID_FEATURE_EDX_MMX
327 | X86_CPUID_FEATURE_EDX_FXSR
328 | X86_CPUID_FEATURE_EDX_SSE
329 | X86_CPUID_FEATURE_EDX_SSE2
330 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
331 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
332 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
333 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
334 | 0;
335 pCPUM->aGuestCpuIdStd[1].ecx &= 0
336 | X86_CPUID_FEATURE_ECX_SSE3
337 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
338 | ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
339 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
340 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
341 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
342 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
343 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
344 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
345 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
346 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
347 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
348 /* ECX Bit 21 - x2APIC support - not yet. */
349 // | X86_CPUID_FEATURE_ECX_X2APIC
350 /* ECX Bit 23 - POPCOUNT instruction. */
351 //| X86_CPUID_FEATURE_ECX_POPCOUNT
352 | 0;
353
354 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
355 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
356 | X86_CPUID_AMD_FEATURE_EDX_VME
357 | X86_CPUID_AMD_FEATURE_EDX_DE
358 | X86_CPUID_AMD_FEATURE_EDX_PSE
359 | X86_CPUID_AMD_FEATURE_EDX_TSC
360 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
361 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
362 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
363 | X86_CPUID_AMD_FEATURE_EDX_CX8
364 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
365 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
366 //| X86_CPUID_AMD_FEATURE_EDX_SEP
367 | X86_CPUID_AMD_FEATURE_EDX_MTRR
368 | X86_CPUID_AMD_FEATURE_EDX_PGE
369 | X86_CPUID_AMD_FEATURE_EDX_MCA
370 | X86_CPUID_AMD_FEATURE_EDX_CMOV
371 | X86_CPUID_AMD_FEATURE_EDX_PAT
372 | X86_CPUID_AMD_FEATURE_EDX_PSE36
373 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
374 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
375 | X86_CPUID_AMD_FEATURE_EDX_MMX
376 | X86_CPUID_AMD_FEATURE_EDX_FXSR
377 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
378 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
379 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
380 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
381 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
382 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
383 | 0;
384 pCPUM->aGuestCpuIdExt[1].ecx &= 0
385 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
386 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
387 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
388 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
389 /** Note: This could prevent migration from AMD to Intel CPUs! */
390 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
391 //| X86_CPUID_AMD_FEATURE_ECX_ABM
392 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
393 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
394 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
395 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
396 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
397 //| X86_CPUID_AMD_FEATURE_ECX_WDT
398 | 0;
399
400 /*
401 * Hide HTT, multicode, SMP, whatever.
402 * (APIC-ID := 0 and #LogCpus := 0)
403 */
404 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
405#ifdef VBOX_WITH_MULTI_CORE
406 if (pVM->cCpus > 1)
407 {
408 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
409 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
410 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
411 }
412#endif
413
414 /* Cpuid 2:
415 * Intel: Cache and TLB information
416 * AMD: Reserved
417 * Safe to expose
418 */
419
420 /* Cpuid 3:
421 * Intel: EAX, EBX - reserved
422 * ECX, EDX - Processor Serial Number if available, otherwise reserved
423 * AMD: Reserved
424 * Safe to expose
425 */
426 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
427 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
428
429 /* Cpuid 4:
430 * Intel: Deterministic Cache Parameters Leaf
431 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
432 * AMD: Reserved
433 * Safe to expose, except for EAX:
434 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
435 * Bits 31-26: Maximum number of processor cores in this physical package**
436 * @Note These SMP values are constant regardless of ECX
437 */
438 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
439 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
440#ifdef VBOX_WITH_MULTI_CORE
441 if ( pVM->cCpus > 1
442 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
443 {
444 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
445 /* One logical processor with possibly multiple cores. */
446 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
447 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
448 }
449#endif
450
451 /* Cpuid 5: Monitor/mwait Leaf
452 * Intel: ECX, EDX - reserved
453 * EAX, EBX - Smallest and largest monitor line size
454 * AMD: EDX - reserved
455 * EAX, EBX - Smallest and largest monitor line size
456 * ECX - extensions (ignored for now)
457 * Safe to expose
458 */
459 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
460 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
461
462 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
463
464 /*
465 * Determine the default.
466 *
467 * Intel returns values of the highest standard function, while AMD
468 * returns zeros. VIA on the other hand seems to returning nothing or
469 * perhaps some random garbage, we don't try to duplicate this behavior.
470 */
471 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
472 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
473 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
474
475 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
476 * Safe to pass on to the guest.
477 *
478 * Intel: 0x800000005 reserved
479 * 0x800000006 L2 cache information
480 * AMD: 0x800000005 L1 cache information
481 * 0x800000006 L2/L3 cache information
482 */
483
484 /* Cpuid 0x800000007:
485 * AMD: EAX, EBX, ECX - reserved
486 * EDX: Advanced Power Management Information
487 * Intel: Reserved
488 */
489 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
490 {
491 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
492
493 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
494
495 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
496 {
497 /* Only expose the TSC invariant capability bit to the guest. */
498 pCPUM->aGuestCpuIdExt[7].edx &= 0
499 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
500 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
501 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
502 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
503 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
504 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
505 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
506 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
507#if 1
508 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
509 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
510 */
511#else
512 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
513#endif
514 | 0;
515 }
516 else
517 pCPUM->aGuestCpuIdExt[7].edx = 0;
518 }
519
520 /* Cpuid 0x800000008:
521 * AMD: EBX, EDX - reserved
522 * EAX: Virtual/Physical address Size
523 * ECX: Number of cores + APICIdCoreIdSize
524 * Intel: EAX: Virtual/Physical address Size
525 * EBX, ECX, EDX - reserved
526 */
527 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
528 {
529 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
530 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
531 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
532 * NC (0-7) Number of cores; 0 equals 1 core */
533 pCPUM->aGuestCpuIdExt[8].ecx = 0;
534#ifdef VBOX_WITH_MULTI_CORE
535 if ( pVM->cCpus > 1
536 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
537 {
538 /* Legacy method to determine the number of cores. */
539 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
540 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
541
542 }
543#endif
544 }
545
546 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
547 * Limit the number of standard CPUID leafs to 0..2 to prevent NT4 from
548 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
549 * This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
550 * @todo r=bird: The intel docs states that leafs 3 is included, why don't we?
551 */
552 bool fNt4LeafLimit;
553 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
554 if (fNt4LeafLimit)
555 pCPUM->aGuestCpuIdStd[0].eax = 2;
556
557 /*
558 * Limit it the number of entries and fill the remaining with the defaults.
559 *
560 * The limits are masking off stuff about power saving and similar, this
561 * is perhaps a bit crudely done as there is probably some relatively harmless
562 * info too in these leaves (like words about having a constant TSC).
563 */
564 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
565 pCPUM->aGuestCpuIdStd[0].eax = 5;
566
567 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
568 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
569
570 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
571 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
572 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
573 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
574 : 0;
575 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
576 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
577
578 /*
579 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
580 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
581 * of processors from (cpuid(4).eax >> 26) + 1.
582 */
583 if (pVM->cCpus == 1)
584 pCPUM->aGuestCpuIdStd[4].eax = 0;
585
586 /*
587 * Centaur stuff (VIA).
588 *
589 * The important part here (we think) is to make sure the 0xc0000000
590 * function returns 0xc0000001. As for the features, we don't currently
591 * let on about any of those... 0xc0000002 seems to be some
592 * temperature/hz/++ stuff, include it as well (static).
593 */
594 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
595 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
596 {
597 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
598 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
599 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
600 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
601 i++)
602 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
603 }
604 else
605 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
606 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
607
608
609 /*
610 * Load CPUID overrides from configuration.
611 */
612 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
613 * Overloads the CPUID leaf values. */
614 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
615 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
616 for (i=0;; )
617 {
618 while (cElements-- > 0)
619 {
620 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
621 if (pNode)
622 {
623 uint32_t u32;
624 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
625 if (RT_SUCCESS(rc))
626 pCpuId->eax = u32;
627 else
628 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
629
630 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
631 if (RT_SUCCESS(rc))
632 pCpuId->ebx = u32;
633 else
634 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
635
636 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
637 if (RT_SUCCESS(rc))
638 pCpuId->ecx = u32;
639 else
640 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
641
642 rc = CFGMR3QueryU32(pNode, "edx", &u32);
643 if (RT_SUCCESS(rc))
644 pCpuId->edx = u32;
645 else
646 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
647 }
648 pCpuId++;
649 i++;
650 }
651
652 /* next */
653 if ((i & UINT32_C(0xc0000000)) == 0)
654 {
655 pCpuId = &pCPUM->aGuestCpuIdExt[0];
656 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
657 i = UINT32_C(0x80000000);
658 }
659 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
660 {
661 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
662 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
663 i = UINT32_C(0xc0000000);
664 }
665 else
666 break;
667 }
668
669 /* Check if PAE was explicitely enabled by the user. */
670 bool fEnable = false;
671 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
672 if (RT_SUCCESS(rc) && fEnable)
673 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
674
675 /*
676 * Log the cpuid and we're good.
677 */
678 RTCPUSET OnlineSet;
679 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
680 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
681 LogRel(("************************* CPUID dump ************************\n"));
682 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
683 LogRel(("\n"));
684 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
685 LogRel(("******************** End of CPUID dump **********************\n"));
686 return VINF_SUCCESS;
687}
688
689
690
691
692/**
693 * Applies relocations to data and code managed by this
694 * component. This function will be called at init and
695 * whenever the VMM need to relocate it self inside the GC.
696 *
697 * The CPUM will update the addresses used by the switcher.
698 *
699 * @param pVM The VM.
700 */
701VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
702{
703 LogFlow(("CPUMR3Relocate\n"));
704 for (VMCPUID i = 0; i < pVM->cCpus; i++)
705 {
706 /*
707 * Switcher pointers.
708 */
709 PVMCPU pVCpu = &pVM->aCpus[i];
710 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
711 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
712 }
713}
714
715
716/**
717 * Terminates the CPUM.
718 *
719 * Termination means cleaning up and freeing all resources,
720 * the VM it self is at this point powered off or suspended.
721 *
722 * @returns VBox status code.
723 * @param pVM The VM to operate on.
724 */
725VMMR3DECL(int) CPUMR3Term(PVM pVM)
726{
727 CPUMR3TermCPU(pVM);
728 return 0;
729}
730
731
732/**
733 * Terminates the per-VCPU CPUM.
734 *
735 * Termination means cleaning up and freeing all resources,
736 * the VM it self is at this point powered off or suspended.
737 *
738 * @returns VBox status code.
739 * @param pVM The VM to operate on.
740 */
741VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
742{
743#ifdef VBOX_WITH_CRASHDUMP_MAGIC
744 for (VMCPUID i = 0; i < pVM->cCpus; i++)
745 {
746 PVMCPU pVCpu = &pVM->aCpus[i];
747 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
748
749 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
750 pVCpu->cpum.s.uMagic = 0;
751 pCtx->dr[5] = 0;
752 }
753#endif
754 return 0;
755}
756
757VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
758{
759 /* @todo anything different for VCPU > 0? */
760 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
761
762 /*
763 * Initialize everything to ZERO first.
764 */
765 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
766 memset(pCtx, 0, sizeof(*pCtx));
767 pVCpu->cpum.s.fUseFlags = fUseFlags;
768
769 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
770 pCtx->eip = 0x0000fff0;
771 pCtx->edx = 0x00000600; /* P6 processor */
772 pCtx->eflags.Bits.u1Reserved0 = 1;
773
774 pCtx->cs = 0xf000;
775 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
776 pCtx->csHid.u32Limit = 0x0000ffff;
777 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
778 pCtx->csHid.Attr.n.u1Present = 1;
779 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
780
781 pCtx->dsHid.u32Limit = 0x0000ffff;
782 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
783 pCtx->dsHid.Attr.n.u1Present = 1;
784 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
785
786 pCtx->esHid.u32Limit = 0x0000ffff;
787 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
788 pCtx->esHid.Attr.n.u1Present = 1;
789 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
790
791 pCtx->fsHid.u32Limit = 0x0000ffff;
792 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
793 pCtx->fsHid.Attr.n.u1Present = 1;
794 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
795
796 pCtx->gsHid.u32Limit = 0x0000ffff;
797 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
798 pCtx->gsHid.Attr.n.u1Present = 1;
799 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
800
801 pCtx->ssHid.u32Limit = 0x0000ffff;
802 pCtx->ssHid.Attr.n.u1Present = 1;
803 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
804 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
805
806 pCtx->idtr.cbIdt = 0xffff;
807 pCtx->gdtr.cbGdt = 0xffff;
808
809 pCtx->ldtrHid.u32Limit = 0xffff;
810 pCtx->ldtrHid.Attr.n.u1Present = 1;
811 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
812
813 pCtx->trHid.u32Limit = 0xffff;
814 pCtx->trHid.Attr.n.u1Present = 1;
815 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
816
817 pCtx->dr[6] = X86_DR6_INIT_VAL;
818 pCtx->dr[7] = X86_DR7_INIT_VAL;
819
820 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
821 pCtx->fpu.FCW = 0x37f;
822
823 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
824 pCtx->fpu.MXCSR = 0x1F80;
825
826 /* Init PAT MSR */
827 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
828
829 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
830 * The Intel docs don't mention it.
831 */
832 pCtx->msrEFER = 0;
833}
834
835/**
836 * Resets the CPU.
837 *
838 * @returns VINF_SUCCESS.
839 * @param pVM The VM handle.
840 */
841VMMR3DECL(void) CPUMR3Reset(PVM pVM)
842{
843 for (VMCPUID i = 0; i < pVM->cCpus; i++)
844 {
845 CPUMR3ResetCpu(&pVM->aCpus[i]);
846
847#ifdef VBOX_WITH_CRASHDUMP_MAGIC
848 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
849
850 /* Magic marker for searching in crash dumps. */
851 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
852 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
853 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
854#endif
855 }
856}
857
858#ifdef VBOX_WITH_LIVE_MIGRATION
859
860/**
861 * Called both in pass 0 and the final pass.
862 *
863 * @param pVM The VM handle.
864 * @param pSSM The saved state handle.
865 */
866static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
867{
868 /*
869 * Save all the CPU ID leafs here so we can check them for compatability
870 * upon loading.
871 */
872 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
873 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
874
875 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
876 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
877
878 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
879 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
880
881 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
882
883 /*
884 * Save a good portion of the raw CPU IDs as well as they may come in
885 * handy when validating features for raw mode.
886 */
887 CPUMCPUID aRawStd[8];
888 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
889 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
890 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
891 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
892
893 CPUMCPUID aRawExt[16];
894 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
895 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
896 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
897 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
898}
899
900
901/**
902 * Loads the CPU ID leafs saved by pass 0.
903 *
904 * @returns VBox status code.
905 * @param pVM The VM handle.
906 * @param pSSM The saved state handle.
907 * @param uVersion The format version.
908 */
909static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
910{
911 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
912
913 /*
914 * Load them into stack buffers first.
915 */
916 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
917 uint32_t cGuestCpuIdStd;
918 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
919 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
920 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
921 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
922
923 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
924 uint32_t cGuestCpuIdExt;
925 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
926 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
927 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
928 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
929
930 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
931 uint32_t cGuestCpuIdCentaur;
932 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
933 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
934 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
935 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
936
937 CPUMCPUID GuestCpuIdDef;
938 rc = SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
939 AssertRCReturn(rc, rc);
940
941 CPUMCPUID aRawStd[8];
942 uint32_t cRawStd;
943 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
944 if (cRawStd > RT_ELEMENTS(aRawStd))
945 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
946 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
947
948 CPUMCPUID aRawExt[16];
949 uint32_t cRawExt;
950 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
951 if (cRawExt > RT_ELEMENTS(aRawExt))
952 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
953 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
954 AssertRCReturn(rc, rc);
955
956 /*
957 * Note that we support restoring less than the current amount of standard
958 * leaves because we've been allowed more is newer version of VBox.
959 *
960 * So, pad new entries with the default.
961 */
962 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
963 aGuestCpuIdStd[i] = GuestCpuIdDef;
964
965 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
966 aGuestCpuIdExt[i] = GuestCpuIdDef;
967
968 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
969 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
970
971 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
972 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
973
974 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
975 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
976
977 /*
978 * Get the raw CPU IDs for the current host.
979 */
980 CPUMCPUID aHostRawStd[8];
981 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
982 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
983
984 CPUMCPUID aHostRawExt[16];
985 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
986 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
987
988 /*
989 * Now for the fun part...
990 */
991
992
993 /*
994 * We're good, commit the CPU ID leafs.
995 */
996 memcmp(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
997 memcmp(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
998 memcmp(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
999 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1000
1001 return VINF_SUCCESS;
1002}
1003
1004
1005/**
1006 * Pass 0 live exec callback.
1007 *
1008 * @returns VINF_SSM_DONT_CALL_AGAIN.
1009 * @param pVM The VM handle.
1010 * @param pSSM The saved state handle.
1011 * @param uPass The pass (0).
1012 */
1013static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1014{
1015 AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1016 cpumR3SaveCpuId(pVM, pSSM);
1017 return VINF_SSM_DONT_CALL_AGAIN;
1018}
1019
1020#endif /* VBOX_WITH_LIVE_MIGRATION */
1021
1022/**
1023 * Execute state save operation.
1024 *
1025 * @returns VBox status code.
1026 * @param pVM VM Handle.
1027 * @param pSSM SSM operation handle.
1028 */
1029static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1030{
1031 /*
1032 * Save.
1033 */
1034 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1035 {
1036 PVMCPU pVCpu = &pVM->aCpus[i];
1037
1038 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1039 }
1040
1041 SSMR3PutU32(pSSM, pVM->cCpus);
1042 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1043 {
1044 PVMCPU pVCpu = &pVM->aCpus[i];
1045
1046 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1047 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1048 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1049 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1050 }
1051
1052#ifdef VBOX_WITH_LIVE_MIGRATION
1053 cpumR3SaveCpuId(pVM, pSSM);
1054 return VINF_SUCCESS;
1055#else
1056
1057 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1058 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1059
1060 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1061 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1062
1063 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1064 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1065
1066 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1067
1068 /* Add the cpuid for checking that the cpu is unchanged. */
1069 uint32_t au32CpuId[8] = {0};
1070 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1071 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1072 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
1073#endif
1074}
1075
1076
1077/**
1078 * Load a version 1.6 CPUMCTX structure.
1079 *
1080 * @returns VBox status code.
1081 * @param pVM VM Handle.
1082 * @param pCpumctx16 Version 1.6 CPUMCTX
1083 */
1084static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1085{
1086#define CPUMCTX16_LOADREG(RegName) \
1087 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1088
1089#define CPUMCTX16_LOADDRXREG(RegName) \
1090 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1091
1092#define CPUMCTX16_LOADHIDREG(RegName) \
1093 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1094 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1095 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1096
1097#define CPUMCTX16_LOADSEGREG(RegName) \
1098 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1099 CPUMCTX16_LOADHIDREG(RegName);
1100
1101 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1102
1103 CPUMCTX16_LOADREG(rax);
1104 CPUMCTX16_LOADREG(rbx);
1105 CPUMCTX16_LOADREG(rcx);
1106 CPUMCTX16_LOADREG(rdx);
1107 CPUMCTX16_LOADREG(rdi);
1108 CPUMCTX16_LOADREG(rsi);
1109 CPUMCTX16_LOADREG(rbp);
1110 CPUMCTX16_LOADREG(esp);
1111 CPUMCTX16_LOADREG(rip);
1112 CPUMCTX16_LOADREG(rflags);
1113
1114 CPUMCTX16_LOADSEGREG(cs);
1115 CPUMCTX16_LOADSEGREG(ds);
1116 CPUMCTX16_LOADSEGREG(es);
1117 CPUMCTX16_LOADSEGREG(fs);
1118 CPUMCTX16_LOADSEGREG(gs);
1119 CPUMCTX16_LOADSEGREG(ss);
1120
1121 CPUMCTX16_LOADREG(r8);
1122 CPUMCTX16_LOADREG(r9);
1123 CPUMCTX16_LOADREG(r10);
1124 CPUMCTX16_LOADREG(r11);
1125 CPUMCTX16_LOADREG(r12);
1126 CPUMCTX16_LOADREG(r13);
1127 CPUMCTX16_LOADREG(r14);
1128 CPUMCTX16_LOADREG(r15);
1129
1130 CPUMCTX16_LOADREG(cr0);
1131 CPUMCTX16_LOADREG(cr2);
1132 CPUMCTX16_LOADREG(cr3);
1133 CPUMCTX16_LOADREG(cr4);
1134
1135 CPUMCTX16_LOADDRXREG(0);
1136 CPUMCTX16_LOADDRXREG(1);
1137 CPUMCTX16_LOADDRXREG(2);
1138 CPUMCTX16_LOADDRXREG(3);
1139 CPUMCTX16_LOADDRXREG(4);
1140 CPUMCTX16_LOADDRXREG(5);
1141 CPUMCTX16_LOADDRXREG(6);
1142 CPUMCTX16_LOADDRXREG(7);
1143
1144 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
1145 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
1146 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
1147 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
1148
1149 CPUMCTX16_LOADREG(ldtr);
1150 CPUMCTX16_LOADREG(tr);
1151
1152 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
1153
1154 CPUMCTX16_LOADREG(msrEFER);
1155 CPUMCTX16_LOADREG(msrSTAR);
1156 CPUMCTX16_LOADREG(msrPAT);
1157 CPUMCTX16_LOADREG(msrLSTAR);
1158 CPUMCTX16_LOADREG(msrCSTAR);
1159 CPUMCTX16_LOADREG(msrSFMASK);
1160 CPUMCTX16_LOADREG(msrKERNELGSBASE);
1161
1162 CPUMCTX16_LOADHIDREG(ldtr);
1163 CPUMCTX16_LOADHIDREG(tr);
1164
1165#undef CPUMCTX16_LOADSEGREG
1166#undef CPUMCTX16_LOADHIDREG
1167#undef CPUMCTX16_LOADDRXREG
1168#undef CPUMCTX16_LOADREG
1169}
1170
1171
1172/**
1173 * Execute state load operation.
1174 *
1175 * @returns VBox status code.
1176 * @param pVM VM Handle.
1177 * @param pSSM SSM operation handle.
1178 * @param uVersion Data layout version.
1179 * @param uPass The data pass.
1180 */
1181static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1182{
1183 /*
1184 * Validate version.
1185 */
1186 if ( uVersion != CPUM_SAVED_STATE_VERSION
1187 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1188 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1189 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1190 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1191 {
1192 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1193 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1194 }
1195
1196 if (uPass == SSM_PASS_FINAL)
1197 {
1198 /*
1199 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1200 * really old SSM file versions.)
1201 */
1202 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1203 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1204 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1205 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1206
1207 /*
1208 * Restore.
1209 */
1210 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1211 {
1212 PVMCPU pVCpu = &pVM->aCpus[i];
1213 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1214 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1215
1216 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1217 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1218 pVCpu->cpum.s.Hyper.esp = uESP;
1219 }
1220
1221 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1222 {
1223 CPUMCTX_VER1_6 cpumctx16;
1224 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1225 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1226
1227 /* Save the old cpumctx state into the new one. */
1228 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1229
1230 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1231 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1232 }
1233 else
1234 {
1235 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1236 {
1237 uint32_t cCpus;
1238 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1239 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1240 VERR_SSM_UNEXPECTED_DATA);
1241 }
1242 AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1243 || pVM->cCpus == 1,
1244 ("cCpus=%u\n", pVM->cCpus),
1245 VERR_SSM_UNEXPECTED_DATA);
1246
1247 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1248 {
1249 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1250 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1251 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1252 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1253 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1254 }
1255 }
1256 }
1257
1258#ifdef VBOX_WITH_LIVE_MIGRATION
1259 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1260 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1261
1262 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1263 * actually required. */
1264#endif
1265
1266 /*
1267 * Restore the CPUID leaves.
1268 *
1269 * Note that we support restoring less than the current amount of standard
1270 * leaves because we've been allowed more is newer version of VBox.
1271 */
1272 uint32_t cElements;
1273 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1274 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1275 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1276 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1277
1278 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1279 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1280 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1281 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1282
1283 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1284 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1285 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1286 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1287
1288 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1289
1290 /*
1291 * Check that the basic cpuid id information is unchanged.
1292 */
1293 /** @todo we should check the 64 bits capabilities too! */
1294 uint32_t au32CpuId[8] = {0};
1295 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1296 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1297 uint32_t au32CpuIdSaved[8];
1298 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1299 if (RT_SUCCESS(rc))
1300 {
1301 /* Ignore CPU stepping. */
1302 au32CpuId[4] &= 0xfffffff0;
1303 au32CpuIdSaved[4] &= 0xfffffff0;
1304
1305 /* Ignore APIC ID (AMD specs). */
1306 au32CpuId[5] &= ~0xff000000;
1307 au32CpuIdSaved[5] &= ~0xff000000;
1308
1309 /* Ignore the number of Logical CPUs (AMD specs). */
1310 au32CpuId[5] &= ~0x00ff0000;
1311 au32CpuIdSaved[5] &= ~0x00ff0000;
1312
1313 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1314 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1315 | X86_CPUID_FEATURE_ECX_VMX
1316 | X86_CPUID_FEATURE_ECX_SMX
1317 | X86_CPUID_FEATURE_ECX_EST
1318 | X86_CPUID_FEATURE_ECX_TM2
1319 | X86_CPUID_FEATURE_ECX_CNTXID
1320 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1321 | X86_CPUID_FEATURE_ECX_PDCM
1322 | X86_CPUID_FEATURE_ECX_DCA
1323 | X86_CPUID_FEATURE_ECX_X2APIC
1324 );
1325 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1326 | X86_CPUID_FEATURE_ECX_VMX
1327 | X86_CPUID_FEATURE_ECX_SMX
1328 | X86_CPUID_FEATURE_ECX_EST
1329 | X86_CPUID_FEATURE_ECX_TM2
1330 | X86_CPUID_FEATURE_ECX_CNTXID
1331 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1332 | X86_CPUID_FEATURE_ECX_PDCM
1333 | X86_CPUID_FEATURE_ECX_DCA
1334 | X86_CPUID_FEATURE_ECX_X2APIC
1335 );
1336
1337 /* Make sure we don't forget to update the masks when enabling
1338 * features in the future.
1339 */
1340 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1341 ( X86_CPUID_FEATURE_ECX_DTES64
1342 | X86_CPUID_FEATURE_ECX_VMX
1343 | X86_CPUID_FEATURE_ECX_SMX
1344 | X86_CPUID_FEATURE_ECX_EST
1345 | X86_CPUID_FEATURE_ECX_TM2
1346 | X86_CPUID_FEATURE_ECX_CNTXID
1347 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1348 | X86_CPUID_FEATURE_ECX_PDCM
1349 | X86_CPUID_FEATURE_ECX_DCA
1350 | X86_CPUID_FEATURE_ECX_X2APIC
1351 )));
1352 /* do the compare */
1353 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1354 {
1355 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1356 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1357 "Saved=%.*Rhxs\n"
1358 "Real =%.*Rhxs\n",
1359 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1360 sizeof(au32CpuId), au32CpuId));
1361 else
1362 {
1363 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1364 "Saved=%.*Rhxs\n"
1365 "Real =%.*Rhxs\n",
1366 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1367 sizeof(au32CpuId), au32CpuId));
1368 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1369 }
1370 }
1371 }
1372
1373 return rc;
1374}
1375
1376
1377/**
1378 * Formats the EFLAGS value into mnemonics.
1379 *
1380 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1381 * @param efl The EFLAGS value.
1382 */
1383static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1384{
1385 /*
1386 * Format the flags.
1387 */
1388 static const struct
1389 {
1390 const char *pszSet; const char *pszClear; uint32_t fFlag;
1391 } s_aFlags[] =
1392 {
1393 { "vip",NULL, X86_EFL_VIP },
1394 { "vif",NULL, X86_EFL_VIF },
1395 { "ac", NULL, X86_EFL_AC },
1396 { "vm", NULL, X86_EFL_VM },
1397 { "rf", NULL, X86_EFL_RF },
1398 { "nt", NULL, X86_EFL_NT },
1399 { "ov", "nv", X86_EFL_OF },
1400 { "dn", "up", X86_EFL_DF },
1401 { "ei", "di", X86_EFL_IF },
1402 { "tf", NULL, X86_EFL_TF },
1403 { "nt", "pl", X86_EFL_SF },
1404 { "nz", "zr", X86_EFL_ZF },
1405 { "ac", "na", X86_EFL_AF },
1406 { "po", "pe", X86_EFL_PF },
1407 { "cy", "nc", X86_EFL_CF },
1408 };
1409 char *psz = pszEFlags;
1410 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1411 {
1412 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1413 if (pszAdd)
1414 {
1415 strcpy(psz, pszAdd);
1416 psz += strlen(pszAdd);
1417 *psz++ = ' ';
1418 }
1419 }
1420 psz[-1] = '\0';
1421}
1422
1423
1424/**
1425 * Formats a full register dump.
1426 *
1427 * @param pVM VM Handle.
1428 * @param pCtx The context to format.
1429 * @param pCtxCore The context core to format.
1430 * @param pHlp Output functions.
1431 * @param enmType The dump type.
1432 * @param pszPrefix Register name prefix.
1433 */
1434static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1435{
1436 /*
1437 * Format the EFLAGS.
1438 */
1439 uint32_t efl = pCtxCore->eflags.u32;
1440 char szEFlags[80];
1441 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1442
1443 /*
1444 * Format the registers.
1445 */
1446 switch (enmType)
1447 {
1448 case CPUMDUMPTYPE_TERSE:
1449 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1450 pHlp->pfnPrintf(pHlp,
1451 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1452 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1453 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1454 "%sr14=%016RX64 %sr15=%016RX64\n"
1455 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1456 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1457 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1458 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1459 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1460 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1461 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1462 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1463 else
1464 pHlp->pfnPrintf(pHlp,
1465 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1466 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1467 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1468 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1469 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1470 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1471 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1472 break;
1473
1474 case CPUMDUMPTYPE_DEFAULT:
1475 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1476 pHlp->pfnPrintf(pHlp,
1477 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1478 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1479 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1480 "%sr14=%016RX64 %sr15=%016RX64\n"
1481 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1482 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1483 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1484 ,
1485 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1486 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1487 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1488 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1489 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1490 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1491 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1492 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1493 else
1494 pHlp->pfnPrintf(pHlp,
1495 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1496 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1497 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1498 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1499 ,
1500 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1501 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1502 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1503 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1504 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1505 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1506 break;
1507
1508 case CPUMDUMPTYPE_VERBOSE:
1509 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1510 pHlp->pfnPrintf(pHlp,
1511 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1512 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1513 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1514 "%sr14=%016RX64 %sr15=%016RX64\n"
1515 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1516 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1517 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1518 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1519 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1520 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1521 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1522 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1523 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1524 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1525 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1526 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1527 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1528 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1529 ,
1530 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1531 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1532 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1533 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1534 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1535 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1536 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1537 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1538 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1539 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1540 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1541 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1542 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1543 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1544 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1545 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1546 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1547 else
1548 pHlp->pfnPrintf(pHlp,
1549 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1550 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1551 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1552 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1553 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1554 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1555 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1556 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1557 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1558 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1559 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1560 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1561 ,
1562 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1563 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1564 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1565 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1566 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1567 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1568 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1569 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1570 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1571 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1572 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1573 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1574
1575 pHlp->pfnPrintf(pHlp,
1576 "FPU:\n"
1577 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1578 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1579 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1580 ,
1581 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1582 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1583 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1584 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1585
1586 pHlp->pfnPrintf(pHlp,
1587 "MSR:\n"
1588 "%sEFER =%016RX64\n"
1589 "%sPAT =%016RX64\n"
1590 "%sSTAR =%016RX64\n"
1591 "%sCSTAR =%016RX64\n"
1592 "%sLSTAR =%016RX64\n"
1593 "%sSFMASK =%016RX64\n"
1594 "%sKERNELGSBASE =%016RX64\n",
1595 pszPrefix, pCtx->msrEFER,
1596 pszPrefix, pCtx->msrPAT,
1597 pszPrefix, pCtx->msrSTAR,
1598 pszPrefix, pCtx->msrCSTAR,
1599 pszPrefix, pCtx->msrLSTAR,
1600 pszPrefix, pCtx->msrSFMASK,
1601 pszPrefix, pCtx->msrKERNELGSBASE);
1602 break;
1603 }
1604}
1605
1606
1607/**
1608 * Display all cpu states and any other cpum info.
1609 *
1610 * @param pVM VM Handle.
1611 * @param pHlp The info helper functions.
1612 * @param pszArgs Arguments, ignored.
1613 */
1614static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1615{
1616 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1617 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1618 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1619 cpumR3InfoHost(pVM, pHlp, pszArgs);
1620}
1621
1622
1623/**
1624 * Parses the info argument.
1625 *
1626 * The argument starts with 'verbose', 'terse' or 'default' and then
1627 * continues with the comment string.
1628 *
1629 * @param pszArgs The pointer to the argument string.
1630 * @param penmType Where to store the dump type request.
1631 * @param ppszComment Where to store the pointer to the comment string.
1632 */
1633static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1634{
1635 if (!pszArgs)
1636 {
1637 *penmType = CPUMDUMPTYPE_DEFAULT;
1638 *ppszComment = "";
1639 }
1640 else
1641 {
1642 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1643 {
1644 pszArgs += 5;
1645 *penmType = CPUMDUMPTYPE_VERBOSE;
1646 }
1647 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1648 {
1649 pszArgs += 5;
1650 *penmType = CPUMDUMPTYPE_TERSE;
1651 }
1652 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1653 {
1654 pszArgs += 7;
1655 *penmType = CPUMDUMPTYPE_DEFAULT;
1656 }
1657 else
1658 *penmType = CPUMDUMPTYPE_DEFAULT;
1659 *ppszComment = RTStrStripL(pszArgs);
1660 }
1661}
1662
1663
1664/**
1665 * Display the guest cpu state.
1666 *
1667 * @param pVM VM Handle.
1668 * @param pHlp The info helper functions.
1669 * @param pszArgs Arguments, ignored.
1670 */
1671static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1672{
1673 CPUMDUMPTYPE enmType;
1674 const char *pszComment;
1675 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1676
1677 /* @todo SMP support! */
1678 PVMCPU pVCpu = VMMGetCpu(pVM);
1679 if (!pVCpu)
1680 pVCpu = &pVM->aCpus[0];
1681
1682 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1683
1684 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1685 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1686}
1687
1688
1689/**
1690 * Display the current guest instruction
1691 *
1692 * @param pVM VM Handle.
1693 * @param pHlp The info helper functions.
1694 * @param pszArgs Arguments, ignored.
1695 */
1696static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1697{
1698 char szInstruction[256];
1699 /* @todo SMP support! */
1700 PVMCPU pVCpu = VMMGetCpu(pVM);
1701 if (!pVCpu)
1702 pVCpu = &pVM->aCpus[0];
1703
1704 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1705 if (RT_SUCCESS(rc))
1706 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1707}
1708
1709
1710/**
1711 * Display the hypervisor cpu state.
1712 *
1713 * @param pVM VM Handle.
1714 * @param pHlp The info helper functions.
1715 * @param pszArgs Arguments, ignored.
1716 */
1717static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1718{
1719 CPUMDUMPTYPE enmType;
1720 const char *pszComment;
1721 /* @todo SMP */
1722 PVMCPU pVCpu = &pVM->aCpus[0];
1723
1724 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1725 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1726 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1727 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1728}
1729
1730
1731/**
1732 * Display the host cpu state.
1733 *
1734 * @param pVM VM Handle.
1735 * @param pHlp The info helper functions.
1736 * @param pszArgs Arguments, ignored.
1737 */
1738static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1739{
1740 CPUMDUMPTYPE enmType;
1741 const char *pszComment;
1742 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1743 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1744
1745 /*
1746 * Format the EFLAGS.
1747 */
1748 /* @todo SMP */
1749 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1750#if HC_ARCH_BITS == 32
1751 uint32_t efl = pCtx->eflags.u32;
1752#else
1753 uint64_t efl = pCtx->rflags;
1754#endif
1755 char szEFlags[80];
1756 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1757
1758 /*
1759 * Format the registers.
1760 */
1761#if HC_ARCH_BITS == 32
1762# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1763 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1764# endif
1765 {
1766 pHlp->pfnPrintf(pHlp,
1767 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1768 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1769 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1770 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1771 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1772 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1773 ,
1774 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1775 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1776 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1777 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1778 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1779 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1780 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1781 }
1782# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1783 else
1784# endif
1785#endif
1786#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1787 {
1788 pHlp->pfnPrintf(pHlp,
1789 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1790 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1791 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1792 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1793 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1794 "r14=%016RX64 r15=%016RX64\n"
1795 "iopl=%d %31s\n"
1796 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1797 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1798 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1799 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1800 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1801 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1802 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1803 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1804 ,
1805 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1806 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1807 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1808 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1809 pCtx->r11, pCtx->r12, pCtx->r13,
1810 pCtx->r14, pCtx->r15,
1811 X86_EFL_GET_IOPL(efl), szEFlags,
1812 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1813 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1814 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1815 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1816 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1817 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1818 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1819 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1820 }
1821#endif
1822}
1823
1824
1825/**
1826 * Get L1 cache / TLS associativity.
1827 */
1828static const char *getCacheAss(unsigned u, char *pszBuf)
1829{
1830 if (u == 0)
1831 return "res0 ";
1832 if (u == 1)
1833 return "direct";
1834 if (u >= 256)
1835 return "???";
1836
1837 RTStrPrintf(pszBuf, 16, "%d way", u);
1838 return pszBuf;
1839}
1840
1841
1842/**
1843 * Get L2 cache soociativity.
1844 */
1845const char *getL2CacheAss(unsigned u)
1846{
1847 switch (u)
1848 {
1849 case 0: return "off ";
1850 case 1: return "direct";
1851 case 2: return "2 way ";
1852 case 3: return "res3 ";
1853 case 4: return "4 way ";
1854 case 5: return "res5 ";
1855 case 6: return "8 way "; case 7: return "res7 ";
1856 case 8: return "16 way";
1857 case 9: return "res9 ";
1858 case 10: return "res10 ";
1859 case 11: return "res11 ";
1860 case 12: return "res12 ";
1861 case 13: return "res13 ";
1862 case 14: return "res14 ";
1863 case 15: return "fully ";
1864 default:
1865 return "????";
1866 }
1867}
1868
1869
1870/**
1871 * Display the guest CpuId leaves.
1872 *
1873 * @param pVM VM Handle.
1874 * @param pHlp The info helper functions.
1875 * @param pszArgs "terse", "default" or "verbose".
1876 */
1877static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1878{
1879 /*
1880 * Parse the argument.
1881 */
1882 unsigned iVerbosity = 1;
1883 if (pszArgs)
1884 {
1885 pszArgs = RTStrStripL(pszArgs);
1886 if (!strcmp(pszArgs, "terse"))
1887 iVerbosity--;
1888 else if (!strcmp(pszArgs, "verbose"))
1889 iVerbosity++;
1890 }
1891
1892 /*
1893 * Start cracking.
1894 */
1895 CPUMCPUID Host;
1896 CPUMCPUID Guest;
1897 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1898
1899 pHlp->pfnPrintf(pHlp,
1900 " RAW Standard CPUIDs\n"
1901 " Function eax ebx ecx edx\n");
1902 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1903 {
1904 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1905 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1906
1907 pHlp->pfnPrintf(pHlp,
1908 "Gst: %08x %08x %08x %08x %08x%s\n"
1909 "Hst: %08x %08x %08x %08x\n",
1910 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1911 i <= cStdMax ? "" : "*",
1912 Host.eax, Host.ebx, Host.ecx, Host.edx);
1913 }
1914
1915 /*
1916 * If verbose, decode it.
1917 */
1918 if (iVerbosity)
1919 {
1920 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1921 pHlp->pfnPrintf(pHlp,
1922 "Name: %.04s%.04s%.04s\n"
1923 "Supports: 0-%x\n",
1924 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1925 }
1926
1927 /*
1928 * Get Features.
1929 */
1930 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1931 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1932 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1933 if (cStdMax >= 1 && iVerbosity)
1934 {
1935 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1936 uint32_t uEAX = Guest.eax;
1937
1938 pHlp->pfnPrintf(pHlp,
1939 "Family: %d \tExtended: %d \tEffective: %d\n"
1940 "Model: %d \tExtended: %d \tEffective: %d\n"
1941 "Stepping: %d\n"
1942 "APIC ID: %#04x\n"
1943 "Logical CPUs: %d\n"
1944 "CLFLUSH Size: %d\n"
1945 "Brand ID: %#04x\n",
1946 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1947 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1948 ASMGetCpuStepping(uEAX),
1949 (Guest.ebx >> 24) & 0xff,
1950 (Guest.ebx >> 16) & 0xff,
1951 (Guest.ebx >> 8) & 0xff,
1952 (Guest.ebx >> 0) & 0xff);
1953 if (iVerbosity == 1)
1954 {
1955 uint32_t uEDX = Guest.edx;
1956 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1957 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1958 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1959 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1960 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1961 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1962 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1963 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1964 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1965 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1966 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1967 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1968 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1969 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1970 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1971 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1972 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1973 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1974 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1975 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1976 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1977 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1978 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1979 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1980 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1981 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1982 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1983 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1984 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1985 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1986 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1987 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1988 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1989 pHlp->pfnPrintf(pHlp, "\n");
1990
1991 uint32_t uECX = Guest.ecx;
1992 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1993 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1994 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1995 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1996 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1997 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1998 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1999 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
2000 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2001 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2002 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
2003 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2004 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2005 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
2006 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2007 for (unsigned iBit = 14; iBit < 32; iBit++)
2008 if (uECX & RT_BIT(iBit))
2009 pHlp->pfnPrintf(pHlp, " %d", iBit);
2010 pHlp->pfnPrintf(pHlp, "\n");
2011 }
2012 else
2013 {
2014 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2015
2016 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2017 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2018 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2019 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2020
2021 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2022 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2023 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2024 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2025 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2026 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2027 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2028 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2029 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2030 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2031 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2032 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2033 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2034 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2035 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
2036 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
2037 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
2038 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
2039 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
2040 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
2041 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
2042 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
2043 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
2044 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
2045 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
2046 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
2047 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
2048 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
2049 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
2050 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
2051 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
2052 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
2053 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
2054
2055 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
2056 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
2057 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
2058 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
2059 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
2060 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
2061 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
2062 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2063 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
2064 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
2065 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
2066 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
2067 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
2068 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
2069 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
2070 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
2071 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
2072 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
2073 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
2074 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
2075 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
2076 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
2077 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
2078 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
2079 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
2080 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
2081 }
2082 }
2083 if (cStdMax >= 2 && iVerbosity)
2084 {
2085 /** @todo */
2086 }
2087
2088 /*
2089 * Extended.
2090 * Implemented after AMD specs.
2091 */
2092 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
2093
2094 pHlp->pfnPrintf(pHlp,
2095 "\n"
2096 " RAW Extended CPUIDs\n"
2097 " Function eax ebx ecx edx\n");
2098 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
2099 {
2100 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
2101 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2102
2103 pHlp->pfnPrintf(pHlp,
2104 "Gst: %08x %08x %08x %08x %08x%s\n"
2105 "Hst: %08x %08x %08x %08x\n",
2106 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2107 i <= cExtMax ? "" : "*",
2108 Host.eax, Host.ebx, Host.ecx, Host.edx);
2109 }
2110
2111 /*
2112 * Understandable output
2113 */
2114 if (iVerbosity)
2115 {
2116 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
2117 pHlp->pfnPrintf(pHlp,
2118 "Ext Name: %.4s%.4s%.4s\n"
2119 "Ext Supports: 0x80000000-%#010x\n",
2120 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2121 }
2122
2123 if (iVerbosity && cExtMax >= 1)
2124 {
2125 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
2126 uint32_t uEAX = Guest.eax;
2127 pHlp->pfnPrintf(pHlp,
2128 "Family: %d \tExtended: %d \tEffective: %d\n"
2129 "Model: %d \tExtended: %d \tEffective: %d\n"
2130 "Stepping: %d\n"
2131 "Brand ID: %#05x\n",
2132 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2133 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2134 ASMGetCpuStepping(uEAX),
2135 Guest.ebx & 0xfff);
2136
2137 if (iVerbosity == 1)
2138 {
2139 uint32_t uEDX = Guest.edx;
2140 pHlp->pfnPrintf(pHlp, "Features EDX: ");
2141 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2142 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2143 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2144 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2145 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2146 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2147 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2148 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2149 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2150 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2151 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2152 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
2153 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2154 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2155 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2156 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2157 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2158 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2159 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
2160 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
2161 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
2162 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
2163 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
2164 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2165 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2166 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
2167 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
2168 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
2169 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
2170 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
2171 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
2172 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
2173 pHlp->pfnPrintf(pHlp, "\n");
2174
2175 uint32_t uECX = Guest.ecx;
2176 pHlp->pfnPrintf(pHlp, "Features ECX: ");
2177 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
2178 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
2179 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
2180 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
2181 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
2182 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
2183 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
2184 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
2185 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
2186 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
2187 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
2188 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
2189 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
2190 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
2191 for (unsigned iBit = 5; iBit < 32; iBit++)
2192 if (uECX & RT_BIT(iBit))
2193 pHlp->pfnPrintf(pHlp, " %d", iBit);
2194 pHlp->pfnPrintf(pHlp, "\n");
2195 }
2196 else
2197 {
2198 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2199
2200 uint32_t uEdxGst = Guest.edx;
2201 uint32_t uEdxHst = Host.edx;
2202 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2203 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2204 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2205 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2206 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2207 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2208 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2209 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2210 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2211 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2212 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2213 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2214 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2215 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2216 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2217 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2218 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2219 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2220 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2221 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2222 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2223 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2224 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2225 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2226 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2227 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2228 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2229 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2230 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2231 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2232 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2233 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2234 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2235
2236 uint32_t uEcxGst = Guest.ecx;
2237 uint32_t uEcxHst = Host.ecx;
2238 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2239 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2240 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2241 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2242 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2243 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2244 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2245 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2246 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2247 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2248 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2249 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2250 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2251 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2252 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2253 }
2254 }
2255
2256 if (iVerbosity && cExtMax >= 2)
2257 {
2258 char szString[4*4*3+1] = {0};
2259 uint32_t *pu32 = (uint32_t *)szString;
2260 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2261 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2262 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2263 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2264 if (cExtMax >= 3)
2265 {
2266 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2267 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2268 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2269 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2270 }
2271 if (cExtMax >= 4)
2272 {
2273 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2274 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2275 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2276 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2277 }
2278 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2279 }
2280
2281 if (iVerbosity && cExtMax >= 5)
2282 {
2283 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2284 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2285 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2286 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2287 char sz1[32];
2288 char sz2[32];
2289
2290 pHlp->pfnPrintf(pHlp,
2291 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2292 "TLB 2/4M Data: %s %3d entries\n",
2293 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2294 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2295 pHlp->pfnPrintf(pHlp,
2296 "TLB 4K Instr/Uni: %s %3d entries\n"
2297 "TLB 4K Data: %s %3d entries\n",
2298 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2299 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2300 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2301 "L1 Instr Cache Lines Per Tag: %d\n"
2302 "L1 Instr Cache Associativity: %s\n"
2303 "L1 Instr Cache Size: %d KB\n",
2304 (uEDX >> 0) & 0xff,
2305 (uEDX >> 8) & 0xff,
2306 getCacheAss((uEDX >> 16) & 0xff, sz1),
2307 (uEDX >> 24) & 0xff);
2308 pHlp->pfnPrintf(pHlp,
2309 "L1 Data Cache Line Size: %d bytes\n"
2310 "L1 Data Cache Lines Per Tag: %d\n"
2311 "L1 Data Cache Associativity: %s\n"
2312 "L1 Data Cache Size: %d KB\n",
2313 (uECX >> 0) & 0xff,
2314 (uECX >> 8) & 0xff,
2315 getCacheAss((uECX >> 16) & 0xff, sz1),
2316 (uECX >> 24) & 0xff);
2317 }
2318
2319 if (iVerbosity && cExtMax >= 6)
2320 {
2321 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2322 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2323 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2324
2325 pHlp->pfnPrintf(pHlp,
2326 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2327 "L2 TLB 2/4M Data: %s %4d entries\n",
2328 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2329 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2330 pHlp->pfnPrintf(pHlp,
2331 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2332 "L2 TLB 4K Data: %s %4d entries\n",
2333 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2334 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2335 pHlp->pfnPrintf(pHlp,
2336 "L2 Cache Line Size: %d bytes\n"
2337 "L2 Cache Lines Per Tag: %d\n"
2338 "L2 Cache Associativity: %s\n"
2339 "L2 Cache Size: %d KB\n",
2340 (uEDX >> 0) & 0xff,
2341 (uEDX >> 8) & 0xf,
2342 getL2CacheAss((uEDX >> 12) & 0xf),
2343 (uEDX >> 16) & 0xffff);
2344 }
2345
2346 if (iVerbosity && cExtMax >= 7)
2347 {
2348 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2349
2350 pHlp->pfnPrintf(pHlp, "APM Features: ");
2351 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2352 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2353 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2354 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2355 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2356 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2357 for (unsigned iBit = 6; iBit < 32; iBit++)
2358 if (uEDX & RT_BIT(iBit))
2359 pHlp->pfnPrintf(pHlp, " %d", iBit);
2360 pHlp->pfnPrintf(pHlp, "\n");
2361 }
2362
2363 if (iVerbosity && cExtMax >= 8)
2364 {
2365 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2366 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2367
2368 pHlp->pfnPrintf(pHlp,
2369 "Physical Address Width: %d bits\n"
2370 "Virtual Address Width: %d bits\n",
2371 (uEAX >> 0) & 0xff,
2372 (uEAX >> 8) & 0xff);
2373 pHlp->pfnPrintf(pHlp,
2374 "Physical Core Count: %d\n",
2375 (uECX >> 0) & 0xff);
2376 }
2377
2378
2379 /*
2380 * Centaur.
2381 */
2382 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2383
2384 pHlp->pfnPrintf(pHlp,
2385 "\n"
2386 " RAW Centaur CPUIDs\n"
2387 " Function eax ebx ecx edx\n");
2388 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2389 {
2390 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2391 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2392
2393 pHlp->pfnPrintf(pHlp,
2394 "Gst: %08x %08x %08x %08x %08x%s\n"
2395 "Hst: %08x %08x %08x %08x\n",
2396 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2397 i <= cCentaurMax ? "" : "*",
2398 Host.eax, Host.ebx, Host.ecx, Host.edx);
2399 }
2400
2401 /*
2402 * Understandable output
2403 */
2404 if (iVerbosity)
2405 {
2406 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2407 pHlp->pfnPrintf(pHlp,
2408 "Centaur Supports: 0xc0000000-%#010x\n",
2409 Guest.eax);
2410 }
2411
2412 if (iVerbosity && cCentaurMax >= 1)
2413 {
2414 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2415 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2416 uint32_t uEdxHst = Host.edx;
2417
2418 if (iVerbosity == 1)
2419 {
2420 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2421 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2422 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2423 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2424 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2425 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2426 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2427 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2428 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2429 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2430 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2431 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2432 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2433 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2434 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2435 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2436 for (unsigned iBit = 14; iBit < 32; iBit++)
2437 if (uEdxGst & RT_BIT(iBit))
2438 pHlp->pfnPrintf(pHlp, " %d", iBit);
2439 pHlp->pfnPrintf(pHlp, "\n");
2440 }
2441 else
2442 {
2443 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2444 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2445 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2446 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2447 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2448 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2449 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2450 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2451 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2452 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2453 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2454 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2455 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2456 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2457 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2458 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2459 for (unsigned iBit = 14; iBit < 32; iBit++)
2460 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2461 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2462 pHlp->pfnPrintf(pHlp, "\n");
2463 }
2464 }
2465}
2466
2467
2468/**
2469 * Structure used when disassembling and instructions in DBGF.
2470 * This is used so the reader function can get the stuff it needs.
2471 */
2472typedef struct CPUMDISASSTATE
2473{
2474 /** Pointer to the CPU structure. */
2475 PDISCPUSTATE pCpu;
2476 /** The VM handle. */
2477 PVM pVM;
2478 /** The VMCPU handle. */
2479 PVMCPU pVCpu;
2480 /** Pointer to the first byte in the segemnt. */
2481 RTGCUINTPTR GCPtrSegBase;
2482 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2483 RTGCUINTPTR GCPtrSegEnd;
2484 /** The size of the segment minus 1. */
2485 RTGCUINTPTR cbSegLimit;
2486 /** Pointer to the current page - R3 Ptr. */
2487 void const *pvPageR3;
2488 /** Pointer to the current page - GC Ptr. */
2489 RTGCPTR pvPageGC;
2490 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2491 PGMPAGEMAPLOCK PageMapLock;
2492 /** Whether the PageMapLock is valid or not. */
2493 bool fLocked;
2494 /** 64 bits mode or not. */
2495 bool f64Bits;
2496} CPUMDISASSTATE, *PCPUMDISASSTATE;
2497
2498
2499/**
2500 * Instruction reader.
2501 *
2502 * @returns VBox status code.
2503 * @param PtrSrc Address to read from.
2504 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2505 * @param pu8Dst Where to store the bytes.
2506 * @param cbRead Number of bytes to read.
2507 * @param uDisCpu Pointer to the disassembler cpu state.
2508 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2509 */
2510static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2511{
2512 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2513 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2514 Assert(cbRead > 0);
2515 for (;;)
2516 {
2517 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2518
2519 /* Need to update the page translation? */
2520 if ( !pState->pvPageR3
2521 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2522 {
2523 int rc = VINF_SUCCESS;
2524
2525 /* translate the address */
2526 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2527 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2528 && !HWACCMIsEnabled(pState->pVM))
2529 {
2530 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2531 if (!pState->pvPageR3)
2532 rc = VERR_INVALID_POINTER;
2533 }
2534 else
2535 {
2536 /* Release mapping lock previously acquired. */
2537 if (pState->fLocked)
2538 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2539 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2540 pState->fLocked = RT_SUCCESS_NP(rc);
2541 }
2542 if (RT_FAILURE(rc))
2543 {
2544 pState->pvPageR3 = NULL;
2545 return rc;
2546 }
2547 }
2548
2549 /* check the segemnt limit */
2550 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2551 return VERR_OUT_OF_SELECTOR_BOUNDS;
2552
2553 /* calc how much we can read */
2554 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2555 if (!pState->f64Bits)
2556 {
2557 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2558 if (cb > cbSeg && cbSeg)
2559 cb = cbSeg;
2560 }
2561 if (cb > cbRead)
2562 cb = cbRead;
2563
2564 /* read and advance */
2565 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2566 cbRead -= cb;
2567 if (!cbRead)
2568 return VINF_SUCCESS;
2569 pu8Dst += cb;
2570 PtrSrc += cb;
2571 }
2572}
2573
2574
2575/**
2576 * Disassemble an instruction and return the information in the provided structure.
2577 *
2578 * @returns VBox status code.
2579 * @param pVM VM Handle
2580 * @param pVCpu VMCPU Handle
2581 * @param pCtx CPU context
2582 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2583 * @param pCpu Disassembly state
2584 * @param pszPrefix String prefix for logging (debug only)
2585 *
2586 */
2587VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2588{
2589 CPUMDISASSTATE State;
2590 int rc;
2591
2592 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2593 State.pCpu = pCpu;
2594 State.pvPageGC = 0;
2595 State.pvPageR3 = NULL;
2596 State.pVM = pVM;
2597 State.pVCpu = pVCpu;
2598 State.fLocked = false;
2599 State.f64Bits = false;
2600
2601 /*
2602 * Get selector information.
2603 */
2604 if ( (pCtx->cr0 & X86_CR0_PE)
2605 && pCtx->eflags.Bits.u1VM == 0)
2606 {
2607 if (CPUMAreHiddenSelRegsValid(pVM))
2608 {
2609 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2610 State.GCPtrSegBase = pCtx->csHid.u64Base;
2611 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2612 State.cbSegLimit = pCtx->csHid.u32Limit;
2613 pCpu->mode = (State.f64Bits)
2614 ? CPUMODE_64BIT
2615 : pCtx->csHid.Attr.n.u1DefBig
2616 ? CPUMODE_32BIT
2617 : CPUMODE_16BIT;
2618 }
2619 else
2620 {
2621 DBGFSELINFO SelInfo;
2622
2623 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2624 if (RT_FAILURE(rc))
2625 {
2626 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2627 return rc;
2628 }
2629
2630 /*
2631 * Validate the selector.
2632 */
2633 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2634 if (RT_FAILURE(rc))
2635 {
2636 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2637 return rc;
2638 }
2639 State.GCPtrSegBase = SelInfo.GCPtrBase;
2640 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2641 State.cbSegLimit = SelInfo.cbLimit;
2642 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2643 }
2644 }
2645 else
2646 {
2647 /* real or V86 mode */
2648 pCpu->mode = CPUMODE_16BIT;
2649 State.GCPtrSegBase = pCtx->cs * 16;
2650 State.GCPtrSegEnd = 0xFFFFFFFF;
2651 State.cbSegLimit = 0xFFFFFFFF;
2652 }
2653
2654 /*
2655 * Disassemble the instruction.
2656 */
2657 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2658 pCpu->apvUserData[0] = &State;
2659
2660 uint32_t cbInstr;
2661#ifndef LOG_ENABLED
2662 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2663 if (RT_SUCCESS(rc))
2664 {
2665#else
2666 char szOutput[160];
2667 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2668 if (RT_SUCCESS(rc))
2669 {
2670 /* log it */
2671 if (pszPrefix)
2672 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2673 else
2674 Log(("%s", szOutput));
2675#endif
2676 rc = VINF_SUCCESS;
2677 }
2678 else
2679 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2680
2681 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2682 if (State.fLocked)
2683 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2684
2685 return rc;
2686}
2687
2688#ifdef DEBUG
2689
2690/**
2691 * Disassemble an instruction and dump it to the log
2692 *
2693 * @returns VBox status code.
2694 * @param pVM VM Handle
2695 * @param pVCpu VMCPU Handle
2696 * @param pCtx CPU context
2697 * @param pc GC instruction pointer
2698 * @param pszPrefix String prefix for logging
2699 *
2700 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2701 */
2702VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2703{
2704 DISCPUSTATE Cpu;
2705 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2706}
2707
2708
2709/**
2710 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2711 *
2712 * @internal
2713 */
2714VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2715{
2716 /* @todo SMP support!! */
2717 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2718}
2719
2720#endif /* DEBUG */
2721
2722/**
2723 * API for controlling a few of the CPU features found in CR4.
2724 *
2725 * Currently only X86_CR4_TSD is accepted as input.
2726 *
2727 * @returns VBox status code.
2728 *
2729 * @param pVM The VM handle.
2730 * @param fOr The CR4 OR mask.
2731 * @param fAnd The CR4 AND mask.
2732 */
2733VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2734{
2735 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2736 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2737
2738 pVM->cpum.s.CR4.OrMask &= fAnd;
2739 pVM->cpum.s.CR4.OrMask |= fOr;
2740
2741 return VINF_SUCCESS;
2742}
2743
2744
2745/**
2746 * Gets a pointer to the array of standard CPUID leafs.
2747 *
2748 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2749 *
2750 * @returns Pointer to the standard CPUID leafs (read-only).
2751 * @param pVM The VM handle.
2752 * @remark Intended for PATM.
2753 */
2754VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2755{
2756 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2757}
2758
2759
2760/**
2761 * Gets a pointer to the array of extended CPUID leafs.
2762 *
2763 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2764 *
2765 * @returns Pointer to the extended CPUID leafs (read-only).
2766 * @param pVM The VM handle.
2767 * @remark Intended for PATM.
2768 */
2769VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2770{
2771 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2772}
2773
2774
2775/**
2776 * Gets a pointer to the array of centaur CPUID leafs.
2777 *
2778 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2779 *
2780 * @returns Pointer to the centaur CPUID leafs (read-only).
2781 * @param pVM The VM handle.
2782 * @remark Intended for PATM.
2783 */
2784VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2785{
2786 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2787}
2788
2789
2790/**
2791 * Gets a pointer to the default CPUID leaf.
2792 *
2793 * @returns Pointer to the default CPUID leaf (read-only).
2794 * @param pVM The VM handle.
2795 * @remark Intended for PATM.
2796 */
2797VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2798{
2799 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2800}
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