VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 22042

Last change on this file since 22042 was 22042, checked in by vboxsync, 16 years ago

VMM: refactor CPUID limitation, passed OSType

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1/* $Id: CPUM.cpp 22042 2009-08-06 16:58:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319 | X86_CPUID_FEATURE_ECX_SSE3
320 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
321 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
322 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
323 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
324 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
325 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
326 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
327 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
328 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
329 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
330 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
331 /* ECX Bit 21 - x2APIC support - not yet. */
332 // | X86_CPUID_FEATURE_ECX_X2APIC
333 /* ECX Bit 23 - POPCOUNT instruction. */
334 //| X86_CPUID_FEATURE_ECX_POPCOUNT
335 | 0;
336
337 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
338 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
339 | X86_CPUID_AMD_FEATURE_EDX_VME
340 | X86_CPUID_AMD_FEATURE_EDX_DE
341 | X86_CPUID_AMD_FEATURE_EDX_PSE
342 | X86_CPUID_AMD_FEATURE_EDX_TSC
343 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
344 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
345 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
346 | X86_CPUID_AMD_FEATURE_EDX_CX8
347 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
348 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
349 //| X86_CPUID_AMD_FEATURE_EDX_SEP
350 | X86_CPUID_AMD_FEATURE_EDX_MTRR
351 | X86_CPUID_AMD_FEATURE_EDX_PGE
352 | X86_CPUID_AMD_FEATURE_EDX_MCA
353 | X86_CPUID_AMD_FEATURE_EDX_CMOV
354 | X86_CPUID_AMD_FEATURE_EDX_PAT
355 | X86_CPUID_AMD_FEATURE_EDX_PSE36
356 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
357 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
358 | X86_CPUID_AMD_FEATURE_EDX_MMX
359 | X86_CPUID_AMD_FEATURE_EDX_FXSR
360 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
361 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
362 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
363 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
364 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
365 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
366 | 0;
367 pCPUM->aGuestCpuIdExt[1].ecx &= 0
368 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
369 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
370 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
371 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
372 /** Note: This could prevent migration from AMD to Intel CPUs! */
373 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
374 //| X86_CPUID_AMD_FEATURE_ECX_ABM
375 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
376 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
377 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
378 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
379 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
380 //| X86_CPUID_AMD_FEATURE_ECX_WDT
381 | 0;
382
383 /*
384 * Hide HTT, multicode, SMP, whatever.
385 * (APIC-ID := 0 and #LogCpus := 0)
386 */
387 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
388#ifdef VBOX_WITH_MULTI_CORE
389 if (pVM->cCPUs > 1)
390 {
391 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
392 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCPUs << 16);
393 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
394 }
395#endif
396
397 /* Cpuid 2:
398 * Intel: Cache and TLB information
399 * AMD: Reserved
400 * Safe to expose
401 */
402
403 /* Cpuid 3:
404 * Intel: EAX, EBX - reserved
405 * ECX, EDX - Processor Serial Number if available, otherwise reserved
406 * AMD: Reserved
407 * Safe to expose
408 */
409 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
410 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
411
412 /* Cpuid 4:
413 * Intel: Deterministic Cache Parameters Leaf
414 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
415 * AMD: Reserved
416 * Safe to expose, except for EAX:
417 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
418 * Bits 31-26: Maximum number of processor cores in this physical package**
419 * @Note These SMP values are constant regardless of ECX
420 */
421 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
422 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
423#ifdef VBOX_WITH_MULTI_CORE
424 if ( pVM->cCPUs > 1
425 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
426 {
427 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
428 /* One logical processor with possibly multiple cores. */
429 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
430 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
431 }
432#endif
433
434 /* Cpuid 5: Monitor/mwait Leaf
435 * Intel: ECX, EDX - reserved
436 * EAX, EBX - Smallest and largest monitor line size
437 * AMD: EDX - reserved
438 * EAX, EBX - Smallest and largest monitor line size
439 * ECX - extensions (ignored for now)
440 * Safe to expose
441 */
442 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
443 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
444
445 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
446
447 /*
448 * Determine the default.
449 *
450 * Intel returns values of the highest standard function, while AMD
451 * returns zeros. VIA on the other hand seems to returning nothing or
452 * perhaps some random garbage, we don't try to duplicate this behavior.
453 */
454 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
455 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
456 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
457
458 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
459 * Safe to pass on to the guest.
460 *
461 * Intel: 0x800000005 reserved
462 * 0x800000006 L2 cache information
463 * AMD: 0x800000005 L1 cache information
464 * 0x800000006 L2/L3 cache information
465 */
466
467 /* Cpuid 0x800000007:
468 * AMD: EAX, EBX, ECX - reserved
469 * EDX: Advanced Power Management Information
470 * Intel: Reserved
471 */
472 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
473 {
474 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
475
476 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
477
478 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
479 {
480 /* Only expose the TSC invariant capability bit to the guest. */
481 pCPUM->aGuestCpuIdExt[7].edx &= 0
482 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
483 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
484 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
485 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
486 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
487 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
488 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
489 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
490#if 1
491 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
492 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
493 */
494#else
495 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
496#endif
497 | 0;
498 }
499 else
500 pCPUM->aGuestCpuIdExt[7].edx = 0;
501 }
502
503 /* Cpuid 0x800000008:
504 * AMD: EBX, EDX - reserved
505 * EAX: Virtual/Physical address Size
506 * ECX: Number of cores + APICIdCoreIdSize
507 * Intel: EAX: Virtual/Physical address Size
508 * EBX, ECX, EDX - reserved
509 */
510 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
511 {
512 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
513 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
514 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
515 * NC (0-7) Number of cores; 0 equals 1 core */
516 pCPUM->aGuestCpuIdExt[8].ecx = 0;
517#ifdef VBOX_WITH_MULTI_CORE
518 if ( pVM->cCPUs > 1
519 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
520 {
521 /* Legacy method to determine the number of cores. */
522 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
523 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
524
525 }
526#endif
527 }
528
529 /*
530 * Limit it the number of entries and fill the remaining with the defaults.
531 *
532 * The limits are masking off stuff about power saving and similar, this
533 * is perhaps a bit crudely done as there is probably some relatively harmless
534 * info too in these leaves (like words about having a constant TSC).
535 */
536 {
537 bool fNt4LeafLimit;
538 PCFGMNODE pNode = CFGMR3GetRoot(pVM);
539 int rc = CFGMR3QueryBoolDef(pNode, "NT4LeafLimit", &fNt4LeafLimit, false);
540 if (RT_SUCCESS(rc) && fNt4LeafLimit)
541 pCPUM->aGuestCpuIdStd[0].eax = 2;
542 }
543 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
544 pCPUM->aGuestCpuIdStd[0].eax = 5;
545
546 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
547 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
548
549 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
550 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
551 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
552 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
553 : 0;
554 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
555 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
556
557 /*
558 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
559 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
560 * We currently don't support more than 1 processor.
561 */
562 if (pVM->cCPUs == 1)
563 pCPUM->aGuestCpuIdStd[4].eax = 0;
564
565 /*
566 * Centaur stuff (VIA).
567 *
568 * The important part here (we think) is to make sure the 0xc0000000
569 * function returns 0xc0000001. As for the features, we don't currently
570 * let on about any of those... 0xc0000002 seems to be some
571 * temperature/hz/++ stuff, include it as well (static).
572 */
573 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
574 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
575 {
576 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
577 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
578 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
579 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
580 i++)
581 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
582 }
583 else
584 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
585 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
586
587
588 /*
589 * Load CPUID overrides from configuration.
590 */
591 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
592 * Overloads the CPUID leaf values. */
593 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
594 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
595 for (i=0;; )
596 {
597 while (cElements-- > 0)
598 {
599 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
600 if (pNode)
601 {
602 uint32_t u32;
603 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
604 if (RT_SUCCESS(rc))
605 pCpuId->eax = u32;
606 else
607 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
608
609 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
610 if (RT_SUCCESS(rc))
611 pCpuId->ebx = u32;
612 else
613 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
614
615 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
616 if (RT_SUCCESS(rc))
617 pCpuId->ecx = u32;
618 else
619 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
620
621 rc = CFGMR3QueryU32(pNode, "edx", &u32);
622 if (RT_SUCCESS(rc))
623 pCpuId->edx = u32;
624 else
625 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
626 }
627 pCpuId++;
628 i++;
629 }
630
631 /* next */
632 if ((i & UINT32_C(0xc0000000)) == 0)
633 {
634 pCpuId = &pCPUM->aGuestCpuIdExt[0];
635 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
636 i = UINT32_C(0x80000000);
637 }
638 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
639 {
640 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
641 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
642 i = UINT32_C(0xc0000000);
643 }
644 else
645 break;
646 }
647
648 /* Check if PAE was explicitely enabled by the user. */
649 bool fEnable = false;
650 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
651 if (RT_SUCCESS(rc) && fEnable)
652 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
653
654 /*
655 * Log the cpuid and we're good.
656 */
657 RTCPUSET OnlineSet;
658 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
659 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
660 LogRel(("************************* CPUID dump ************************\n"));
661 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
662 LogRel(("\n"));
663 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
664 LogRel(("******************** End of CPUID dump **********************\n"));
665 return VINF_SUCCESS;
666}
667
668
669
670
671/**
672 * Applies relocations to data and code managed by this
673 * component. This function will be called at init and
674 * whenever the VMM need to relocate it self inside the GC.
675 *
676 * The CPUM will update the addresses used by the switcher.
677 *
678 * @param pVM The VM.
679 */
680VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
681{
682 LogFlow(("CPUMR3Relocate\n"));
683 for (unsigned i=0;i<pVM->cCPUs;i++)
684 {
685 PVMCPU pVCpu = &pVM->aCpus[i];
686 /*
687 * Switcher pointers.
688 */
689 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
690 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
691 }
692}
693
694
695/**
696 * Terminates the CPUM.
697 *
698 * Termination means cleaning up and freeing all resources,
699 * the VM it self is at this point powered off or suspended.
700 *
701 * @returns VBox status code.
702 * @param pVM The VM to operate on.
703 */
704VMMR3DECL(int) CPUMR3Term(PVM pVM)
705{
706 CPUMR3TermCPU(pVM);
707 return 0;
708}
709
710
711/**
712 * Terminates the per-VCPU CPUM.
713 *
714 * Termination means cleaning up and freeing all resources,
715 * the VM it self is at this point powered off or suspended.
716 *
717 * @returns VBox status code.
718 * @param pVM The VM to operate on.
719 */
720VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
721{
722#ifdef VBOX_WITH_CRASHDUMP_MAGIC
723 for (unsigned i=0;i<pVM->cCPUs;i++)
724 {
725 PVMCPU pVCpu = &pVM->aCpus[i];
726 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
727
728 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
729 pVCpu->cpum.s.uMagic = 0;
730 pCtx->dr[5] = 0;
731 }
732#endif
733 return 0;
734}
735
736VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
737{
738 /* @todo anything different for VCPU > 0? */
739 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
740
741 /*
742 * Initialize everything to ZERO first.
743 */
744 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
745 memset(pCtx, 0, sizeof(*pCtx));
746 pVCpu->cpum.s.fUseFlags = fUseFlags;
747
748 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
749 pCtx->eip = 0x0000fff0;
750 pCtx->edx = 0x00000600; /* P6 processor */
751 pCtx->eflags.Bits.u1Reserved0 = 1;
752
753 pCtx->cs = 0xf000;
754 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
755 pCtx->csHid.u32Limit = 0x0000ffff;
756 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
757 pCtx->csHid.Attr.n.u1Present = 1;
758 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
759
760 pCtx->dsHid.u32Limit = 0x0000ffff;
761 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
762 pCtx->dsHid.Attr.n.u1Present = 1;
763 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
764
765 pCtx->esHid.u32Limit = 0x0000ffff;
766 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
767 pCtx->esHid.Attr.n.u1Present = 1;
768 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
769
770 pCtx->fsHid.u32Limit = 0x0000ffff;
771 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
772 pCtx->fsHid.Attr.n.u1Present = 1;
773 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
774
775 pCtx->gsHid.u32Limit = 0x0000ffff;
776 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
777 pCtx->gsHid.Attr.n.u1Present = 1;
778 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
779
780 pCtx->ssHid.u32Limit = 0x0000ffff;
781 pCtx->ssHid.Attr.n.u1Present = 1;
782 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
783 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
784
785 pCtx->idtr.cbIdt = 0xffff;
786 pCtx->gdtr.cbGdt = 0xffff;
787
788 pCtx->ldtrHid.u32Limit = 0xffff;
789 pCtx->ldtrHid.Attr.n.u1Present = 1;
790 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
791
792 pCtx->trHid.u32Limit = 0xffff;
793 pCtx->trHid.Attr.n.u1Present = 1;
794 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
795
796 pCtx->dr[6] = X86_DR6_INIT_VAL;
797 pCtx->dr[7] = X86_DR7_INIT_VAL;
798
799 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
800 pCtx->fpu.FCW = 0x37f;
801
802 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
803 pCtx->fpu.MXCSR = 0x1F80;
804
805 /* Init PAT MSR */
806 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
807
808 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
809 * The Intel docs don't mention it.
810 */
811 pCtx->msrEFER = 0;
812}
813
814/**
815 * Resets the CPU.
816 *
817 * @returns VINF_SUCCESS.
818 * @param pVM The VM handle.
819 */
820VMMR3DECL(void) CPUMR3Reset(PVM pVM)
821{
822 for (unsigned i=0;i<pVM->cCPUs;i++)
823 {
824 CPUMR3ResetCpu(&pVM->aCpus[i]);
825
826#ifdef VBOX_WITH_CRASHDUMP_MAGIC
827 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
828
829 /* Magic marker for searching in crash dumps. */
830 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
831 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
832 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
833#endif
834 }
835}
836
837
838/**
839 * Execute state save operation.
840 *
841 * @returns VBox status code.
842 * @param pVM VM Handle.
843 * @param pSSM SSM operation handle.
844 */
845static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
846{
847 /*
848 * Save.
849 */
850 for (unsigned i=0;i<pVM->cCPUs;i++)
851 {
852 PVMCPU pVCpu = &pVM->aCpus[i];
853
854 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
855 }
856
857 SSMR3PutU32(pSSM, pVM->cCPUs);
858 for (unsigned i=0;i<pVM->cCPUs;i++)
859 {
860 PVMCPU pVCpu = &pVM->aCpus[i];
861
862 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
863 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
864 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
865 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
866 }
867
868 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
869 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
870
871 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
872 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
873
874 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
875 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
876
877 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
878
879 /* Add the cpuid for checking that the cpu is unchanged. */
880 uint32_t au32CpuId[8] = {0};
881 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
882 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
883 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
884}
885
886
887/**
888 * Load a version 1.6 CPUMCTX structure.
889 *
890 * @returns VBox status code.
891 * @param pVM VM Handle.
892 * @param pCpumctx16 Version 1.6 CPUMCTX
893 */
894static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
895{
896#define CPUMCTX16_LOADREG(RegName) \
897 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
898
899#define CPUMCTX16_LOADDRXREG(RegName) \
900 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
901
902#define CPUMCTX16_LOADHIDREG(RegName) \
903 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
904 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
905 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
906
907#define CPUMCTX16_LOADSEGREG(RegName) \
908 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
909 CPUMCTX16_LOADHIDREG(RegName);
910
911 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
912
913 CPUMCTX16_LOADREG(rax);
914 CPUMCTX16_LOADREG(rbx);
915 CPUMCTX16_LOADREG(rcx);
916 CPUMCTX16_LOADREG(rdx);
917 CPUMCTX16_LOADREG(rdi);
918 CPUMCTX16_LOADREG(rsi);
919 CPUMCTX16_LOADREG(rbp);
920 CPUMCTX16_LOADREG(esp);
921 CPUMCTX16_LOADREG(rip);
922 CPUMCTX16_LOADREG(rflags);
923
924 CPUMCTX16_LOADSEGREG(cs);
925 CPUMCTX16_LOADSEGREG(ds);
926 CPUMCTX16_LOADSEGREG(es);
927 CPUMCTX16_LOADSEGREG(fs);
928 CPUMCTX16_LOADSEGREG(gs);
929 CPUMCTX16_LOADSEGREG(ss);
930
931 CPUMCTX16_LOADREG(r8);
932 CPUMCTX16_LOADREG(r9);
933 CPUMCTX16_LOADREG(r10);
934 CPUMCTX16_LOADREG(r11);
935 CPUMCTX16_LOADREG(r12);
936 CPUMCTX16_LOADREG(r13);
937 CPUMCTX16_LOADREG(r14);
938 CPUMCTX16_LOADREG(r15);
939
940 CPUMCTX16_LOADREG(cr0);
941 CPUMCTX16_LOADREG(cr2);
942 CPUMCTX16_LOADREG(cr3);
943 CPUMCTX16_LOADREG(cr4);
944
945 CPUMCTX16_LOADDRXREG(0);
946 CPUMCTX16_LOADDRXREG(1);
947 CPUMCTX16_LOADDRXREG(2);
948 CPUMCTX16_LOADDRXREG(3);
949 CPUMCTX16_LOADDRXREG(4);
950 CPUMCTX16_LOADDRXREG(5);
951 CPUMCTX16_LOADDRXREG(6);
952 CPUMCTX16_LOADDRXREG(7);
953
954 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
955 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
956 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
957 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
958
959 CPUMCTX16_LOADREG(ldtr);
960 CPUMCTX16_LOADREG(tr);
961
962 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
963
964 CPUMCTX16_LOADREG(msrEFER);
965 CPUMCTX16_LOADREG(msrSTAR);
966 CPUMCTX16_LOADREG(msrPAT);
967 CPUMCTX16_LOADREG(msrLSTAR);
968 CPUMCTX16_LOADREG(msrCSTAR);
969 CPUMCTX16_LOADREG(msrSFMASK);
970 CPUMCTX16_LOADREG(msrKERNELGSBASE);
971
972 CPUMCTX16_LOADHIDREG(ldtr);
973 CPUMCTX16_LOADHIDREG(tr);
974
975#undef CPUMCTX16_LOADSEGREG
976#undef CPUMCTX16_LOADHIDREG
977#undef CPUMCTX16_LOADDRXREG
978#undef CPUMCTX16_LOADREG
979}
980
981
982/**
983 * Execute state load operation.
984 *
985 * @returns VBox status code.
986 * @param pVM VM Handle.
987 * @param pSSM SSM operation handle.
988 * @param u32Version Data layout version.
989 */
990static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
991{
992 /*
993 * Validate version.
994 */
995 if ( u32Version != CPUM_SAVED_STATE_VERSION
996 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
997 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
998 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
999 {
1000 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
1001 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1002 }
1003
1004 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1005 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1006 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1007 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
1008 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1009
1010 /*
1011 * Restore.
1012 */
1013 for (unsigned i=0;i<pVM->cCPUs;i++)
1014 {
1015 PVMCPU pVCpu = &pVM->aCpus[i];
1016 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1017 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1018
1019 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1020 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1021 pVCpu->cpum.s.Hyper.esp = uESP;
1022 }
1023
1024 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1025 {
1026 CPUMCTX_VER1_6 cpumctx16;
1027 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1028 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1029
1030 /* Save the old cpumctx state into the new one. */
1031 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1032
1033 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1034 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1035 }
1036 else
1037 {
1038 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1039 {
1040 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1041 AssertRCReturn(rc, rc);
1042 }
1043
1044 if ( !pVM->cCPUs
1045 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1046 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1047 && pVM->cCPUs != 1))
1048 {
1049 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1050 return VERR_SSM_UNEXPECTED_DATA;
1051 }
1052
1053 for (unsigned i=0;i<pVM->cCPUs;i++)
1054 {
1055 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1056 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1057 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1058 if (u32Version == CPUM_SAVED_STATE_VERSION)
1059 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1060 }
1061 }
1062
1063
1064 uint32_t cElements;
1065 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1066 /* Support old saved states with a smaller standard cpuid array. */
1067 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1068 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1069 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1070
1071 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1072 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1073 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1074 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1075
1076 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1077 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1078 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1079 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1080
1081 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1082
1083 /*
1084 * Check that the basic cpuid id information is unchanged.
1085 * @todo we should check the 64 bits capabilities too!
1086 */
1087 uint32_t au32CpuId[8] = {0};
1088 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1089 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1090 uint32_t au32CpuIdSaved[8];
1091 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1092 if (RT_SUCCESS(rc))
1093 {
1094 /* Ignore CPU stepping. */
1095 au32CpuId[4] &= 0xfffffff0;
1096 au32CpuIdSaved[4] &= 0xfffffff0;
1097
1098 /* Ignore APIC ID (AMD specs). */
1099 au32CpuId[5] &= ~0xff000000;
1100 au32CpuIdSaved[5] &= ~0xff000000;
1101
1102 /* Ignore the number of Logical CPUs (AMD specs). */
1103 au32CpuId[5] &= ~0x00ff0000;
1104 au32CpuIdSaved[5] &= ~0x00ff0000;
1105
1106 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1107 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1108 | X86_CPUID_FEATURE_ECX_VMX
1109 | X86_CPUID_FEATURE_ECX_SMX
1110 | X86_CPUID_FEATURE_ECX_EST
1111 | X86_CPUID_FEATURE_ECX_TM2
1112 | X86_CPUID_FEATURE_ECX_CNTXID
1113 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1114 | X86_CPUID_FEATURE_ECX_PDCM
1115 | X86_CPUID_FEATURE_ECX_DCA
1116 | X86_CPUID_FEATURE_ECX_X2APIC
1117 );
1118 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1119 | X86_CPUID_FEATURE_ECX_VMX
1120 | X86_CPUID_FEATURE_ECX_SMX
1121 | X86_CPUID_FEATURE_ECX_EST
1122 | X86_CPUID_FEATURE_ECX_TM2
1123 | X86_CPUID_FEATURE_ECX_CNTXID
1124 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1125 | X86_CPUID_FEATURE_ECX_PDCM
1126 | X86_CPUID_FEATURE_ECX_DCA
1127 | X86_CPUID_FEATURE_ECX_X2APIC
1128 );
1129
1130 /* Make sure we don't forget to update the masks when enabling
1131 * features in the future.
1132 */
1133 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
1134 ( X86_CPUID_FEATURE_ECX_DTES64
1135 | X86_CPUID_FEATURE_ECX_VMX
1136 | X86_CPUID_FEATURE_ECX_SMX
1137 | X86_CPUID_FEATURE_ECX_EST
1138 | X86_CPUID_FEATURE_ECX_TM2
1139 | X86_CPUID_FEATURE_ECX_CNTXID
1140 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1141 | X86_CPUID_FEATURE_ECX_PDCM
1142 | X86_CPUID_FEATURE_ECX_DCA
1143 | X86_CPUID_FEATURE_ECX_X2APIC
1144 )));
1145 /* do the compare */
1146 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1147 {
1148 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1149 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1150 "Saved=%.*Rhxs\n"
1151 "Real =%.*Rhxs\n",
1152 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1153 sizeof(au32CpuId), au32CpuId));
1154 else
1155 {
1156 LogRel(("cpumR3Load: CpuId mismatch!\n"
1157 "Saved=%.*Rhxs\n"
1158 "Real =%.*Rhxs\n",
1159 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1160 sizeof(au32CpuId), au32CpuId));
1161 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1162 }
1163 }
1164 }
1165
1166 return rc;
1167}
1168
1169
1170/**
1171 * Formats the EFLAGS value into mnemonics.
1172 *
1173 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1174 * @param efl The EFLAGS value.
1175 */
1176static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1177{
1178 /*
1179 * Format the flags.
1180 */
1181 static const struct
1182 {
1183 const char *pszSet; const char *pszClear; uint32_t fFlag;
1184 } s_aFlags[] =
1185 {
1186 { "vip",NULL, X86_EFL_VIP },
1187 { "vif",NULL, X86_EFL_VIF },
1188 { "ac", NULL, X86_EFL_AC },
1189 { "vm", NULL, X86_EFL_VM },
1190 { "rf", NULL, X86_EFL_RF },
1191 { "nt", NULL, X86_EFL_NT },
1192 { "ov", "nv", X86_EFL_OF },
1193 { "dn", "up", X86_EFL_DF },
1194 { "ei", "di", X86_EFL_IF },
1195 { "tf", NULL, X86_EFL_TF },
1196 { "nt", "pl", X86_EFL_SF },
1197 { "nz", "zr", X86_EFL_ZF },
1198 { "ac", "na", X86_EFL_AF },
1199 { "po", "pe", X86_EFL_PF },
1200 { "cy", "nc", X86_EFL_CF },
1201 };
1202 char *psz = pszEFlags;
1203 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1204 {
1205 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1206 if (pszAdd)
1207 {
1208 strcpy(psz, pszAdd);
1209 psz += strlen(pszAdd);
1210 *psz++ = ' ';
1211 }
1212 }
1213 psz[-1] = '\0';
1214}
1215
1216
1217/**
1218 * Formats a full register dump.
1219 *
1220 * @param pVM VM Handle.
1221 * @param pCtx The context to format.
1222 * @param pCtxCore The context core to format.
1223 * @param pHlp Output functions.
1224 * @param enmType The dump type.
1225 * @param pszPrefix Register name prefix.
1226 */
1227static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1228{
1229 /*
1230 * Format the EFLAGS.
1231 */
1232 uint32_t efl = pCtxCore->eflags.u32;
1233 char szEFlags[80];
1234 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1235
1236 /*
1237 * Format the registers.
1238 */
1239 switch (enmType)
1240 {
1241 case CPUMDUMPTYPE_TERSE:
1242 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1243 pHlp->pfnPrintf(pHlp,
1244 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1245 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1246 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1247 "%sr14=%016RX64 %sr15=%016RX64\n"
1248 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1249 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1250 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1251 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1252 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1253 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1254 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1255 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1256 else
1257 pHlp->pfnPrintf(pHlp,
1258 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1259 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1260 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1261 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1262 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1263 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1264 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1265 break;
1266
1267 case CPUMDUMPTYPE_DEFAULT:
1268 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1269 pHlp->pfnPrintf(pHlp,
1270 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1271 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1272 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1273 "%sr14=%016RX64 %sr15=%016RX64\n"
1274 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1275 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1276 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1277 ,
1278 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1279 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1280 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1281 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1282 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1283 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1284 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1285 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1286 else
1287 pHlp->pfnPrintf(pHlp,
1288 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1289 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1290 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1291 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1292 ,
1293 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1294 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1295 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1296 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1297 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1298 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1299 break;
1300
1301 case CPUMDUMPTYPE_VERBOSE:
1302 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1303 pHlp->pfnPrintf(pHlp,
1304 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1305 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1306 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1307 "%sr14=%016RX64 %sr15=%016RX64\n"
1308 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1309 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1310 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1311 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1312 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1313 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1314 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1315 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1316 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1317 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1318 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1319 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1320 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1321 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1322 ,
1323 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1324 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1325 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1326 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1327 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1328 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1329 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1330 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1331 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1332 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1333 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1334 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1335 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1336 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1337 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1338 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1339 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1340 else
1341 pHlp->pfnPrintf(pHlp,
1342 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1343 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1344 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1345 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1346 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1347 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1348 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1349 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1350 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1351 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1352 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1353 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1354 ,
1355 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1356 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1357 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1358 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1359 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1360 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1361 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1362 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1363 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1364 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1365 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1366 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1367
1368 pHlp->pfnPrintf(pHlp,
1369 "FPU:\n"
1370 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1371 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1372 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1373 ,
1374 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1375 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1376 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1377 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1378
1379 pHlp->pfnPrintf(pHlp,
1380 "MSR:\n"
1381 "%sEFER =%016RX64\n"
1382 "%sPAT =%016RX64\n"
1383 "%sSTAR =%016RX64\n"
1384 "%sCSTAR =%016RX64\n"
1385 "%sLSTAR =%016RX64\n"
1386 "%sSFMASK =%016RX64\n"
1387 "%sKERNELGSBASE =%016RX64\n",
1388 pszPrefix, pCtx->msrEFER,
1389 pszPrefix, pCtx->msrPAT,
1390 pszPrefix, pCtx->msrSTAR,
1391 pszPrefix, pCtx->msrCSTAR,
1392 pszPrefix, pCtx->msrLSTAR,
1393 pszPrefix, pCtx->msrSFMASK,
1394 pszPrefix, pCtx->msrKERNELGSBASE);
1395 break;
1396 }
1397}
1398
1399
1400/**
1401 * Display all cpu states and any other cpum info.
1402 *
1403 * @param pVM VM Handle.
1404 * @param pHlp The info helper functions.
1405 * @param pszArgs Arguments, ignored.
1406 */
1407static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1408{
1409 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1410 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1411 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1412 cpumR3InfoHost(pVM, pHlp, pszArgs);
1413}
1414
1415
1416/**
1417 * Parses the info argument.
1418 *
1419 * The argument starts with 'verbose', 'terse' or 'default' and then
1420 * continues with the comment string.
1421 *
1422 * @param pszArgs The pointer to the argument string.
1423 * @param penmType Where to store the dump type request.
1424 * @param ppszComment Where to store the pointer to the comment string.
1425 */
1426static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1427{
1428 if (!pszArgs)
1429 {
1430 *penmType = CPUMDUMPTYPE_DEFAULT;
1431 *ppszComment = "";
1432 }
1433 else
1434 {
1435 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1436 {
1437 pszArgs += 5;
1438 *penmType = CPUMDUMPTYPE_VERBOSE;
1439 }
1440 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1441 {
1442 pszArgs += 5;
1443 *penmType = CPUMDUMPTYPE_TERSE;
1444 }
1445 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1446 {
1447 pszArgs += 7;
1448 *penmType = CPUMDUMPTYPE_DEFAULT;
1449 }
1450 else
1451 *penmType = CPUMDUMPTYPE_DEFAULT;
1452 *ppszComment = RTStrStripL(pszArgs);
1453 }
1454}
1455
1456
1457/**
1458 * Display the guest cpu state.
1459 *
1460 * @param pVM VM Handle.
1461 * @param pHlp The info helper functions.
1462 * @param pszArgs Arguments, ignored.
1463 */
1464static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1465{
1466 CPUMDUMPTYPE enmType;
1467 const char *pszComment;
1468 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1469
1470 /* @todo SMP support! */
1471 PVMCPU pVCpu = VMMGetCpu(pVM);
1472 if (!pVCpu)
1473 pVCpu = &pVM->aCpus[0];
1474
1475 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1476
1477 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1478 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1479}
1480
1481
1482/**
1483 * Display the current guest instruction
1484 *
1485 * @param pVM VM Handle.
1486 * @param pHlp The info helper functions.
1487 * @param pszArgs Arguments, ignored.
1488 */
1489static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1490{
1491 char szInstruction[256];
1492 /* @todo SMP support! */
1493 PVMCPU pVCpu = VMMGetCpu(pVM);
1494 if (!pVCpu)
1495 pVCpu = &pVM->aCpus[0];
1496
1497 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1498 if (RT_SUCCESS(rc))
1499 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1500}
1501
1502
1503/**
1504 * Display the hypervisor cpu state.
1505 *
1506 * @param pVM VM Handle.
1507 * @param pHlp The info helper functions.
1508 * @param pszArgs Arguments, ignored.
1509 */
1510static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1511{
1512 CPUMDUMPTYPE enmType;
1513 const char *pszComment;
1514 /* @todo SMP */
1515 PVMCPU pVCpu = &pVM->aCpus[0];
1516
1517 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1518 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1519 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1520 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1521}
1522
1523
1524/**
1525 * Display the host cpu state.
1526 *
1527 * @param pVM VM Handle.
1528 * @param pHlp The info helper functions.
1529 * @param pszArgs Arguments, ignored.
1530 */
1531static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1532{
1533 CPUMDUMPTYPE enmType;
1534 const char *pszComment;
1535 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1536 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1537
1538 /*
1539 * Format the EFLAGS.
1540 */
1541 /* @todo SMP */
1542 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1543#if HC_ARCH_BITS == 32
1544 uint32_t efl = pCtx->eflags.u32;
1545#else
1546 uint64_t efl = pCtx->rflags;
1547#endif
1548 char szEFlags[80];
1549 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1550
1551 /*
1552 * Format the registers.
1553 */
1554#if HC_ARCH_BITS == 32
1555# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1556 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1557# endif
1558 {
1559 pHlp->pfnPrintf(pHlp,
1560 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1561 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1562 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1563 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1564 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1565 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1566 ,
1567 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1568 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1569 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1570 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1571 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1572 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1573 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1574 }
1575# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1576 else
1577# endif
1578#endif
1579#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1580 {
1581 pHlp->pfnPrintf(pHlp,
1582 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1583 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1584 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1585 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1586 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1587 "r14=%016RX64 r15=%016RX64\n"
1588 "iopl=%d %31s\n"
1589 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1590 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1591 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1592 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1593 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1594 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1595 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1596 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1597 ,
1598 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1599 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1600 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1601 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1602 pCtx->r11, pCtx->r12, pCtx->r13,
1603 pCtx->r14, pCtx->r15,
1604 X86_EFL_GET_IOPL(efl), szEFlags,
1605 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1606 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1607 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1608 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1609 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1610 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1611 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1612 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1613 }
1614#endif
1615}
1616
1617
1618/**
1619 * Get L1 cache / TLS associativity.
1620 */
1621static const char *getCacheAss(unsigned u, char *pszBuf)
1622{
1623 if (u == 0)
1624 return "res0 ";
1625 if (u == 1)
1626 return "direct";
1627 if (u >= 256)
1628 return "???";
1629
1630 RTStrPrintf(pszBuf, 16, "%d way", u);
1631 return pszBuf;
1632}
1633
1634
1635/**
1636 * Get L2 cache soociativity.
1637 */
1638const char *getL2CacheAss(unsigned u)
1639{
1640 switch (u)
1641 {
1642 case 0: return "off ";
1643 case 1: return "direct";
1644 case 2: return "2 way ";
1645 case 3: return "res3 ";
1646 case 4: return "4 way ";
1647 case 5: return "res5 ";
1648 case 6: return "8 way "; case 7: return "res7 ";
1649 case 8: return "16 way";
1650 case 9: return "res9 ";
1651 case 10: return "res10 ";
1652 case 11: return "res11 ";
1653 case 12: return "res12 ";
1654 case 13: return "res13 ";
1655 case 14: return "res14 ";
1656 case 15: return "fully ";
1657 default:
1658 return "????";
1659 }
1660}
1661
1662
1663/**
1664 * Display the guest CpuId leaves.
1665 *
1666 * @param pVM VM Handle.
1667 * @param pHlp The info helper functions.
1668 * @param pszArgs "terse", "default" or "verbose".
1669 */
1670static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1671{
1672 /*
1673 * Parse the argument.
1674 */
1675 unsigned iVerbosity = 1;
1676 if (pszArgs)
1677 {
1678 pszArgs = RTStrStripL(pszArgs);
1679 if (!strcmp(pszArgs, "terse"))
1680 iVerbosity--;
1681 else if (!strcmp(pszArgs, "verbose"))
1682 iVerbosity++;
1683 }
1684
1685 /*
1686 * Start cracking.
1687 */
1688 CPUMCPUID Host;
1689 CPUMCPUID Guest;
1690 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1691
1692 pHlp->pfnPrintf(pHlp,
1693 " RAW Standard CPUIDs\n"
1694 " Function eax ebx ecx edx\n");
1695 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1696 {
1697 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1698 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1699
1700 pHlp->pfnPrintf(pHlp,
1701 "Gst: %08x %08x %08x %08x %08x%s\n"
1702 "Hst: %08x %08x %08x %08x\n",
1703 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1704 i <= cStdMax ? "" : "*",
1705 Host.eax, Host.ebx, Host.ecx, Host.edx);
1706 }
1707
1708 /*
1709 * If verbose, decode it.
1710 */
1711 if (iVerbosity)
1712 {
1713 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1714 pHlp->pfnPrintf(pHlp,
1715 "Name: %.04s%.04s%.04s\n"
1716 "Supports: 0-%x\n",
1717 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1718 }
1719
1720 /*
1721 * Get Features.
1722 */
1723 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1724 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1725 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1726 if (cStdMax >= 1 && iVerbosity)
1727 {
1728 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1729 uint32_t uEAX = Guest.eax;
1730
1731 pHlp->pfnPrintf(pHlp,
1732 "Family: %d \tExtended: %d \tEffective: %d\n"
1733 "Model: %d \tExtended: %d \tEffective: %d\n"
1734 "Stepping: %d\n"
1735 "APIC ID: %#04x\n"
1736 "Logical CPUs: %d\n"
1737 "CLFLUSH Size: %d\n"
1738 "Brand ID: %#04x\n",
1739 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1740 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1741 ASMGetCpuStepping(uEAX),
1742 (Guest.ebx >> 24) & 0xff,
1743 (Guest.ebx >> 16) & 0xff,
1744 (Guest.ebx >> 8) & 0xff,
1745 (Guest.ebx >> 0) & 0xff);
1746 if (iVerbosity == 1)
1747 {
1748 uint32_t uEDX = Guest.edx;
1749 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1750 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1751 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1752 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1753 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1754 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1755 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1756 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1757 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1758 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1759 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1760 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1761 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1762 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1763 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1764 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1765 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1766 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1767 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1768 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1769 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1770 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1771 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1772 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1773 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1774 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1775 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1776 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1777 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1778 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1779 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1780 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1781 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1782 pHlp->pfnPrintf(pHlp, "\n");
1783
1784 uint32_t uECX = Guest.ecx;
1785 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1786 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1787 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1788 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1789 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1790 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1791 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1792 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1793 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1794 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1795 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1796 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1797 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1798 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1799 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1800 for (unsigned iBit = 14; iBit < 32; iBit++)
1801 if (uECX & RT_BIT(iBit))
1802 pHlp->pfnPrintf(pHlp, " %d", iBit);
1803 pHlp->pfnPrintf(pHlp, "\n");
1804 }
1805 else
1806 {
1807 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1808
1809 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1810 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1811 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1812 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1813
1814 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1815 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1816 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1817 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1818 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1819 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1820 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1821 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1822 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1823 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1824 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1825 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1826 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1827 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1828 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1829 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1830 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1831 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1832 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1833 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1834 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1835 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1836 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1837 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1838 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1839 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1840 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1841 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1842 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1843 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1844 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1845 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1846 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1847
1848 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1849 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
1850 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
1851 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1852 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1853 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1854 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
1855 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1856 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1857 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1858 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1859 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved2, EcxHost.u2Reserved2);
1860 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1861 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1862 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
1863 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
1864 pHlp->pfnPrintf(pHlp, "Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
1865 pHlp->pfnPrintf(pHlp, "Supports SSE4_1 or not = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
1866 pHlp->pfnPrintf(pHlp, "Supports SSE4_2 or not = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
1867 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
1868 pHlp->pfnPrintf(pHlp, "Supports MOVBE = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
1869 pHlp->pfnPrintf(pHlp, "Supports POPCNT = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
1870 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1871 pHlp->pfnPrintf(pHlp, "Supports XSAVE = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
1872 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
1873 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u4Reserved5, EcxHost.u4Reserved5);
1874 }
1875 }
1876 if (cStdMax >= 2 && iVerbosity)
1877 {
1878 /** @todo */
1879 }
1880
1881 /*
1882 * Extended.
1883 * Implemented after AMD specs.
1884 */
1885 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1886
1887 pHlp->pfnPrintf(pHlp,
1888 "\n"
1889 " RAW Extended CPUIDs\n"
1890 " Function eax ebx ecx edx\n");
1891 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1892 {
1893 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1894 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1895
1896 pHlp->pfnPrintf(pHlp,
1897 "Gst: %08x %08x %08x %08x %08x%s\n"
1898 "Hst: %08x %08x %08x %08x\n",
1899 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1900 i <= cExtMax ? "" : "*",
1901 Host.eax, Host.ebx, Host.ecx, Host.edx);
1902 }
1903
1904 /*
1905 * Understandable output
1906 */
1907 if (iVerbosity)
1908 {
1909 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1910 pHlp->pfnPrintf(pHlp,
1911 "Ext Name: %.4s%.4s%.4s\n"
1912 "Ext Supports: 0x80000000-%#010x\n",
1913 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1914 }
1915
1916 if (iVerbosity && cExtMax >= 1)
1917 {
1918 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1919 uint32_t uEAX = Guest.eax;
1920 pHlp->pfnPrintf(pHlp,
1921 "Family: %d \tExtended: %d \tEffective: %d\n"
1922 "Model: %d \tExtended: %d \tEffective: %d\n"
1923 "Stepping: %d\n"
1924 "Brand ID: %#05x\n",
1925 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1926 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1927 ASMGetCpuStepping(uEAX),
1928 Guest.ebx & 0xfff);
1929
1930 if (iVerbosity == 1)
1931 {
1932 uint32_t uEDX = Guest.edx;
1933 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1934 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1935 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1936 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1937 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1938 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1939 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1940 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1941 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1942 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1943 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1944 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1945 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1946 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1947 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1948 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1949 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1950 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1951 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1952 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1953 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1954 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1955 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1956 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1957 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1958 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1959 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1960 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1961 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1962 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1963 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1964 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1965 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1966 pHlp->pfnPrintf(pHlp, "\n");
1967
1968 uint32_t uECX = Guest.ecx;
1969 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1970 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1971 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1972 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1973 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1974 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1975 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1976 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1977 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1978 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1979 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1980 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1981 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1982 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1983 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1984 for (unsigned iBit = 5; iBit < 32; iBit++)
1985 if (uECX & RT_BIT(iBit))
1986 pHlp->pfnPrintf(pHlp, " %d", iBit);
1987 pHlp->pfnPrintf(pHlp, "\n");
1988 }
1989 else
1990 {
1991 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1992
1993 uint32_t uEdxGst = Guest.edx;
1994 uint32_t uEdxHst = Host.edx;
1995 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1996 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1997 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1998 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1999 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2000 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2001 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2002 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2003 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2004 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2005 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2006 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2007 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2008 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2009 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2010 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
2011 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
2012 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
2013 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
2014 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
2015 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
2016 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
2017 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
2018 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
2019 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
2020 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
2021 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
2022 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
2023 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
2024 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
2025 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
2026 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
2027 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
2028
2029 uint32_t uEcxGst = Guest.ecx;
2030 uint32_t uEcxHst = Host.ecx;
2031 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
2032 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
2033 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
2034 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
2035 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
2036 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
2037 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
2038 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
2039 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
2040 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
2041 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
2042 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
2043 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
2044 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
2045 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
2046 }
2047 }
2048
2049 if (iVerbosity && cExtMax >= 2)
2050 {
2051 char szString[4*4*3+1] = {0};
2052 uint32_t *pu32 = (uint32_t *)szString;
2053 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2054 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2055 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2056 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2057 if (cExtMax >= 3)
2058 {
2059 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2060 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2061 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2062 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2063 }
2064 if (cExtMax >= 4)
2065 {
2066 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2067 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2068 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2069 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2070 }
2071 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2072 }
2073
2074 if (iVerbosity && cExtMax >= 5)
2075 {
2076 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2077 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2078 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2079 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2080 char sz1[32];
2081 char sz2[32];
2082
2083 pHlp->pfnPrintf(pHlp,
2084 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2085 "TLB 2/4M Data: %s %3d entries\n",
2086 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2087 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2088 pHlp->pfnPrintf(pHlp,
2089 "TLB 4K Instr/Uni: %s %3d entries\n"
2090 "TLB 4K Data: %s %3d entries\n",
2091 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2092 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2093 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2094 "L1 Instr Cache Lines Per Tag: %d\n"
2095 "L1 Instr Cache Associativity: %s\n"
2096 "L1 Instr Cache Size: %d KB\n",
2097 (uEDX >> 0) & 0xff,
2098 (uEDX >> 8) & 0xff,
2099 getCacheAss((uEDX >> 16) & 0xff, sz1),
2100 (uEDX >> 24) & 0xff);
2101 pHlp->pfnPrintf(pHlp,
2102 "L1 Data Cache Line Size: %d bytes\n"
2103 "L1 Data Cache Lines Per Tag: %d\n"
2104 "L1 Data Cache Associativity: %s\n"
2105 "L1 Data Cache Size: %d KB\n",
2106 (uECX >> 0) & 0xff,
2107 (uECX >> 8) & 0xff,
2108 getCacheAss((uECX >> 16) & 0xff, sz1),
2109 (uECX >> 24) & 0xff);
2110 }
2111
2112 if (iVerbosity && cExtMax >= 6)
2113 {
2114 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2115 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2116 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2117
2118 pHlp->pfnPrintf(pHlp,
2119 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2120 "L2 TLB 2/4M Data: %s %4d entries\n",
2121 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2122 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2123 pHlp->pfnPrintf(pHlp,
2124 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2125 "L2 TLB 4K Data: %s %4d entries\n",
2126 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2127 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2128 pHlp->pfnPrintf(pHlp,
2129 "L2 Cache Line Size: %d bytes\n"
2130 "L2 Cache Lines Per Tag: %d\n"
2131 "L2 Cache Associativity: %s\n"
2132 "L2 Cache Size: %d KB\n",
2133 (uEDX >> 0) & 0xff,
2134 (uEDX >> 8) & 0xf,
2135 getL2CacheAss((uEDX >> 12) & 0xf),
2136 (uEDX >> 16) & 0xffff);
2137 }
2138
2139 if (iVerbosity && cExtMax >= 7)
2140 {
2141 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2142
2143 pHlp->pfnPrintf(pHlp, "APM Features: ");
2144 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2145 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2146 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2147 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2148 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2149 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2150 for (unsigned iBit = 6; iBit < 32; iBit++)
2151 if (uEDX & RT_BIT(iBit))
2152 pHlp->pfnPrintf(pHlp, " %d", iBit);
2153 pHlp->pfnPrintf(pHlp, "\n");
2154 }
2155
2156 if (iVerbosity && cExtMax >= 8)
2157 {
2158 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2159 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2160
2161 pHlp->pfnPrintf(pHlp,
2162 "Physical Address Width: %d bits\n"
2163 "Virtual Address Width: %d bits\n",
2164 (uEAX >> 0) & 0xff,
2165 (uEAX >> 8) & 0xff);
2166 pHlp->pfnPrintf(pHlp,
2167 "Physical Core Count: %d\n",
2168 (uECX >> 0) & 0xff);
2169 }
2170
2171
2172 /*
2173 * Centaur.
2174 */
2175 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2176
2177 pHlp->pfnPrintf(pHlp,
2178 "\n"
2179 " RAW Centaur CPUIDs\n"
2180 " Function eax ebx ecx edx\n");
2181 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2182 {
2183 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2184 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2185
2186 pHlp->pfnPrintf(pHlp,
2187 "Gst: %08x %08x %08x %08x %08x%s\n"
2188 "Hst: %08x %08x %08x %08x\n",
2189 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2190 i <= cCentaurMax ? "" : "*",
2191 Host.eax, Host.ebx, Host.ecx, Host.edx);
2192 }
2193
2194 /*
2195 * Understandable output
2196 */
2197 if (iVerbosity)
2198 {
2199 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2200 pHlp->pfnPrintf(pHlp,
2201 "Centaur Supports: 0xc0000000-%#010x\n",
2202 Guest.eax);
2203 }
2204
2205 if (iVerbosity && cCentaurMax >= 1)
2206 {
2207 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2208 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2209 uint32_t uEdxHst = Host.edx;
2210
2211 if (iVerbosity == 1)
2212 {
2213 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2214 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2215 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2216 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2217 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2218 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2219 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2220 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2221 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2222 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2223 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2224 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2225 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2226 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2227 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2228 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2229 for (unsigned iBit = 14; iBit < 32; iBit++)
2230 if (uEdxGst & RT_BIT(iBit))
2231 pHlp->pfnPrintf(pHlp, " %d", iBit);
2232 pHlp->pfnPrintf(pHlp, "\n");
2233 }
2234 else
2235 {
2236 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2237 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2238 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2239 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2240 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2241 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2242 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2243 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2244 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2245 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2246 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2247 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2248 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2249 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2250 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2251 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2252 for (unsigned iBit = 14; iBit < 32; iBit++)
2253 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2254 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2255 pHlp->pfnPrintf(pHlp, "\n");
2256 }
2257 }
2258}
2259
2260
2261/**
2262 * Structure used when disassembling and instructions in DBGF.
2263 * This is used so the reader function can get the stuff it needs.
2264 */
2265typedef struct CPUMDISASSTATE
2266{
2267 /** Pointer to the CPU structure. */
2268 PDISCPUSTATE pCpu;
2269 /** The VM handle. */
2270 PVM pVM;
2271 /** The VMCPU handle. */
2272 PVMCPU pVCpu;
2273 /** Pointer to the first byte in the segemnt. */
2274 RTGCUINTPTR GCPtrSegBase;
2275 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2276 RTGCUINTPTR GCPtrSegEnd;
2277 /** The size of the segment minus 1. */
2278 RTGCUINTPTR cbSegLimit;
2279 /** Pointer to the current page - R3 Ptr. */
2280 void const *pvPageR3;
2281 /** Pointer to the current page - GC Ptr. */
2282 RTGCPTR pvPageGC;
2283 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2284 PGMPAGEMAPLOCK PageMapLock;
2285 /** Whether the PageMapLock is valid or not. */
2286 bool fLocked;
2287 /** 64 bits mode or not. */
2288 bool f64Bits;
2289} CPUMDISASSTATE, *PCPUMDISASSTATE;
2290
2291
2292/**
2293 * Instruction reader.
2294 *
2295 * @returns VBox status code.
2296 * @param PtrSrc Address to read from.
2297 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2298 * @param pu8Dst Where to store the bytes.
2299 * @param cbRead Number of bytes to read.
2300 * @param uDisCpu Pointer to the disassembler cpu state.
2301 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2302 */
2303static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2304{
2305 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2306 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2307 Assert(cbRead > 0);
2308 for (;;)
2309 {
2310 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2311
2312 /* Need to update the page translation? */
2313 if ( !pState->pvPageR3
2314 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2315 {
2316 int rc = VINF_SUCCESS;
2317
2318 /* translate the address */
2319 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2320 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2321 && !HWACCMIsEnabled(pState->pVM))
2322 {
2323 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2324 if (!pState->pvPageR3)
2325 rc = VERR_INVALID_POINTER;
2326 }
2327 else
2328 {
2329 /* Release mapping lock previously acquired. */
2330 if (pState->fLocked)
2331 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2332 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2333 pState->fLocked = RT_SUCCESS_NP(rc);
2334 }
2335 if (RT_FAILURE(rc))
2336 {
2337 pState->pvPageR3 = NULL;
2338 return rc;
2339 }
2340 }
2341
2342 /* check the segemnt limit */
2343 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2344 return VERR_OUT_OF_SELECTOR_BOUNDS;
2345
2346 /* calc how much we can read */
2347 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2348 if (!pState->f64Bits)
2349 {
2350 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2351 if (cb > cbSeg && cbSeg)
2352 cb = cbSeg;
2353 }
2354 if (cb > cbRead)
2355 cb = cbRead;
2356
2357 /* read and advance */
2358 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2359 cbRead -= cb;
2360 if (!cbRead)
2361 return VINF_SUCCESS;
2362 pu8Dst += cb;
2363 PtrSrc += cb;
2364 }
2365}
2366
2367
2368/**
2369 * Disassemble an instruction and return the information in the provided structure.
2370 *
2371 * @returns VBox status code.
2372 * @param pVM VM Handle
2373 * @param pVCpu VMCPU Handle
2374 * @param pCtx CPU context
2375 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2376 * @param pCpu Disassembly state
2377 * @param pszPrefix String prefix for logging (debug only)
2378 *
2379 */
2380VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2381{
2382 CPUMDISASSTATE State;
2383 int rc;
2384
2385 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2386 State.pCpu = pCpu;
2387 State.pvPageGC = 0;
2388 State.pvPageR3 = NULL;
2389 State.pVM = pVM;
2390 State.pVCpu = pVCpu;
2391 State.fLocked = false;
2392 State.f64Bits = false;
2393
2394 /*
2395 * Get selector information.
2396 */
2397 if ( (pCtx->cr0 & X86_CR0_PE)
2398 && pCtx->eflags.Bits.u1VM == 0)
2399 {
2400 if (CPUMAreHiddenSelRegsValid(pVM))
2401 {
2402 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2403 State.GCPtrSegBase = pCtx->csHid.u64Base;
2404 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2405 State.cbSegLimit = pCtx->csHid.u32Limit;
2406 pCpu->mode = (State.f64Bits)
2407 ? CPUMODE_64BIT
2408 : pCtx->csHid.Attr.n.u1DefBig
2409 ? CPUMODE_32BIT
2410 : CPUMODE_16BIT;
2411 }
2412 else
2413 {
2414 DBGFSELINFO SelInfo;
2415
2416 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2417 if (RT_FAILURE(rc))
2418 {
2419 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2420 return rc;
2421 }
2422
2423 /*
2424 * Validate the selector.
2425 */
2426 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2427 if (RT_FAILURE(rc))
2428 {
2429 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2430 return rc;
2431 }
2432 State.GCPtrSegBase = SelInfo.GCPtrBase;
2433 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2434 State.cbSegLimit = SelInfo.cbLimit;
2435 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2436 }
2437 }
2438 else
2439 {
2440 /* real or V86 mode */
2441 pCpu->mode = CPUMODE_16BIT;
2442 State.GCPtrSegBase = pCtx->cs * 16;
2443 State.GCPtrSegEnd = 0xFFFFFFFF;
2444 State.cbSegLimit = 0xFFFFFFFF;
2445 }
2446
2447 /*
2448 * Disassemble the instruction.
2449 */
2450 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2451 pCpu->apvUserData[0] = &State;
2452
2453 uint32_t cbInstr;
2454#ifndef LOG_ENABLED
2455 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2456 if (RT_SUCCESS(rc))
2457 {
2458#else
2459 char szOutput[160];
2460 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2461 if (RT_SUCCESS(rc))
2462 {
2463 /* log it */
2464 if (pszPrefix)
2465 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2466 else
2467 Log(("%s", szOutput));
2468#endif
2469 rc = VINF_SUCCESS;
2470 }
2471 else
2472 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2473
2474 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2475 if (State.fLocked)
2476 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2477
2478 return rc;
2479}
2480
2481#ifdef DEBUG
2482
2483/**
2484 * Disassemble an instruction and dump it to the log
2485 *
2486 * @returns VBox status code.
2487 * @param pVM VM Handle
2488 * @param pVCpu VMCPU Handle
2489 * @param pCtx CPU context
2490 * @param pc GC instruction pointer
2491 * @param pszPrefix String prefix for logging
2492 *
2493 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2494 */
2495VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2496{
2497 DISCPUSTATE Cpu;
2498 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2499}
2500
2501
2502/**
2503 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2504 *
2505 * @internal
2506 */
2507VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2508{
2509 /* @todo SMP support!! */
2510 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2511}
2512
2513#endif /* DEBUG */
2514
2515/**
2516 * API for controlling a few of the CPU features found in CR4.
2517 *
2518 * Currently only X86_CR4_TSD is accepted as input.
2519 *
2520 * @returns VBox status code.
2521 *
2522 * @param pVM The VM handle.
2523 * @param fOr The CR4 OR mask.
2524 * @param fAnd The CR4 AND mask.
2525 */
2526VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2527{
2528 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2529 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2530
2531 pVM->cpum.s.CR4.OrMask &= fAnd;
2532 pVM->cpum.s.CR4.OrMask |= fOr;
2533
2534 return VINF_SUCCESS;
2535}
2536
2537
2538/**
2539 * Gets a pointer to the array of standard CPUID leafs.
2540 *
2541 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2542 *
2543 * @returns Pointer to the standard CPUID leafs (read-only).
2544 * @param pVM The VM handle.
2545 * @remark Intended for PATM.
2546 */
2547VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2548{
2549 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2550}
2551
2552
2553/**
2554 * Gets a pointer to the array of extended CPUID leafs.
2555 *
2556 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2557 *
2558 * @returns Pointer to the extended CPUID leafs (read-only).
2559 * @param pVM The VM handle.
2560 * @remark Intended for PATM.
2561 */
2562VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2563{
2564 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2565}
2566
2567
2568/**
2569 * Gets a pointer to the array of centaur CPUID leafs.
2570 *
2571 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2572 *
2573 * @returns Pointer to the centaur CPUID leafs (read-only).
2574 * @param pVM The VM handle.
2575 * @remark Intended for PATM.
2576 */
2577VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2578{
2579 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2580}
2581
2582
2583/**
2584 * Gets a pointer to the default CPUID leaf.
2585 *
2586 * @returns Pointer to the default CPUID leaf (read-only).
2587 * @param pVM The VM handle.
2588 * @remark Intended for PATM.
2589 */
2590VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2591{
2592 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2593}
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