VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 20914

Last change on this file since 20914 was 20914, checked in by vboxsync, 15 years ago

Corrected cpuid values for multi-core vcpus.
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1/* $Id: CPUM.cpp 20914 2009-06-25 08:16:14Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** Enable multi-core VCPUs. */
70#define VBOX_WITH_MULTI_CORE
71
72/** The saved state version. */
73#define CPUM_SAVED_STATE_VERSION 10
74/** The saved state version for the 2.1 trunk before the MSR changes. */
75#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
76/** The saved state version of 2.0, used for backwards compatibility. */
77#define CPUM_SAVED_STATE_VERSION_VER2_0 8
78/** The saved state version of 1.6, used for backwards compatability. */
79#define CPUM_SAVED_STATE_VERSION_VER1_6 6
80
81
82/*******************************************************************************
83* Structures and Typedefs *
84*******************************************************************************/
85
86/**
87 * What kind of cpu info dump to perform.
88 */
89typedef enum CPUMDUMPTYPE
90{
91 CPUMDUMPTYPE_TERSE,
92 CPUMDUMPTYPE_DEFAULT,
93 CPUMDUMPTYPE_VERBOSE
94
95} CPUMDUMPTYPE;
96/** Pointer to a cpu info dump type. */
97typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
98
99
100/*******************************************************************************
101* Internal Functions *
102*******************************************************************************/
103static int cpumR3CpuIdInit(PVM pVM);
104static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
105static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
106static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112
113
114/**
115 * Initializes the CPUM.
116 *
117 * @returns VBox status code.
118 * @param pVM The VM to operate on.
119 */
120VMMR3DECL(int) CPUMR3Init(PVM pVM)
121{
122 LogFlow(("CPUMR3Init\n"));
123
124 /*
125 * Assert alignment and sizes.
126 */
127 AssertCompileMemberAlignment(VM, cpum.s, 32);
128 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
129 AssertCompileSizeAlignment(CPUMCTX, 64);
130 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
131 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
132 AssertCompileMemberAlignment(VM, cpum, 64);
133 AssertCompileMemberAlignment(VM, aCpus, 64);
134 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
135 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
136
137 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
138 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
139 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
140
141 /* Calculate the offset from CPUMCPU to CPUM. */
142 for (unsigned i=0;i<pVM->cCPUs;i++)
143 {
144 PVMCPU pVCpu = &pVM->aCpus[i];
145
146 /*
147 * Setup any fixed pointers and offsets.
148 */
149 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
150 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
151
152 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
153 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
154 }
155
156 /*
157 * Check that the CPU supports the minimum features we require.
158 */
159 if (!ASMHasCpuId())
160 {
161 Log(("The CPU doesn't support CPUID!\n"));
162 return VERR_UNSUPPORTED_CPU;
163 }
164 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
165 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
166
167 /* Setup the CR4 AND and OR masks used in the switcher */
168 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
169 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
170 {
171 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
172 /* No FXSAVE implies no SSE */
173 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
174 pVM->cpum.s.CR4.OrMask = 0;
175 }
176 else
177 {
178 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
179 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
180 }
181
182 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
183 {
184 Log(("The CPU doesn't support MMX!\n"));
185 return VERR_UNSUPPORTED_CPU;
186 }
187 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
188 {
189 Log(("The CPU doesn't support TSC!\n"));
190 return VERR_UNSUPPORTED_CPU;
191 }
192 /* Bogus on AMD? */
193 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
194 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
195
196 /*
197 * Setup hypervisor startup values.
198 */
199
200 /*
201 * Register saved state data item.
202 */
203 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
204 NULL, cpumR3Save, NULL,
205 NULL, cpumR3Load, NULL);
206 if (RT_FAILURE(rc))
207 return rc;
208
209 /* Query the CPU manufacturer. */
210 uint32_t uEAX, uEBX, uECX, uEDX;
211 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
212 if ( uEAX >= 1
213 && uEBX == X86_CPUID_VENDOR_AMD_EBX
214 && uECX == X86_CPUID_VENDOR_AMD_ECX
215 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
216 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
217 else if ( uEAX >= 1
218 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
219 && uECX == X86_CPUID_VENDOR_INTEL_ECX
220 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
221 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
222 else /** @todo Via */
223 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
224
225 /*
226 * Register info handlers.
227 */
228 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
229 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
230 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
231 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
232 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
233 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
234
235 /*
236 * Initialize the Guest CPU state.
237 */
238 rc = cpumR3CpuIdInit(pVM);
239 if (RT_FAILURE(rc))
240 return rc;
241 CPUMR3Reset(pVM);
242 return VINF_SUCCESS;
243}
244
245
246/**
247 * Initializes the per-VCPU CPUM.
248 *
249 * @returns VBox status code.
250 * @param pVM The VM to operate on.
251 */
252VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
253{
254 LogFlow(("CPUMR3InitCPU\n"));
255 return VINF_SUCCESS;
256}
257
258
259/**
260 * Initializes the emulated CPU's cpuid information.
261 *
262 * @returns VBox status code.
263 * @param pVM The VM to operate on.
264 */
265static int cpumR3CpuIdInit(PVM pVM)
266{
267 PCPUM pCPUM = &pVM->cpum.s;
268 uint32_t i;
269
270 /*
271 * Get the host CPUIDs.
272 */
273 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
274 ASMCpuId_Idx_ECX(i, 0,
275 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
276 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
277 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
278 ASMCpuId(0x80000000 + i,
279 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
280 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
281 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
282 ASMCpuId(0xc0000000 + i,
283 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
284 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
285
286
287 /*
288 * Only report features we can support.
289 */
290 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
291 | X86_CPUID_FEATURE_EDX_VME
292 | X86_CPUID_FEATURE_EDX_DE
293 | X86_CPUID_FEATURE_EDX_PSE
294 | X86_CPUID_FEATURE_EDX_TSC
295 | X86_CPUID_FEATURE_EDX_MSR
296 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
297 | X86_CPUID_FEATURE_EDX_MCE
298 | X86_CPUID_FEATURE_EDX_CX8
299 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
300 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
301 //| X86_CPUID_FEATURE_EDX_SEP
302 | X86_CPUID_FEATURE_EDX_MTRR
303 | X86_CPUID_FEATURE_EDX_PGE
304 | X86_CPUID_FEATURE_EDX_MCA
305 | X86_CPUID_FEATURE_EDX_CMOV
306 | X86_CPUID_FEATURE_EDX_PAT
307 | X86_CPUID_FEATURE_EDX_PSE36
308 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
309 | X86_CPUID_FEATURE_EDX_CLFSH
310 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
311 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
312 | X86_CPUID_FEATURE_EDX_MMX
313 | X86_CPUID_FEATURE_EDX_FXSR
314 | X86_CPUID_FEATURE_EDX_SSE
315 | X86_CPUID_FEATURE_EDX_SSE2
316 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
317 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
318 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
319 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
320 | 0;
321 pCPUM->aGuestCpuIdStd[1].ecx &= 0
322 | X86_CPUID_FEATURE_ECX_SSE3
323 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
324 | ((pVM->cCPUs == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
325 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
326 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
327 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
328 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
329 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
330 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
331 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
332 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
333 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
334 /* ECX Bit 21 - x2APIC support - not yet. */
335 // | X86_CPUID_FEATURE_ECX_X2APIC
336 /* ECX Bit 23 - POPCOUNT instruction. */
337 //| X86_CPUID_FEATURE_ECX_POPCOUNT
338 | 0;
339
340 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
341 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
342 | X86_CPUID_AMD_FEATURE_EDX_VME
343 | X86_CPUID_AMD_FEATURE_EDX_DE
344 | X86_CPUID_AMD_FEATURE_EDX_PSE
345 | X86_CPUID_AMD_FEATURE_EDX_TSC
346 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
347 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
348 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
349 | X86_CPUID_AMD_FEATURE_EDX_CX8
350 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
351 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
352 //| X86_CPUID_AMD_FEATURE_EDX_SEP
353 | X86_CPUID_AMD_FEATURE_EDX_MTRR
354 | X86_CPUID_AMD_FEATURE_EDX_PGE
355 | X86_CPUID_AMD_FEATURE_EDX_MCA
356 | X86_CPUID_AMD_FEATURE_EDX_CMOV
357 | X86_CPUID_AMD_FEATURE_EDX_PAT
358 | X86_CPUID_AMD_FEATURE_EDX_PSE36
359 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
360 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
361 | X86_CPUID_AMD_FEATURE_EDX_MMX
362 | X86_CPUID_AMD_FEATURE_EDX_FXSR
363 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
364 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
365 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
366 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
367 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
368 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
369 | 0;
370 pCPUM->aGuestCpuIdExt[1].ecx &= 0
371 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
372 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
373 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
374 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
375 /** Note: This could prevent migration from AMD to Intel CPUs! */
376 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
377 //| X86_CPUID_AMD_FEATURE_ECX_ABM
378 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
379 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
380 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
381 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
382 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
383 //| X86_CPUID_AMD_FEATURE_ECX_WDT
384 | 0;
385
386 /*
387 * Hide HTT, multicode, SMP, whatever.
388 * (APIC-ID := 0 and #LogCpus := 0)
389 */
390 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
391#ifdef VBOX_WITH_MULTI_CORE
392 if (pVM->cCPUs > 1)
393 {
394 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
395 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCPUs << 16);
396 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
397 }
398#endif
399
400 /* Cpuid 2:
401 * Intel: Cache and TLB information
402 * AMD: Reserved
403 * Safe to expose
404 */
405
406 /* Cpuid 3:
407 * Intel: EAX, EBX - reserved
408 * ECX, EDX - Processor Serial Number if available, otherwise reserved
409 * AMD: Reserved
410 * Safe to expose
411 */
412 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
413 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
414
415 /* Cpuid 4:
416 * Intel: Deterministic Cache Parameters Leaf
417 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
418 * AMD: Reserved
419 * Safe to expose, except for EAX:
420 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
421 * Bits 31-26: Maximum number of processor cores in this physical package**
422 * @Note These SMP values are constant regardless of ECX
423 */
424 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
425 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
426#ifdef VBOX_WITH_MULTI_CORE
427 if ( pVM->cCPUs > 1
428 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
429 {
430 AssertReturn(pVM->cCPUs <= 64, VERR_TOO_MANY_CPUS);
431 /* One logical processor with possibly multiple cores. */
432 pCPUM->aGuestCpuIdStd[4].eax |= (pVM->cCPUs << 26); /* 6 bits only -> 64 cores! */
433 }
434#endif
435
436 /* Cpuid 5: Monitor/mwait Leaf
437 * Intel: ECX, EDX - reserved
438 * EAX, EBX - Smallest and largest monitor line size
439 * AMD: EDX - reserved
440 * EAX, EBX - Smallest and largest monitor line size
441 * ECX - extensions (ignored for now)
442 * Safe to expose
443 */
444 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
445 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
446
447 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
448
449 /*
450 * Determine the default.
451 *
452 * Intel returns values of the highest standard function, while AMD
453 * returns zeros. VIA on the other hand seems to returning nothing or
454 * perhaps some random garbage, we don't try to duplicate this behavior.
455 */
456 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
457 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
458 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
459
460 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
461 * Safe to pass on to the guest.
462 *
463 * Intel: 0x800000005 reserved
464 * 0x800000006 L2 cache information
465 * AMD: 0x800000005 L1 cache information
466 * 0x800000006 L2/L3 cache information
467 */
468
469 /* Cpuid 0x800000007:
470 * AMD: EAX, EBX, ECX - reserved
471 * EDX: Advanced Power Management Information
472 * Intel: Reserved
473 */
474 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
475 {
476 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
477
478 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
479
480 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
481 {
482 /* Only expose the TSC invariant capability bit to the guest. */
483 pCPUM->aGuestCpuIdExt[7].edx &= 0
484 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
485 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
486 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
487 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
488 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
489 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
490 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
491 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
492#if 1
493 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
494 * that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
495 */
496#else
497 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
498#endif
499 | 0;
500 }
501 else
502 pCPUM->aGuestCpuIdExt[7].edx = 0;
503 }
504
505 /* Cpuid 0x800000008:
506 * AMD: EBX, EDX - reserved
507 * EAX: Virtual/Physical address Size
508 * ECX: Number of cores + APICIdCoreIdSize
509 * Intel: EAX: Virtual/Physical address Size
510 * EBX, ECX, EDX - reserved
511 */
512 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
513 {
514 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
515 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
516 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
517 * NC (0-7) Number of cores; 0 equals 1 core */
518 pCPUM->aGuestCpuIdExt[8].ecx = 0;
519#ifdef VBOX_WITH_MULTI_CORE
520 if ( pVM->cCPUs > 1
521 && pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
522 {
523 /* Legacy method to determine the number of cores. */
524 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
525 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCPUs - 1); /* NC: Number of CPU cores - 1; 8 bits */
526
527 }
528#endif
529 }
530
531 /*
532 * Limit it the number of entries and fill the remaining with the defaults.
533 *
534 * The limits are masking off stuff about power saving and similar, this
535 * is perhaps a bit crudely done as there is probably some relatively harmless
536 * info too in these leaves (like words about having a constant TSC).
537 */
538#if 0
539 /** @todo NT4 installation regression - investigate */
540 /** Note from Intel manuals:
541 * CPUID leaves > 3 < 80000000 are visible only when
542 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
543 *
544 */
545 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
546 pCPUM->aGuestCpuIdStd[0].eax = 5;
547#else
548 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
549 pCPUM->aGuestCpuIdStd[0].eax = 2;
550#endif
551 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
552 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
553
554 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
555 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
556 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
557 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
558 : 0;
559 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
560 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
561
562 /*
563 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
564 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
565 * We currently don't support more than 1 processor.
566 */
567 pCPUM->aGuestCpuIdStd[4].eax = 0;
568
569 /*
570 * Centaur stuff (VIA).
571 *
572 * The important part here (we think) is to make sure the 0xc0000000
573 * function returns 0xc0000001. As for the features, we don't currently
574 * let on about any of those... 0xc0000002 seems to be some
575 * temperature/hz/++ stuff, include it as well (static).
576 */
577 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
578 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
579 {
580 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
581 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
582 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
583 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
584 i++)
585 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
586 }
587 else
588 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
589 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
590
591
592 /*
593 * Load CPUID overrides from configuration.
594 */
595 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
596 * Overloads the CPUID leaf values. */
597 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
598 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
599 for (i=0;; )
600 {
601 while (cElements-- > 0)
602 {
603 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
604 if (pNode)
605 {
606 uint32_t u32;
607 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
608 if (RT_SUCCESS(rc))
609 pCpuId->eax = u32;
610 else
611 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
612
613 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
614 if (RT_SUCCESS(rc))
615 pCpuId->ebx = u32;
616 else
617 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
618
619 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
620 if (RT_SUCCESS(rc))
621 pCpuId->ecx = u32;
622 else
623 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
624
625 rc = CFGMR3QueryU32(pNode, "edx", &u32);
626 if (RT_SUCCESS(rc))
627 pCpuId->edx = u32;
628 else
629 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
630 }
631 pCpuId++;
632 i++;
633 }
634
635 /* next */
636 if ((i & UINT32_C(0xc0000000)) == 0)
637 {
638 pCpuId = &pCPUM->aGuestCpuIdExt[0];
639 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
640 i = UINT32_C(0x80000000);
641 }
642 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
643 {
644 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
645 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
646 i = UINT32_C(0xc0000000);
647 }
648 else
649 break;
650 }
651
652 /* Check if PAE was explicitely enabled by the user. */
653 bool fEnable = false;
654 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
655 if (RT_SUCCESS(rc) && fEnable)
656 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
657
658 /*
659 * Log the cpuid and we're good.
660 */
661 RTCPUSET OnlineSet;
662 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
663 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
664 LogRel(("************************* CPUID dump ************************\n"));
665 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
666 LogRel(("\n"));
667 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
668 LogRel(("******************** End of CPUID dump **********************\n"));
669 return VINF_SUCCESS;
670}
671
672
673
674
675/**
676 * Applies relocations to data and code managed by this
677 * component. This function will be called at init and
678 * whenever the VMM need to relocate it self inside the GC.
679 *
680 * The CPUM will update the addresses used by the switcher.
681 *
682 * @param pVM The VM.
683 */
684VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
685{
686 LogFlow(("CPUMR3Relocate\n"));
687 for (unsigned i=0;i<pVM->cCPUs;i++)
688 {
689 PVMCPU pVCpu = &pVM->aCpus[i];
690 /*
691 * Switcher pointers.
692 */
693 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
694 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
695 }
696}
697
698
699/**
700 * Terminates the CPUM.
701 *
702 * Termination means cleaning up and freeing all resources,
703 * the VM it self is at this point powered off or suspended.
704 *
705 * @returns VBox status code.
706 * @param pVM The VM to operate on.
707 */
708VMMR3DECL(int) CPUMR3Term(PVM pVM)
709{
710 CPUMR3TermCPU(pVM);
711 return 0;
712}
713
714
715/**
716 * Terminates the per-VCPU CPUM.
717 *
718 * Termination means cleaning up and freeing all resources,
719 * the VM it self is at this point powered off or suspended.
720 *
721 * @returns VBox status code.
722 * @param pVM The VM to operate on.
723 */
724VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
725{
726#ifdef VBOX_WITH_CRASHDUMP_MAGIC
727 for (unsigned i=0;i<pVM->cCPUs;i++)
728 {
729 PVMCPU pVCpu = &pVM->aCpus[i];
730 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
731
732 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
733 pVCpu->cpum.s.uMagic = 0;
734 pCtx->dr[5] = 0;
735 }
736#endif
737 return 0;
738}
739
740VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
741{
742 /* @todo anything different for VCPU > 0? */
743 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
744
745 /*
746 * Initialize everything to ZERO first.
747 */
748 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
749 memset(pCtx, 0, sizeof(*pCtx));
750 pVCpu->cpum.s.fUseFlags = fUseFlags;
751
752 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
753 pCtx->eip = 0x0000fff0;
754 pCtx->edx = 0x00000600; /* P6 processor */
755 pCtx->eflags.Bits.u1Reserved0 = 1;
756
757 pCtx->cs = 0xf000;
758 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
759 pCtx->csHid.u32Limit = 0x0000ffff;
760 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
761 pCtx->csHid.Attr.n.u1Present = 1;
762 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
763
764 pCtx->dsHid.u32Limit = 0x0000ffff;
765 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
766 pCtx->dsHid.Attr.n.u1Present = 1;
767 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
768
769 pCtx->esHid.u32Limit = 0x0000ffff;
770 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
771 pCtx->esHid.Attr.n.u1Present = 1;
772 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
773
774 pCtx->fsHid.u32Limit = 0x0000ffff;
775 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
776 pCtx->fsHid.Attr.n.u1Present = 1;
777 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
778
779 pCtx->gsHid.u32Limit = 0x0000ffff;
780 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
781 pCtx->gsHid.Attr.n.u1Present = 1;
782 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
783
784 pCtx->ssHid.u32Limit = 0x0000ffff;
785 pCtx->ssHid.Attr.n.u1Present = 1;
786 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
787 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
788
789 pCtx->idtr.cbIdt = 0xffff;
790 pCtx->gdtr.cbGdt = 0xffff;
791
792 pCtx->ldtrHid.u32Limit = 0xffff;
793 pCtx->ldtrHid.Attr.n.u1Present = 1;
794 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
795
796 pCtx->trHid.u32Limit = 0xffff;
797 pCtx->trHid.Attr.n.u1Present = 1;
798 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
799
800 pCtx->dr[6] = X86_DR6_INIT_VAL;
801 pCtx->dr[7] = X86_DR7_INIT_VAL;
802
803 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
804 pCtx->fpu.FCW = 0x37f;
805
806 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
807 pCtx->fpu.MXCSR = 0x1F80;
808
809 /* Init PAT MSR */
810 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
811
812 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
813 * The Intel docs don't mention it.
814 */
815 pCtx->msrEFER = 0;
816}
817
818/**
819 * Resets the CPU.
820 *
821 * @returns VINF_SUCCESS.
822 * @param pVM The VM handle.
823 */
824VMMR3DECL(void) CPUMR3Reset(PVM pVM)
825{
826 for (unsigned i=0;i<pVM->cCPUs;i++)
827 {
828 CPUMR3ResetCpu(&pVM->aCpus[i]);
829
830#ifdef VBOX_WITH_CRASHDUMP_MAGIC
831 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
832
833 /* Magic marker for searching in crash dumps. */
834 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
835 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
836 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
837#endif
838 }
839}
840
841
842/**
843 * Execute state save operation.
844 *
845 * @returns VBox status code.
846 * @param pVM VM Handle.
847 * @param pSSM SSM operation handle.
848 */
849static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
850{
851 /*
852 * Save.
853 */
854 for (unsigned i=0;i<pVM->cCPUs;i++)
855 {
856 PVMCPU pVCpu = &pVM->aCpus[i];
857
858 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
859 }
860
861 SSMR3PutU32(pSSM, pVM->cCPUs);
862 for (unsigned i=0;i<pVM->cCPUs;i++)
863 {
864 PVMCPU pVCpu = &pVM->aCpus[i];
865
866 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
867 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
868 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
869 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
870 }
871
872 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
873 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
874
875 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
876 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
877
878 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
879 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
880
881 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
882
883 /* Add the cpuid for checking that the cpu is unchanged. */
884 uint32_t au32CpuId[8] = {0};
885 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
886 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
887 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
888}
889
890
891/**
892 * Load a version 1.6 CPUMCTX structure.
893 *
894 * @returns VBox status code.
895 * @param pVM VM Handle.
896 * @param pCpumctx16 Version 1.6 CPUMCTX
897 */
898static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
899{
900#define CPUMCTX16_LOADREG(RegName) \
901 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
902
903#define CPUMCTX16_LOADDRXREG(RegName) \
904 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
905
906#define CPUMCTX16_LOADHIDREG(RegName) \
907 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
908 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
909 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
910
911#define CPUMCTX16_LOADSEGREG(RegName) \
912 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
913 CPUMCTX16_LOADHIDREG(RegName);
914
915 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
916
917 CPUMCTX16_LOADREG(rax);
918 CPUMCTX16_LOADREG(rbx);
919 CPUMCTX16_LOADREG(rcx);
920 CPUMCTX16_LOADREG(rdx);
921 CPUMCTX16_LOADREG(rdi);
922 CPUMCTX16_LOADREG(rsi);
923 CPUMCTX16_LOADREG(rbp);
924 CPUMCTX16_LOADREG(esp);
925 CPUMCTX16_LOADREG(rip);
926 CPUMCTX16_LOADREG(rflags);
927
928 CPUMCTX16_LOADSEGREG(cs);
929 CPUMCTX16_LOADSEGREG(ds);
930 CPUMCTX16_LOADSEGREG(es);
931 CPUMCTX16_LOADSEGREG(fs);
932 CPUMCTX16_LOADSEGREG(gs);
933 CPUMCTX16_LOADSEGREG(ss);
934
935 CPUMCTX16_LOADREG(r8);
936 CPUMCTX16_LOADREG(r9);
937 CPUMCTX16_LOADREG(r10);
938 CPUMCTX16_LOADREG(r11);
939 CPUMCTX16_LOADREG(r12);
940 CPUMCTX16_LOADREG(r13);
941 CPUMCTX16_LOADREG(r14);
942 CPUMCTX16_LOADREG(r15);
943
944 CPUMCTX16_LOADREG(cr0);
945 CPUMCTX16_LOADREG(cr2);
946 CPUMCTX16_LOADREG(cr3);
947 CPUMCTX16_LOADREG(cr4);
948
949 CPUMCTX16_LOADDRXREG(0);
950 CPUMCTX16_LOADDRXREG(1);
951 CPUMCTX16_LOADDRXREG(2);
952 CPUMCTX16_LOADDRXREG(3);
953 CPUMCTX16_LOADDRXREG(4);
954 CPUMCTX16_LOADDRXREG(5);
955 CPUMCTX16_LOADDRXREG(6);
956 CPUMCTX16_LOADDRXREG(7);
957
958 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
959 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
960 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
961 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
962
963 CPUMCTX16_LOADREG(ldtr);
964 CPUMCTX16_LOADREG(tr);
965
966 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
967
968 CPUMCTX16_LOADREG(msrEFER);
969 CPUMCTX16_LOADREG(msrSTAR);
970 CPUMCTX16_LOADREG(msrPAT);
971 CPUMCTX16_LOADREG(msrLSTAR);
972 CPUMCTX16_LOADREG(msrCSTAR);
973 CPUMCTX16_LOADREG(msrSFMASK);
974 CPUMCTX16_LOADREG(msrKERNELGSBASE);
975
976 CPUMCTX16_LOADHIDREG(ldtr);
977 CPUMCTX16_LOADHIDREG(tr);
978
979#undef CPUMCTX16_LOADSEGREG
980#undef CPUMCTX16_LOADHIDREG
981#undef CPUMCTX16_LOADDRXREG
982#undef CPUMCTX16_LOADREG
983}
984
985
986/**
987 * Execute state load operation.
988 *
989 * @returns VBox status code.
990 * @param pVM VM Handle.
991 * @param pSSM SSM operation handle.
992 * @param u32Version Data layout version.
993 */
994static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
995{
996 /*
997 * Validate version.
998 */
999 if ( u32Version != CPUM_SAVED_STATE_VERSION
1000 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1001 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
1002 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
1003 {
1004 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
1005 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1006 }
1007
1008 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
1009 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1010 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1011 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
1012 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1013
1014 /*
1015 * Restore.
1016 */
1017 for (unsigned i=0;i<pVM->cCPUs;i++)
1018 {
1019 PVMCPU pVCpu = &pVM->aCpus[i];
1020 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1021 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
1022
1023 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1024 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1025 pVCpu->cpum.s.Hyper.esp = uESP;
1026 }
1027
1028 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1029 {
1030 CPUMCTX_VER1_6 cpumctx16;
1031 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1032 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1033
1034 /* Save the old cpumctx state into the new one. */
1035 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1036
1037 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1038 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1039 }
1040 else
1041 {
1042 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1043 {
1044 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1045 AssertRCReturn(rc, rc);
1046 }
1047
1048 if ( !pVM->cCPUs
1049 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1050 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1051 && pVM->cCPUs != 1))
1052 {
1053 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1054 return VERR_SSM_UNEXPECTED_DATA;
1055 }
1056
1057 for (unsigned i=0;i<pVM->cCPUs;i++)
1058 {
1059 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1060 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1061 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1062 if (u32Version == CPUM_SAVED_STATE_VERSION)
1063 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1064 }
1065 }
1066
1067
1068 uint32_t cElements;
1069 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1070 /* Support old saved states with a smaller standard cpuid array. */
1071 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1072 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1073 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1074
1075 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1076 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1077 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1078 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1079
1080 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1081 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1082 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1083 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1084
1085 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1086
1087 /*
1088 * Check that the basic cpuid id information is unchanged.
1089 * @todo we should check the 64 bits capabilities too!
1090 */
1091 uint32_t au32CpuId[8] = {0};
1092 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1093 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1094 uint32_t au32CpuIdSaved[8];
1095 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1096 if (RT_SUCCESS(rc))
1097 {
1098 /* Ignore CPU stepping. */
1099 au32CpuId[4] &= 0xfffffff0;
1100 au32CpuIdSaved[4] &= 0xfffffff0;
1101
1102 /* Ignore APIC ID (AMD specs). */
1103 au32CpuId[5] &= ~0xff000000;
1104 au32CpuIdSaved[5] &= ~0xff000000;
1105
1106 /* Ignore the number of Logical CPUs (AMD specs). */
1107 au32CpuId[5] &= ~0x00ff0000;
1108 au32CpuIdSaved[5] &= ~0x00ff0000;
1109
1110 /* do the compare */
1111 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1112 {
1113 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1114 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1115 "Saved=%.*Rhxs\n"
1116 "Real =%.*Rhxs\n",
1117 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1118 sizeof(au32CpuId), au32CpuId));
1119 else
1120 {
1121 LogRel(("cpumR3Load: CpuId mismatch!\n"
1122 "Saved=%.*Rhxs\n"
1123 "Real =%.*Rhxs\n",
1124 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1125 sizeof(au32CpuId), au32CpuId));
1126 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1127 }
1128 }
1129 }
1130
1131 return rc;
1132}
1133
1134
1135/**
1136 * Formats the EFLAGS value into mnemonics.
1137 *
1138 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1139 * @param efl The EFLAGS value.
1140 */
1141static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1142{
1143 /*
1144 * Format the flags.
1145 */
1146 static const struct
1147 {
1148 const char *pszSet; const char *pszClear; uint32_t fFlag;
1149 } s_aFlags[] =
1150 {
1151 { "vip",NULL, X86_EFL_VIP },
1152 { "vif",NULL, X86_EFL_VIF },
1153 { "ac", NULL, X86_EFL_AC },
1154 { "vm", NULL, X86_EFL_VM },
1155 { "rf", NULL, X86_EFL_RF },
1156 { "nt", NULL, X86_EFL_NT },
1157 { "ov", "nv", X86_EFL_OF },
1158 { "dn", "up", X86_EFL_DF },
1159 { "ei", "di", X86_EFL_IF },
1160 { "tf", NULL, X86_EFL_TF },
1161 { "nt", "pl", X86_EFL_SF },
1162 { "nz", "zr", X86_EFL_ZF },
1163 { "ac", "na", X86_EFL_AF },
1164 { "po", "pe", X86_EFL_PF },
1165 { "cy", "nc", X86_EFL_CF },
1166 };
1167 char *psz = pszEFlags;
1168 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1169 {
1170 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1171 if (pszAdd)
1172 {
1173 strcpy(psz, pszAdd);
1174 psz += strlen(pszAdd);
1175 *psz++ = ' ';
1176 }
1177 }
1178 psz[-1] = '\0';
1179}
1180
1181
1182/**
1183 * Formats a full register dump.
1184 *
1185 * @param pVM VM Handle.
1186 * @param pCtx The context to format.
1187 * @param pCtxCore The context core to format.
1188 * @param pHlp Output functions.
1189 * @param enmType The dump type.
1190 * @param pszPrefix Register name prefix.
1191 */
1192static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1193{
1194 /*
1195 * Format the EFLAGS.
1196 */
1197 uint32_t efl = pCtxCore->eflags.u32;
1198 char szEFlags[80];
1199 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1200
1201 /*
1202 * Format the registers.
1203 */
1204 switch (enmType)
1205 {
1206 case CPUMDUMPTYPE_TERSE:
1207 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1208 pHlp->pfnPrintf(pHlp,
1209 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1210 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1211 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1212 "%sr14=%016RX64 %sr15=%016RX64\n"
1213 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1214 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1215 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1216 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1217 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1218 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1219 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1220 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1221 else
1222 pHlp->pfnPrintf(pHlp,
1223 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1224 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1225 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1226 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1227 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1228 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1229 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1230 break;
1231
1232 case CPUMDUMPTYPE_DEFAULT:
1233 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1234 pHlp->pfnPrintf(pHlp,
1235 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1236 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1237 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1238 "%sr14=%016RX64 %sr15=%016RX64\n"
1239 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1240 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1241 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1242 ,
1243 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1244 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1245 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1246 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1247 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1248 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1249 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1250 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1251 else
1252 pHlp->pfnPrintf(pHlp,
1253 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1254 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1255 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1256 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1257 ,
1258 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1259 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1260 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1261 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1262 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1263 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1264 break;
1265
1266 case CPUMDUMPTYPE_VERBOSE:
1267 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1268 pHlp->pfnPrintf(pHlp,
1269 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1270 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1271 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1272 "%sr14=%016RX64 %sr15=%016RX64\n"
1273 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1274 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1275 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1276 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1277 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1278 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1279 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1280 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1281 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1282 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1283 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1284 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1285 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1286 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1287 ,
1288 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1289 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1290 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1291 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1292 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1293 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1294 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1295 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1296 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1297 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1298 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1299 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1300 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1301 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1302 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1303 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1304 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1305 else
1306 pHlp->pfnPrintf(pHlp,
1307 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1308 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1309 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1310 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1311 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1312 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1313 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1314 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1315 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1316 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1317 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1318 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1319 ,
1320 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1321 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1322 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1323 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1324 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1325 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1326 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1327 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1328 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1329 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1330 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1331 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1332
1333 pHlp->pfnPrintf(pHlp,
1334 "FPU:\n"
1335 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1336 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1337 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1338 ,
1339 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1340 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1341 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1342 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1343
1344 pHlp->pfnPrintf(pHlp,
1345 "MSR:\n"
1346 "%sEFER =%016RX64\n"
1347 "%sPAT =%016RX64\n"
1348 "%sSTAR =%016RX64\n"
1349 "%sCSTAR =%016RX64\n"
1350 "%sLSTAR =%016RX64\n"
1351 "%sSFMASK =%016RX64\n"
1352 "%sKERNELGSBASE =%016RX64\n",
1353 pszPrefix, pCtx->msrEFER,
1354 pszPrefix, pCtx->msrPAT,
1355 pszPrefix, pCtx->msrSTAR,
1356 pszPrefix, pCtx->msrCSTAR,
1357 pszPrefix, pCtx->msrLSTAR,
1358 pszPrefix, pCtx->msrSFMASK,
1359 pszPrefix, pCtx->msrKERNELGSBASE);
1360 break;
1361 }
1362}
1363
1364
1365/**
1366 * Display all cpu states and any other cpum info.
1367 *
1368 * @param pVM VM Handle.
1369 * @param pHlp The info helper functions.
1370 * @param pszArgs Arguments, ignored.
1371 */
1372static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1373{
1374 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1375 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1376 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1377 cpumR3InfoHost(pVM, pHlp, pszArgs);
1378}
1379
1380
1381/**
1382 * Parses the info argument.
1383 *
1384 * The argument starts with 'verbose', 'terse' or 'default' and then
1385 * continues with the comment string.
1386 *
1387 * @param pszArgs The pointer to the argument string.
1388 * @param penmType Where to store the dump type request.
1389 * @param ppszComment Where to store the pointer to the comment string.
1390 */
1391static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1392{
1393 if (!pszArgs)
1394 {
1395 *penmType = CPUMDUMPTYPE_DEFAULT;
1396 *ppszComment = "";
1397 }
1398 else
1399 {
1400 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1401 {
1402 pszArgs += 5;
1403 *penmType = CPUMDUMPTYPE_VERBOSE;
1404 }
1405 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1406 {
1407 pszArgs += 5;
1408 *penmType = CPUMDUMPTYPE_TERSE;
1409 }
1410 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1411 {
1412 pszArgs += 7;
1413 *penmType = CPUMDUMPTYPE_DEFAULT;
1414 }
1415 else
1416 *penmType = CPUMDUMPTYPE_DEFAULT;
1417 *ppszComment = RTStrStripL(pszArgs);
1418 }
1419}
1420
1421
1422/**
1423 * Display the guest cpu state.
1424 *
1425 * @param pVM VM Handle.
1426 * @param pHlp The info helper functions.
1427 * @param pszArgs Arguments, ignored.
1428 */
1429static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1430{
1431 CPUMDUMPTYPE enmType;
1432 const char *pszComment;
1433 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1434
1435 /* @todo SMP support! */
1436 PVMCPU pVCpu = VMMGetCpu(pVM);
1437 if (!pVCpu)
1438 pVCpu = &pVM->aCpus[0];
1439
1440 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1441
1442 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1443 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1444}
1445
1446
1447/**
1448 * Display the current guest instruction
1449 *
1450 * @param pVM VM Handle.
1451 * @param pHlp The info helper functions.
1452 * @param pszArgs Arguments, ignored.
1453 */
1454static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1455{
1456 char szInstruction[256];
1457 /* @todo SMP support! */
1458 PVMCPU pVCpu = VMMGetCpu(pVM);
1459 if (!pVCpu)
1460 pVCpu = &pVM->aCpus[0];
1461
1462 int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1463 if (RT_SUCCESS(rc))
1464 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1465}
1466
1467
1468/**
1469 * Display the hypervisor cpu state.
1470 *
1471 * @param pVM VM Handle.
1472 * @param pHlp The info helper functions.
1473 * @param pszArgs Arguments, ignored.
1474 */
1475static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1476{
1477 CPUMDUMPTYPE enmType;
1478 const char *pszComment;
1479 /* @todo SMP */
1480 PVMCPU pVCpu = &pVM->aCpus[0];
1481
1482 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1483 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1484 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1485 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1486}
1487
1488
1489/**
1490 * Display the host cpu state.
1491 *
1492 * @param pVM VM Handle.
1493 * @param pHlp The info helper functions.
1494 * @param pszArgs Arguments, ignored.
1495 */
1496static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1497{
1498 CPUMDUMPTYPE enmType;
1499 const char *pszComment;
1500 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1501 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1502
1503 /*
1504 * Format the EFLAGS.
1505 */
1506 /* @todo SMP */
1507 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1508#if HC_ARCH_BITS == 32
1509 uint32_t efl = pCtx->eflags.u32;
1510#else
1511 uint64_t efl = pCtx->rflags;
1512#endif
1513 char szEFlags[80];
1514 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1515
1516 /*
1517 * Format the registers.
1518 */
1519#if HC_ARCH_BITS == 32
1520# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1521 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1522# endif
1523 {
1524 pHlp->pfnPrintf(pHlp,
1525 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1526 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1527 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1528 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1529 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1530 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1531 ,
1532 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1533 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1534 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1535 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1536 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1537 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1538 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1539 }
1540# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1541 else
1542# endif
1543#endif
1544#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1545 {
1546 pHlp->pfnPrintf(pHlp,
1547 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1548 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1549 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1550 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1551 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1552 "r14=%016RX64 r15=%016RX64\n"
1553 "iopl=%d %31s\n"
1554 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1555 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1556 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1557 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1558 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1559 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1560 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1561 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1562 ,
1563 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1564 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1565 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1566 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1567 pCtx->r11, pCtx->r12, pCtx->r13,
1568 pCtx->r14, pCtx->r15,
1569 X86_EFL_GET_IOPL(efl), szEFlags,
1570 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1571 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1572 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1573 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1574 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1575 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1576 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1577 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1578 }
1579#endif
1580}
1581
1582
1583/**
1584 * Get L1 cache / TLS associativity.
1585 */
1586static const char *getCacheAss(unsigned u, char *pszBuf)
1587{
1588 if (u == 0)
1589 return "res0 ";
1590 if (u == 1)
1591 return "direct";
1592 if (u >= 256)
1593 return "???";
1594
1595 RTStrPrintf(pszBuf, 16, "%d way", u);
1596 return pszBuf;
1597}
1598
1599
1600/**
1601 * Get L2 cache soociativity.
1602 */
1603const char *getL2CacheAss(unsigned u)
1604{
1605 switch (u)
1606 {
1607 case 0: return "off ";
1608 case 1: return "direct";
1609 case 2: return "2 way ";
1610 case 3: return "res3 ";
1611 case 4: return "4 way ";
1612 case 5: return "res5 ";
1613 case 6: return "8 way "; case 7: return "res7 ";
1614 case 8: return "16 way";
1615 case 9: return "res9 ";
1616 case 10: return "res10 ";
1617 case 11: return "res11 ";
1618 case 12: return "res12 ";
1619 case 13: return "res13 ";
1620 case 14: return "res14 ";
1621 case 15: return "fully ";
1622 default:
1623 return "????";
1624 }
1625}
1626
1627
1628/**
1629 * Display the guest CpuId leaves.
1630 *
1631 * @param pVM VM Handle.
1632 * @param pHlp The info helper functions.
1633 * @param pszArgs "terse", "default" or "verbose".
1634 */
1635static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1636{
1637 /*
1638 * Parse the argument.
1639 */
1640 unsigned iVerbosity = 1;
1641 if (pszArgs)
1642 {
1643 pszArgs = RTStrStripL(pszArgs);
1644 if (!strcmp(pszArgs, "terse"))
1645 iVerbosity--;
1646 else if (!strcmp(pszArgs, "verbose"))
1647 iVerbosity++;
1648 }
1649
1650 /*
1651 * Start cracking.
1652 */
1653 CPUMCPUID Host;
1654 CPUMCPUID Guest;
1655 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1656
1657 pHlp->pfnPrintf(pHlp,
1658 " RAW Standard CPUIDs\n"
1659 " Function eax ebx ecx edx\n");
1660 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1661 {
1662 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1663 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1664
1665 pHlp->pfnPrintf(pHlp,
1666 "Gst: %08x %08x %08x %08x %08x%s\n"
1667 "Hst: %08x %08x %08x %08x\n",
1668 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1669 i <= cStdMax ? "" : "*",
1670 Host.eax, Host.ebx, Host.ecx, Host.edx);
1671 }
1672
1673 /*
1674 * If verbose, decode it.
1675 */
1676 if (iVerbosity)
1677 {
1678 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1679 pHlp->pfnPrintf(pHlp,
1680 "Name: %.04s%.04s%.04s\n"
1681 "Supports: 0-%x\n",
1682 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1683 }
1684
1685 /*
1686 * Get Features.
1687 */
1688 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1689 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1690 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1691 if (cStdMax >= 1 && iVerbosity)
1692 {
1693 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1694 uint32_t uEAX = Guest.eax;
1695
1696 pHlp->pfnPrintf(pHlp,
1697 "Family: %d \tExtended: %d \tEffective: %d\n"
1698 "Model: %d \tExtended: %d \tEffective: %d\n"
1699 "Stepping: %d\n"
1700 "APIC ID: %#04x\n"
1701 "Logical CPUs: %d\n"
1702 "CLFLUSH Size: %d\n"
1703 "Brand ID: %#04x\n",
1704 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1705 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1706 ASMGetCpuStepping(uEAX),
1707 (Guest.ebx >> 24) & 0xff,
1708 (Guest.ebx >> 16) & 0xff,
1709 (Guest.ebx >> 8) & 0xff,
1710 (Guest.ebx >> 0) & 0xff);
1711 if (iVerbosity == 1)
1712 {
1713 uint32_t uEDX = Guest.edx;
1714 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1715 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1716 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1717 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1718 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1719 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1720 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1721 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1722 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1723 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1724 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1725 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1726 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1727 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1728 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1729 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1730 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1731 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1732 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1733 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1734 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1735 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1736 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1737 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1738 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1739 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1740 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1741 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1742 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1743 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1744 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1745 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1746 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1747 pHlp->pfnPrintf(pHlp, "\n");
1748
1749 uint32_t uECX = Guest.ecx;
1750 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1751 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1752 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1753 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1754 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1755 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1756 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1757 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1758 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1759 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1760 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1761 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1762 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1763 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1764 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1765 for (unsigned iBit = 14; iBit < 32; iBit++)
1766 if (uECX & RT_BIT(iBit))
1767 pHlp->pfnPrintf(pHlp, " %d", iBit);
1768 pHlp->pfnPrintf(pHlp, "\n");
1769 }
1770 else
1771 {
1772 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1773
1774 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1775 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1776 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1777 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1778
1779 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1780 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1781 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1782 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1783 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1784 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1785 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1786 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1787 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1788 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1789 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1790 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1791 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1792 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1793 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1794 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1795 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1796 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1797 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1798 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1799 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1800 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1801 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1802 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1803 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1804 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1805 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1806 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1807 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1808 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1809 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1810 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1811 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1812
1813 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1814 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1815 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1816 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1817 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1818 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1819 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1820 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1821 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1822 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1823 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1824 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1825 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1826 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1827 }
1828 }
1829 if (cStdMax >= 2 && iVerbosity)
1830 {
1831 /** @todo */
1832 }
1833
1834 /*
1835 * Extended.
1836 * Implemented after AMD specs.
1837 */
1838 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1839
1840 pHlp->pfnPrintf(pHlp,
1841 "\n"
1842 " RAW Extended CPUIDs\n"
1843 " Function eax ebx ecx edx\n");
1844 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1845 {
1846 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1847 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1848
1849 pHlp->pfnPrintf(pHlp,
1850 "Gst: %08x %08x %08x %08x %08x%s\n"
1851 "Hst: %08x %08x %08x %08x\n",
1852 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1853 i <= cExtMax ? "" : "*",
1854 Host.eax, Host.ebx, Host.ecx, Host.edx);
1855 }
1856
1857 /*
1858 * Understandable output
1859 */
1860 if (iVerbosity)
1861 {
1862 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1863 pHlp->pfnPrintf(pHlp,
1864 "Ext Name: %.4s%.4s%.4s\n"
1865 "Ext Supports: 0x80000000-%#010x\n",
1866 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1867 }
1868
1869 if (iVerbosity && cExtMax >= 1)
1870 {
1871 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1872 uint32_t uEAX = Guest.eax;
1873 pHlp->pfnPrintf(pHlp,
1874 "Family: %d \tExtended: %d \tEffective: %d\n"
1875 "Model: %d \tExtended: %d \tEffective: %d\n"
1876 "Stepping: %d\n"
1877 "Brand ID: %#05x\n",
1878 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1879 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1880 ASMGetCpuStepping(uEAX),
1881 Guest.ebx & 0xfff);
1882
1883 if (iVerbosity == 1)
1884 {
1885 uint32_t uEDX = Guest.edx;
1886 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1887 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1888 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1889 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1890 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1891 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1892 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1893 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1894 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1895 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1896 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1897 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1898 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1899 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1900 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1901 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1902 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1903 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1904 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1905 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1906 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1907 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1908 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1909 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1910 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1911 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1912 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1913 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1914 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1915 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1916 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1917 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1918 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1919 pHlp->pfnPrintf(pHlp, "\n");
1920
1921 uint32_t uECX = Guest.ecx;
1922 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1923 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1924 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1925 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1926 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1927 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1928 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1929 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1930 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1931 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1932 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1933 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1934 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1935 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1936 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1937 for (unsigned iBit = 5; iBit < 32; iBit++)
1938 if (uECX & RT_BIT(iBit))
1939 pHlp->pfnPrintf(pHlp, " %d", iBit);
1940 pHlp->pfnPrintf(pHlp, "\n");
1941 }
1942 else
1943 {
1944 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1945
1946 uint32_t uEdxGst = Guest.edx;
1947 uint32_t uEdxHst = Host.edx;
1948 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1949 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1950 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1951 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1952 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1953 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1954 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1955 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1956 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1957 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1958 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1959 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1960 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1961 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1962 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1963 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1964 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1965 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1966 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1967 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1968 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1969 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1970 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1971 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1972 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1973 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1974 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1975 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1976 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1977 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1978 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1979 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1980 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1981
1982 uint32_t uEcxGst = Guest.ecx;
1983 uint32_t uEcxHst = Host.ecx;
1984 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1985 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1986 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1987 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1988 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1989 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1990 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1991 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1992 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1993 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1994 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1995 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1996 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1997 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1998 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1999 }
2000 }
2001
2002 if (iVerbosity && cExtMax >= 2)
2003 {
2004 char szString[4*4*3+1] = {0};
2005 uint32_t *pu32 = (uint32_t *)szString;
2006 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
2007 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
2008 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
2009 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
2010 if (cExtMax >= 3)
2011 {
2012 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
2013 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
2014 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
2015 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
2016 }
2017 if (cExtMax >= 4)
2018 {
2019 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
2020 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
2021 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
2022 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
2023 }
2024 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
2025 }
2026
2027 if (iVerbosity && cExtMax >= 5)
2028 {
2029 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
2030 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
2031 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
2032 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2033 char sz1[32];
2034 char sz2[32];
2035
2036 pHlp->pfnPrintf(pHlp,
2037 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2038 "TLB 2/4M Data: %s %3d entries\n",
2039 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2040 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2041 pHlp->pfnPrintf(pHlp,
2042 "TLB 4K Instr/Uni: %s %3d entries\n"
2043 "TLB 4K Data: %s %3d entries\n",
2044 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2045 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2046 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2047 "L1 Instr Cache Lines Per Tag: %d\n"
2048 "L1 Instr Cache Associativity: %s\n"
2049 "L1 Instr Cache Size: %d KB\n",
2050 (uEDX >> 0) & 0xff,
2051 (uEDX >> 8) & 0xff,
2052 getCacheAss((uEDX >> 16) & 0xff, sz1),
2053 (uEDX >> 24) & 0xff);
2054 pHlp->pfnPrintf(pHlp,
2055 "L1 Data Cache Line Size: %d bytes\n"
2056 "L1 Data Cache Lines Per Tag: %d\n"
2057 "L1 Data Cache Associativity: %s\n"
2058 "L1 Data Cache Size: %d KB\n",
2059 (uECX >> 0) & 0xff,
2060 (uECX >> 8) & 0xff,
2061 getCacheAss((uECX >> 16) & 0xff, sz1),
2062 (uECX >> 24) & 0xff);
2063 }
2064
2065 if (iVerbosity && cExtMax >= 6)
2066 {
2067 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2068 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2069 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2070
2071 pHlp->pfnPrintf(pHlp,
2072 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2073 "L2 TLB 2/4M Data: %s %4d entries\n",
2074 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2075 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2076 pHlp->pfnPrintf(pHlp,
2077 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2078 "L2 TLB 4K Data: %s %4d entries\n",
2079 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2080 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2081 pHlp->pfnPrintf(pHlp,
2082 "L2 Cache Line Size: %d bytes\n"
2083 "L2 Cache Lines Per Tag: %d\n"
2084 "L2 Cache Associativity: %s\n"
2085 "L2 Cache Size: %d KB\n",
2086 (uEDX >> 0) & 0xff,
2087 (uEDX >> 8) & 0xf,
2088 getL2CacheAss((uEDX >> 12) & 0xf),
2089 (uEDX >> 16) & 0xffff);
2090 }
2091
2092 if (iVerbosity && cExtMax >= 7)
2093 {
2094 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2095
2096 pHlp->pfnPrintf(pHlp, "APM Features: ");
2097 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2098 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2099 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2100 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2101 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2102 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2103 for (unsigned iBit = 6; iBit < 32; iBit++)
2104 if (uEDX & RT_BIT(iBit))
2105 pHlp->pfnPrintf(pHlp, " %d", iBit);
2106 pHlp->pfnPrintf(pHlp, "\n");
2107 }
2108
2109 if (iVerbosity && cExtMax >= 8)
2110 {
2111 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2112 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2113
2114 pHlp->pfnPrintf(pHlp,
2115 "Physical Address Width: %d bits\n"
2116 "Virtual Address Width: %d bits\n",
2117 (uEAX >> 0) & 0xff,
2118 (uEAX >> 8) & 0xff);
2119 pHlp->pfnPrintf(pHlp,
2120 "Physical Core Count: %d\n",
2121 (uECX >> 0) & 0xff);
2122 }
2123
2124
2125 /*
2126 * Centaur.
2127 */
2128 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2129
2130 pHlp->pfnPrintf(pHlp,
2131 "\n"
2132 " RAW Centaur CPUIDs\n"
2133 " Function eax ebx ecx edx\n");
2134 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2135 {
2136 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2137 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2138
2139 pHlp->pfnPrintf(pHlp,
2140 "Gst: %08x %08x %08x %08x %08x%s\n"
2141 "Hst: %08x %08x %08x %08x\n",
2142 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2143 i <= cCentaurMax ? "" : "*",
2144 Host.eax, Host.ebx, Host.ecx, Host.edx);
2145 }
2146
2147 /*
2148 * Understandable output
2149 */
2150 if (iVerbosity)
2151 {
2152 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2153 pHlp->pfnPrintf(pHlp,
2154 "Centaur Supports: 0xc0000000-%#010x\n",
2155 Guest.eax);
2156 }
2157
2158 if (iVerbosity && cCentaurMax >= 1)
2159 {
2160 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2161 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2162 uint32_t uEdxHst = Host.edx;
2163
2164 if (iVerbosity == 1)
2165 {
2166 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2167 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2168 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2169 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2170 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2171 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2172 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2173 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2174 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2175 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2176 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2177 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2178 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2179 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2180 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2181 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2182 for (unsigned iBit = 14; iBit < 32; iBit++)
2183 if (uEdxGst & RT_BIT(iBit))
2184 pHlp->pfnPrintf(pHlp, " %d", iBit);
2185 pHlp->pfnPrintf(pHlp, "\n");
2186 }
2187 else
2188 {
2189 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2190 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2191 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2192 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2193 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2194 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2195 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2196 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2197 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2198 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2199 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2200 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2201 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2202 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2203 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2204 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2205 for (unsigned iBit = 14; iBit < 32; iBit++)
2206 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2207 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2208 pHlp->pfnPrintf(pHlp, "\n");
2209 }
2210 }
2211}
2212
2213
2214/**
2215 * Structure used when disassembling and instructions in DBGF.
2216 * This is used so the reader function can get the stuff it needs.
2217 */
2218typedef struct CPUMDISASSTATE
2219{
2220 /** Pointer to the CPU structure. */
2221 PDISCPUSTATE pCpu;
2222 /** The VM handle. */
2223 PVM pVM;
2224 /** The VMCPU handle. */
2225 PVMCPU pVCpu;
2226 /** Pointer to the first byte in the segemnt. */
2227 RTGCUINTPTR GCPtrSegBase;
2228 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2229 RTGCUINTPTR GCPtrSegEnd;
2230 /** The size of the segment minus 1. */
2231 RTGCUINTPTR cbSegLimit;
2232 /** Pointer to the current page - R3 Ptr. */
2233 void const *pvPageR3;
2234 /** Pointer to the current page - GC Ptr. */
2235 RTGCPTR pvPageGC;
2236 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2237 PGMPAGEMAPLOCK PageMapLock;
2238 /** Whether the PageMapLock is valid or not. */
2239 bool fLocked;
2240 /** 64 bits mode or not. */
2241 bool f64Bits;
2242} CPUMDISASSTATE, *PCPUMDISASSTATE;
2243
2244
2245/**
2246 * Instruction reader.
2247 *
2248 * @returns VBox status code.
2249 * @param PtrSrc Address to read from.
2250 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2251 * @param pu8Dst Where to store the bytes.
2252 * @param cbRead Number of bytes to read.
2253 * @param uDisCpu Pointer to the disassembler cpu state.
2254 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2255 */
2256static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2257{
2258 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2259 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2260 Assert(cbRead > 0);
2261 for (;;)
2262 {
2263 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2264
2265 /* Need to update the page translation? */
2266 if ( !pState->pvPageR3
2267 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2268 {
2269 int rc = VINF_SUCCESS;
2270
2271 /* translate the address */
2272 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2273 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2274 && !HWACCMIsEnabled(pState->pVM))
2275 {
2276 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2277 if (!pState->pvPageR3)
2278 rc = VERR_INVALID_POINTER;
2279 }
2280 else
2281 {
2282 /* Release mapping lock previously acquired. */
2283 if (pState->fLocked)
2284 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2285 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2286 pState->fLocked = RT_SUCCESS_NP(rc);
2287 }
2288 if (RT_FAILURE(rc))
2289 {
2290 pState->pvPageR3 = NULL;
2291 return rc;
2292 }
2293 }
2294
2295 /* check the segemnt limit */
2296 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2297 return VERR_OUT_OF_SELECTOR_BOUNDS;
2298
2299 /* calc how much we can read */
2300 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2301 if (!pState->f64Bits)
2302 {
2303 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2304 if (cb > cbSeg && cbSeg)
2305 cb = cbSeg;
2306 }
2307 if (cb > cbRead)
2308 cb = cbRead;
2309
2310 /* read and advance */
2311 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2312 cbRead -= cb;
2313 if (!cbRead)
2314 return VINF_SUCCESS;
2315 pu8Dst += cb;
2316 PtrSrc += cb;
2317 }
2318}
2319
2320
2321/**
2322 * Disassemble an instruction and return the information in the provided structure.
2323 *
2324 * @returns VBox status code.
2325 * @param pVM VM Handle
2326 * @param pVCpu VMCPU Handle
2327 * @param pCtx CPU context
2328 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2329 * @param pCpu Disassembly state
2330 * @param pszPrefix String prefix for logging (debug only)
2331 *
2332 */
2333VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2334{
2335 CPUMDISASSTATE State;
2336 int rc;
2337
2338 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2339 State.pCpu = pCpu;
2340 State.pvPageGC = 0;
2341 State.pvPageR3 = NULL;
2342 State.pVM = pVM;
2343 State.pVCpu = pVCpu;
2344 State.fLocked = false;
2345 State.f64Bits = false;
2346
2347 /*
2348 * Get selector information.
2349 */
2350 if ( (pCtx->cr0 & X86_CR0_PE)
2351 && pCtx->eflags.Bits.u1VM == 0)
2352 {
2353 if (CPUMAreHiddenSelRegsValid(pVM))
2354 {
2355 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2356 State.GCPtrSegBase = pCtx->csHid.u64Base;
2357 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2358 State.cbSegLimit = pCtx->csHid.u32Limit;
2359 pCpu->mode = (State.f64Bits)
2360 ? CPUMODE_64BIT
2361 : pCtx->csHid.Attr.n.u1DefBig
2362 ? CPUMODE_32BIT
2363 : CPUMODE_16BIT;
2364 }
2365 else
2366 {
2367 DBGFSELINFO SelInfo;
2368
2369 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2370 if (RT_FAILURE(rc))
2371 {
2372 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2373 return rc;
2374 }
2375
2376 /*
2377 * Validate the selector.
2378 */
2379 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2380 if (RT_FAILURE(rc))
2381 {
2382 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2383 return rc;
2384 }
2385 State.GCPtrSegBase = SelInfo.GCPtrBase;
2386 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2387 State.cbSegLimit = SelInfo.cbLimit;
2388 pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2389 }
2390 }
2391 else
2392 {
2393 /* real or V86 mode */
2394 pCpu->mode = CPUMODE_16BIT;
2395 State.GCPtrSegBase = pCtx->cs * 16;
2396 State.GCPtrSegEnd = 0xFFFFFFFF;
2397 State.cbSegLimit = 0xFFFFFFFF;
2398 }
2399
2400 /*
2401 * Disassemble the instruction.
2402 */
2403 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2404 pCpu->apvUserData[0] = &State;
2405
2406 uint32_t cbInstr;
2407#ifndef LOG_ENABLED
2408 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2409 if (RT_SUCCESS(rc))
2410 {
2411#else
2412 char szOutput[160];
2413 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2414 if (RT_SUCCESS(rc))
2415 {
2416 /* log it */
2417 if (pszPrefix)
2418 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2419 else
2420 Log(("%s", szOutput));
2421#endif
2422 rc = VINF_SUCCESS;
2423 }
2424 else
2425 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2426
2427 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2428 if (State.fLocked)
2429 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2430
2431 return rc;
2432}
2433
2434#ifdef DEBUG
2435
2436/**
2437 * Disassemble an instruction and dump it to the log
2438 *
2439 * @returns VBox status code.
2440 * @param pVM VM Handle
2441 * @param pVCpu VMCPU Handle
2442 * @param pCtx CPU context
2443 * @param pc GC instruction pointer
2444 * @param pszPrefix String prefix for logging
2445 *
2446 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2447 */
2448VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2449{
2450 DISCPUSTATE Cpu;
2451 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2452}
2453
2454
2455/**
2456 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2457 *
2458 * @internal
2459 */
2460VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2461{
2462 /* @todo SMP support!! */
2463 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2464}
2465
2466#endif /* DEBUG */
2467
2468/**
2469 * API for controlling a few of the CPU features found in CR4.
2470 *
2471 * Currently only X86_CR4_TSD is accepted as input.
2472 *
2473 * @returns VBox status code.
2474 *
2475 * @param pVM The VM handle.
2476 * @param fOr The CR4 OR mask.
2477 * @param fAnd The CR4 AND mask.
2478 */
2479VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2480{
2481 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2482 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2483
2484 pVM->cpum.s.CR4.OrMask &= fAnd;
2485 pVM->cpum.s.CR4.OrMask |= fOr;
2486
2487 return VINF_SUCCESS;
2488}
2489
2490
2491/**
2492 * Gets a pointer to the array of standard CPUID leafs.
2493 *
2494 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2495 *
2496 * @returns Pointer to the standard CPUID leafs (read-only).
2497 * @param pVM The VM handle.
2498 * @remark Intended for PATM.
2499 */
2500VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2501{
2502 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2503}
2504
2505
2506/**
2507 * Gets a pointer to the array of extended CPUID leafs.
2508 *
2509 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2510 *
2511 * @returns Pointer to the extended CPUID leafs (read-only).
2512 * @param pVM The VM handle.
2513 * @remark Intended for PATM.
2514 */
2515VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2516{
2517 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2518}
2519
2520
2521/**
2522 * Gets a pointer to the array of centaur CPUID leafs.
2523 *
2524 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2525 *
2526 * @returns Pointer to the centaur CPUID leafs (read-only).
2527 * @param pVM The VM handle.
2528 * @remark Intended for PATM.
2529 */
2530VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2531{
2532 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2533}
2534
2535
2536/**
2537 * Gets a pointer to the default CPUID leaf.
2538 *
2539 * @returns Pointer to the default CPUID leaf (read-only).
2540 * @param pVM The VM handle.
2541 * @remark Intended for PATM.
2542 */
2543VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2544{
2545 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2546}
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