VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 19420

Last change on this file since 19420 was 19403, checked in by vboxsync, 15 years ago

VBox/parma.h,VMM: VMCPU_MAX_CPU_COUNT & VMM_MAX_CPUS => VMM_MAX_CPU_COUNT, added VMM_MIN_CPU_COUNT for schema future replacement dropping a hint about these constants Main.
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File size: 113.1 KB
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1/* $Id: CPUM.cpp 19403 2009-05-05 22:23:42Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertCompileMemberAlignment(VM, cpum.s, 32);
125 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126 AssertCompileSizeAlignment(CPUMCTX, 64);
127 AssertCompileSizeAlignment(CPUMCTXMSR, 64);
128 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
129 AssertCompileMemberAlignment(VM, cpum, 64);
130 AssertCompileMemberAlignment(VM, aCpus, 64);
131 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
132 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
133
134 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
135 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
136 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
137
138 /* Calculate the offset from CPUMCPU to CPUM. */
139 for (unsigned i=0;i<pVM->cCPUs;i++)
140 {
141 PVMCPU pVCpu = &pVM->aCpus[i];
142
143 /*
144 * Setup any fixed pointers and offsets.
145 */
146 pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
147 pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
148
149 pVCpu->cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
150 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
151 }
152
153 /*
154 * Check that the CPU supports the minimum features we require.
155 */
156 if (!ASMHasCpuId())
157 {
158 Log(("The CPU doesn't support CPUID!\n"));
159 return VERR_UNSUPPORTED_CPU;
160 }
161 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
162 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
163
164 /* Setup the CR4 AND and OR masks used in the switcher */
165 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
167 {
168 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
169 /* No FXSAVE implies no SSE */
170 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
171 pVM->cpum.s.CR4.OrMask = 0;
172 }
173 else
174 {
175 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
176 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
177 }
178
179 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
180 {
181 Log(("The CPU doesn't support MMX!\n"));
182 return VERR_UNSUPPORTED_CPU;
183 }
184 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
185 {
186 Log(("The CPU doesn't support TSC!\n"));
187 return VERR_UNSUPPORTED_CPU;
188 }
189 /* Bogus on AMD? */
190 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
191 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
192
193 /*
194 * Setup hypervisor startup values.
195 */
196
197 /*
198 * Register saved state data item.
199 */
200 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
201 NULL, cpumR3Save, NULL,
202 NULL, cpumR3Load, NULL);
203 if (RT_FAILURE(rc))
204 return rc;
205
206 /* Query the CPU manufacturer. */
207 uint32_t uEAX, uEBX, uECX, uEDX;
208 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
209 if ( uEAX >= 1
210 && uEBX == X86_CPUID_VENDOR_AMD_EBX
211 && uECX == X86_CPUID_VENDOR_AMD_ECX
212 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
213 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
214 else if ( uEAX >= 1
215 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
216 && uECX == X86_CPUID_VENDOR_INTEL_ECX
217 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
218 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
219 else /** @todo Via */
220 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
221
222 /*
223 * Register info handlers.
224 */
225 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
226 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
227 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
228 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
229 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
230 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
231
232 /*
233 * Initialize the Guest CPU state.
234 */
235 rc = cpumR3CpuIdInit(pVM);
236 if (RT_FAILURE(rc))
237 return rc;
238 CPUMR3Reset(pVM);
239 return VINF_SUCCESS;
240}
241
242
243/**
244 * Initializes the per-VCPU CPUM.
245 *
246 * @returns VBox status code.
247 * @param pVM The VM to operate on.
248 */
249VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
250{
251 LogFlow(("CPUMR3InitCPU\n"));
252 return VINF_SUCCESS;
253}
254
255
256/**
257 * Initializes the emulated CPU's cpuid information.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262static int cpumR3CpuIdInit(PVM pVM)
263{
264 PCPUM pCPUM = &pVM->cpum.s;
265 uint32_t i;
266
267 /*
268 * Get the host CPUIDs.
269 */
270 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
271 ASMCpuId_Idx_ECX(i, 0,
272 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
273 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
274 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
275 ASMCpuId(0x80000000 + i,
276 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
277 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
278 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
279 ASMCpuId(0xc0000000 + i,
280 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
281 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
282
283
284 /*
285 * Only report features we can support.
286 */
287 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
288 | X86_CPUID_FEATURE_EDX_VME
289 | X86_CPUID_FEATURE_EDX_DE
290 | X86_CPUID_FEATURE_EDX_PSE
291 | X86_CPUID_FEATURE_EDX_TSC
292 | X86_CPUID_FEATURE_EDX_MSR
293 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
294 | X86_CPUID_FEATURE_EDX_MCE
295 | X86_CPUID_FEATURE_EDX_CX8
296 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
297 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
298 //| X86_CPUID_FEATURE_EDX_SEP
299 | X86_CPUID_FEATURE_EDX_MTRR
300 | X86_CPUID_FEATURE_EDX_PGE
301 | X86_CPUID_FEATURE_EDX_MCA
302 | X86_CPUID_FEATURE_EDX_CMOV
303 | X86_CPUID_FEATURE_EDX_PAT
304 | X86_CPUID_FEATURE_EDX_PSE36
305 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
306 | X86_CPUID_FEATURE_EDX_CLFSH
307 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
308 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
309 | X86_CPUID_FEATURE_EDX_MMX
310 | X86_CPUID_FEATURE_EDX_FXSR
311 | X86_CPUID_FEATURE_EDX_SSE
312 | X86_CPUID_FEATURE_EDX_SSE2
313 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
314 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
315 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
316 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
317 | 0;
318 pCPUM->aGuestCpuIdStd[1].ecx &= 0
319 | X86_CPUID_FEATURE_ECX_SSE3
320 | X86_CPUID_FEATURE_ECX_MONITOR
321 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
322 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
323 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
324 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
325 //| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
326 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
327 //| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
328 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
329 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
330 /* ECX Bit 21 - x2APIC support - not yet. */
331 // | X86_CPUID_FEATURE_ECX_X2APIC
332 /* ECX Bit 23 - POPCOUNT instruction. */
333 //| X86_CPUID_FEATURE_ECX_POPCOUNT
334 | 0;
335
336 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
337 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
338 | X86_CPUID_AMD_FEATURE_EDX_VME
339 | X86_CPUID_AMD_FEATURE_EDX_DE
340 | X86_CPUID_AMD_FEATURE_EDX_PSE
341 | X86_CPUID_AMD_FEATURE_EDX_TSC
342 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
343 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
344 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
345 | X86_CPUID_AMD_FEATURE_EDX_CX8
346 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
347 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
348 //| X86_CPUID_AMD_FEATURE_EDX_SEP
349 | X86_CPUID_AMD_FEATURE_EDX_MTRR
350 | X86_CPUID_AMD_FEATURE_EDX_PGE
351 | X86_CPUID_AMD_FEATURE_EDX_MCA
352 | X86_CPUID_AMD_FEATURE_EDX_CMOV
353 | X86_CPUID_AMD_FEATURE_EDX_PAT
354 | X86_CPUID_AMD_FEATURE_EDX_PSE36
355 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
356 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
357 | X86_CPUID_AMD_FEATURE_EDX_MMX
358 | X86_CPUID_AMD_FEATURE_EDX_FXSR
359 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
360 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
361 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
362 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
363 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
364 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
365 | 0;
366 pCPUM->aGuestCpuIdExt[1].ecx &= 0
367 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
368 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
369 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
370 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
371 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
372 //| X86_CPUID_AMD_FEATURE_ECX_ABM
373 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
374 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
375 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
376 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
377 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
378 //| X86_CPUID_AMD_FEATURE_ECX_WDT
379 | 0;
380
381 /*
382 * Hide HTT, multicode, SMP, whatever.
383 * (APIC-ID := 0 and #LogCpus := 0)
384 */
385 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
386#ifdef VBOX_WITH_MULTI_CORE
387 /* Set the Maximum number of addressable IDs for logical processors in this physical package (bits 16-23) */
388 pCPUM->aGuestCpuIdStd[1].ebx |= ((pVM->cCPUs - 1) << 16);
389
390 if (pVM->cCPUs > 1)
391 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
392#endif
393
394 /* Cpuid 2:
395 * Intel: Cache and TLB information
396 * AMD: Reserved
397 * Safe to expose
398 */
399
400 /* Cpuid 3:
401 * Intel: EAX, EBX - reserved
402 * ECX, EDX - Processor Serial Number if available, otherwise reserved
403 * AMD: Reserved
404 * Safe to expose
405 */
406 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
407 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
408
409 /* Cpuid 4:
410 * Intel: Deterministic Cache Parameters Leaf
411 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
412 * AMD: Reserved
413 * Safe to expose, except for EAX:
414 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
415 * Bits 31-26: Maximum number of processor cores in this physical package**
416 * @Note These SMP values are constant regardless of ECX
417 */
418 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
419 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
420#ifdef VBOX_WITH_MULTI_CORE
421 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_INTEL)
422 {
423 /* One logical processor with possibly multiple cores. */
424 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCPUs - 1) << 26); /* 6 bits only -> 64 cores! */
425 }
426#endif
427
428 /* Cpuid 5: Monitor/mwait Leaf
429 * Intel: ECX, EDX - reserved
430 * EAX, EBX - Smallest and largest monitor line size
431 * AMD: EDX - reserved
432 * EAX, EBX - Smallest and largest monitor line size
433 * ECX - extensions (ignored for now)
434 * Safe to expose
435 */
436 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
437 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
438
439 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
440
441 /*
442 * Determine the default.
443 *
444 * Intel returns values of the highest standard function, while AMD
445 * returns zeros. VIA on the other hand seems to returning nothing or
446 * perhaps some random garbage, we don't try to duplicate this behavior.
447 */
448 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
449 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
450 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
451
452 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
453 * Safe to pass on to the guest.
454 *
455 * Intel: 0x800000005 reserved
456 * 0x800000006 L2 cache information
457 * AMD: 0x800000005 L1 cache information
458 * 0x800000006 L2/L3 cache information
459 */
460
461 /* Cpuid 0x800000007:
462 * AMD: EAX, EBX, ECX - reserved
463 * EDX: Advanced Power Management Information
464 * Intel: Reserved
465 */
466 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
467 {
468 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
469
470 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
471
472 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
473 {
474 /* Only expose the TSC invariant capability bit to the guest. */
475 pCPUM->aGuestCpuIdExt[7].edx &= 0
476 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
477 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
478 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
479 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
480 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
481 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
482 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
483 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
484 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
485 | 0;
486 }
487 else
488 pCPUM->aGuestCpuIdExt[7].edx = 0;
489 }
490
491 /* Cpuid 0x800000008:
492 * AMD: EBX, EDX - reserved
493 * EAX: Virtual/Physical address Size
494 * ECX: Number of cores + APICIdCoreIdSize
495 * Intel: EAX: Virtual/Physical address Size
496 * EBX, ECX, EDX - reserved
497 */
498 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
499 {
500 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
501 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
502 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
503 * NC (0-7) Number of cores; 0 equals 1 core */
504 pCPUM->aGuestCpuIdExt[8].ecx = 0;
505#ifdef VBOX_WITH_MULTI_CORE
506 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
507 {
508
509 }
510#endif
511 }
512
513 /*
514 * Limit it the number of entries and fill the remaining with the defaults.
515 *
516 * The limits are masking off stuff about power saving and similar, this
517 * is perhaps a bit crudely done as there is probably some relatively harmless
518 * info too in these leaves (like words about having a constant TSC).
519 */
520#if 0
521 /** @todo NT4 installation regression - investigate */
522 /** Note from Intel manuals:
523 * CPUID leaves > 3 < 80000000 are visible only when
524 * IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
525 *
526 */
527 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
528 pCPUM->aGuestCpuIdStd[0].eax = 5;
529#else
530 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
531 pCPUM->aGuestCpuIdStd[0].eax = 2;
532#endif
533 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
534 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
535
536 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
537 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
538 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
539 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
540 : 0;
541 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
542 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
543
544 /*
545 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
546 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
547 * We currently don't support more than 1 processor.
548 */
549 pCPUM->aGuestCpuIdStd[4].eax = 0;
550
551 /*
552 * Centaur stuff (VIA).
553 *
554 * The important part here (we think) is to make sure the 0xc0000000
555 * function returns 0xc0000001. As for the features, we don't currently
556 * let on about any of those... 0xc0000002 seems to be some
557 * temperature/hz/++ stuff, include it as well (static).
558 */
559 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
560 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
561 {
562 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
563 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
564 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
565 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
566 i++)
567 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
568 }
569 else
570 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
571 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
572
573
574 /*
575 * Load CPUID overrides from configuration.
576 */
577 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
578 * Overloads the CPUID leaf values. */
579 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
580 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
581 for (i=0;; )
582 {
583 while (cElements-- > 0)
584 {
585 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
586 if (pNode)
587 {
588 uint32_t u32;
589 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
590 if (RT_SUCCESS(rc))
591 pCpuId->eax = u32;
592 else
593 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
594
595 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
596 if (RT_SUCCESS(rc))
597 pCpuId->ebx = u32;
598 else
599 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
600
601 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
602 if (RT_SUCCESS(rc))
603 pCpuId->ecx = u32;
604 else
605 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
606
607 rc = CFGMR3QueryU32(pNode, "edx", &u32);
608 if (RT_SUCCESS(rc))
609 pCpuId->edx = u32;
610 else
611 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
612 }
613 pCpuId++;
614 i++;
615 }
616
617 /* next */
618 if ((i & UINT32_C(0xc0000000)) == 0)
619 {
620 pCpuId = &pCPUM->aGuestCpuIdExt[0];
621 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
622 i = UINT32_C(0x80000000);
623 }
624 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
625 {
626 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
627 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
628 i = UINT32_C(0xc0000000);
629 }
630 else
631 break;
632 }
633
634 /* Check if PAE was explicitely enabled by the user. */
635 bool fEnable = false;
636 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
637 if (RT_SUCCESS(rc) && fEnable)
638 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
639
640 /*
641 * Log the cpuid and we're good.
642 */
643 RTCPUSET OnlineSet;
644 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
645 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
646 LogRel(("************************* CPUID dump ************************\n"));
647 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
648 LogRel(("\n"));
649 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
650 LogRel(("******************** End of CPUID dump **********************\n"));
651 return VINF_SUCCESS;
652}
653
654
655
656
657/**
658 * Applies relocations to data and code managed by this
659 * component. This function will be called at init and
660 * whenever the VMM need to relocate it self inside the GC.
661 *
662 * The CPUM will update the addresses used by the switcher.
663 *
664 * @param pVM The VM.
665 */
666VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
667{
668 LogFlow(("CPUMR3Relocate\n"));
669 for (unsigned i=0;i<pVM->cCPUs;i++)
670 {
671 PVMCPU pVCpu = &pVM->aCpus[i];
672 /*
673 * Switcher pointers.
674 */
675 pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
676 Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
677 }
678}
679
680
681/**
682 * Terminates the CPUM.
683 *
684 * Termination means cleaning up and freeing all resources,
685 * the VM it self is at this point powered off or suspended.
686 *
687 * @returns VBox status code.
688 * @param pVM The VM to operate on.
689 */
690VMMR3DECL(int) CPUMR3Term(PVM pVM)
691{
692 CPUMR3TermCPU(pVM);
693 return 0;
694}
695
696
697/**
698 * Terminates the per-VCPU CPUM.
699 *
700 * Termination means cleaning up and freeing all resources,
701 * the VM it self is at this point powered off or suspended.
702 *
703 * @returns VBox status code.
704 * @param pVM The VM to operate on.
705 */
706VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
707{
708#ifdef VBOX_WITH_CRASHDUMP_MAGIC
709 for (unsigned i=0;i<pVM->cCPUs;i++)
710 {
711 PVMCPU pVCpu = &pVM->aCpus[i];
712 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
713
714 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
715 pVCpu->cpum.s.uMagic = 0;
716 pCtx->dr[5] = 0;
717 }
718#endif
719 return 0;
720}
721
722
723/**
724 * Resets the CPU.
725 *
726 * @returns VINF_SUCCESS.
727 * @param pVM The VM handle.
728 */
729VMMR3DECL(void) CPUMR3Reset(PVM pVM)
730{
731 /* @todo anything different for VCPU > 0? */
732 for (unsigned i=0;i<pVM->cCPUs;i++)
733 {
734 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
735
736 /*
737 * Initialize everything to ZERO first.
738 */
739 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
740 memset(pCtx, 0, sizeof(*pCtx));
741 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
742
743 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
744 pCtx->eip = 0x0000fff0;
745 pCtx->edx = 0x00000600; /* P6 processor */
746 pCtx->eflags.Bits.u1Reserved0 = 1;
747
748 pCtx->cs = 0xf000;
749 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
750 pCtx->csHid.u32Limit = 0x0000ffff;
751 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
752 pCtx->csHid.Attr.n.u1Present = 1;
753 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
754
755 pCtx->dsHid.u32Limit = 0x0000ffff;
756 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
757 pCtx->dsHid.Attr.n.u1Present = 1;
758 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
759
760 pCtx->esHid.u32Limit = 0x0000ffff;
761 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
762 pCtx->esHid.Attr.n.u1Present = 1;
763 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
764
765 pCtx->fsHid.u32Limit = 0x0000ffff;
766 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
767 pCtx->fsHid.Attr.n.u1Present = 1;
768 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
769
770 pCtx->gsHid.u32Limit = 0x0000ffff;
771 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
772 pCtx->gsHid.Attr.n.u1Present = 1;
773 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
774
775 pCtx->ssHid.u32Limit = 0x0000ffff;
776 pCtx->ssHid.Attr.n.u1Present = 1;
777 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
778 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
779
780 pCtx->idtr.cbIdt = 0xffff;
781 pCtx->gdtr.cbGdt = 0xffff;
782
783 pCtx->ldtrHid.u32Limit = 0xffff;
784 pCtx->ldtrHid.Attr.n.u1Present = 1;
785 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
786
787 pCtx->trHid.u32Limit = 0xffff;
788 pCtx->trHid.Attr.n.u1Present = 1;
789 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
790
791 pCtx->dr[6] = X86_DR6_INIT_VAL;
792 pCtx->dr[7] = X86_DR7_INIT_VAL;
793
794 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
795 pCtx->fpu.FCW = 0x37f;
796
797 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
798 pCtx->fpu.MXCSR = 0x1F80;
799
800 /* Init PAT MSR */
801 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
802
803 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
804 * The Intel docs don't mention it.
805 */
806 pCtx->msrEFER = 0;
807
808#ifdef VBOX_WITH_CRASHDUMP_MAGIC
809 /* Magic marker for searching in crash dumps. */
810 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
811 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
812 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
813#endif
814 }
815}
816
817
818/**
819 * Execute state save operation.
820 *
821 * @returns VBox status code.
822 * @param pVM VM Handle.
823 * @param pSSM SSM operation handle.
824 */
825static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
826{
827 /*
828 * Save.
829 */
830 for (unsigned i=0;i<pVM->cCPUs;i++)
831 {
832 PVMCPU pVCpu = &pVM->aCpus[i];
833
834 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
835 }
836
837 SSMR3PutU32(pSSM, pVM->cCPUs);
838 for (unsigned i=0;i<pVM->cCPUs;i++)
839 {
840 PVMCPU pVCpu = &pVM->aCpus[i];
841
842 SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
843 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
844 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
845 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
846 }
847
848 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
849 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
850
851 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
852 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
853
854 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
855 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
856
857 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
858
859 /* Add the cpuid for checking that the cpu is unchanged. */
860 uint32_t au32CpuId[8] = {0};
861 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
862 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
863 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
864}
865
866
867/**
868 * Load a version 1.6 CPUMCTX structure.
869 *
870 * @returns VBox status code.
871 * @param pVM VM Handle.
872 * @param pCpumctx16 Version 1.6 CPUMCTX
873 */
874static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
875{
876#define CPUMCTX16_LOADREG(RegName) \
877 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
878
879#define CPUMCTX16_LOADDRXREG(RegName) \
880 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
881
882#define CPUMCTX16_LOADHIDREG(RegName) \
883 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
884 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
885 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
886
887#define CPUMCTX16_LOADSEGREG(RegName) \
888 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
889 CPUMCTX16_LOADHIDREG(RegName);
890
891 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
892
893 CPUMCTX16_LOADREG(rax);
894 CPUMCTX16_LOADREG(rbx);
895 CPUMCTX16_LOADREG(rcx);
896 CPUMCTX16_LOADREG(rdx);
897 CPUMCTX16_LOADREG(rdi);
898 CPUMCTX16_LOADREG(rsi);
899 CPUMCTX16_LOADREG(rbp);
900 CPUMCTX16_LOADREG(esp);
901 CPUMCTX16_LOADREG(rip);
902 CPUMCTX16_LOADREG(rflags);
903
904 CPUMCTX16_LOADSEGREG(cs);
905 CPUMCTX16_LOADSEGREG(ds);
906 CPUMCTX16_LOADSEGREG(es);
907 CPUMCTX16_LOADSEGREG(fs);
908 CPUMCTX16_LOADSEGREG(gs);
909 CPUMCTX16_LOADSEGREG(ss);
910
911 CPUMCTX16_LOADREG(r8);
912 CPUMCTX16_LOADREG(r9);
913 CPUMCTX16_LOADREG(r10);
914 CPUMCTX16_LOADREG(r11);
915 CPUMCTX16_LOADREG(r12);
916 CPUMCTX16_LOADREG(r13);
917 CPUMCTX16_LOADREG(r14);
918 CPUMCTX16_LOADREG(r15);
919
920 CPUMCTX16_LOADREG(cr0);
921 CPUMCTX16_LOADREG(cr2);
922 CPUMCTX16_LOADREG(cr3);
923 CPUMCTX16_LOADREG(cr4);
924
925 CPUMCTX16_LOADDRXREG(0);
926 CPUMCTX16_LOADDRXREG(1);
927 CPUMCTX16_LOADDRXREG(2);
928 CPUMCTX16_LOADDRXREG(3);
929 CPUMCTX16_LOADDRXREG(4);
930 CPUMCTX16_LOADDRXREG(5);
931 CPUMCTX16_LOADDRXREG(6);
932 CPUMCTX16_LOADDRXREG(7);
933
934 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
935 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
936 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
937 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
938
939 CPUMCTX16_LOADREG(ldtr);
940 CPUMCTX16_LOADREG(tr);
941
942 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
943
944 CPUMCTX16_LOADREG(msrEFER);
945 CPUMCTX16_LOADREG(msrSTAR);
946 CPUMCTX16_LOADREG(msrPAT);
947 CPUMCTX16_LOADREG(msrLSTAR);
948 CPUMCTX16_LOADREG(msrCSTAR);
949 CPUMCTX16_LOADREG(msrSFMASK);
950 CPUMCTX16_LOADREG(msrKERNELGSBASE);
951
952 CPUMCTX16_LOADHIDREG(ldtr);
953 CPUMCTX16_LOADHIDREG(tr);
954
955#undef CPUMCTX16_LOADSEGREG
956#undef CPUMCTX16_LOADHIDREG
957#undef CPUMCTX16_LOADDRXREG
958#undef CPUMCTX16_LOADREG
959}
960
961
962/**
963 * Execute state load operation.
964 *
965 * @returns VBox status code.
966 * @param pVM VM Handle.
967 * @param pSSM SSM operation handle.
968 * @param u32Version Data layout version.
969 */
970static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
971{
972 /*
973 * Validate version.
974 */
975 if ( u32Version != CPUM_SAVED_STATE_VERSION
976 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
977 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
978 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
979 {
980 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
981 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
982 }
983
984 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
985 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
986 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
987 else if (u32Version <= CPUM_SAVED_STATE_VERSION)
988 SSMR3SetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
989
990 /*
991 * Restore.
992 */
993 for (unsigned i=0;i<pVM->cCPUs;i++)
994 {
995 PVMCPU pVCpu = &pVM->aCpus[i];
996 uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
997 uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
998
999 SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1000 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1001 pVCpu->cpum.s.Hyper.esp = uESP;
1002 }
1003
1004 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
1005 {
1006 CPUMCTX_VER1_6 cpumctx16;
1007 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
1008 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
1009
1010 /* Save the old cpumctx state into the new one. */
1011 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
1012
1013 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
1014 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
1015 }
1016 else
1017 {
1018 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1019 {
1020 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
1021 AssertRCReturn(rc, rc);
1022 }
1023
1024 if ( !pVM->cCPUs
1025 || pVM->cCPUs > VMM_MAX_CPU_COUNT
1026 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
1027 && pVM->cCPUs != 1))
1028 {
1029 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
1030 return VERR_SSM_UNEXPECTED_DATA;
1031 }
1032
1033 for (unsigned i=0;i<pVM->cCPUs;i++)
1034 {
1035 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
1036 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
1037 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
1038 if (u32Version == CPUM_SAVED_STATE_VERSION)
1039 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
1040 }
1041 }
1042
1043
1044 uint32_t cElements;
1045 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1046 /* Support old saved states with a smaller standard cpuid array. */
1047 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1048 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1049 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
1050
1051 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1052 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1053 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1054 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1055
1056 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1057 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1058 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1059 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1060
1061 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1062
1063 /*
1064 * Check that the basic cpuid id information is unchanged.
1065 * @todo we should check the 64 bits capabilities too!
1066 */
1067 uint32_t au32CpuId[8] = {0};
1068 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1069 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1070 uint32_t au32CpuIdSaved[8];
1071 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1072 if (RT_SUCCESS(rc))
1073 {
1074 /* Ignore CPU stepping. */
1075 au32CpuId[4] &= 0xfffffff0;
1076 au32CpuIdSaved[4] &= 0xfffffff0;
1077
1078 /* Ignore APIC ID (AMD specs). */
1079 au32CpuId[5] &= ~0xff000000;
1080 au32CpuIdSaved[5] &= ~0xff000000;
1081
1082 /* Ignore the number of Logical CPUs (AMD specs). */
1083 au32CpuId[5] &= ~0x00ff0000;
1084 au32CpuIdSaved[5] &= ~0x00ff0000;
1085
1086 /* do the compare */
1087 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1088 {
1089 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1090 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1091 "Saved=%.*Rhxs\n"
1092 "Real =%.*Rhxs\n",
1093 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1094 sizeof(au32CpuId), au32CpuId));
1095 else
1096 {
1097 LogRel(("cpumR3Load: CpuId mismatch!\n"
1098 "Saved=%.*Rhxs\n"
1099 "Real =%.*Rhxs\n",
1100 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1101 sizeof(au32CpuId), au32CpuId));
1102 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1103 }
1104 }
1105 }
1106
1107 return rc;
1108}
1109
1110
1111/**
1112 * Formats the EFLAGS value into mnemonics.
1113 *
1114 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1115 * @param efl The EFLAGS value.
1116 */
1117static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1118{
1119 /*
1120 * Format the flags.
1121 */
1122 static const struct
1123 {
1124 const char *pszSet; const char *pszClear; uint32_t fFlag;
1125 } s_aFlags[] =
1126 {
1127 { "vip",NULL, X86_EFL_VIP },
1128 { "vif",NULL, X86_EFL_VIF },
1129 { "ac", NULL, X86_EFL_AC },
1130 { "vm", NULL, X86_EFL_VM },
1131 { "rf", NULL, X86_EFL_RF },
1132 { "nt", NULL, X86_EFL_NT },
1133 { "ov", "nv", X86_EFL_OF },
1134 { "dn", "up", X86_EFL_DF },
1135 { "ei", "di", X86_EFL_IF },
1136 { "tf", NULL, X86_EFL_TF },
1137 { "nt", "pl", X86_EFL_SF },
1138 { "nz", "zr", X86_EFL_ZF },
1139 { "ac", "na", X86_EFL_AF },
1140 { "po", "pe", X86_EFL_PF },
1141 { "cy", "nc", X86_EFL_CF },
1142 };
1143 char *psz = pszEFlags;
1144 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1145 {
1146 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1147 if (pszAdd)
1148 {
1149 strcpy(psz, pszAdd);
1150 psz += strlen(pszAdd);
1151 *psz++ = ' ';
1152 }
1153 }
1154 psz[-1] = '\0';
1155}
1156
1157
1158/**
1159 * Formats a full register dump.
1160 *
1161 * @param pVM VM Handle.
1162 * @param pCtx The context to format.
1163 * @param pCtxCore The context core to format.
1164 * @param pHlp Output functions.
1165 * @param enmType The dump type.
1166 * @param pszPrefix Register name prefix.
1167 */
1168static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1169{
1170 /*
1171 * Format the EFLAGS.
1172 */
1173 uint32_t efl = pCtxCore->eflags.u32;
1174 char szEFlags[80];
1175 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1176
1177 /*
1178 * Format the registers.
1179 */
1180 switch (enmType)
1181 {
1182 case CPUMDUMPTYPE_TERSE:
1183 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1184 pHlp->pfnPrintf(pHlp,
1185 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1186 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1187 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1188 "%sr14=%016RX64 %sr15=%016RX64\n"
1189 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1190 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1191 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1192 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1193 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1194 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1195 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1196 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1197 else
1198 pHlp->pfnPrintf(pHlp,
1199 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1200 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1201 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1202 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1203 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1204 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1205 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1206 break;
1207
1208 case CPUMDUMPTYPE_DEFAULT:
1209 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1210 pHlp->pfnPrintf(pHlp,
1211 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1212 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1213 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1214 "%sr14=%016RX64 %sr15=%016RX64\n"
1215 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1216 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1217 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1218 ,
1219 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1220 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1221 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1222 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1223 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1224 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1225 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1226 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1227 else
1228 pHlp->pfnPrintf(pHlp,
1229 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1230 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1231 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1232 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1233 ,
1234 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1235 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1236 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1237 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1238 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1239 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1240 break;
1241
1242 case CPUMDUMPTYPE_VERBOSE:
1243 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1244 pHlp->pfnPrintf(pHlp,
1245 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1246 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1247 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1248 "%sr14=%016RX64 %sr15=%016RX64\n"
1249 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1250 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1251 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1252 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1253 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1254 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1255 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1256 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1257 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1258 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1259 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1260 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1261 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1262 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1263 ,
1264 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1265 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1266 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1267 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1268 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1269 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1270 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1271 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1272 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1273 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1274 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1275 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1276 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1277 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1278 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1279 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1280 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1281 else
1282 pHlp->pfnPrintf(pHlp,
1283 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1284 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1285 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1286 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1287 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1288 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1289 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1290 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1291 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1292 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1293 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1294 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1295 ,
1296 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1297 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1298 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1299 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1300 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1301 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1302 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1303 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1304 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1305 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1306 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1307 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1308
1309 pHlp->pfnPrintf(pHlp,
1310 "FPU:\n"
1311 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1312 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1313 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1314 ,
1315 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1316 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1317 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1318 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1319
1320 pHlp->pfnPrintf(pHlp,
1321 "MSR:\n"
1322 "%sEFER =%016RX64\n"
1323 "%sPAT =%016RX64\n"
1324 "%sSTAR =%016RX64\n"
1325 "%sCSTAR =%016RX64\n"
1326 "%sLSTAR =%016RX64\n"
1327 "%sSFMASK =%016RX64\n"
1328 "%sKERNELGSBASE =%016RX64\n",
1329 pszPrefix, pCtx->msrEFER,
1330 pszPrefix, pCtx->msrPAT,
1331 pszPrefix, pCtx->msrSTAR,
1332 pszPrefix, pCtx->msrCSTAR,
1333 pszPrefix, pCtx->msrLSTAR,
1334 pszPrefix, pCtx->msrSFMASK,
1335 pszPrefix, pCtx->msrKERNELGSBASE);
1336 break;
1337 }
1338}
1339
1340
1341/**
1342 * Display all cpu states and any other cpum info.
1343 *
1344 * @param pVM VM Handle.
1345 * @param pHlp The info helper functions.
1346 * @param pszArgs Arguments, ignored.
1347 */
1348static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1349{
1350 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1351 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1352 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1353 cpumR3InfoHost(pVM, pHlp, pszArgs);
1354}
1355
1356
1357/**
1358 * Parses the info argument.
1359 *
1360 * The argument starts with 'verbose', 'terse' or 'default' and then
1361 * continues with the comment string.
1362 *
1363 * @param pszArgs The pointer to the argument string.
1364 * @param penmType Where to store the dump type request.
1365 * @param ppszComment Where to store the pointer to the comment string.
1366 */
1367static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1368{
1369 if (!pszArgs)
1370 {
1371 *penmType = CPUMDUMPTYPE_DEFAULT;
1372 *ppszComment = "";
1373 }
1374 else
1375 {
1376 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1377 {
1378 pszArgs += 5;
1379 *penmType = CPUMDUMPTYPE_VERBOSE;
1380 }
1381 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1382 {
1383 pszArgs += 5;
1384 *penmType = CPUMDUMPTYPE_TERSE;
1385 }
1386 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1387 {
1388 pszArgs += 7;
1389 *penmType = CPUMDUMPTYPE_DEFAULT;
1390 }
1391 else
1392 *penmType = CPUMDUMPTYPE_DEFAULT;
1393 *ppszComment = RTStrStripL(pszArgs);
1394 }
1395}
1396
1397
1398/**
1399 * Display the guest cpu state.
1400 *
1401 * @param pVM VM Handle.
1402 * @param pHlp The info helper functions.
1403 * @param pszArgs Arguments, ignored.
1404 */
1405static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1406{
1407 CPUMDUMPTYPE enmType;
1408 const char *pszComment;
1409 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1410 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1411
1412 /* @todo SMP support! */
1413 PVMCPU pVCpu = &pVM->aCpus[0];
1414 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1415 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1416}
1417
1418
1419/**
1420 * Display the current guest instruction
1421 *
1422 * @param pVM VM Handle.
1423 * @param pHlp The info helper functions.
1424 * @param pszArgs Arguments, ignored.
1425 */
1426static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1427{
1428 char szInstruction[256];
1429 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1430 if (RT_SUCCESS(rc))
1431 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1432}
1433
1434
1435/**
1436 * Display the hypervisor cpu state.
1437 *
1438 * @param pVM VM Handle.
1439 * @param pHlp The info helper functions.
1440 * @param pszArgs Arguments, ignored.
1441 */
1442static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1443{
1444 CPUMDUMPTYPE enmType;
1445 const char *pszComment;
1446 /* @todo SMP */
1447 PVMCPU pVCpu = &pVM->aCpus[0];
1448
1449 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1450 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1451 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1452 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1453}
1454
1455
1456/**
1457 * Display the host cpu state.
1458 *
1459 * @param pVM VM Handle.
1460 * @param pHlp The info helper functions.
1461 * @param pszArgs Arguments, ignored.
1462 */
1463static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1464{
1465 CPUMDUMPTYPE enmType;
1466 const char *pszComment;
1467 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1468 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1469
1470 /*
1471 * Format the EFLAGS.
1472 */
1473 /* @todo SMP */
1474 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1475#if HC_ARCH_BITS == 32
1476 uint32_t efl = pCtx->eflags.u32;
1477#else
1478 uint64_t efl = pCtx->rflags;
1479#endif
1480 char szEFlags[80];
1481 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1482
1483 /*
1484 * Format the registers.
1485 */
1486#if HC_ARCH_BITS == 32
1487# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1488 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1489# endif
1490 {
1491 pHlp->pfnPrintf(pHlp,
1492 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1493 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1494 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1495 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1496 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1497 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1498 ,
1499 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1500 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1501 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1502 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1503 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1504 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1505 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1506 }
1507# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1508 else
1509# endif
1510#endif
1511#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1512 {
1513 pHlp->pfnPrintf(pHlp,
1514 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1515 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1516 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1517 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1518 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1519 "r14=%016RX64 r15=%016RX64\n"
1520 "iopl=%d %31s\n"
1521 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1522 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1523 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1524 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1525 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1526 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1527 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1528 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1529 ,
1530 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1531 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1532 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1533 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1534 pCtx->r11, pCtx->r12, pCtx->r13,
1535 pCtx->r14, pCtx->r15,
1536 X86_EFL_GET_IOPL(efl), szEFlags,
1537 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1538 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1539 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1540 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1541 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1542 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1543 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1544 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1545 }
1546#endif
1547}
1548
1549
1550/**
1551 * Get L1 cache / TLS associativity.
1552 */
1553static const char *getCacheAss(unsigned u, char *pszBuf)
1554{
1555 if (u == 0)
1556 return "res0 ";
1557 if (u == 1)
1558 return "direct";
1559 if (u >= 256)
1560 return "???";
1561
1562 RTStrPrintf(pszBuf, 16, "%d way", u);
1563 return pszBuf;
1564}
1565
1566
1567/**
1568 * Get L2 cache soociativity.
1569 */
1570const char *getL2CacheAss(unsigned u)
1571{
1572 switch (u)
1573 {
1574 case 0: return "off ";
1575 case 1: return "direct";
1576 case 2: return "2 way ";
1577 case 3: return "res3 ";
1578 case 4: return "4 way ";
1579 case 5: return "res5 ";
1580 case 6: return "8 way "; case 7: return "res7 ";
1581 case 8: return "16 way";
1582 case 9: return "res9 ";
1583 case 10: return "res10 ";
1584 case 11: return "res11 ";
1585 case 12: return "res12 ";
1586 case 13: return "res13 ";
1587 case 14: return "res14 ";
1588 case 15: return "fully ";
1589 default:
1590 return "????";
1591 }
1592}
1593
1594
1595/**
1596 * Display the guest CpuId leaves.
1597 *
1598 * @param pVM VM Handle.
1599 * @param pHlp The info helper functions.
1600 * @param pszArgs "terse", "default" or "verbose".
1601 */
1602static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1603{
1604 /*
1605 * Parse the argument.
1606 */
1607 unsigned iVerbosity = 1;
1608 if (pszArgs)
1609 {
1610 pszArgs = RTStrStripL(pszArgs);
1611 if (!strcmp(pszArgs, "terse"))
1612 iVerbosity--;
1613 else if (!strcmp(pszArgs, "verbose"))
1614 iVerbosity++;
1615 }
1616
1617 /*
1618 * Start cracking.
1619 */
1620 CPUMCPUID Host;
1621 CPUMCPUID Guest;
1622 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1623
1624 pHlp->pfnPrintf(pHlp,
1625 " RAW Standard CPUIDs\n"
1626 " Function eax ebx ecx edx\n");
1627 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1628 {
1629 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1630 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1631
1632 pHlp->pfnPrintf(pHlp,
1633 "Gst: %08x %08x %08x %08x %08x%s\n"
1634 "Hst: %08x %08x %08x %08x\n",
1635 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1636 i <= cStdMax ? "" : "*",
1637 Host.eax, Host.ebx, Host.ecx, Host.edx);
1638 }
1639
1640 /*
1641 * If verbose, decode it.
1642 */
1643 if (iVerbosity)
1644 {
1645 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1646 pHlp->pfnPrintf(pHlp,
1647 "Name: %.04s%.04s%.04s\n"
1648 "Supports: 0-%x\n",
1649 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1650 }
1651
1652 /*
1653 * Get Features.
1654 */
1655 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1656 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1657 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1658 if (cStdMax >= 1 && iVerbosity)
1659 {
1660 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1661 uint32_t uEAX = Guest.eax;
1662
1663 pHlp->pfnPrintf(pHlp,
1664 "Family: %d \tExtended: %d \tEffective: %d\n"
1665 "Model: %d \tExtended: %d \tEffective: %d\n"
1666 "Stepping: %d\n"
1667 "APIC ID: %#04x\n"
1668 "Logical CPUs: %d\n"
1669 "CLFLUSH Size: %d\n"
1670 "Brand ID: %#04x\n",
1671 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1672 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1673 ASMGetCpuStepping(uEAX),
1674 (Guest.ebx >> 24) & 0xff,
1675 (Guest.ebx >> 16) & 0xff,
1676 (Guest.ebx >> 8) & 0xff,
1677 (Guest.ebx >> 0) & 0xff);
1678 if (iVerbosity == 1)
1679 {
1680 uint32_t uEDX = Guest.edx;
1681 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1682 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1683 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1684 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1685 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1686 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1687 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1688 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1689 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1690 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1691 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1692 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1693 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1694 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1695 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1696 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1697 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1698 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1699 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1700 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1701 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1702 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1703 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1704 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1705 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1706 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1707 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1708 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1709 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1710 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1711 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1712 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1713 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1714 pHlp->pfnPrintf(pHlp, "\n");
1715
1716 uint32_t uECX = Guest.ecx;
1717 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1718 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1719 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1720 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1721 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1722 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1723 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1724 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1725 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1726 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1727 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1728 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1729 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1730 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1731 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1732 for (unsigned iBit = 14; iBit < 32; iBit++)
1733 if (uECX & RT_BIT(iBit))
1734 pHlp->pfnPrintf(pHlp, " %d", iBit);
1735 pHlp->pfnPrintf(pHlp, "\n");
1736 }
1737 else
1738 {
1739 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1740
1741 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1742 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1743 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1744 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1745
1746 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1747 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1748 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1749 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1750 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1751 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1752 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1753 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1754 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1755 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1756 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1757 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1758 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1759 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1760 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1761 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1762 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1763 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1764 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1765 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1766 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1767 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1768 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1769 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1770 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1771 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1772 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1773 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1774 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1775 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1776 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1777 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1778 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1779
1780 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1781 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1782 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1783 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1784 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1785 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1786 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1787 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1788 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1789 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1790 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1791 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1792 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1793 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1794 }
1795 }
1796 if (cStdMax >= 2 && iVerbosity)
1797 {
1798 /** @todo */
1799 }
1800
1801 /*
1802 * Extended.
1803 * Implemented after AMD specs.
1804 */
1805 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1806
1807 pHlp->pfnPrintf(pHlp,
1808 "\n"
1809 " RAW Extended CPUIDs\n"
1810 " Function eax ebx ecx edx\n");
1811 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1812 {
1813 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1814 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1815
1816 pHlp->pfnPrintf(pHlp,
1817 "Gst: %08x %08x %08x %08x %08x%s\n"
1818 "Hst: %08x %08x %08x %08x\n",
1819 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1820 i <= cExtMax ? "" : "*",
1821 Host.eax, Host.ebx, Host.ecx, Host.edx);
1822 }
1823
1824 /*
1825 * Understandable output
1826 */
1827 if (iVerbosity)
1828 {
1829 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1830 pHlp->pfnPrintf(pHlp,
1831 "Ext Name: %.4s%.4s%.4s\n"
1832 "Ext Supports: 0x80000000-%#010x\n",
1833 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1834 }
1835
1836 if (iVerbosity && cExtMax >= 1)
1837 {
1838 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1839 uint32_t uEAX = Guest.eax;
1840 pHlp->pfnPrintf(pHlp,
1841 "Family: %d \tExtended: %d \tEffective: %d\n"
1842 "Model: %d \tExtended: %d \tEffective: %d\n"
1843 "Stepping: %d\n"
1844 "Brand ID: %#05x\n",
1845 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1846 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1847 ASMGetCpuStepping(uEAX),
1848 Guest.ebx & 0xfff);
1849
1850 if (iVerbosity == 1)
1851 {
1852 uint32_t uEDX = Guest.edx;
1853 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1854 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1855 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1856 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1857 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1858 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1859 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1860 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1861 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1862 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1863 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1864 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1865 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1866 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1867 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1868 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1869 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1870 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1871 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1872 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1873 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1874 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1875 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1876 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1877 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1878 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1879 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1880 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1881 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1882 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1883 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1884 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1885 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1886 pHlp->pfnPrintf(pHlp, "\n");
1887
1888 uint32_t uECX = Guest.ecx;
1889 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1890 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1891 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1892 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1893 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1894 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1895 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1896 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1897 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1898 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1899 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1900 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1901 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1902 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1903 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1904 for (unsigned iBit = 5; iBit < 32; iBit++)
1905 if (uECX & RT_BIT(iBit))
1906 pHlp->pfnPrintf(pHlp, " %d", iBit);
1907 pHlp->pfnPrintf(pHlp, "\n");
1908 }
1909 else
1910 {
1911 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1912
1913 uint32_t uEdxGst = Guest.edx;
1914 uint32_t uEdxHst = Host.edx;
1915 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1916 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1917 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1918 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1919 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1920 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1921 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1922 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1923 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1924 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1925 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1926 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1927 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1928 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1929 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1930 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1931 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1932 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1933 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1934 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1935 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1936 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1937 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1938 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1939 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1940 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1941 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1942 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1943 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1944 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1945 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1946 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1947 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1948
1949 uint32_t uEcxGst = Guest.ecx;
1950 uint32_t uEcxHst = Host.ecx;
1951 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1952 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1953 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1954 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1955 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1956 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1957 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1958 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1959 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1960 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1961 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1962 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1963 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1964 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1965 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1966 }
1967 }
1968
1969 if (iVerbosity && cExtMax >= 2)
1970 {
1971 char szString[4*4*3+1] = {0};
1972 uint32_t *pu32 = (uint32_t *)szString;
1973 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1974 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1975 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1976 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1977 if (cExtMax >= 3)
1978 {
1979 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1980 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1981 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1982 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1983 }
1984 if (cExtMax >= 4)
1985 {
1986 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1987 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1988 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1989 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1990 }
1991 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1992 }
1993
1994 if (iVerbosity && cExtMax >= 5)
1995 {
1996 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1997 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1998 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1999 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
2000 char sz1[32];
2001 char sz2[32];
2002
2003 pHlp->pfnPrintf(pHlp,
2004 "TLB 2/4M Instr/Uni: %s %3d entries\n"
2005 "TLB 2/4M Data: %s %3d entries\n",
2006 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
2007 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
2008 pHlp->pfnPrintf(pHlp,
2009 "TLB 4K Instr/Uni: %s %3d entries\n"
2010 "TLB 4K Data: %s %3d entries\n",
2011 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
2012 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
2013 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
2014 "L1 Instr Cache Lines Per Tag: %d\n"
2015 "L1 Instr Cache Associativity: %s\n"
2016 "L1 Instr Cache Size: %d KB\n",
2017 (uEDX >> 0) & 0xff,
2018 (uEDX >> 8) & 0xff,
2019 getCacheAss((uEDX >> 16) & 0xff, sz1),
2020 (uEDX >> 24) & 0xff);
2021 pHlp->pfnPrintf(pHlp,
2022 "L1 Data Cache Line Size: %d bytes\n"
2023 "L1 Data Cache Lines Per Tag: %d\n"
2024 "L1 Data Cache Associativity: %s\n"
2025 "L1 Data Cache Size: %d KB\n",
2026 (uECX >> 0) & 0xff,
2027 (uECX >> 8) & 0xff,
2028 getCacheAss((uECX >> 16) & 0xff, sz1),
2029 (uECX >> 24) & 0xff);
2030 }
2031
2032 if (iVerbosity && cExtMax >= 6)
2033 {
2034 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
2035 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
2036 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
2037
2038 pHlp->pfnPrintf(pHlp,
2039 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
2040 "L2 TLB 2/4M Data: %s %4d entries\n",
2041 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
2042 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
2043 pHlp->pfnPrintf(pHlp,
2044 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
2045 "L2 TLB 4K Data: %s %4d entries\n",
2046 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
2047 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
2048 pHlp->pfnPrintf(pHlp,
2049 "L2 Cache Line Size: %d bytes\n"
2050 "L2 Cache Lines Per Tag: %d\n"
2051 "L2 Cache Associativity: %s\n"
2052 "L2 Cache Size: %d KB\n",
2053 (uEDX >> 0) & 0xff,
2054 (uEDX >> 8) & 0xf,
2055 getL2CacheAss((uEDX >> 12) & 0xf),
2056 (uEDX >> 16) & 0xffff);
2057 }
2058
2059 if (iVerbosity && cExtMax >= 7)
2060 {
2061 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
2062
2063 pHlp->pfnPrintf(pHlp, "APM Features: ");
2064 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
2065 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
2066 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
2067 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
2068 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
2069 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
2070 for (unsigned iBit = 6; iBit < 32; iBit++)
2071 if (uEDX & RT_BIT(iBit))
2072 pHlp->pfnPrintf(pHlp, " %d", iBit);
2073 pHlp->pfnPrintf(pHlp, "\n");
2074 }
2075
2076 if (iVerbosity && cExtMax >= 8)
2077 {
2078 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2079 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2080
2081 pHlp->pfnPrintf(pHlp,
2082 "Physical Address Width: %d bits\n"
2083 "Virtual Address Width: %d bits\n",
2084 (uEAX >> 0) & 0xff,
2085 (uEAX >> 8) & 0xff);
2086 pHlp->pfnPrintf(pHlp,
2087 "Physical Core Count: %d\n",
2088 (uECX >> 0) & 0xff);
2089 }
2090
2091
2092 /*
2093 * Centaur.
2094 */
2095 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2096
2097 pHlp->pfnPrintf(pHlp,
2098 "\n"
2099 " RAW Centaur CPUIDs\n"
2100 " Function eax ebx ecx edx\n");
2101 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2102 {
2103 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2104 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2105
2106 pHlp->pfnPrintf(pHlp,
2107 "Gst: %08x %08x %08x %08x %08x%s\n"
2108 "Hst: %08x %08x %08x %08x\n",
2109 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2110 i <= cCentaurMax ? "" : "*",
2111 Host.eax, Host.ebx, Host.ecx, Host.edx);
2112 }
2113
2114 /*
2115 * Understandable output
2116 */
2117 if (iVerbosity)
2118 {
2119 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2120 pHlp->pfnPrintf(pHlp,
2121 "Centaur Supports: 0xc0000000-%#010x\n",
2122 Guest.eax);
2123 }
2124
2125 if (iVerbosity && cCentaurMax >= 1)
2126 {
2127 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2128 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2129 uint32_t uEdxHst = Host.edx;
2130
2131 if (iVerbosity == 1)
2132 {
2133 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2134 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2135 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2136 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2137 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2138 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2139 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2140 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2141 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2142 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2143 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2144 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2145 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2146 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2147 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2148 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2149 for (unsigned iBit = 14; iBit < 32; iBit++)
2150 if (uEdxGst & RT_BIT(iBit))
2151 pHlp->pfnPrintf(pHlp, " %d", iBit);
2152 pHlp->pfnPrintf(pHlp, "\n");
2153 }
2154 else
2155 {
2156 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2157 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2158 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2159 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2160 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2161 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2162 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2163 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2164 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2165 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2166 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2167 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2168 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2169 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2170 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2171 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2172 for (unsigned iBit = 14; iBit < 32; iBit++)
2173 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2174 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2175 pHlp->pfnPrintf(pHlp, "\n");
2176 }
2177 }
2178}
2179
2180
2181/**
2182 * Structure used when disassembling and instructions in DBGF.
2183 * This is used so the reader function can get the stuff it needs.
2184 */
2185typedef struct CPUMDISASSTATE
2186{
2187 /** Pointer to the CPU structure. */
2188 PDISCPUSTATE pCpu;
2189 /** The VM handle. */
2190 PVM pVM;
2191 /** The VMCPU handle. */
2192 PVMCPU pVCpu;
2193 /** Pointer to the first byte in the segemnt. */
2194 RTGCUINTPTR GCPtrSegBase;
2195 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2196 RTGCUINTPTR GCPtrSegEnd;
2197 /** The size of the segment minus 1. */
2198 RTGCUINTPTR cbSegLimit;
2199 /** Pointer to the current page - R3 Ptr. */
2200 void const *pvPageR3;
2201 /** Pointer to the current page - GC Ptr. */
2202 RTGCPTR pvPageGC;
2203 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2204 PGMPAGEMAPLOCK PageMapLock;
2205 /** Whether the PageMapLock is valid or not. */
2206 bool fLocked;
2207 /** 64 bits mode or not. */
2208 bool f64Bits;
2209} CPUMDISASSTATE, *PCPUMDISASSTATE;
2210
2211
2212/**
2213 * Instruction reader.
2214 *
2215 * @returns VBox status code.
2216 * @param PtrSrc Address to read from.
2217 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2218 * @param pu8Dst Where to store the bytes.
2219 * @param cbRead Number of bytes to read.
2220 * @param uDisCpu Pointer to the disassembler cpu state.
2221 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2222 */
2223static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2224{
2225 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2226 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2227 Assert(cbRead > 0);
2228 for (;;)
2229 {
2230 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2231
2232 /* Need to update the page translation? */
2233 if ( !pState->pvPageR3
2234 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2235 {
2236 int rc = VINF_SUCCESS;
2237
2238 /* translate the address */
2239 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2240 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2241 && !HWACCMIsEnabled(pState->pVM))
2242 {
2243 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2244 if (!pState->pvPageR3)
2245 rc = VERR_INVALID_POINTER;
2246 }
2247 else
2248 {
2249 /* Release mapping lock previously acquired. */
2250 if (pState->fLocked)
2251 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2252 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2253 pState->fLocked = RT_SUCCESS_NP(rc);
2254 }
2255 if (RT_FAILURE(rc))
2256 {
2257 pState->pvPageR3 = NULL;
2258 return rc;
2259 }
2260 }
2261
2262 /* check the segemnt limit */
2263 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2264 return VERR_OUT_OF_SELECTOR_BOUNDS;
2265
2266 /* calc how much we can read */
2267 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2268 if (!pState->f64Bits)
2269 {
2270 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2271 if (cb > cbSeg && cbSeg)
2272 cb = cbSeg;
2273 }
2274 if (cb > cbRead)
2275 cb = cbRead;
2276
2277 /* read and advance */
2278 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2279 cbRead -= cb;
2280 if (!cbRead)
2281 return VINF_SUCCESS;
2282 pu8Dst += cb;
2283 PtrSrc += cb;
2284 }
2285}
2286
2287
2288/**
2289 * Disassemble an instruction and return the information in the provided structure.
2290 *
2291 * @returns VBox status code.
2292 * @param pVM VM Handle
2293 * @param pVCpu VMCPU Handle
2294 * @param pCtx CPU context
2295 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2296 * @param pCpu Disassembly state
2297 * @param pszPrefix String prefix for logging (debug only)
2298 *
2299 */
2300VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2301{
2302 CPUMDISASSTATE State;
2303 int rc;
2304
2305 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2306 State.pCpu = pCpu;
2307 State.pvPageGC = 0;
2308 State.pvPageR3 = NULL;
2309 State.pVM = pVM;
2310 State.pVCpu = pVCpu;
2311 State.fLocked = false;
2312 State.f64Bits = false;
2313
2314 /*
2315 * Get selector information.
2316 */
2317 if ( (pCtx->cr0 & X86_CR0_PE)
2318 && pCtx->eflags.Bits.u1VM == 0)
2319 {
2320 if (CPUMAreHiddenSelRegsValid(pVM))
2321 {
2322 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2323 State.GCPtrSegBase = pCtx->csHid.u64Base;
2324 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2325 State.cbSegLimit = pCtx->csHid.u32Limit;
2326 pCpu->mode = (State.f64Bits)
2327 ? CPUMODE_64BIT
2328 : pCtx->csHid.Attr.n.u1DefBig
2329 ? CPUMODE_32BIT
2330 : CPUMODE_16BIT;
2331 }
2332 else
2333 {
2334 DBGFSELINFO SelInfo;
2335
2336 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2337 if (RT_FAILURE(rc))
2338 {
2339 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2340 return rc;
2341 }
2342
2343 /*
2344 * Validate the selector.
2345 */
2346 rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
2347 if (RT_FAILURE(rc))
2348 {
2349 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2350 return rc;
2351 }
2352 State.GCPtrSegBase = SelInfo.GCPtrBase;
2353 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2354 State.cbSegLimit = SelInfo.cbLimit;
2355 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2356 }
2357 }
2358 else
2359 {
2360 /* real or V86 mode */
2361 pCpu->mode = CPUMODE_16BIT;
2362 State.GCPtrSegBase = pCtx->cs * 16;
2363 State.GCPtrSegEnd = 0xFFFFFFFF;
2364 State.cbSegLimit = 0xFFFFFFFF;
2365 }
2366
2367 /*
2368 * Disassemble the instruction.
2369 */
2370 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2371 pCpu->apvUserData[0] = &State;
2372
2373 uint32_t cbInstr;
2374#ifndef LOG_ENABLED
2375 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2376 if (RT_SUCCESS(rc))
2377 {
2378#else
2379 char szOutput[160];
2380 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2381 if (RT_SUCCESS(rc))
2382 {
2383 /* log it */
2384 if (pszPrefix)
2385 Log(("%s: %s", pszPrefix, szOutput));
2386 else
2387 Log(("%s", szOutput));
2388#endif
2389 rc = VINF_SUCCESS;
2390 }
2391 else
2392 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2393
2394 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2395 if (State.fLocked)
2396 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2397
2398 return rc;
2399}
2400
2401#ifdef DEBUG
2402
2403/**
2404 * Disassemble an instruction and dump it to the log
2405 *
2406 * @returns VBox status code.
2407 * @param pVM VM Handle
2408 * @param pVCpu VMCPU Handle
2409 * @param pCtx CPU context
2410 * @param pc GC instruction pointer
2411 * @param pszPrefix String prefix for logging
2412 *
2413 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2414 */
2415VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2416{
2417 DISCPUSTATE Cpu;
2418 CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
2419}
2420
2421
2422/**
2423 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2424 *
2425 * @internal
2426 */
2427VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2428{
2429 /* @todo SMP support!! */
2430 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
2431}
2432
2433#endif /* DEBUG */
2434
2435/**
2436 * API for controlling a few of the CPU features found in CR4.
2437 *
2438 * Currently only X86_CR4_TSD is accepted as input.
2439 *
2440 * @returns VBox status code.
2441 *
2442 * @param pVM The VM handle.
2443 * @param fOr The CR4 OR mask.
2444 * @param fAnd The CR4 AND mask.
2445 */
2446VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2447{
2448 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2449 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2450
2451 pVM->cpum.s.CR4.OrMask &= fAnd;
2452 pVM->cpum.s.CR4.OrMask |= fOr;
2453
2454 return VINF_SUCCESS;
2455}
2456
2457
2458/**
2459 * Gets a pointer to the array of standard CPUID leafs.
2460 *
2461 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
2462 *
2463 * @returns Pointer to the standard CPUID leafs (read-only).
2464 * @param pVM The VM handle.
2465 * @remark Intended for PATM.
2466 */
2467VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
2468{
2469 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
2470}
2471
2472
2473/**
2474 * Gets a pointer to the array of extended CPUID leafs.
2475 *
2476 * CPUMGetGuestCpuIdExtMax() give the size of the array.
2477 *
2478 * @returns Pointer to the extended CPUID leafs (read-only).
2479 * @param pVM The VM handle.
2480 * @remark Intended for PATM.
2481 */
2482VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
2483{
2484 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
2485}
2486
2487
2488/**
2489 * Gets a pointer to the array of centaur CPUID leafs.
2490 *
2491 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
2492 *
2493 * @returns Pointer to the centaur CPUID leafs (read-only).
2494 * @param pVM The VM handle.
2495 * @remark Intended for PATM.
2496 */
2497VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
2498{
2499 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
2500}
2501
2502
2503/**
2504 * Gets a pointer to the default CPUID leaf.
2505 *
2506 * @returns Pointer to the default CPUID leaf (read-only).
2507 * @param pVM The VM handle.
2508 * @remark Intended for PATM.
2509 */
2510VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
2511{
2512 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
2513}
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