VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 14672

Last change on this file since 14672 was 14411, checked in by vboxsync, 16 years ago

RDTSCP support added. Enabled only for AMD-V guests.
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1/* $Id: CPUM.cpp 14411 2008-11-20 13:26:47Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 *
35 * @see grp_cpum
36 */
37
38/*******************************************************************************
39* Header Files *
40*******************************************************************************/
41#define LOG_GROUP LOG_GROUP_CPUM
42#include <VBox/cpum.h>
43#include <VBox/cpumdis.h>
44#include <VBox/pgm.h>
45#include <VBox/pdm.h>
46#include <VBox/mm.h>
47#include <VBox/selm.h>
48#include <VBox/dbgf.h>
49#include <VBox/patm.h>
50#include <VBox/hwaccm.h>
51#include <VBox/ssm.h>
52#include "CPUMInternal.h"
53#include <VBox/vm.h>
54
55#include <VBox/param.h>
56#include <VBox/dis.h>
57#include <VBox/err.h>
58#include <VBox/log.h>
59#include <iprt/assert.h>
60#include <iprt/asm.h>
61#include <iprt/string.h>
62#include <iprt/mp.h>
63#include <iprt/cpuset.h>
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The saved state version. */
70#define CPUM_SAVED_STATE_VERSION 10
71/** The saved state version for the 2.1 trunk before the MSR changes. */
72#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
73/** The saved state version of 2.0, used for backwards compatibility. */
74#define CPUM_SAVED_STATE_VERSION_VER2_0 8
75/** The saved state version of 1.6, used for backwards compatability. */
76#define CPUM_SAVED_STATE_VERSION_VER1_6 6
77
78
79/*******************************************************************************
80* Structures and Typedefs *
81*******************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91
92} CPUMDUMPTYPE;
93/** Pointer to a cpu info dump type. */
94typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
95
96
97/*******************************************************************************
98* Internal Functions *
99*******************************************************************************/
100static int cpumR3CpuIdInit(PVM pVM);
101static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/**
112 * Initializes the CPUM.
113 *
114 * @returns VBox status code.
115 * @param pVM The VM to operate on.
116 */
117VMMR3DECL(int) CPUMR3Init(PVM pVM)
118{
119 LogFlow(("CPUMR3Init\n"));
120
121 /*
122 * Assert alignment and sizes.
123 */
124 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
125 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
126
127 /*
128 * Setup any fixed pointers and offsets.
129 */
130 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
131 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
132
133 /* Hidden selector registers are invalid by default. */
134 pVM->cpum.s.fValidHiddenSelRegs = false;
135
136 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
137 pVM->cpum.s.ulOffCPUMCPU = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
138 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.ulOffCPUMCPU == (uintptr_t)&pVM->aCpus[0].cpum);
139
140 /* Calculate the offset from CPUMCPU to CPUM. */
141 for (unsigned i=0;i<pVM->cCPUs;i++)
142 {
143 pVM->aCpus[i].cpum.s.ulOffCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
144 Assert((uintptr_t)&pVM->aCpus[i].cpum - pVM->aCpus[i].cpum.s.ulOffCPUM == (uintptr_t)&pVM->cpum);
145 }
146
147 /*
148 * Check that the CPU supports the minimum features we require.
149 */
150 if (!ASMHasCpuId())
151 {
152 Log(("The CPU doesn't support CPUID!\n"));
153 return VERR_UNSUPPORTED_CPU;
154 }
155 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
156 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
157
158 /* Setup the CR4 AND and OR masks used in the switcher */
159 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
160 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
161 {
162 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
163 /* No FXSAVE implies no SSE */
164 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
165 pVM->cpum.s.CR4.OrMask = 0;
166 }
167 else
168 {
169 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
170 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
171 }
172
173 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
174 {
175 Log(("The CPU doesn't support MMX!\n"));
176 return VERR_UNSUPPORTED_CPU;
177 }
178 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
179 {
180 Log(("The CPU doesn't support TSC!\n"));
181 return VERR_UNSUPPORTED_CPU;
182 }
183 /* Bogus on AMD? */
184 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
185 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
186
187 /*
188 * Setup hypervisor startup values.
189 */
190
191 /*
192 * Register saved state data item.
193 */
194 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
195 NULL, cpumR3Save, NULL,
196 NULL, cpumR3Load, NULL);
197 if (RT_FAILURE(rc))
198 return rc;
199
200 /* Query the CPU manufacturer. */
201 uint32_t uEAX, uEBX, uECX, uEDX;
202 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
203 if ( uEAX >= 1
204 && uEBX == X86_CPUID_VENDOR_AMD_EBX
205 && uECX == X86_CPUID_VENDOR_AMD_ECX
206 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
207 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
208 else if ( uEAX >= 1
209 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
210 && uECX == X86_CPUID_VENDOR_INTEL_ECX
211 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
212 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
213 else /** @todo Via */
214 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
215
216 /*
217 * Register info handlers.
218 */
219 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
220 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
221 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
222 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
223 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
224 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
225
226 /*
227 * Initialize the Guest CPU state.
228 */
229 rc = cpumR3CpuIdInit(pVM);
230 if (RT_FAILURE(rc))
231 return rc;
232 CPUMR3Reset(pVM);
233 return VINF_SUCCESS;
234}
235
236
237/**
238 * Initializes the per-VCPU CPUM.
239 *
240 * @returns VBox status code.
241 * @param pVM The VM to operate on.
242 */
243VMMR3DECL(int) CPUMR3InitCPU(PVM pVM)
244{
245 LogFlow(("CPUMR3InitCPU\n"));
246 return VINF_SUCCESS;
247}
248
249
250/**
251 * Initializes the emulated CPU's cpuid information.
252 *
253 * @returns VBox status code.
254 * @param pVM The VM to operate on.
255 */
256static int cpumR3CpuIdInit(PVM pVM)
257{
258 PCPUM pCPUM = &pVM->cpum.s;
259 uint32_t i;
260
261 /*
262 * Get the host CPUIDs.
263 */
264 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
265 ASMCpuId_Idx_ECX(i, 0,
266 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
267 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
268 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
269 ASMCpuId(0x80000000 + i,
270 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
271 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
272 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
273 ASMCpuId(0xc0000000 + i,
274 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
275 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
276
277
278 /*
279 * Only report features we can support.
280 */
281 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
282 | X86_CPUID_FEATURE_EDX_VME
283 | X86_CPUID_FEATURE_EDX_DE
284 | X86_CPUID_FEATURE_EDX_PSE
285 | X86_CPUID_FEATURE_EDX_TSC
286 | X86_CPUID_FEATURE_EDX_MSR
287 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
288 | X86_CPUID_FEATURE_EDX_MCE
289 | X86_CPUID_FEATURE_EDX_CX8
290 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
291 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
292 //| X86_CPUID_FEATURE_EDX_SEP
293 | X86_CPUID_FEATURE_EDX_MTRR
294 | X86_CPUID_FEATURE_EDX_PGE
295 | X86_CPUID_FEATURE_EDX_MCA
296 | X86_CPUID_FEATURE_EDX_CMOV
297 | X86_CPUID_FEATURE_EDX_PAT
298 | X86_CPUID_FEATURE_EDX_PSE36
299 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
300 | X86_CPUID_FEATURE_EDX_CLFSH
301 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
302 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
303 | X86_CPUID_FEATURE_EDX_MMX
304 | X86_CPUID_FEATURE_EDX_FXSR
305 | X86_CPUID_FEATURE_EDX_SSE
306 | X86_CPUID_FEATURE_EDX_SSE2
307 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
308 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
309 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
310 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
311 | 0;
312 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
313 | X86_CPUID_FEATURE_ECX_MONITOR
314 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
315 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
316 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
317 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
318 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
319 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
320 //| X86_CPUID_FEATURE_ECX_CX16
321 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
322 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
323 /* ECX Bit 21 - x2APIC support - not yet. */
324 // | X86_CPUID_FEATURE_ECX_X2APIC
325 /* ECX Bit 23 - POPCOUNT instruction. */
326 //| X86_CPUID_FEATURE_ECX_POPCOUNT
327 | 0;
328
329 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
330 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
331 | X86_CPUID_AMD_FEATURE_EDX_VME
332 | X86_CPUID_AMD_FEATURE_EDX_DE
333 | X86_CPUID_AMD_FEATURE_EDX_PSE
334 | X86_CPUID_AMD_FEATURE_EDX_TSC
335 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
336 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
337 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
338 | X86_CPUID_AMD_FEATURE_EDX_CX8
339 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
340 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
341 //| X86_CPUID_AMD_FEATURE_EDX_SEP
342 | X86_CPUID_AMD_FEATURE_EDX_MTRR
343 | X86_CPUID_AMD_FEATURE_EDX_PGE
344 | X86_CPUID_AMD_FEATURE_EDX_MCA
345 | X86_CPUID_AMD_FEATURE_EDX_CMOV
346 | X86_CPUID_AMD_FEATURE_EDX_PAT
347 | X86_CPUID_AMD_FEATURE_EDX_PSE36
348 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
349 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
350 | X86_CPUID_AMD_FEATURE_EDX_MMX
351 | X86_CPUID_AMD_FEATURE_EDX_FXSR
352 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
353 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
354 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
355 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
356 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
357 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
358 | 0;
359 pCPUM->aGuestCpuIdExt[1].ecx &= 0
360 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
361 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
362 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
363 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
364 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
365 //| X86_CPUID_AMD_FEATURE_ECX_ABM
366 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
367 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
368 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
369 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
370 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
371 //| X86_CPUID_AMD_FEATURE_ECX_WDT
372 | 0;
373
374 /*
375 * Hide HTT, multicode, SMP, whatever.
376 * (APIC-ID := 0 and #LogCpus := 0)
377 */
378 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
379
380 /* Cpuid 2:
381 * Intel: Cache and TLB information
382 * AMD: Reserved
383 * Safe to expose
384 */
385
386 /* Cpuid 3:
387 * Intel: EAX, EBX - reserved
388 * ECX, EDX - Processor Serial Number if available, otherwise reserved
389 * AMD: Reserved
390 * Safe to expose
391 */
392 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
393 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
394
395 /* Cpuid 4:
396 * Intel: Deterministic Cache Parameters Leaf
397 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
398 * AMD: Reserved
399 * Safe to expose, except for EAX:
400 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
401 * Bits 31-26: Maximum number of processor cores in this physical package**
402 */
403 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
404 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
405
406 /* Cpuid 5: Monitor/mwait Leaf
407 * Intel: ECX, EDX - reserved
408 * EAX, EBX - Smallest and largest monitor line size
409 * AMD: EDX - reserved
410 * EAX, EBX - Smallest and largest monitor line size
411 * ECX - extensions (ignored for now)
412 * Safe to expose
413 */
414 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
415 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
416
417 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
418
419 /*
420 * Determine the default.
421 *
422 * Intel returns values of the highest standard function, while AMD
423 * returns zeros. VIA on the other hand seems to returning nothing or
424 * perhaps some random garbage, we don't try to duplicate this behavior.
425 */
426 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
427 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
428 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
429
430 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
431 * Safe to pass on to the guest.
432 *
433 * Intel: 0x800000005 reserved
434 * 0x800000006 L2 cache information
435 * AMD: 0x800000005 L1 cache information
436 * 0x800000006 L2/L3 cache information
437 */
438
439 /* Cpuid 0x800000007:
440 * AMD: EAX, EBX, ECX - reserved
441 * EDX: Advanced Power Management Information
442 * Intel: Reserved
443 */
444 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
445 {
446 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
447
448 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
449
450 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
451 {
452 /* Only expose the TSC invariant capability bit to the guest. */
453 pCPUM->aGuestCpuIdExt[7].edx &= 0
454 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
455 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
456 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
457 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
458 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
459 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
460 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
461 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
462 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
463 | 0;
464 }
465 else
466 pCPUM->aGuestCpuIdExt[7].edx = 0;
467 }
468
469 /* Cpuid 0x800000008:
470 * AMD: EBX, EDX - reserved
471 * EAX: Virtual/Physical address Size
472 * ECX: Number of cores + APICIdCoreIdSize
473 * Intel: EAX: Virtual/Physical address Size
474 * EBX, ECX, EDX - reserved
475 */
476 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
477 {
478 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
479 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
480 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
481 * NC (0-7) Number of cores; 0 equals 1 core */
482 pCPUM->aGuestCpuIdExt[8].ecx = 0;
483 }
484
485 /*
486 * Limit it the number of entries and fill the remaining with the defaults.
487 *
488 * The limits are masking off stuff about power saving and similar, this
489 * is perhaps a bit crudely done as there is probably some relatively harmless
490 * info too in these leaves (like words about having a constant TSC).
491 */
492#if 0
493 /** @todo NT4 installation regression - investigate */
494 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
495 pCPUM->aGuestCpuIdStd[0].eax = 5;
496#else
497 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
498 pCPUM->aGuestCpuIdStd[0].eax = 2;
499#endif
500 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
501 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
502
503 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
504 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
505 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
506 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
507 : 0;
508 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
509 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
510
511 /*
512 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
513 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
514 * We currently don't support more than 1 processor.
515 */
516 pCPUM->aGuestCpuIdStd[4].eax = 0;
517
518 /*
519 * Centaur stuff (VIA).
520 *
521 * The important part here (we think) is to make sure the 0xc0000000
522 * function returns 0xc0000001. As for the features, we don't currently
523 * let on about any of those... 0xc0000002 seems to be some
524 * temperature/hz/++ stuff, include it as well (static).
525 */
526 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
527 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
528 {
529 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
530 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
531 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
532 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
533 i++)
534 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
535 }
536 else
537 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
538 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
539
540
541 /*
542 * Load CPUID overrides from configuration.
543 */
544 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
545 * Overloads the CPUID leaf values. */
546 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
547 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
548 for (i=0;; )
549 {
550 while (cElements-- > 0)
551 {
552 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
553 if (pNode)
554 {
555 uint32_t u32;
556 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
557 if (RT_SUCCESS(rc))
558 pCpuId->eax = u32;
559 else
560 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
561
562 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
563 if (RT_SUCCESS(rc))
564 pCpuId->ebx = u32;
565 else
566 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
567
568 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
569 if (RT_SUCCESS(rc))
570 pCpuId->ecx = u32;
571 else
572 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
573
574 rc = CFGMR3QueryU32(pNode, "edx", &u32);
575 if (RT_SUCCESS(rc))
576 pCpuId->edx = u32;
577 else
578 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
579 }
580 pCpuId++;
581 i++;
582 }
583
584 /* next */
585 if ((i & UINT32_C(0xc0000000)) == 0)
586 {
587 pCpuId = &pCPUM->aGuestCpuIdExt[0];
588 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
589 i = UINT32_C(0x80000000);
590 }
591 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
592 {
593 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
594 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
595 i = UINT32_C(0xc0000000);
596 }
597 else
598 break;
599 }
600
601 /* Check if PAE was explicitely enabled by the user. */
602 bool fEnable = false;
603 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
604 if (RT_SUCCESS(rc) && fEnable)
605 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
606
607 /*
608 * Log the cpuid and we're good.
609 */
610 RTCPUSET OnlineSet;
611 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
612 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
613 LogRel(("************************* CPUID dump ************************\n"));
614 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
615 LogRel(("\n"));
616 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
617 LogRel(("******************** End of CPUID dump **********************\n"));
618 return VINF_SUCCESS;
619}
620
621
622
623
624/**
625 * Applies relocations to data and code managed by this
626 * component. This function will be called at init and
627 * whenever the VMM need to relocate it self inside the GC.
628 *
629 * The CPUM will update the addresses used by the switcher.
630 *
631 * @param pVM The VM.
632 */
633VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
634{
635 LogFlow(("CPUMR3Relocate\n"));
636 /*
637 * Switcher pointers.
638 */
639 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
640 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
641}
642
643
644/**
645 * Terminates the CPUM.
646 *
647 * Termination means cleaning up and freeing all resources,
648 * the VM it self is at this point powered off or suspended.
649 *
650 * @returns VBox status code.
651 * @param pVM The VM to operate on.
652 */
653VMMR3DECL(int) CPUMR3Term(PVM pVM)
654{
655 /** @todo ? */
656 return 0;
657}
658
659
660/**
661 * Terminates the per-VCPU CPUM.
662 *
663 * Termination means cleaning up and freeing all resources,
664 * the VM it self is at this point powered off or suspended.
665 *
666 * @returns VBox status code.
667 * @param pVM The VM to operate on.
668 */
669VMMR3DECL(int) CPUMR3TermCPU(PVM pVM)
670{
671 return 0;
672}
673
674
675/**
676 * Resets the CPU.
677 *
678 * @returns VINF_SUCCESS.
679 * @param pVM The VM handle.
680 */
681VMMR3DECL(void) CPUMR3Reset(PVM pVM)
682{
683 /* @todo anything different for VCPU > 0? */
684 for (unsigned i=0;i<pVM->cCPUs;i++)
685 {
686 PCPUMCTX pCtx = CPUMQueryGuestCtxPtrEx(pVM, &pVM->aCpus[i]);
687
688 /*
689 * Initialize everything to ZERO first.
690 */
691 uint32_t fUseFlags = pVM->aCpus[i].cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
692 memset(pCtx, 0, sizeof(*pCtx));
693 pVM->aCpus[i].cpum.s.fUseFlags = fUseFlags;
694
695 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
696 pCtx->eip = 0x0000fff0;
697 pCtx->edx = 0x00000600; /* P6 processor */
698 pCtx->eflags.Bits.u1Reserved0 = 1;
699
700 pCtx->cs = 0xf000;
701 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
702 pCtx->csHid.u32Limit = 0x0000ffff;
703 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
704 pCtx->csHid.Attr.n.u1Present = 1;
705 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
706
707 pCtx->dsHid.u32Limit = 0x0000ffff;
708 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
709 pCtx->dsHid.Attr.n.u1Present = 1;
710 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
711
712 pCtx->esHid.u32Limit = 0x0000ffff;
713 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
714 pCtx->esHid.Attr.n.u1Present = 1;
715 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
716
717 pCtx->fsHid.u32Limit = 0x0000ffff;
718 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
719 pCtx->fsHid.Attr.n.u1Present = 1;
720 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
721
722 pCtx->gsHid.u32Limit = 0x0000ffff;
723 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
724 pCtx->gsHid.Attr.n.u1Present = 1;
725 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
726
727 pCtx->ssHid.u32Limit = 0x0000ffff;
728 pCtx->ssHid.Attr.n.u1Present = 1;
729 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
730 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
731
732 pCtx->idtr.cbIdt = 0xffff;
733 pCtx->gdtr.cbGdt = 0xffff;
734
735 pCtx->ldtrHid.u32Limit = 0xffff;
736 pCtx->ldtrHid.Attr.n.u1Present = 1;
737 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
738
739 pCtx->trHid.u32Limit = 0xffff;
740 pCtx->trHid.Attr.n.u1Present = 1;
741 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
742
743 pCtx->dr[6] = X86_DR6_INIT_VAL;
744 pCtx->dr[7] = X86_DR7_INIT_VAL;
745
746 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
747 pCtx->fpu.FCW = 0x37f;
748
749 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
750 pCtx->fpu.MXCSR = 0x1F80;
751
752 /* Init PAT MSR */
753 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
754
755 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
756 * The Intel docs don't mention it.
757 */
758 pCtx->msrEFER = 0;
759 }
760}
761
762
763/**
764 * Execute state save operation.
765 *
766 * @returns VBox status code.
767 * @param pVM VM Handle.
768 * @param pSSM SSM operation handle.
769 */
770static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
771{
772 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
773 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
774
775 /*
776 * Save.
777 */
778 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
779
780 SSMR3PutU32(pSSM, pVM->cCPUs);
781 for (unsigned i=0;i<pVM->cCPUs;i++)
782 {
783 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
784 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fUseFlags);
785 SSMR3PutU32(pSSM, pVM->aCpus[i].cpum.s.fChanged);
786 SSMR3PutMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
787 }
788
789 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
790 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
791
792 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
793 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
794
795 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
796 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
797
798 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
799
800 /* Add the cpuid for checking that the cpu is unchanged. */
801 uint32_t au32CpuId[8] = {0};
802 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
803 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
804 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
805}
806
807
808/**
809 * Load a version 1.6 CPUMCTX structure.
810 *
811 * @returns VBox status code.
812 * @param pVM VM Handle.
813 * @param pCpumctx16 Version 1.6 CPUMCTX
814 */
815static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
816{
817#define CPUMCTX16_LOADREG(RegName) \
818 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
819
820#define CPUMCTX16_LOADDRXREG(RegName) \
821 pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
822
823#define CPUMCTX16_LOADHIDREG(RegName) \
824 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
825 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
826 pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
827
828#define CPUMCTX16_LOADSEGREG(RegName) \
829 pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
830 CPUMCTX16_LOADHIDREG(RegName);
831
832 pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
833
834 CPUMCTX16_LOADREG(rax);
835 CPUMCTX16_LOADREG(rbx);
836 CPUMCTX16_LOADREG(rcx);
837 CPUMCTX16_LOADREG(rdx);
838 CPUMCTX16_LOADREG(rdi);
839 CPUMCTX16_LOADREG(rsi);
840 CPUMCTX16_LOADREG(rbp);
841 CPUMCTX16_LOADREG(esp);
842 CPUMCTX16_LOADREG(rip);
843 CPUMCTX16_LOADREG(rflags);
844
845 CPUMCTX16_LOADSEGREG(cs);
846 CPUMCTX16_LOADSEGREG(ds);
847 CPUMCTX16_LOADSEGREG(es);
848 CPUMCTX16_LOADSEGREG(fs);
849 CPUMCTX16_LOADSEGREG(gs);
850 CPUMCTX16_LOADSEGREG(ss);
851
852 CPUMCTX16_LOADREG(r8);
853 CPUMCTX16_LOADREG(r9);
854 CPUMCTX16_LOADREG(r10);
855 CPUMCTX16_LOADREG(r11);
856 CPUMCTX16_LOADREG(r12);
857 CPUMCTX16_LOADREG(r13);
858 CPUMCTX16_LOADREG(r14);
859 CPUMCTX16_LOADREG(r15);
860
861 CPUMCTX16_LOADREG(cr0);
862 CPUMCTX16_LOADREG(cr2);
863 CPUMCTX16_LOADREG(cr3);
864 CPUMCTX16_LOADREG(cr4);
865
866 CPUMCTX16_LOADDRXREG(0);
867 CPUMCTX16_LOADDRXREG(1);
868 CPUMCTX16_LOADDRXREG(2);
869 CPUMCTX16_LOADDRXREG(3);
870 CPUMCTX16_LOADDRXREG(4);
871 CPUMCTX16_LOADDRXREG(5);
872 CPUMCTX16_LOADDRXREG(6);
873 CPUMCTX16_LOADDRXREG(7);
874
875 pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
876 pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
877 pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
878 pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
879
880 CPUMCTX16_LOADREG(ldtr);
881 CPUMCTX16_LOADREG(tr);
882
883 pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
884
885 CPUMCTX16_LOADREG(msrEFER);
886 CPUMCTX16_LOADREG(msrSTAR);
887 CPUMCTX16_LOADREG(msrPAT);
888 CPUMCTX16_LOADREG(msrLSTAR);
889 CPUMCTX16_LOADREG(msrCSTAR);
890 CPUMCTX16_LOADREG(msrSFMASK);
891 CPUMCTX16_LOADREG(msrKERNELGSBASE);
892
893 CPUMCTX16_LOADHIDREG(ldtr);
894 CPUMCTX16_LOADHIDREG(tr);
895
896#undef CPUMCTX16_LOADSEGREG
897#undef CPUMCTX16_LOADHIDREG
898#undef CPUMCTX16_LOADDRXREG
899#undef CPUMCTX16_LOADREG
900}
901
902
903/**
904 * Execute state load operation.
905 *
906 * @returns VBox status code.
907 * @param pVM VM Handle.
908 * @param pSSM SSM operation handle.
909 * @param u32Version Data layout version.
910 */
911static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
912{
913 /*
914 * Validate version.
915 */
916 if ( u32Version != CPUM_SAVED_STATE_VERSION
917 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
918 && u32Version != CPUM_SAVED_STATE_VERSION_VER2_0
919 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
920 {
921 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
922 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
923 }
924
925 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
926 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
927 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
928 else
929 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
930
931 /*
932 * Restore.
933 */
934 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
935 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
936 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
937 pVM->cpum.s.Hyper.cr3 = uCR3;
938 pVM->cpum.s.Hyper.esp = uESP;
939 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
940 {
941 CPUMCTX_VER1_6 cpumctx16;
942 memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
943 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
944
945 /* Save the old cpumctx state into the new one. */
946 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
947
948 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
949 SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
950 }
951 else
952 {
953 if (u32Version >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
954 {
955 int rc = SSMR3GetU32(pSSM, &pVM->cCPUs);
956 AssertRCReturn(rc, rc);
957 }
958
959 if ( !pVM->cCPUs
960 || pVM->cCPUs > VMCPU_MAX_CPU_COUNT
961 || ( u32Version == CPUM_SAVED_STATE_VERSION_VER2_0
962 && pVM->cCPUs != 1))
963 {
964 AssertMsgFailed(("Unexpected number of VMCPUs (%d)\n", pVM->cCPUs));
965 return VERR_SSM_UNEXPECTED_DATA;
966 }
967
968 for (unsigned i=0;i<pVM->cCPUs;i++)
969 {
970 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
971 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
972 SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
973 if (u32Version == CPUM_SAVED_STATE_VERSION)
974 SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
975 }
976 }
977
978
979 uint32_t cElements;
980 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
981 /* Support old saved states with a smaller standard cpuid array. */
982 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
983 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
984 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
985
986 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
987 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
988 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
989 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
990
991 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
992 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
993 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
994 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
995
996 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
997
998 /*
999 * Check that the basic cpuid id information is unchanged.
1000 */
1001 uint32_t au32CpuId[8] = {0};
1002 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1003 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1004 uint32_t au32CpuIdSaved[8];
1005 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1006 if (RT_SUCCESS(rc))
1007 {
1008 /* Ignore APIC ID (AMD specs). */
1009 au32CpuId[5] &= ~0xff000000;
1010 au32CpuIdSaved[5] &= ~0xff000000;
1011 /* Ignore the number of Logical CPUs (AMD specs). */
1012 au32CpuId[5] &= ~0x00ff0000;
1013 au32CpuIdSaved[5] &= ~0x00ff0000;
1014
1015 /* do the compare */
1016 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1017 {
1018 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1019 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1020 "Saved=%.*Rhxs\n"
1021 "Real =%.*Rhxs\n",
1022 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1023 sizeof(au32CpuId), au32CpuId));
1024 else
1025 {
1026 LogRel(("cpumR3Load: CpuId mismatch!\n"
1027 "Saved=%.*Rhxs\n"
1028 "Real =%.*Rhxs\n",
1029 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1030 sizeof(au32CpuId), au32CpuId));
1031 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1032 }
1033 }
1034 }
1035
1036 return rc;
1037}
1038
1039
1040/**
1041 * Formats the EFLAGS value into mnemonics.
1042 *
1043 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1044 * @param efl The EFLAGS value.
1045 */
1046static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1047{
1048 /*
1049 * Format the flags.
1050 */
1051 static const struct
1052 {
1053 const char *pszSet; const char *pszClear; uint32_t fFlag;
1054 } s_aFlags[] =
1055 {
1056 { "vip",NULL, X86_EFL_VIP },
1057 { "vif",NULL, X86_EFL_VIF },
1058 { "ac", NULL, X86_EFL_AC },
1059 { "vm", NULL, X86_EFL_VM },
1060 { "rf", NULL, X86_EFL_RF },
1061 { "nt", NULL, X86_EFL_NT },
1062 { "ov", "nv", X86_EFL_OF },
1063 { "dn", "up", X86_EFL_DF },
1064 { "ei", "di", X86_EFL_IF },
1065 { "tf", NULL, X86_EFL_TF },
1066 { "nt", "pl", X86_EFL_SF },
1067 { "nz", "zr", X86_EFL_ZF },
1068 { "ac", "na", X86_EFL_AF },
1069 { "po", "pe", X86_EFL_PF },
1070 { "cy", "nc", X86_EFL_CF },
1071 };
1072 char *psz = pszEFlags;
1073 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1074 {
1075 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1076 if (pszAdd)
1077 {
1078 strcpy(psz, pszAdd);
1079 psz += strlen(pszAdd);
1080 *psz++ = ' ';
1081 }
1082 }
1083 psz[-1] = '\0';
1084}
1085
1086
1087/**
1088 * Formats a full register dump.
1089 *
1090 * @param pVM VM Handle.
1091 * @param pCtx The context to format.
1092 * @param pCtxCore The context core to format.
1093 * @param pHlp Output functions.
1094 * @param enmType The dump type.
1095 * @param pszPrefix Register name prefix.
1096 */
1097static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1098{
1099 /*
1100 * Format the EFLAGS.
1101 */
1102 uint32_t efl = pCtxCore->eflags.u32;
1103 char szEFlags[80];
1104 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1105
1106 /*
1107 * Format the registers.
1108 */
1109 switch (enmType)
1110 {
1111 case CPUMDUMPTYPE_TERSE:
1112 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1113 pHlp->pfnPrintf(pHlp,
1114 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1115 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1116 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1117 "%sr14=%016RX64 %sr15=%016RX64\n"
1118 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1119 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1120 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1121 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1122 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1123 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1124 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1125 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1126 else
1127 pHlp->pfnPrintf(pHlp,
1128 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1129 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1130 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1131 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1132 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1133 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1134 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1135 break;
1136
1137 case CPUMDUMPTYPE_DEFAULT:
1138 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1139 pHlp->pfnPrintf(pHlp,
1140 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1141 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1142 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1143 "%sr14=%016RX64 %sr15=%016RX64\n"
1144 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1145 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1146 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1147 ,
1148 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1149 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1150 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1151 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1152 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1153 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1154 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1155 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1156 else
1157 pHlp->pfnPrintf(pHlp,
1158 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1159 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1160 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1161 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1162 ,
1163 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1164 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1165 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1166 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1167 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1168 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1169 break;
1170
1171 case CPUMDUMPTYPE_VERBOSE:
1172 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1173 pHlp->pfnPrintf(pHlp,
1174 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1175 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1176 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1177 "%sr14=%016RX64 %sr15=%016RX64\n"
1178 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1179 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1180 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1181 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1182 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1183 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1184 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1185 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1186 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1187 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1188 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1189 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1190 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1191 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1192 ,
1193 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1194 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1195 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1196 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1197 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1198 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1199 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1200 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1201 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1202 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1203 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1204 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1205 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1206 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1207 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1208 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1209 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1210 else
1211 pHlp->pfnPrintf(pHlp,
1212 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1213 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1214 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1215 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1216 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1217 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1218 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1219 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1220 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1221 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1222 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1223 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1224 ,
1225 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1226 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1227 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1228 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1229 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1230 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1231 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1232 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1233 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1234 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1235 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1236 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1237
1238 pHlp->pfnPrintf(pHlp,
1239 "FPU:\n"
1240 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1241 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1242 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1243 ,
1244 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1245 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1246 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1247 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1248
1249 pHlp->pfnPrintf(pHlp,
1250 "MSR:\n"
1251 "%sEFER =%016RX64\n"
1252 "%sPAT =%016RX64\n"
1253 "%sSTAR =%016RX64\n"
1254 "%sCSTAR =%016RX64\n"
1255 "%sLSTAR =%016RX64\n"
1256 "%sSFMASK =%016RX64\n"
1257 "%sKERNELGSBASE =%016RX64\n",
1258 pszPrefix, pCtx->msrEFER,
1259 pszPrefix, pCtx->msrPAT,
1260 pszPrefix, pCtx->msrSTAR,
1261 pszPrefix, pCtx->msrCSTAR,
1262 pszPrefix, pCtx->msrLSTAR,
1263 pszPrefix, pCtx->msrSFMASK,
1264 pszPrefix, pCtx->msrKERNELGSBASE);
1265 break;
1266 }
1267}
1268
1269
1270/**
1271 * Display all cpu states and any other cpum info.
1272 *
1273 * @param pVM VM Handle.
1274 * @param pHlp The info helper functions.
1275 * @param pszArgs Arguments, ignored.
1276 */
1277static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1278{
1279 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1280 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1281 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1282 cpumR3InfoHost(pVM, pHlp, pszArgs);
1283}
1284
1285
1286/**
1287 * Parses the info argument.
1288 *
1289 * The argument starts with 'verbose', 'terse' or 'default' and then
1290 * continues with the comment string.
1291 *
1292 * @param pszArgs The pointer to the argument string.
1293 * @param penmType Where to store the dump type request.
1294 * @param ppszComment Where to store the pointer to the comment string.
1295 */
1296static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1297{
1298 if (!pszArgs)
1299 {
1300 *penmType = CPUMDUMPTYPE_DEFAULT;
1301 *ppszComment = "";
1302 }
1303 else
1304 {
1305 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1306 {
1307 pszArgs += 5;
1308 *penmType = CPUMDUMPTYPE_VERBOSE;
1309 }
1310 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1311 {
1312 pszArgs += 5;
1313 *penmType = CPUMDUMPTYPE_TERSE;
1314 }
1315 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1316 {
1317 pszArgs += 7;
1318 *penmType = CPUMDUMPTYPE_DEFAULT;
1319 }
1320 else
1321 *penmType = CPUMDUMPTYPE_DEFAULT;
1322 *ppszComment = RTStrStripL(pszArgs);
1323 }
1324}
1325
1326
1327/**
1328 * Display the guest cpu state.
1329 *
1330 * @param pVM VM Handle.
1331 * @param pHlp The info helper functions.
1332 * @param pszArgs Arguments, ignored.
1333 */
1334static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1335{
1336 CPUMDUMPTYPE enmType;
1337 const char *pszComment;
1338 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1339 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1340 /* @todo SMP */
1341 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVM);
1342 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1343}
1344
1345
1346/**
1347 * Display the current guest instruction
1348 *
1349 * @param pVM VM Handle.
1350 * @param pHlp The info helper functions.
1351 * @param pszArgs Arguments, ignored.
1352 */
1353static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1354{
1355 char szInstruction[256];
1356 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1357 if (RT_SUCCESS(rc))
1358 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1359}
1360
1361
1362/**
1363 * Display the hypervisor cpu state.
1364 *
1365 * @param pVM VM Handle.
1366 * @param pHlp The info helper functions.
1367 * @param pszArgs Arguments, ignored.
1368 */
1369static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1370{
1371 CPUMDUMPTYPE enmType;
1372 const char *pszComment;
1373 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1374 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1375 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1376 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1377}
1378
1379
1380/**
1381 * Display the host cpu state.
1382 *
1383 * @param pVM VM Handle.
1384 * @param pHlp The info helper functions.
1385 * @param pszArgs Arguments, ignored.
1386 */
1387static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1388{
1389 CPUMDUMPTYPE enmType;
1390 const char *pszComment;
1391 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1392 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1393
1394 /*
1395 * Format the EFLAGS.
1396 */
1397 /* @todo SMP */
1398 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1399#if HC_ARCH_BITS == 32
1400 uint32_t efl = pCtx->eflags.u32;
1401#else
1402 uint64_t efl = pCtx->rflags;
1403#endif
1404 char szEFlags[80];
1405 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1406
1407 /*
1408 * Format the registers.
1409 */
1410#if HC_ARCH_BITS == 32
1411# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1412 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1413# endif
1414 {
1415 pHlp->pfnPrintf(pHlp,
1416 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1417 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1418 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1419 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1420 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1421 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1422 ,
1423 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1424 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1425 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1426 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1427 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1428 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1429 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1430 }
1431# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1432 else
1433# endif
1434#endif
1435#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1436 {
1437 pHlp->pfnPrintf(pHlp,
1438 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1439 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1440 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1441 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1442 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1443 "r14=%016RX64 r15=%016RX64\n"
1444 "iopl=%d %31s\n"
1445 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1446 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1447 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1448 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1449 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1450 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1451 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1452 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1453 ,
1454 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1455 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1456 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1457 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1458 pCtx->r11, pCtx->r12, pCtx->r13,
1459 pCtx->r14, pCtx->r15,
1460 X86_EFL_GET_IOPL(efl), szEFlags,
1461 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1462 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1463 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1464 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1465 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1466 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1467 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1468 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1469 }
1470#endif
1471}
1472
1473
1474/**
1475 * Get L1 cache / TLS associativity.
1476 */
1477static const char *getCacheAss(unsigned u, char *pszBuf)
1478{
1479 if (u == 0)
1480 return "res0 ";
1481 if (u == 1)
1482 return "direct";
1483 if (u >= 256)
1484 return "???";
1485
1486 RTStrPrintf(pszBuf, 16, "%d way", u);
1487 return pszBuf;
1488}
1489
1490
1491/**
1492 * Get L2 cache soociativity.
1493 */
1494const char *getL2CacheAss(unsigned u)
1495{
1496 switch (u)
1497 {
1498 case 0: return "off ";
1499 case 1: return "direct";
1500 case 2: return "2 way ";
1501 case 3: return "res3 ";
1502 case 4: return "4 way ";
1503 case 5: return "res5 ";
1504 case 6: return "8 way "; case 7: return "res7 ";
1505 case 8: return "16 way";
1506 case 9: return "res9 ";
1507 case 10: return "res10 ";
1508 case 11: return "res11 ";
1509 case 12: return "res12 ";
1510 case 13: return "res13 ";
1511 case 14: return "res14 ";
1512 case 15: return "fully ";
1513 default:
1514 return "????";
1515 }
1516}
1517
1518
1519/**
1520 * Display the guest CpuId leaves.
1521 *
1522 * @param pVM VM Handle.
1523 * @param pHlp The info helper functions.
1524 * @param pszArgs "terse", "default" or "verbose".
1525 */
1526static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1527{
1528 /*
1529 * Parse the argument.
1530 */
1531 unsigned iVerbosity = 1;
1532 if (pszArgs)
1533 {
1534 pszArgs = RTStrStripL(pszArgs);
1535 if (!strcmp(pszArgs, "terse"))
1536 iVerbosity--;
1537 else if (!strcmp(pszArgs, "verbose"))
1538 iVerbosity++;
1539 }
1540
1541 /*
1542 * Start cracking.
1543 */
1544 CPUMCPUID Host;
1545 CPUMCPUID Guest;
1546 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1547
1548 pHlp->pfnPrintf(pHlp,
1549 " RAW Standard CPUIDs\n"
1550 " Function eax ebx ecx edx\n");
1551 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1552 {
1553 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1554 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1555
1556 pHlp->pfnPrintf(pHlp,
1557 "Gst: %08x %08x %08x %08x %08x%s\n"
1558 "Hst: %08x %08x %08x %08x\n",
1559 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1560 i <= cStdMax ? "" : "*",
1561 Host.eax, Host.ebx, Host.ecx, Host.edx);
1562 }
1563
1564 /*
1565 * If verbose, decode it.
1566 */
1567 if (iVerbosity)
1568 {
1569 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1570 pHlp->pfnPrintf(pHlp,
1571 "Name: %.04s%.04s%.04s\n"
1572 "Supports: 0-%x\n",
1573 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1574 }
1575
1576 /*
1577 * Get Features.
1578 */
1579 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1580 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1581 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1582 if (cStdMax >= 1 && iVerbosity)
1583 {
1584 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1585 uint32_t uEAX = Guest.eax;
1586
1587 pHlp->pfnPrintf(pHlp,
1588 "Family: %d \tExtended: %d \tEffective: %d\n"
1589 "Model: %d \tExtended: %d \tEffective: %d\n"
1590 "Stepping: %d\n"
1591 "APIC ID: %#04x\n"
1592 "Logical CPUs: %d\n"
1593 "CLFLUSH Size: %d\n"
1594 "Brand ID: %#04x\n",
1595 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1596 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1597 ASMGetCpuStepping(uEAX),
1598 (Guest.ebx >> 24) & 0xff,
1599 (Guest.ebx >> 16) & 0xff,
1600 (Guest.ebx >> 8) & 0xff,
1601 (Guest.ebx >> 0) & 0xff);
1602 if (iVerbosity == 1)
1603 {
1604 uint32_t uEDX = Guest.edx;
1605 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1606 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1607 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1608 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1609 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1610 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1611 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1612 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1613 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1614 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1615 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1616 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1617 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1618 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1619 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1620 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1621 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1622 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1623 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1624 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1625 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1626 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1627 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1628 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1629 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1630 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1631 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1632 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1633 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1634 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1635 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1636 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1637 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1638 pHlp->pfnPrintf(pHlp, "\n");
1639
1640 uint32_t uECX = Guest.ecx;
1641 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1642 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1643 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1644 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1645 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1646 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1647 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1648 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1649 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1650 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1651 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1652 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1653 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1654 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1655 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1656 for (unsigned iBit = 14; iBit < 32; iBit++)
1657 if (uECX & RT_BIT(iBit))
1658 pHlp->pfnPrintf(pHlp, " %d", iBit);
1659 pHlp->pfnPrintf(pHlp, "\n");
1660 }
1661 else
1662 {
1663 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1664
1665 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1666 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1667 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1668 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1669
1670 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1671 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1672 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1673 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1674 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1675 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1676 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1677 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1678 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1679 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1680 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1681 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1682 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1683 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1684 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1685 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1686 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1687 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1688 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1689 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1690 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1691 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1692 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1693 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1694 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1695 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1696 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1697 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1698 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1699 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1700 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1701 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1702 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1703
1704 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1705 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1706 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1707 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1708 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1709 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1710 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1711 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1712 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1713 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1714 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1715 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1716 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1717 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1718 }
1719 }
1720 if (cStdMax >= 2 && iVerbosity)
1721 {
1722 /** @todo */
1723 }
1724
1725 /*
1726 * Extended.
1727 * Implemented after AMD specs.
1728 */
1729 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1730
1731 pHlp->pfnPrintf(pHlp,
1732 "\n"
1733 " RAW Extended CPUIDs\n"
1734 " Function eax ebx ecx edx\n");
1735 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1736 {
1737 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1738 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1739
1740 pHlp->pfnPrintf(pHlp,
1741 "Gst: %08x %08x %08x %08x %08x%s\n"
1742 "Hst: %08x %08x %08x %08x\n",
1743 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1744 i <= cExtMax ? "" : "*",
1745 Host.eax, Host.ebx, Host.ecx, Host.edx);
1746 }
1747
1748 /*
1749 * Understandable output
1750 */
1751 if (iVerbosity)
1752 {
1753 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1754 pHlp->pfnPrintf(pHlp,
1755 "Ext Name: %.4s%.4s%.4s\n"
1756 "Ext Supports: 0x80000000-%#010x\n",
1757 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1758 }
1759
1760 if (iVerbosity && cExtMax >= 1)
1761 {
1762 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1763 uint32_t uEAX = Guest.eax;
1764 pHlp->pfnPrintf(pHlp,
1765 "Family: %d \tExtended: %d \tEffective: %d\n"
1766 "Model: %d \tExtended: %d \tEffective: %d\n"
1767 "Stepping: %d\n"
1768 "Brand ID: %#05x\n",
1769 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1770 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1771 ASMGetCpuStepping(uEAX),
1772 Guest.ebx & 0xfff);
1773
1774 if (iVerbosity == 1)
1775 {
1776 uint32_t uEDX = Guest.edx;
1777 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1778 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1779 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1780 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1781 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1782 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1783 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1784 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1785 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1786 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1787 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1788 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1789 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1790 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1791 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1792 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1793 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1794 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1795 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1796 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1797 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1798 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1799 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1800 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1801 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1802 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1803 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1804 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1805 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1806 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1807 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1808 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1809 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1810 pHlp->pfnPrintf(pHlp, "\n");
1811
1812 uint32_t uECX = Guest.ecx;
1813 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1814 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1815 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1816 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1817 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1818 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1819 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1820 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1821 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1822 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1823 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1824 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1825 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1826 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1827 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1828 for (unsigned iBit = 5; iBit < 32; iBit++)
1829 if (uECX & RT_BIT(iBit))
1830 pHlp->pfnPrintf(pHlp, " %d", iBit);
1831 pHlp->pfnPrintf(pHlp, "\n");
1832 }
1833 else
1834 {
1835 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1836
1837 uint32_t uEdxGst = Guest.edx;
1838 uint32_t uEdxHst = Host.edx;
1839 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1840 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1841 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1842 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1843 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1844 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1845 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1846 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1847 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1848 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1849 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1850 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1851 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1852 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1853 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1854 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1855 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1856 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1857 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1858 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1859 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1860 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1861 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1862 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1863 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1864 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1865 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1866 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1867 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1868 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1869 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1870 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1871 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1872
1873 uint32_t uEcxGst = Guest.ecx;
1874 uint32_t uEcxHst = Host.ecx;
1875 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1876 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1877 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1878 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1879 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1880 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1881 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1882 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1883 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1884 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1885 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1886 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1887 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1888 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1889 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1890 }
1891 }
1892
1893 if (iVerbosity && cExtMax >= 2)
1894 {
1895 char szString[4*4*3+1] = {0};
1896 uint32_t *pu32 = (uint32_t *)szString;
1897 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1898 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1899 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1900 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1901 if (cExtMax >= 3)
1902 {
1903 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1904 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1905 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1906 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1907 }
1908 if (cExtMax >= 4)
1909 {
1910 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1911 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1912 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1913 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1914 }
1915 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1916 }
1917
1918 if (iVerbosity && cExtMax >= 5)
1919 {
1920 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1921 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1922 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1923 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1924 char sz1[32];
1925 char sz2[32];
1926
1927 pHlp->pfnPrintf(pHlp,
1928 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1929 "TLB 2/4M Data: %s %3d entries\n",
1930 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1931 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1932 pHlp->pfnPrintf(pHlp,
1933 "TLB 4K Instr/Uni: %s %3d entries\n"
1934 "TLB 4K Data: %s %3d entries\n",
1935 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1936 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1937 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1938 "L1 Instr Cache Lines Per Tag: %d\n"
1939 "L1 Instr Cache Associativity: %s\n"
1940 "L1 Instr Cache Size: %d KB\n",
1941 (uEDX >> 0) & 0xff,
1942 (uEDX >> 8) & 0xff,
1943 getCacheAss((uEDX >> 16) & 0xff, sz1),
1944 (uEDX >> 24) & 0xff);
1945 pHlp->pfnPrintf(pHlp,
1946 "L1 Data Cache Line Size: %d bytes\n"
1947 "L1 Data Cache Lines Per Tag: %d\n"
1948 "L1 Data Cache Associativity: %s\n"
1949 "L1 Data Cache Size: %d KB\n",
1950 (uECX >> 0) & 0xff,
1951 (uECX >> 8) & 0xff,
1952 getCacheAss((uECX >> 16) & 0xff, sz1),
1953 (uECX >> 24) & 0xff);
1954 }
1955
1956 if (iVerbosity && cExtMax >= 6)
1957 {
1958 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1959 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1960 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1961
1962 pHlp->pfnPrintf(pHlp,
1963 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1964 "L2 TLB 2/4M Data: %s %4d entries\n",
1965 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1966 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1967 pHlp->pfnPrintf(pHlp,
1968 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1969 "L2 TLB 4K Data: %s %4d entries\n",
1970 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1971 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1972 pHlp->pfnPrintf(pHlp,
1973 "L2 Cache Line Size: %d bytes\n"
1974 "L2 Cache Lines Per Tag: %d\n"
1975 "L2 Cache Associativity: %s\n"
1976 "L2 Cache Size: %d KB\n",
1977 (uEDX >> 0) & 0xff,
1978 (uEDX >> 8) & 0xf,
1979 getL2CacheAss((uEDX >> 12) & 0xf),
1980 (uEDX >> 16) & 0xffff);
1981 }
1982
1983 if (iVerbosity && cExtMax >= 7)
1984 {
1985 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1986
1987 pHlp->pfnPrintf(pHlp, "APM Features: ");
1988 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1989 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1990 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1991 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1992 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1993 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1994 for (unsigned iBit = 6; iBit < 32; iBit++)
1995 if (uEDX & RT_BIT(iBit))
1996 pHlp->pfnPrintf(pHlp, " %d", iBit);
1997 pHlp->pfnPrintf(pHlp, "\n");
1998 }
1999
2000 if (iVerbosity && cExtMax >= 8)
2001 {
2002 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
2003 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
2004
2005 pHlp->pfnPrintf(pHlp,
2006 "Physical Address Width: %d bits\n"
2007 "Virtual Address Width: %d bits\n",
2008 (uEAX >> 0) & 0xff,
2009 (uEAX >> 8) & 0xff);
2010 pHlp->pfnPrintf(pHlp,
2011 "Physical Core Count: %d\n",
2012 (uECX >> 0) & 0xff);
2013 }
2014
2015
2016 /*
2017 * Centaur.
2018 */
2019 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
2020
2021 pHlp->pfnPrintf(pHlp,
2022 "\n"
2023 " RAW Centaur CPUIDs\n"
2024 " Function eax ebx ecx edx\n");
2025 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
2026 {
2027 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
2028 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2029
2030 pHlp->pfnPrintf(pHlp,
2031 "Gst: %08x %08x %08x %08x %08x%s\n"
2032 "Hst: %08x %08x %08x %08x\n",
2033 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2034 i <= cCentaurMax ? "" : "*",
2035 Host.eax, Host.ebx, Host.ecx, Host.edx);
2036 }
2037
2038 /*
2039 * Understandable output
2040 */
2041 if (iVerbosity)
2042 {
2043 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
2044 pHlp->pfnPrintf(pHlp,
2045 "Centaur Supports: 0xc0000000-%#010x\n",
2046 Guest.eax);
2047 }
2048
2049 if (iVerbosity && cCentaurMax >= 1)
2050 {
2051 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2052 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
2053 uint32_t uEdxHst = Host.edx;
2054
2055 if (iVerbosity == 1)
2056 {
2057 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
2058 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
2059 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
2060 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
2061 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
2062 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
2063 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
2064 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
2065 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
2066 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2067 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2068 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2069 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2070 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2071 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2072 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2073 for (unsigned iBit = 14; iBit < 32; iBit++)
2074 if (uEdxGst & RT_BIT(iBit))
2075 pHlp->pfnPrintf(pHlp, " %d", iBit);
2076 pHlp->pfnPrintf(pHlp, "\n");
2077 }
2078 else
2079 {
2080 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2081 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2082 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2083 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2084 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2085 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2086 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2087 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2088 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2089 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2090 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2091 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2092 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2093 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2094 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2095 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2096 for (unsigned iBit = 14; iBit < 32; iBit++)
2097 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2098 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2099 pHlp->pfnPrintf(pHlp, "\n");
2100 }
2101 }
2102}
2103
2104
2105/**
2106 * Structure used when disassembling and instructions in DBGF.
2107 * This is used so the reader function can get the stuff it needs.
2108 */
2109typedef struct CPUMDISASSTATE
2110{
2111 /** Pointer to the CPU structure. */
2112 PDISCPUSTATE pCpu;
2113 /** The VM handle. */
2114 PVM pVM;
2115 /** Pointer to the first byte in the segemnt. */
2116 RTGCUINTPTR GCPtrSegBase;
2117 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2118 RTGCUINTPTR GCPtrSegEnd;
2119 /** The size of the segment minus 1. */
2120 RTGCUINTPTR cbSegLimit;
2121 /** Pointer to the current page - R3 Ptr. */
2122 void const *pvPageR3;
2123 /** Pointer to the current page - GC Ptr. */
2124 RTGCPTR pvPageGC;
2125 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2126 PGMPAGEMAPLOCK PageMapLock;
2127 /** Whether the PageMapLock is valid or not. */
2128 bool fLocked;
2129 /** 64 bits mode or not. */
2130 bool f64Bits;
2131} CPUMDISASSTATE, *PCPUMDISASSTATE;
2132
2133
2134/**
2135 * Instruction reader.
2136 *
2137 * @returns VBox status code.
2138 * @param PtrSrc Address to read from.
2139 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2140 * @param pu8Dst Where to store the bytes.
2141 * @param cbRead Number of bytes to read.
2142 * @param uDisCpu Pointer to the disassembler cpu state.
2143 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2144 */
2145static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2146{
2147 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2148 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2149 Assert(cbRead > 0);
2150 for (;;)
2151 {
2152 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2153
2154 /* Need to update the page translation? */
2155 if ( !pState->pvPageR3
2156 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2157 {
2158 int rc = VINF_SUCCESS;
2159
2160 /* translate the address */
2161 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2162 if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
2163 && !HWACCMIsEnabled(pState->pVM))
2164 {
2165 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2166 if (!pState->pvPageR3)
2167 rc = VERR_INVALID_POINTER;
2168 }
2169 else
2170 {
2171 /* Release mapping lock previously acquired. */
2172 if (pState->fLocked)
2173 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2174 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2175 pState->fLocked = RT_SUCCESS_NP(rc);
2176 }
2177 if (RT_FAILURE(rc))
2178 {
2179 pState->pvPageR3 = NULL;
2180 return rc;
2181 }
2182 }
2183
2184 /* check the segemnt limit */
2185 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2186 return VERR_OUT_OF_SELECTOR_BOUNDS;
2187
2188 /* calc how much we can read */
2189 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2190 if (!pState->f64Bits)
2191 {
2192 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2193 if (cb > cbSeg && cbSeg)
2194 cb = cbSeg;
2195 }
2196 if (cb > cbRead)
2197 cb = cbRead;
2198
2199 /* read and advance */
2200 memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2201 cbRead -= cb;
2202 if (!cbRead)
2203 return VINF_SUCCESS;
2204 pu8Dst += cb;
2205 PtrSrc += cb;
2206 }
2207}
2208
2209
2210/**
2211 * Disassemble an instruction and return the information in the provided structure.
2212 *
2213 * @returns VBox status code.
2214 * @param pVM VM Handle
2215 * @param pCtx CPU context
2216 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2217 * @param pCpu Disassembly state
2218 * @param pszPrefix String prefix for logging (debug only)
2219 *
2220 */
2221VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2222{
2223 CPUMDISASSTATE State;
2224 int rc;
2225
2226 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2227 State.pCpu = pCpu;
2228 State.pvPageGC = 0;
2229 State.pvPageR3 = NULL;
2230 State.pVM = pVM;
2231 State.fLocked = false;
2232 State.f64Bits = false;
2233
2234 /*
2235 * Get selector information.
2236 */
2237 if ( (pCtx->cr0 & X86_CR0_PE)
2238 && pCtx->eflags.Bits.u1VM == 0)
2239 {
2240 if (CPUMAreHiddenSelRegsValid(pVM))
2241 {
2242 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2243 State.GCPtrSegBase = pCtx->csHid.u64Base;
2244 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2245 State.cbSegLimit = pCtx->csHid.u32Limit;
2246 pCpu->mode = (State.f64Bits)
2247 ? CPUMODE_64BIT
2248 : pCtx->csHid.Attr.n.u1DefBig
2249 ? CPUMODE_32BIT
2250 : CPUMODE_16BIT;
2251 }
2252 else
2253 {
2254 SELMSELINFO SelInfo;
2255
2256 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2257 if (!RT_SUCCESS(rc))
2258 {
2259 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2260 return rc;
2261 }
2262
2263 /*
2264 * Validate the selector.
2265 */
2266 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2267 if (!RT_SUCCESS(rc))
2268 {
2269 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2270 return rc;
2271 }
2272 State.GCPtrSegBase = SelInfo.GCPtrBase;
2273 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2274 State.cbSegLimit = SelInfo.cbLimit;
2275 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2276 }
2277 }
2278 else
2279 {
2280 /* real or V86 mode */
2281 pCpu->mode = CPUMODE_16BIT;
2282 State.GCPtrSegBase = pCtx->cs * 16;
2283 State.GCPtrSegEnd = 0xFFFFFFFF;
2284 State.cbSegLimit = 0xFFFFFFFF;
2285 }
2286
2287 /*
2288 * Disassemble the instruction.
2289 */
2290 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2291 pCpu->apvUserData[0] = &State;
2292
2293 uint32_t cbInstr;
2294#ifndef LOG_ENABLED
2295 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2296 if (RT_SUCCESS(rc))
2297 {
2298#else
2299 char szOutput[160];
2300 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2301 if (RT_SUCCESS(rc))
2302 {
2303 /* log it */
2304 if (pszPrefix)
2305 Log(("%s: %s", pszPrefix, szOutput));
2306 else
2307 Log(("%s", szOutput));
2308#endif
2309 rc = VINF_SUCCESS;
2310 }
2311 else
2312 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
2313
2314 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2315 if (State.fLocked)
2316 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2317
2318 return rc;
2319}
2320
2321#ifdef DEBUG
2322
2323/**
2324 * Disassemble an instruction and dump it to the log
2325 *
2326 * @returns VBox status code.
2327 * @param pVM VM Handle
2328 * @param pCtx CPU context
2329 * @param pc GC instruction pointer
2330 * @param pszPrefix String prefix for logging
2331 *
2332 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2333 */
2334VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2335{
2336 DISCPUSTATE Cpu;
2337 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2338}
2339
2340
2341/**
2342 * Disassemble an instruction and dump it to the log
2343 *
2344 * @returns VBox status code.
2345 * @param pVM VM Handle
2346 * @param pCtx CPU context
2347 * @param pc GC instruction pointer
2348 * @param pszPrefix String prefix for logging
2349 * @param nrInstructions
2350 *
2351 * @deprecated Create new DBGFR3Disas function to do this.
2352 */
2353VMMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2354{
2355 for (int i = 0; i < nrInstructions; i++)
2356 {
2357 DISCPUSTATE cpu;
2358
2359 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2360 pc += cpu.opsize;
2361 }
2362}
2363
2364
2365/**
2366 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2367 *
2368 * @internal
2369 */
2370VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2371{
2372 /* @todo SMP */
2373 pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(pVM);
2374}
2375
2376#endif /* DEBUG */
2377
2378/**
2379 * API for controlling a few of the CPU features found in CR4.
2380 *
2381 * Currently only X86_CR4_TSD is accepted as input.
2382 *
2383 * @returns VBox status code.
2384 *
2385 * @param pVM The VM handle.
2386 * @param fOr The CR4 OR mask.
2387 * @param fAnd The CR4 AND mask.
2388 */
2389VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2390{
2391 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2392 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2393
2394 pVM->cpum.s.CR4.OrMask &= fAnd;
2395 pVM->cpum.s.CR4.OrMask |= fOr;
2396
2397 return VINF_SUCCESS;
2398}
2399
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