VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 12986

Last change on this file since 12986 was 12971, checked in by vboxsync, 16 years ago

x2APIC bits definitions
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1/* $Id: CPUM.cpp 12971 2008-10-03 11:06:57Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum CPUM - CPU Monitor / Manager
23 *
24 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
25 * also responsible for lazy FPU handling and some of the context loading
26 * in raw mode.
27 *
28 * There are three CPU contexts, the most important one is the guest one (GC).
29 * When running in raw-mode (RC) there is a special hyper context for the VMM
30 * part that floats around inside the guest address space. When running in
31 * raw-mode, CPUM also maintains a host context for saving and restoring
32 * registers accross world switches. This latter is done in cooperation with the
33 * world switcher (@see pg_vmm).
34 */
35
36/*******************************************************************************
37* Header Files *
38*******************************************************************************/
39#define LOG_GROUP LOG_GROUP_CPUM
40#include <VBox/cpum.h>
41#include <VBox/cpumdis.h>
42#include <VBox/pgm.h>
43#include <VBox/pdm.h>
44#include <VBox/mm.h>
45#include <VBox/selm.h>
46#include <VBox/dbgf.h>
47#include <VBox/patm.h>
48#include <VBox/ssm.h>
49#include "CPUMInternal.h"
50#include <VBox/vm.h>
51
52#include <VBox/param.h>
53#include <VBox/dis.h>
54#include <VBox/err.h>
55#include <VBox/log.h>
56#include <iprt/assert.h>
57#include <iprt/asm.h>
58#include <iprt/string.h>
59#include <iprt/mp.h>
60#include <iprt/cpuset.h>
61
62
63/*******************************************************************************
64* Defined Constants And Macros *
65*******************************************************************************/
66/** The saved state version. */
67#define CPUM_SAVED_STATE_VERSION 8
68/** The saved state version of 1.6, used for backwards compatability. */
69#define CPUM_SAVED_STATE_VERSION_VER1_6 6
70
71
72/*******************************************************************************
73* Structures and Typedefs *
74*******************************************************************************/
75
76/**
77 * What kind of cpu info dump to perform.
78 */
79typedef enum CPUMDUMPTYPE
80{
81 CPUMDUMPTYPE_TERSE,
82 CPUMDUMPTYPE_DEFAULT,
83 CPUMDUMPTYPE_VERBOSE
84
85} CPUMDUMPTYPE;
86/** Pointer to a cpu info dump type. */
87typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
88
89
90/*******************************************************************************
91* Internal Functions *
92*******************************************************************************/
93static int cpumR3CpuIdInit(PVM pVM);
94static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
95static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
96static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102
103
104/**
105 * Initializes the CPUM.
106 *
107 * @returns VBox status code.
108 * @param pVM The VM to operate on.
109 */
110CPUMR3DECL(int) CPUMR3Init(PVM pVM)
111{
112 LogFlow(("CPUMR3Init\n"));
113
114 /*
115 * Assert alignment and sizes.
116 */
117 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
118 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
119
120 /*
121 * Setup any fixed pointers and offsets.
122 */
123 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
124 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
125
126 /* Hidden selector registers are invalid by default. */
127 pVM->cpum.s.fValidHiddenSelRegs = false;
128
129 /*
130 * Check that the CPU supports the minimum features we require.
131 */
132 if (!ASMHasCpuId())
133 {
134 Log(("The CPU doesn't support CPUID!\n"));
135 return VERR_UNSUPPORTED_CPU;
136 }
137 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
138 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
139
140 /* Setup the CR4 AND and OR masks used in the switcher */
141 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
142 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
143 {
144 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
145 /* No FXSAVE implies no SSE */
146 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
147 pVM->cpum.s.CR4.OrMask = 0;
148 }
149 else
150 {
151 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
152 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
153 }
154
155 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
156 {
157 Log(("The CPU doesn't support MMX!\n"));
158 return VERR_UNSUPPORTED_CPU;
159 }
160 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
161 {
162 Log(("The CPU doesn't support TSC!\n"));
163 return VERR_UNSUPPORTED_CPU;
164 }
165 /* Bogus on AMD? */
166 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
167 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
168
169 /*
170 * Setup hypervisor startup values.
171 */
172
173 /*
174 * Register saved state data item.
175 */
176 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
177 NULL, cpumR3Save, NULL,
178 NULL, cpumR3Load, NULL);
179 if (VBOX_FAILURE(rc))
180 return rc;
181
182 /* Query the CPU manufacturer. */
183 uint32_t uEAX, uEBX, uECX, uEDX;
184 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
185 if ( uEAX >= 1
186 && uEBX == X86_CPUID_VENDOR_AMD_EBX
187 && uECX == X86_CPUID_VENDOR_AMD_ECX
188 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
189 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
190 else if ( uEAX >= 1
191 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
192 && uECX == X86_CPUID_VENDOR_INTEL_ECX
193 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
194 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
195 else /** @todo Via */
196 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
197
198 /*
199 * Register info handlers.
200 */
201 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
202 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
203 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
204 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
205 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
206 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
207
208 /*
209 * Initialize the Guest CPU state.
210 */
211 rc = cpumR3CpuIdInit(pVM);
212 if (VBOX_FAILURE(rc))
213 return rc;
214 CPUMR3Reset(pVM);
215 return VINF_SUCCESS;
216}
217
218
219/**
220 * Initializes the emulated CPU's cpuid information.
221 *
222 * @returns VBox status code.
223 * @param pVM The VM to operate on.
224 */
225static int cpumR3CpuIdInit(PVM pVM)
226{
227 PCPUM pCPUM = &pVM->cpum.s;
228 uint32_t i;
229
230 /*
231 * Get the host CPUIDs.
232 */
233 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
234 ASMCpuId_Idx_ECX(i, 0,
235 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
236 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
237 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
238 ASMCpuId(0x80000000 + i,
239 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
240 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
241 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
242 ASMCpuId(0xc0000000 + i,
243 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
244 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
245
246
247 /*
248 * Only report features we can support.
249 */
250 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
251 | X86_CPUID_FEATURE_EDX_VME
252 | X86_CPUID_FEATURE_EDX_DE
253 | X86_CPUID_FEATURE_EDX_PSE
254 | X86_CPUID_FEATURE_EDX_TSC
255 | X86_CPUID_FEATURE_EDX_MSR
256 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
257 | X86_CPUID_FEATURE_EDX_MCE
258 | X86_CPUID_FEATURE_EDX_CX8
259 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
260 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
261 //| X86_CPUID_FEATURE_EDX_SEP
262 | X86_CPUID_FEATURE_EDX_MTRR
263 | X86_CPUID_FEATURE_EDX_PGE
264 | X86_CPUID_FEATURE_EDX_MCA
265 | X86_CPUID_FEATURE_EDX_CMOV
266 | X86_CPUID_FEATURE_EDX_PAT
267 | X86_CPUID_FEATURE_EDX_PSE36
268 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
269 | X86_CPUID_FEATURE_EDX_CLFSH
270 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
271 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
272 | X86_CPUID_FEATURE_EDX_MMX
273 | X86_CPUID_FEATURE_EDX_FXSR
274 | X86_CPUID_FEATURE_EDX_SSE
275 | X86_CPUID_FEATURE_EDX_SSE2
276 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
277 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
278 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
279 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
280 | 0;
281 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
282 | X86_CPUID_FEATURE_ECX_MONITOR
283 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
284 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
285 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
286 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
287 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
288 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
289 //| X86_CPUID_FEATURE_ECX_CX16
290 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
291 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
292 /* ECX Bit 21 - x2APIC support - not yet. */
293 // | X86_CPUID_FEATURE_ECX_X2APIC
294 /* ECX Bit 23 - POPCOUNT instruction. */
295 //| X86_CPUID_FEATURE_ECX_POPCOUNT
296 | 0;
297
298 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
299 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
300 | X86_CPUID_AMD_FEATURE_EDX_VME
301 | X86_CPUID_AMD_FEATURE_EDX_DE
302 | X86_CPUID_AMD_FEATURE_EDX_PSE
303 | X86_CPUID_AMD_FEATURE_EDX_TSC
304 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
305 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
306 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
307 | X86_CPUID_AMD_FEATURE_EDX_CX8
308 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
309 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
310 //| X86_CPUID_AMD_FEATURE_EDX_SEP
311 | X86_CPUID_AMD_FEATURE_EDX_MTRR
312 | X86_CPUID_AMD_FEATURE_EDX_PGE
313 | X86_CPUID_AMD_FEATURE_EDX_MCA
314 | X86_CPUID_AMD_FEATURE_EDX_CMOV
315 | X86_CPUID_AMD_FEATURE_EDX_PAT
316 | X86_CPUID_AMD_FEATURE_EDX_PSE36
317 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
318 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
319 | X86_CPUID_AMD_FEATURE_EDX_MMX
320 | X86_CPUID_AMD_FEATURE_EDX_FXSR
321 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
322 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
323 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
324 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
325 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
326 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
327 | 0;
328 pCPUM->aGuestCpuIdExt[1].ecx &= 0
329 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
330 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
331 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
332 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
333 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
334 //| X86_CPUID_AMD_FEATURE_ECX_ABM
335 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
336 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
337 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
338 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
339 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
340 //| X86_CPUID_AMD_FEATURE_ECX_WDT
341 | 0;
342
343 /*
344 * Hide HTT, multicode, SMP, whatever.
345 * (APIC-ID := 0 and #LogCpus := 0)
346 */
347 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
348
349 /* Cpuid 2:
350 * Intel: Cache and TLB information
351 * AMD: Reserved
352 * Safe to expose
353 */
354
355 /* Cpuid 3:
356 * Intel: EAX, EBX - reserved
357 * ECX, EDX - Processor Serial Number if available, otherwise reserved
358 * AMD: Reserved
359 * Safe to expose
360 */
361 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
362 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
363
364 /* Cpuid 4:
365 * Intel: Deterministic Cache Parameters Leaf
366 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
367 * AMD: Reserved
368 * Safe to expose, except for EAX:
369 * Bits 25-14: Maximum number of threads sharing this cache in a physical package (see note)**
370 * Bits 31-26: Maximum number of processor cores in this physical package**
371 */
372 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
373 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
374
375 /* Cpuid 5: Monitor/mwait Leaf
376 * Intel: ECX, EDX - reserved
377 * EAX, EBX - Smallest and largest monitor line size
378 * AMD: EDX - reserved
379 * EAX, EBX - Smallest and largest monitor line size
380 * ECX - extensions (ignored for now)
381 * Safe to expose
382 */
383 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
384 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
385
386 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
387
388 /*
389 * Determine the default.
390 *
391 * Intel returns values of the highest standard function, while AMD
392 * returns zeros. VIA on the other hand seems to returning nothing or
393 * perhaps some random garbage, we don't try to duplicate this behavior.
394 */
395 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
396 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
397 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
398
399 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
400 * Safe to pass on to the guest.
401 *
402 * Intel: 0x800000005 reserved
403 * 0x800000006 L2 cache information
404 * AMD: 0x800000005 L1 cache information
405 * 0x800000006 L2/L3 cache information
406 */
407
408 /* Cpuid 0x800000007:
409 * AMD: EAX, EBX, ECX - reserved
410 * EDX: Advanced Power Management Information
411 * Intel: Reserved
412 */
413 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
414 {
415 Assert(pVM->cpum.s.enmCPUVendor != CPUMCPUVENDOR_INVALID);
416
417 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
418
419 if (pVM->cpum.s.enmCPUVendor == CPUMCPUVENDOR_AMD)
420 {
421 /* Only expose the TSC invariant capability bit to the guest. */
422 pCPUM->aGuestCpuIdExt[7].edx &= 0
423 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
424 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
425 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
426 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
427 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
428 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
429 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
430 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
431 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
432 | 0;
433 }
434 else
435 pCPUM->aGuestCpuIdExt[7].edx = 0;
436 }
437
438 /* Cpuid 0x800000008:
439 * AMD: EBX, EDX - reserved
440 * EAX: Virtual/Physical address Size
441 * ECX: Number of cores + APICIdCoreIdSize
442 * Intel: EAX: Virtual/Physical address Size
443 * EBX, ECX, EDX - reserved
444 */
445 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
446 {
447 /* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
448 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
449 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
450 * NC (0-7) Number of cores; 0 equals 1 core */
451 pCPUM->aGuestCpuIdExt[8].ecx = 0;
452 }
453
454 /*
455 * Limit it the number of entries and fill the remaining with the defaults.
456 *
457 * The limits are masking off stuff about power saving and similar, this
458 * is perhaps a bit crudely done as there is probably some relatively harmless
459 * info too in these leaves (like words about having a constant TSC).
460 */
461#if 0
462 /** @todo NT4 installation regression - investigate */
463 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
464 pCPUM->aGuestCpuIdStd[0].eax = 5;
465#else
466 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
467 pCPUM->aGuestCpuIdStd[0].eax = 2;
468#endif
469 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
470 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
471
472 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
473 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
474 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
475 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
476 : 0;
477 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
478 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
479
480 /*
481 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
482 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
483 * We currently don't support more than 1 processor.
484 */
485 pCPUM->aGuestCpuIdStd[4].eax = 0;
486
487 /*
488 * Centaur stuff (VIA).
489 *
490 * The important part here (we think) is to make sure the 0xc0000000
491 * function returns 0xc0000001. As for the features, we don't currently
492 * let on about any of those... 0xc0000002 seems to be some
493 * temperature/hz/++ stuff, include it as well (static).
494 */
495 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
496 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
497 {
498 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
499 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
500 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
501 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
502 i++)
503 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
504 }
505 else
506 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
507 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
508
509
510 /*
511 * Load CPUID overrides from configuration.
512 */
513 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
514 * Overloads the CPUID leaf values. */
515 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
516 uint32_t cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
517 for (i=0;; )
518 {
519 while (cElements-- > 0)
520 {
521 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
522 if (pNode)
523 {
524 uint32_t u32;
525 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
526 if (VBOX_SUCCESS(rc))
527 pCpuId->eax = u32;
528 else
529 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
530
531 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
532 if (VBOX_SUCCESS(rc))
533 pCpuId->ebx = u32;
534 else
535 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
536
537 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
538 if (VBOX_SUCCESS(rc))
539 pCpuId->ecx = u32;
540 else
541 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
542
543 rc = CFGMR3QueryU32(pNode, "edx", &u32);
544 if (VBOX_SUCCESS(rc))
545 pCpuId->edx = u32;
546 else
547 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
548 }
549 pCpuId++;
550 i++;
551 }
552
553 /* next */
554 if ((i & UINT32_C(0xc0000000)) == 0)
555 {
556 pCpuId = &pCPUM->aGuestCpuIdExt[0];
557 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
558 i = UINT32_C(0x80000000);
559 }
560 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
561 {
562 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
563 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
564 i = UINT32_C(0xc0000000);
565 }
566 else
567 break;
568 }
569
570 /* Check if PAE was explicitely enabled by the user. */
571 bool fEnable = false;
572 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
573 if (VBOX_SUCCESS(rc) && fEnable)
574 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
575
576 /*
577 * Log the cpuid and we're good.
578 */
579 RTCPUSET OnlineSet;
580 LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
581 (int)RTMpGetCount(), RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
582 LogRel(("************************* CPUID dump ************************\n"));
583 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
584 LogRel(("\n"));
585 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
586 LogRel(("******************** End of CPUID dump **********************\n"));
587 return VINF_SUCCESS;
588}
589
590
591
592
593/**
594 * Applies relocations to data and code managed by this
595 * component. This function will be called at init and
596 * whenever the VMM need to relocate it self inside the GC.
597 *
598 * The CPUM will update the addresses used by the switcher.
599 *
600 * @param pVM The VM.
601 */
602CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
603{
604 LogFlow(("CPUMR3Relocate\n"));
605 /*
606 * Switcher pointers.
607 */
608 pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
609 Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
610}
611
612
613/**
614 * Queries the pointer to the internal CPUMCTX structure
615 *
616 * @returns VBox status code.
617 * @param pVM Handle to the virtual machine.
618 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
619 */
620CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
621{
622 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
623 /*
624 * Store the address. (Later we might check how's calling, thus the RC.)
625 */
626 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
627 return VINF_SUCCESS;
628}
629
630
631/**
632 * Terminates the CPUM.
633 *
634 * Termination means cleaning up and freeing all resources,
635 * the VM it self is at this point powered off or suspended.
636 *
637 * @returns VBox status code.
638 * @param pVM The VM to operate on.
639 */
640CPUMR3DECL(int) CPUMR3Term(PVM pVM)
641{
642 /** @todo ? */
643 return 0;
644}
645
646
647/**
648 * Resets the CPU.
649 *
650 * @returns VINF_SUCCESS.
651 * @param pVM The VM handle.
652 */
653CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
654{
655 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
656
657 /*
658 * Initialize everything to ZERO first.
659 */
660 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
661 memset(pCtx, 0, sizeof(*pCtx));
662 pVM->cpum.s.fUseFlags = fUseFlags;
663
664 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
665 pCtx->eip = 0x0000fff0;
666 pCtx->edx = 0x00000600; /* P6 processor */
667 pCtx->eflags.Bits.u1Reserved0 = 1;
668
669 pCtx->cs = 0xf000;
670 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
671 pCtx->csHid.u32Limit = 0x0000ffff;
672 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
673 pCtx->csHid.Attr.n.u1Present = 1;
674 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
675
676 pCtx->dsHid.u32Limit = 0x0000ffff;
677 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
678 pCtx->dsHid.Attr.n.u1Present = 1;
679 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
680
681 pCtx->esHid.u32Limit = 0x0000ffff;
682 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
683 pCtx->esHid.Attr.n.u1Present = 1;
684 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
685
686 pCtx->fsHid.u32Limit = 0x0000ffff;
687 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
688 pCtx->fsHid.Attr.n.u1Present = 1;
689 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
690
691 pCtx->gsHid.u32Limit = 0x0000ffff;
692 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
693 pCtx->gsHid.Attr.n.u1Present = 1;
694 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
695
696 pCtx->ssHid.u32Limit = 0x0000ffff;
697 pCtx->ssHid.Attr.n.u1Present = 1;
698 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
699 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
700
701 pCtx->idtr.cbIdt = 0xffff;
702 pCtx->gdtr.cbGdt = 0xffff;
703
704 pCtx->ldtrHid.u32Limit = 0xffff;
705 pCtx->ldtrHid.Attr.n.u1Present = 1;
706 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
707
708 pCtx->trHid.u32Limit = 0xffff;
709 pCtx->trHid.Attr.n.u1Present = 1;
710 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
711
712 pCtx->dr[6] = X86_DR6_INIT_VAL;
713 pCtx->dr[7] = X86_DR7_INIT_VAL;
714
715 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
716 pCtx->fpu.FCW = 0x37f;
717
718 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
719 pCtx->fpu.MXCSR = 0x1F80;
720
721 /* Init PAT MSR */
722 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
723
724 /* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
725 * The Intel docs don't mention it.
726 */
727 pCtx->msrEFER = 0;
728}
729
730
731/**
732 * Execute state save operation.
733 *
734 * @returns VBox status code.
735 * @param pVM VM Handle.
736 * @param pSSM SSM operation handle.
737 */
738static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
739{
740 /* Set the size of RTGCPTR for use of SSMR3Get/PutGCPtr. */
741 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
742
743 /*
744 * Save.
745 */
746 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
747 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
748 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
749 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
750
751 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
752 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
753
754 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
755 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
756
757 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
758 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
759
760 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
761
762 /* Add the cpuid for checking that the cpu is unchanged. */
763 uint32_t au32CpuId[8] = {0};
764 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
765 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
766 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
767}
768
769
770/**
771 * Load a version 1.6 CPUMCTX structure.
772 *
773 * @returns VBox status code.
774 * @param pVM VM Handle.
775 * @param pCpumctx16 Version 1.6 CPUMCTX
776 */
777static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
778{
779#define CPUMCTX16_LOADREG(RegName) \
780 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
781
782#define CPUMCTX16_LOADDRXREG(RegName) \
783 pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
784
785#define CPUMCTX16_LOADHIDREG(RegName) \
786 pVM->cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
787 pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
788 pVM->cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
789
790#define CPUMCTX16_LOADSEGREG(RegName) \
791 pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
792 CPUMCTX16_LOADHIDREG(RegName);
793
794 pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
795
796 CPUMCTX16_LOADREG(rax);
797 CPUMCTX16_LOADREG(rbx);
798 CPUMCTX16_LOADREG(rcx);
799 CPUMCTX16_LOADREG(rdx);
800 CPUMCTX16_LOADREG(rdi);
801 CPUMCTX16_LOADREG(rsi);
802 CPUMCTX16_LOADREG(rbp);
803 CPUMCTX16_LOADREG(esp);
804 CPUMCTX16_LOADREG(rip);
805 CPUMCTX16_LOADREG(rflags);
806
807 CPUMCTX16_LOADSEGREG(cs);
808 CPUMCTX16_LOADSEGREG(ds);
809 CPUMCTX16_LOADSEGREG(es);
810 CPUMCTX16_LOADSEGREG(fs);
811 CPUMCTX16_LOADSEGREG(gs);
812 CPUMCTX16_LOADSEGREG(ss);
813
814 CPUMCTX16_LOADREG(r8);
815 CPUMCTX16_LOADREG(r9);
816 CPUMCTX16_LOADREG(r10);
817 CPUMCTX16_LOADREG(r11);
818 CPUMCTX16_LOADREG(r12);
819 CPUMCTX16_LOADREG(r13);
820 CPUMCTX16_LOADREG(r14);
821 CPUMCTX16_LOADREG(r15);
822
823 CPUMCTX16_LOADREG(cr0);
824 CPUMCTX16_LOADREG(cr2);
825 CPUMCTX16_LOADREG(cr3);
826 CPUMCTX16_LOADREG(cr4);
827
828 CPUMCTX16_LOADDRXREG(0);
829 CPUMCTX16_LOADDRXREG(1);
830 CPUMCTX16_LOADDRXREG(2);
831 CPUMCTX16_LOADDRXREG(3);
832 CPUMCTX16_LOADDRXREG(4);
833 CPUMCTX16_LOADDRXREG(5);
834 CPUMCTX16_LOADDRXREG(6);
835 CPUMCTX16_LOADDRXREG(7);
836
837 pVM->cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
838 pVM->cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
839 pVM->cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
840 pVM->cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
841
842 CPUMCTX16_LOADREG(ldtr);
843 CPUMCTX16_LOADREG(tr);
844
845 pVM->cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
846
847 CPUMCTX16_LOADREG(msrEFER);
848 CPUMCTX16_LOADREG(msrSTAR);
849 CPUMCTX16_LOADREG(msrPAT);
850 CPUMCTX16_LOADREG(msrLSTAR);
851 CPUMCTX16_LOADREG(msrCSTAR);
852 CPUMCTX16_LOADREG(msrSFMASK);
853 CPUMCTX16_LOADREG(msrKERNELGSBASE);
854
855 CPUMCTX16_LOADHIDREG(ldtr);
856 CPUMCTX16_LOADHIDREG(tr);
857
858#undef CPUMCTX16_LOADSEGREG
859#undef CPUMCTX16_LOADHIDREG
860#undef CPUMCTX16_LOADDRXREG
861#undef CPUMCTX16_LOADREG
862}
863
864
865/**
866 * Execute state load operation.
867 *
868 * @returns VBox status code.
869 * @param pVM VM Handle.
870 * @param pSSM SSM operation handle.
871 * @param u32Version Data layout version.
872 */
873static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
874{
875 /*
876 * Validate version.
877 */
878 if ( u32Version != CPUM_SAVED_STATE_VERSION
879 && u32Version != CPUM_SAVED_STATE_VERSION_VER1_6)
880 {
881 AssertMsgFailed(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
882 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
883 }
884
885 /* Set the size of RTGCPTR for SSMR3GetGCPtr. */
886 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
887 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR32));
888 else
889 SSMR3SetGCPtrSize(pSSM, sizeof(RTGCPTR));
890
891 /*
892 * Restore.
893 */
894 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
895 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
896 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
897 pVM->cpum.s.Hyper.cr3 = uCR3;
898 pVM->cpum.s.Hyper.esp = uESP;
899 if (u32Version == CPUM_SAVED_STATE_VERSION_VER1_6)
900 {
901 CPUMCTX_VER1_6 cpumctx16;
902 memset(&pVM->cpum.s.Guest, 0, sizeof(pVM->cpum.s.Guest));
903 SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
904
905 /* Save the old cpumctx state into the new one. */
906 cpumR3LoadCPUM1_6(pVM, &cpumctx16);
907 }
908 else
909 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
910
911 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
912 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
913
914 uint32_t cElements;
915 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
916 /* Support old saved states with a smaller standard cpuid array. */
917 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
918 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
919 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
920
921 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
922 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
923 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
924 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
925
926 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
927 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
928 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
929 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
930
931 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
932
933 /*
934 * Check that the basic cpuid id information is unchanged.
935 */
936 uint32_t au32CpuId[8] = {0};
937 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
938 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
939 uint32_t au32CpuIdSaved[8];
940 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
941 if (VBOX_SUCCESS(rc))
942 {
943 /* Ignore APIC ID (AMD specs). */
944 au32CpuId[5] &= ~0xff000000;
945 au32CpuIdSaved[5] &= ~0xff000000;
946 /* Ignore the number of Logical CPUs (AMD specs). */
947 au32CpuId[5] &= ~0x00ff0000;
948 au32CpuIdSaved[5] &= ~0x00ff0000;
949
950 /* do the compare */
951 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
952 {
953 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
954 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
955 "Saved=%.*Vhxs\n"
956 "Real =%.*Vhxs\n",
957 sizeof(au32CpuIdSaved), au32CpuIdSaved,
958 sizeof(au32CpuId), au32CpuId));
959 else
960 {
961 LogRel(("cpumR3Load: CpuId mismatch!\n"
962 "Saved=%.*Vhxs\n"
963 "Real =%.*Vhxs\n",
964 sizeof(au32CpuIdSaved), au32CpuIdSaved,
965 sizeof(au32CpuId), au32CpuId));
966 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
967 }
968 }
969 }
970
971 return rc;
972}
973
974
975/**
976 * Formats the EFLAGS value into mnemonics.
977 *
978 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
979 * @param efl The EFLAGS value.
980 */
981static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
982{
983 /*
984 * Format the flags.
985 */
986 static const struct
987 {
988 const char *pszSet; const char *pszClear; uint32_t fFlag;
989 } s_aFlags[] =
990 {
991 { "vip",NULL, X86_EFL_VIP },
992 { "vif",NULL, X86_EFL_VIF },
993 { "ac", NULL, X86_EFL_AC },
994 { "vm", NULL, X86_EFL_VM },
995 { "rf", NULL, X86_EFL_RF },
996 { "nt", NULL, X86_EFL_NT },
997 { "ov", "nv", X86_EFL_OF },
998 { "dn", "up", X86_EFL_DF },
999 { "ei", "di", X86_EFL_IF },
1000 { "tf", NULL, X86_EFL_TF },
1001 { "nt", "pl", X86_EFL_SF },
1002 { "nz", "zr", X86_EFL_ZF },
1003 { "ac", "na", X86_EFL_AF },
1004 { "po", "pe", X86_EFL_PF },
1005 { "cy", "nc", X86_EFL_CF },
1006 };
1007 char *psz = pszEFlags;
1008 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1009 {
1010 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1011 if (pszAdd)
1012 {
1013 strcpy(psz, pszAdd);
1014 psz += strlen(pszAdd);
1015 *psz++ = ' ';
1016 }
1017 }
1018 psz[-1] = '\0';
1019}
1020
1021
1022/**
1023 * Formats a full register dump.
1024 *
1025 * @param pVM VM Handle.
1026 * @param pCtx The context to format.
1027 * @param pCtxCore The context core to format.
1028 * @param pHlp Output functions.
1029 * @param enmType The dump type.
1030 * @param pszPrefix Register name prefix.
1031 */
1032static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
1033{
1034 /*
1035 * Format the EFLAGS.
1036 */
1037 uint32_t efl = pCtxCore->eflags.u32;
1038 char szEFlags[80];
1039 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1040
1041 /*
1042 * Format the registers.
1043 */
1044 switch (enmType)
1045 {
1046 case CPUMDUMPTYPE_TERSE:
1047 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1048 pHlp->pfnPrintf(pHlp,
1049 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1050 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1051 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1052 "%sr14=%016RX64 %sr15=%016RX64\n"
1053 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1054 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1055 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1056 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1057 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1058 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1059 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1060 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1061 else
1062 pHlp->pfnPrintf(pHlp,
1063 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1064 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1065 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1066 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1067 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1068 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1069 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
1070 break;
1071
1072 case CPUMDUMPTYPE_DEFAULT:
1073 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1074 pHlp->pfnPrintf(pHlp,
1075 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1076 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1077 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1078 "%sr14=%016RX64 %sr15=%016RX64\n"
1079 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1080 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1081 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
1082 ,
1083 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1084 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1085 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1086 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1087 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1088 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1089 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1090 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1091 else
1092 pHlp->pfnPrintf(pHlp,
1093 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1094 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1095 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1096 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1097 ,
1098 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1099 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1100 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
1101 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
1102 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1103 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
1104 break;
1105
1106 case CPUMDUMPTYPE_VERBOSE:
1107 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
1108 pHlp->pfnPrintf(pHlp,
1109 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1110 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1111 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1112 "%sr14=%016RX64 %sr15=%016RX64\n"
1113 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1114 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1115 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1116 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1117 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1118 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1119 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1120 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1121 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1122 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1123 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1124 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1125 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1126 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1127 ,
1128 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1129 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1130 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1131 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1132 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1133 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1134 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1135 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1136 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1137 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1138 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1139 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1140 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1141 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1142 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1143 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1144 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1145 else
1146 pHlp->pfnPrintf(pHlp,
1147 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1148 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1149 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1150 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1151 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1152 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1153 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1154 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1155 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1156 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1157 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1158 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1159 ,
1160 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1161 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1162 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1163 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1164 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1165 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1166 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1167 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1168 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1169 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1170 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1171 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1172
1173 pHlp->pfnPrintf(pHlp,
1174 "FPU:\n"
1175 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
1176 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
1177 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1178 ,
1179 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
1180 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
1181 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
1182 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
1183
1184 pHlp->pfnPrintf(pHlp,
1185 "MSR:\n"
1186 "%sEFER =%016RX64\n"
1187 "%sPAT =%016RX64\n"
1188 "%sSTAR =%016RX64\n"
1189 "%sCSTAR =%016RX64\n"
1190 "%sLSTAR =%016RX64\n"
1191 "%sSFMASK =%016RX64\n"
1192 "%sKERNELGSBASE =%016RX64\n",
1193 pszPrefix, pCtx->msrEFER,
1194 pszPrefix, pCtx->msrPAT,
1195 pszPrefix, pCtx->msrSTAR,
1196 pszPrefix, pCtx->msrCSTAR,
1197 pszPrefix, pCtx->msrLSTAR,
1198 pszPrefix, pCtx->msrSFMASK,
1199 pszPrefix, pCtx->msrKERNELGSBASE);
1200 break;
1201 }
1202}
1203
1204
1205/**
1206 * Display all cpu states and any other cpum info.
1207 *
1208 * @param pVM VM Handle.
1209 * @param pHlp The info helper functions.
1210 * @param pszArgs Arguments, ignored.
1211 */
1212static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1213{
1214 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1215 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1216 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1217 cpumR3InfoHost(pVM, pHlp, pszArgs);
1218}
1219
1220
1221/**
1222 * Parses the info argument.
1223 *
1224 * The argument starts with 'verbose', 'terse' or 'default' and then
1225 * continues with the comment string.
1226 *
1227 * @param pszArgs The pointer to the argument string.
1228 * @param penmType Where to store the dump type request.
1229 * @param ppszComment Where to store the pointer to the comment string.
1230 */
1231static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1232{
1233 if (!pszArgs)
1234 {
1235 *penmType = CPUMDUMPTYPE_DEFAULT;
1236 *ppszComment = "";
1237 }
1238 else
1239 {
1240 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1241 {
1242 pszArgs += 5;
1243 *penmType = CPUMDUMPTYPE_VERBOSE;
1244 }
1245 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1246 {
1247 pszArgs += 5;
1248 *penmType = CPUMDUMPTYPE_TERSE;
1249 }
1250 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1251 {
1252 pszArgs += 7;
1253 *penmType = CPUMDUMPTYPE_DEFAULT;
1254 }
1255 else
1256 *penmType = CPUMDUMPTYPE_DEFAULT;
1257 *ppszComment = RTStrStripL(pszArgs);
1258 }
1259}
1260
1261
1262/**
1263 * Display the guest cpu state.
1264 *
1265 * @param pVM VM Handle.
1266 * @param pHlp The info helper functions.
1267 * @param pszArgs Arguments, ignored.
1268 */
1269static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1270{
1271 CPUMDUMPTYPE enmType;
1272 const char *pszComment;
1273 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1274 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1275 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1276}
1277
1278
1279/**
1280 * Display the current guest instruction
1281 *
1282 * @param pVM VM Handle.
1283 * @param pHlp The info helper functions.
1284 * @param pszArgs Arguments, ignored.
1285 */
1286static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1287{
1288 char szInstruction[256];
1289 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1290 if (VBOX_SUCCESS(rc))
1291 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1292}
1293
1294
1295/**
1296 * Display the hypervisor cpu state.
1297 *
1298 * @param pVM VM Handle.
1299 * @param pHlp The info helper functions.
1300 * @param pszArgs Arguments, ignored.
1301 */
1302static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1303{
1304 CPUMDUMPTYPE enmType;
1305 const char *pszComment;
1306 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1307 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1308 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1309 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1310}
1311
1312
1313/**
1314 * Display the host cpu state.
1315 *
1316 * @param pVM VM Handle.
1317 * @param pHlp The info helper functions.
1318 * @param pszArgs Arguments, ignored.
1319 */
1320static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1321{
1322 CPUMDUMPTYPE enmType;
1323 const char *pszComment;
1324 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1325 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1326
1327 /*
1328 * Format the EFLAGS.
1329 */
1330 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1331#if HC_ARCH_BITS == 32
1332 uint32_t efl = pCtx->eflags.u32;
1333#else
1334 uint64_t efl = pCtx->rflags;
1335#endif
1336 char szEFlags[80];
1337 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1338
1339 /*
1340 * Format the registers.
1341 */
1342#if HC_ARCH_BITS == 32
1343# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1344 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1345# endif
1346 {
1347 pHlp->pfnPrintf(pHlp,
1348 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1349 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1350 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1351 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1352 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1353 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1354 ,
1355 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1356 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1357 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1358 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1359 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1360 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1361 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1362 }
1363# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1364 else
1365# endif
1366#endif
1367#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1368 {
1369 pHlp->pfnPrintf(pHlp,
1370 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1371 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1372 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1373 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1374 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1375 "r14=%016RX64 r15=%016RX64\n"
1376 "iopl=%d %31s\n"
1377 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1378 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1379 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1380 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1381 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1382 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1383 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1384 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1385 ,
1386 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1387 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1388 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1389 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1390 pCtx->r11, pCtx->r12, pCtx->r13,
1391 pCtx->r14, pCtx->r15,
1392 X86_EFL_GET_IOPL(efl), szEFlags,
1393 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1394 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1395 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1396 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1397 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1398 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1399 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1400 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1401 }
1402#endif
1403}
1404
1405
1406/**
1407 * Get L1 cache / TLS associativity.
1408 */
1409static const char *getCacheAss(unsigned u, char *pszBuf)
1410{
1411 if (u == 0)
1412 return "res0 ";
1413 if (u == 1)
1414 return "direct";
1415 if (u >= 256)
1416 return "???";
1417
1418 RTStrPrintf(pszBuf, 16, "%d way", u);
1419 return pszBuf;
1420}
1421
1422
1423/**
1424 * Get L2 cache soociativity.
1425 */
1426const char *getL2CacheAss(unsigned u)
1427{
1428 switch (u)
1429 {
1430 case 0: return "off ";
1431 case 1: return "direct";
1432 case 2: return "2 way ";
1433 case 3: return "res3 ";
1434 case 4: return "4 way ";
1435 case 5: return "res5 ";
1436 case 6: return "8 way "; case 7: return "res7 ";
1437 case 8: return "16 way";
1438 case 9: return "res9 ";
1439 case 10: return "res10 ";
1440 case 11: return "res11 ";
1441 case 12: return "res12 ";
1442 case 13: return "res13 ";
1443 case 14: return "res14 ";
1444 case 15: return "fully ";
1445 default:
1446 return "????";
1447 }
1448}
1449
1450
1451/**
1452 * Display the guest CpuId leaves.
1453 *
1454 * @param pVM VM Handle.
1455 * @param pHlp The info helper functions.
1456 * @param pszArgs "terse", "default" or "verbose".
1457 */
1458static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1459{
1460 /*
1461 * Parse the argument.
1462 */
1463 unsigned iVerbosity = 1;
1464 if (pszArgs)
1465 {
1466 pszArgs = RTStrStripL(pszArgs);
1467 if (!strcmp(pszArgs, "terse"))
1468 iVerbosity--;
1469 else if (!strcmp(pszArgs, "verbose"))
1470 iVerbosity++;
1471 }
1472
1473 /*
1474 * Start cracking.
1475 */
1476 CPUMCPUID Host;
1477 CPUMCPUID Guest;
1478 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1479
1480 pHlp->pfnPrintf(pHlp,
1481 " RAW Standard CPUIDs\n"
1482 " Function eax ebx ecx edx\n");
1483 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1484 {
1485 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1486 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1487
1488 pHlp->pfnPrintf(pHlp,
1489 "Gst: %08x %08x %08x %08x %08x%s\n"
1490 "Hst: %08x %08x %08x %08x\n",
1491 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1492 i <= cStdMax ? "" : "*",
1493 Host.eax, Host.ebx, Host.ecx, Host.edx);
1494 }
1495
1496 /*
1497 * If verbose, decode it.
1498 */
1499 if (iVerbosity)
1500 {
1501 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1502 pHlp->pfnPrintf(pHlp,
1503 "Name: %.04s%.04s%.04s\n"
1504 "Supports: 0-%x\n",
1505 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1506 }
1507
1508 /*
1509 * Get Features.
1510 */
1511 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1512 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1513 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1514 if (cStdMax >= 1 && iVerbosity)
1515 {
1516 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1517 uint32_t uEAX = Guest.eax;
1518
1519 pHlp->pfnPrintf(pHlp,
1520 "Family: %d \tExtended: %d \tEffective: %d\n"
1521 "Model: %d \tExtended: %d \tEffective: %d\n"
1522 "Stepping: %d\n"
1523 "APIC ID: %#04x\n"
1524 "Logical CPUs: %d\n"
1525 "CLFLUSH Size: %d\n"
1526 "Brand ID: %#04x\n",
1527 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1528 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1529 ASMGetCpuStepping(uEAX),
1530 (Guest.ebx >> 24) & 0xff,
1531 (Guest.ebx >> 16) & 0xff,
1532 (Guest.ebx >> 8) & 0xff,
1533 (Guest.ebx >> 0) & 0xff);
1534 if (iVerbosity == 1)
1535 {
1536 uint32_t uEDX = Guest.edx;
1537 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1538 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1539 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1540 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1541 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1542 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1543 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1544 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1545 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1546 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1547 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1548 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1549 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1550 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1551 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1552 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1553 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1554 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1555 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1556 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1557 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1558 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1559 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1560 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1561 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1562 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1563 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1564 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1565 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1566 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1567 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1568 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1569 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1570 pHlp->pfnPrintf(pHlp, "\n");
1571
1572 uint32_t uECX = Guest.ecx;
1573 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1574 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1575 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1576 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1577 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1578 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1579 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1580 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1581 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1582 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1583 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1584 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1585 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1586 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1587 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1588 for (unsigned iBit = 14; iBit < 32; iBit++)
1589 if (uECX & RT_BIT(iBit))
1590 pHlp->pfnPrintf(pHlp, " %d", iBit);
1591 pHlp->pfnPrintf(pHlp, "\n");
1592 }
1593 else
1594 {
1595 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1596
1597 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1598 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1599 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1600 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1601
1602 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1603 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1604 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1605 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1606 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1607 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1608 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1609 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1610 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1611 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1612 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1613 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1614 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1615 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1616 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1617 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1618 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1619 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1620 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1621 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1622 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1623 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1624 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1625 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1626 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1627 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1628 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1629 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1630 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1631 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1632 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1633 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1634 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1635
1636 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1637 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1638 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1639 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1640 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1641 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1642 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1643 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1644 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1645 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1646 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1647 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1648 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1649 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1650 }
1651 }
1652 if (cStdMax >= 2 && iVerbosity)
1653 {
1654 /** @todo */
1655 }
1656
1657 /*
1658 * Extended.
1659 * Implemented after AMD specs.
1660 */
1661 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1662
1663 pHlp->pfnPrintf(pHlp,
1664 "\n"
1665 " RAW Extended CPUIDs\n"
1666 " Function eax ebx ecx edx\n");
1667 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1668 {
1669 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1670 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1671
1672 pHlp->pfnPrintf(pHlp,
1673 "Gst: %08x %08x %08x %08x %08x%s\n"
1674 "Hst: %08x %08x %08x %08x\n",
1675 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1676 i <= cExtMax ? "" : "*",
1677 Host.eax, Host.ebx, Host.ecx, Host.edx);
1678 }
1679
1680 /*
1681 * Understandable output
1682 */
1683 if (iVerbosity)
1684 {
1685 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1686 pHlp->pfnPrintf(pHlp,
1687 "Ext Name: %.4s%.4s%.4s\n"
1688 "Ext Supports: 0x80000000-%#010x\n",
1689 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1690 }
1691
1692 if (iVerbosity && cExtMax >= 1)
1693 {
1694 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1695 uint32_t uEAX = Guest.eax;
1696 pHlp->pfnPrintf(pHlp,
1697 "Family: %d \tExtended: %d \tEffective: %d\n"
1698 "Model: %d \tExtended: %d \tEffective: %d\n"
1699 "Stepping: %d\n"
1700 "Brand ID: %#05x\n",
1701 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1702 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1703 ASMGetCpuStepping(uEAX),
1704 Guest.ebx & 0xfff);
1705
1706 if (iVerbosity == 1)
1707 {
1708 uint32_t uEDX = Guest.edx;
1709 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1710 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1711 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1712 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1713 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1714 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1715 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1716 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1717 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1718 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1719 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1720 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1721 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1722 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1723 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1724 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1725 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1726 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1727 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1728 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1729 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1730 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1731 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1732 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1733 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1734 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1735 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1736 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1737 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1738 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1739 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1740 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1741 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1742 pHlp->pfnPrintf(pHlp, "\n");
1743
1744 uint32_t uECX = Guest.ecx;
1745 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1746 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1747 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1748 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1749 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1750 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1751 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1752 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1753 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1754 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1755 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1756 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1757 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1758 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1759 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1760 for (unsigned iBit = 5; iBit < 32; iBit++)
1761 if (uECX & RT_BIT(iBit))
1762 pHlp->pfnPrintf(pHlp, " %d", iBit);
1763 pHlp->pfnPrintf(pHlp, "\n");
1764 }
1765 else
1766 {
1767 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1768
1769 uint32_t uEdxGst = Guest.edx;
1770 uint32_t uEdxHst = Host.edx;
1771 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1772 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1773 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1774 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1775 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1776 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1777 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1778 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1779 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1780 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1781 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1782 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1783 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1784 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1785 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1786 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1787 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1788 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1789 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1790 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1791 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1792 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1793 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1794 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1795 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1796 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1797 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1798 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1799 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1800 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1801 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1802 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1803 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1804
1805 uint32_t uEcxGst = Guest.ecx;
1806 uint32_t uEcxHst = Host.ecx;
1807 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1808 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1809 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1810 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1811 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1812 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1813 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1814 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1815 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1816 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1817 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1818 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1819 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1820 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1821 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1822 }
1823 }
1824
1825 if (iVerbosity && cExtMax >= 2)
1826 {
1827 char szString[4*4*3+1] = {0};
1828 uint32_t *pu32 = (uint32_t *)szString;
1829 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1830 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1831 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1832 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1833 if (cExtMax >= 3)
1834 {
1835 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1836 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1837 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1838 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1839 }
1840 if (cExtMax >= 4)
1841 {
1842 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1843 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1844 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1845 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1846 }
1847 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1848 }
1849
1850 if (iVerbosity && cExtMax >= 5)
1851 {
1852 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1853 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1854 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1855 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1856 char sz1[32];
1857 char sz2[32];
1858
1859 pHlp->pfnPrintf(pHlp,
1860 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1861 "TLB 2/4M Data: %s %3d entries\n",
1862 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1863 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1864 pHlp->pfnPrintf(pHlp,
1865 "TLB 4K Instr/Uni: %s %3d entries\n"
1866 "TLB 4K Data: %s %3d entries\n",
1867 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1868 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1869 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1870 "L1 Instr Cache Lines Per Tag: %d\n"
1871 "L1 Instr Cache Associativity: %s\n"
1872 "L1 Instr Cache Size: %d KB\n",
1873 (uEDX >> 0) & 0xff,
1874 (uEDX >> 8) & 0xff,
1875 getCacheAss((uEDX >> 16) & 0xff, sz1),
1876 (uEDX >> 24) & 0xff);
1877 pHlp->pfnPrintf(pHlp,
1878 "L1 Data Cache Line Size: %d bytes\n"
1879 "L1 Data Cache Lines Per Tag: %d\n"
1880 "L1 Data Cache Associativity: %s\n"
1881 "L1 Data Cache Size: %d KB\n",
1882 (uECX >> 0) & 0xff,
1883 (uECX >> 8) & 0xff,
1884 getCacheAss((uECX >> 16) & 0xff, sz1),
1885 (uECX >> 24) & 0xff);
1886 }
1887
1888 if (iVerbosity && cExtMax >= 6)
1889 {
1890 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1891 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1892 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1893
1894 pHlp->pfnPrintf(pHlp,
1895 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1896 "L2 TLB 2/4M Data: %s %4d entries\n",
1897 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1898 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1899 pHlp->pfnPrintf(pHlp,
1900 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1901 "L2 TLB 4K Data: %s %4d entries\n",
1902 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1903 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1904 pHlp->pfnPrintf(pHlp,
1905 "L2 Cache Line Size: %d bytes\n"
1906 "L2 Cache Lines Per Tag: %d\n"
1907 "L2 Cache Associativity: %s\n"
1908 "L2 Cache Size: %d KB\n",
1909 (uEDX >> 0) & 0xff,
1910 (uEDX >> 8) & 0xf,
1911 getL2CacheAss((uEDX >> 12) & 0xf),
1912 (uEDX >> 16) & 0xffff);
1913 }
1914
1915 if (iVerbosity && cExtMax >= 7)
1916 {
1917 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1918
1919 pHlp->pfnPrintf(pHlp, "APM Features: ");
1920 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1921 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1922 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1923 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1924 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1925 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1926 for (unsigned iBit = 6; iBit < 32; iBit++)
1927 if (uEDX & RT_BIT(iBit))
1928 pHlp->pfnPrintf(pHlp, " %d", iBit);
1929 pHlp->pfnPrintf(pHlp, "\n");
1930 }
1931
1932 if (iVerbosity && cExtMax >= 8)
1933 {
1934 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1935 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1936
1937 pHlp->pfnPrintf(pHlp,
1938 "Physical Address Width: %d bits\n"
1939 "Virtual Address Width: %d bits\n",
1940 (uEAX >> 0) & 0xff,
1941 (uEAX >> 8) & 0xff);
1942 pHlp->pfnPrintf(pHlp,
1943 "Physical Core Count: %d\n",
1944 (uECX >> 0) & 0xff);
1945 }
1946
1947
1948 /*
1949 * Centaur.
1950 */
1951 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1952
1953 pHlp->pfnPrintf(pHlp,
1954 "\n"
1955 " RAW Centaur CPUIDs\n"
1956 " Function eax ebx ecx edx\n");
1957 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1958 {
1959 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1960 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1961
1962 pHlp->pfnPrintf(pHlp,
1963 "Gst: %08x %08x %08x %08x %08x%s\n"
1964 "Hst: %08x %08x %08x %08x\n",
1965 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1966 i <= cCentaurMax ? "" : "*",
1967 Host.eax, Host.ebx, Host.ecx, Host.edx);
1968 }
1969
1970 /*
1971 * Understandable output
1972 */
1973 if (iVerbosity)
1974 {
1975 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1976 pHlp->pfnPrintf(pHlp,
1977 "Centaur Supports: 0xc0000000-%#010x\n",
1978 Guest.eax);
1979 }
1980
1981 if (iVerbosity && cCentaurMax >= 1)
1982 {
1983 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1984 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1985 uint32_t uEdxHst = Host.edx;
1986
1987 if (iVerbosity == 1)
1988 {
1989 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1990 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1991 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1992 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1993 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1994 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1995 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1996 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1997 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1998 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1999 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
2000 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
2001 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
2002 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
2003 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
2004 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
2005 for (unsigned iBit = 14; iBit < 32; iBit++)
2006 if (uEdxGst & RT_BIT(iBit))
2007 pHlp->pfnPrintf(pHlp, " %d", iBit);
2008 pHlp->pfnPrintf(pHlp, "\n");
2009 }
2010 else
2011 {
2012 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2013 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
2014 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
2015 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
2016 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
2017 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
2018 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
2019 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
2020 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
2021 /* possibly indicating MM/HE and MM/HE-E on older chips... */
2022 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
2023 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
2024 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
2025 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
2026 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
2027 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
2028 for (unsigned iBit = 14; iBit < 32; iBit++)
2029 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
2030 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
2031 pHlp->pfnPrintf(pHlp, "\n");
2032 }
2033 }
2034}
2035
2036
2037/**
2038 * Structure used when disassembling and instructions in DBGF.
2039 * This is used so the reader function can get the stuff it needs.
2040 */
2041typedef struct CPUMDISASSTATE
2042{
2043 /** Pointer to the CPU structure. */
2044 PDISCPUSTATE pCpu;
2045 /** The VM handle. */
2046 PVM pVM;
2047 /** Pointer to the first byte in the segemnt. */
2048 RTGCUINTPTR GCPtrSegBase;
2049 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2050 RTGCUINTPTR GCPtrSegEnd;
2051 /** The size of the segment minus 1. */
2052 RTGCUINTPTR cbSegLimit;
2053 /** Pointer to the current page - HC Ptr. */
2054 void const *pvPageHC;
2055 /** Pointer to the current page - GC Ptr. */
2056 RTGCPTR pvPageGC;
2057 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2058 PGMPAGEMAPLOCK PageMapLock;
2059 /** Whether the PageMapLock is valid or not. */
2060 bool fLocked;
2061 /** 64 bits mode or not. */
2062 bool f64Bits;
2063} CPUMDISASSTATE, *PCPUMDISASSTATE;
2064
2065
2066/**
2067 * Instruction reader.
2068 *
2069 * @returns VBox status code.
2070 * @param PtrSrc Address to read from.
2071 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
2072 * @param pu8Dst Where to store the bytes.
2073 * @param cbRead Number of bytes to read.
2074 * @param uDisCpu Pointer to the disassembler cpu state.
2075 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
2076 */
2077static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
2078{
2079 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
2080 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
2081 Assert(cbRead > 0);
2082 for (;;)
2083 {
2084 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
2085
2086 /* Need to update the page translation? */
2087 if ( !pState->pvPageHC
2088 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2089 {
2090 int rc = VINF_SUCCESS;
2091
2092 /* translate the address */
2093 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2094 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2095 {
2096 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
2097 if (!pState->pvPageHC)
2098 rc = VERR_INVALID_POINTER;
2099 }
2100 else
2101 {
2102 /* Release mapping lock previously acquired. */
2103 if (pState->fLocked)
2104 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2105 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
2106 pState->fLocked = RT_SUCCESS_NP(rc);
2107 }
2108 if (VBOX_FAILURE(rc))
2109 {
2110 pState->pvPageHC = NULL;
2111 return rc;
2112 }
2113 }
2114
2115 /* check the segemnt limit */
2116 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
2117 return VERR_OUT_OF_SELECTOR_BOUNDS;
2118
2119 /* calc how much we can read */
2120 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2121 if (!pState->f64Bits)
2122 {
2123 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2124 if (cb > cbSeg && cbSeg)
2125 cb = cbSeg;
2126 }
2127 if (cb > cbRead)
2128 cb = cbRead;
2129
2130 /* read and advance */
2131 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
2132 cbRead -= cb;
2133 if (!cbRead)
2134 return VINF_SUCCESS;
2135 pu8Dst += cb;
2136 PtrSrc += cb;
2137 }
2138}
2139
2140
2141/**
2142 * Disassemble an instruction and return the information in the provided structure.
2143 *
2144 * @returns VBox status code.
2145 * @param pVM VM Handle
2146 * @param pCtx CPU context
2147 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2148 * @param pCpu Disassembly state
2149 * @param pszPrefix String prefix for logging (debug only)
2150 *
2151 */
2152CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2153{
2154 CPUMDISASSTATE State;
2155 int rc;
2156
2157 const PGMMODE enmMode = PGMGetGuestMode(pVM);
2158 State.pCpu = pCpu;
2159 State.pvPageGC = 0;
2160 State.pvPageHC = NULL;
2161 State.pVM = pVM;
2162 State.fLocked = false;
2163 State.f64Bits = false;
2164
2165 /*
2166 * Get selector information.
2167 */
2168 if ( (pCtx->cr0 & X86_CR0_PE)
2169 && pCtx->eflags.Bits.u1VM == 0)
2170 {
2171 if (CPUMAreHiddenSelRegsValid(pVM))
2172 {
2173 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
2174 State.GCPtrSegBase = pCtx->csHid.u64Base;
2175 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
2176 State.cbSegLimit = pCtx->csHid.u32Limit;
2177 pCpu->mode = (State.f64Bits)
2178 ? CPUMODE_64BIT
2179 : pCtx->csHid.Attr.n.u1DefBig
2180 ? CPUMODE_32BIT
2181 : CPUMODE_16BIT;
2182 }
2183 else
2184 {
2185 SELMSELINFO SelInfo;
2186
2187 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
2188 if (!VBOX_SUCCESS(rc))
2189 {
2190 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2191 return rc;
2192 }
2193
2194 /*
2195 * Validate the selector.
2196 */
2197 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
2198 if (!VBOX_SUCCESS(rc))
2199 {
2200 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
2201 return rc;
2202 }
2203 State.GCPtrSegBase = SelInfo.GCPtrBase;
2204 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
2205 State.cbSegLimit = SelInfo.cbLimit;
2206 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
2207 }
2208 }
2209 else
2210 {
2211 /* real or V86 mode */
2212 pCpu->mode = CPUMODE_16BIT;
2213 State.GCPtrSegBase = pCtx->cs * 16;
2214 State.GCPtrSegEnd = 0xFFFFFFFF;
2215 State.cbSegLimit = 0xFFFFFFFF;
2216 }
2217
2218 /*
2219 * Disassemble the instruction.
2220 */
2221 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2222 pCpu->apvUserData[0] = &State;
2223
2224 uint32_t cbInstr;
2225#ifndef LOG_ENABLED
2226 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2227 if (VBOX_SUCCESS(rc))
2228 {
2229#else
2230 char szOutput[160];
2231 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2232 if (VBOX_SUCCESS(rc))
2233 {
2234 /* log it */
2235 if (pszPrefix)
2236 Log(("%s: %s", pszPrefix, szOutput));
2237 else
2238 Log(("%s", szOutput));
2239#endif
2240 rc = VINF_SUCCESS;
2241 }
2242 else
2243 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2244
2245 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2246 if (State.fLocked)
2247 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2248
2249 return rc;
2250}
2251
2252#ifdef DEBUG
2253
2254/**
2255 * Disassemble an instruction and dump it to the log
2256 *
2257 * @returns VBox status code.
2258 * @param pVM VM Handle
2259 * @param pCtx CPU context
2260 * @param pc GC instruction pointer
2261 * @param pszPrefix String prefix for logging
2262 *
2263 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2264 */
2265CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
2266{
2267 DISCPUSTATE Cpu;
2268 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, pszPrefix);
2269}
2270
2271
2272/**
2273 * Disassemble an instruction and dump it to the log
2274 *
2275 * @returns VBox status code.
2276 * @param pVM VM Handle
2277 * @param pCtx CPU context
2278 * @param pc GC instruction pointer
2279 * @param pszPrefix String prefix for logging
2280 * @param nrInstructions
2281 *
2282 * @deprecated Create new DBGFR3Disas function to do this.
2283 */
2284CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix, int nrInstructions)
2285{
2286 for (int i = 0; i < nrInstructions; i++)
2287 {
2288 DISCPUSTATE cpu;
2289
2290 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, pszPrefix);
2291 pc += cpu.opsize;
2292 }
2293}
2294
2295
2296/**
2297 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2298 *
2299 * @internal
2300 */
2301CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2302{
2303 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2304}
2305
2306#endif /* DEBUG */
2307
2308/**
2309 * API for controlling a few of the CPU features found in CR4.
2310 *
2311 * Currently only X86_CR4_TSD is accepted as input.
2312 *
2313 * @returns VBox status code.
2314 *
2315 * @param pVM The VM handle.
2316 * @param fOr The CR4 OR mask.
2317 * @param fAnd The CR4 AND mask.
2318 */
2319CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2320{
2321 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2322 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2323
2324 pVM->cpum.s.CR4.OrMask &= fAnd;
2325 pVM->cpum.s.CR4.OrMask |= fOr;
2326
2327 return VINF_SUCCESS;
2328}
2329
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