VirtualBox

source: vbox/trunk/src/VBox/VMM/CPUM.cpp@ 10377

Last change on this file since 10377 was 10353, checked in by vboxsync, 16 years ago

TPR caching for VT-x. Removed the CR8 register from CPUMCTX.
  • Property svn:eol-style set to native
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File size: 98.6 KB
Line 
1/* $Id: CPUM.cpp 10353 2008-07-08 11:12:52Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/** @page pg_cpum
23 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
24 * also responsible for lazy FPU handling and some of the context loading
25 * in raw mode.
26 *
27 * There are three CPU contexts, the most important one is the guest one (GC).
28 * When running in raw-mode (RC) there is a special hyper context for the VMM
29 * that floats around inside the guest address space. When running in raw-mode
30 * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
31 * context for saving and restoring registers accross world switches. This latter
32 * is done in cooperation with the world switcher (@see pg_vmm).
33 */
34
35/*******************************************************************************
36* Header Files *
37*******************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/cpum.h>
40#include <VBox/cpumdis.h>
41#include <VBox/pgm.h>
42#include <VBox/pdm.h>
43#include <VBox/mm.h>
44#include <VBox/selm.h>
45#include <VBox/dbgf.h>
46#include <VBox/patm.h>
47#include <VBox/ssm.h>
48#include "CPUMInternal.h"
49#include <VBox/vm.h>
50
51#include <VBox/param.h>
52#include <VBox/dis.h>
53#include <VBox/err.h>
54#include <VBox/log.h>
55#include <iprt/assert.h>
56#include <iprt/asm.h>
57#include <iprt/string.h>
58#include <iprt/system.h>
59
60
61/*******************************************************************************
62* Defined Constants And Macros *
63*******************************************************************************/
64/** The saved state version. */
65#define CPUM_SAVED_STATE_VERSION 8
66
67
68/*******************************************************************************
69* Structures and Typedefs *
70*******************************************************************************/
71
72/**
73 * What kind of cpu info dump to perform.
74 */
75typedef enum CPUMDUMPTYPE
76{
77 CPUMDUMPTYPE_TERSE,
78 CPUMDUMPTYPE_DEFAULT,
79 CPUMDUMPTYPE_VERBOSE
80
81} CPUMDUMPTYPE;
82/** Pointer to a cpu info dump type. */
83typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static int cpumR3CpuIdInit(PVM pVM);
90static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
91static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
92static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
93static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
94static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
95static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
96static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
97static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
98
99
100/**
101 * Initializes the CPUM.
102 *
103 * @returns VBox status code.
104 * @param pVM The VM to operate on.
105 */
106CPUMR3DECL(int) CPUMR3Init(PVM pVM)
107{
108 LogFlow(("CPUMR3Init\n"));
109
110 /*
111 * Assert alignment and sizes.
112 */
113 AssertRelease(!(RT_OFFSETOF(VM, cpum.s) & 31));
114 AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
115
116 /*
117 * Setup any fixed pointers and offsets.
118 */
119 pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
120 pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
121 pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
122 pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
123
124 /* Hidden selector registers are invalid by default. */
125 pVM->cpum.s.fValidHiddenSelRegs = false;
126
127 /*
128 * Check that the CPU supports the minimum features we require.
129 */
130 /** @todo check the contract! */
131 if (!ASMHasCpuId())
132 {
133 Log(("The CPU doesn't support CPUID!\n"));
134 return VERR_UNSUPPORTED_CPU;
135 }
136 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
137
138 /* Setup the CR4 AND and OR masks used in the switcher */
139 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
140 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
141 {
142 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
143 /* No FXSAVE implies no SSE */
144 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
145 pVM->cpum.s.CR4.OrMask = 0;
146 }
147 else
148 {
149 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
150 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
151 }
152
153 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
154 {
155 Log(("The CPU doesn't support MMX!\n"));
156 return VERR_UNSUPPORTED_CPU;
157 }
158 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
159 {
160 Log(("The CPU doesn't support TSC!\n"));
161 return VERR_UNSUPPORTED_CPU;
162 }
163 /* Bogus on AMD? */
164 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
165 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
166
167 /*
168 * Setup hypervisor startup values.
169 */
170
171 /*
172 * Register saved state data item.
173 */
174 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
175 NULL, cpumR3Save, NULL,
176 NULL, cpumR3Load, NULL);
177 if (VBOX_FAILURE(rc))
178 return rc;
179
180 /* Query the CPU manufacturer. */
181 uint32_t uEAX, uEBX, uECX, uEDX;
182 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
183 if ( uEAX >= 1
184 && uEBX == X86_CPUID_VENDOR_AMD_EBX
185 && uECX == X86_CPUID_VENDOR_AMD_ECX
186 && uEDX == X86_CPUID_VENDOR_AMD_EDX)
187 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_AMD;
188 else if ( uEAX >= 1
189 && uEBX == X86_CPUID_VENDOR_INTEL_EBX
190 && uECX == X86_CPUID_VENDOR_INTEL_ECX
191 && uEDX == X86_CPUID_VENDOR_INTEL_EDX)
192 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_INTEL;
193 else /** @todo Via */
194 pVM->cpum.s.enmCPUVendor = CPUMCPUVENDOR_UNKNOWN;
195
196 /*
197 * Register info handlers.
198 */
199 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
200 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
201 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
202 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
203 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
204 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
205
206 /*
207 * Initialize the Guest CPU state.
208 */
209 rc = cpumR3CpuIdInit(pVM);
210 if (VBOX_FAILURE(rc))
211 return rc;
212 CPUMR3Reset(pVM);
213 return VINF_SUCCESS;
214}
215
216
217/**
218 * Initializes the emulated CPU's cpuid information.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223static int cpumR3CpuIdInit(PVM pVM)
224{
225 PCPUM pCPUM = &pVM->cpum.s;
226 uint32_t i;
227
228 /*
229 * Get the host CPUIDs.
230 */
231 for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
232 ASMCpuId_Idx_ECX(i, 0,
233 &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
234 &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
235 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
236 ASMCpuId(0x80000000 + i,
237 &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
238 &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
239 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
240 ASMCpuId(0xc0000000 + i,
241 &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
242 &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
243
244
245 /*
246 * Only report features we can support.
247 */
248 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
249 | X86_CPUID_FEATURE_EDX_VME
250 | X86_CPUID_FEATURE_EDX_DE
251 | X86_CPUID_FEATURE_EDX_PSE
252 | X86_CPUID_FEATURE_EDX_TSC
253 | X86_CPUID_FEATURE_EDX_MSR
254 //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
255 | X86_CPUID_FEATURE_EDX_MCE
256 | X86_CPUID_FEATURE_EDX_CX8
257 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
258 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
259 //| X86_CPUID_FEATURE_EDX_SEP
260 | X86_CPUID_FEATURE_EDX_MTRR
261 | X86_CPUID_FEATURE_EDX_PGE
262 | X86_CPUID_FEATURE_EDX_MCA
263 | X86_CPUID_FEATURE_EDX_CMOV
264 | X86_CPUID_FEATURE_EDX_PAT
265 //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
266 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
267 | X86_CPUID_FEATURE_EDX_CLFSH
268 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
269 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
270 | X86_CPUID_FEATURE_EDX_MMX
271 | X86_CPUID_FEATURE_EDX_FXSR
272 | X86_CPUID_FEATURE_EDX_SSE
273 | X86_CPUID_FEATURE_EDX_SSE2
274 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
275 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
276 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
277 //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
278 | 0;
279 pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
280 | X86_CPUID_FEATURE_ECX_MONITOR
281 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
282 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
283 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
284 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
285 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
286 /* ECX Bit 13 - CX16 - CMPXCHG16B. */
287 //| X86_CPUID_FEATURE_ECX_CX16
288 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
289 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
290 /* ECX Bit 23 - POPCOUNT instruction. */
291 //| X86_CPUID_FEATURE_ECX_POPCOUNT
292 | 0;
293
294 /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
295 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
296 | X86_CPUID_AMD_FEATURE_EDX_VME
297 | X86_CPUID_AMD_FEATURE_EDX_DE
298 | X86_CPUID_AMD_FEATURE_EDX_PSE
299 | X86_CPUID_AMD_FEATURE_EDX_TSC
300 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
301 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
302 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
303 | X86_CPUID_AMD_FEATURE_EDX_CX8
304 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
305 /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
306 //| X86_CPUID_AMD_FEATURE_EDX_SEP
307 | X86_CPUID_AMD_FEATURE_EDX_MTRR
308 | X86_CPUID_AMD_FEATURE_EDX_PGE
309 | X86_CPUID_AMD_FEATURE_EDX_MCA
310 | X86_CPUID_AMD_FEATURE_EDX_CMOV
311 | X86_CPUID_AMD_FEATURE_EDX_PAT
312 //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
313 //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
314 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
315 | X86_CPUID_AMD_FEATURE_EDX_MMX
316 | X86_CPUID_AMD_FEATURE_EDX_FXSR
317 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
318 //| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
319 //| X86_CPUID_AMD_FEATURE_EDX_RDTSCP
320 //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
321 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
322 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
323 | 0;
324 pCPUM->aGuestCpuIdExt[1].ecx &= 0
325 //| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
326 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
327 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
328 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
329 //| X86_CPUID_AMD_FEATURE_ECX_CR8L
330 //| X86_CPUID_AMD_FEATURE_ECX_ABM
331 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
332 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
333 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
334 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
335 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
336 //| X86_CPUID_AMD_FEATURE_ECX_WDT
337 | 0;
338
339 /*
340 * Hide HTT, multicode, SMP, whatever.
341 * (APIC-ID := 0 and #LogCpus := 0)
342 */
343 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
344
345 /*
346 * Determine the default.
347 *
348 * Intel returns values of the highest standard function, while AMD
349 * returns zeros. VIA on the other hand seems to returning nothing or
350 * perhaps some random garbage, we don't try duplicate this behavior.
351 */
352 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10,
353 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
354 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
355
356 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
357 * Safe to pass on to the guest.
358 *
359 * Intel: 0x800000005 reserved
360 * 0x800000006 L2 cache information
361 * AMD: 0x800000005 L1 cache information
362 * 0x800000006 L2/L3 cache information
363 */
364
365 /*
366 * Limit it the number of entries and fill the remaining with the defaults.
367 *
368 * The limits are masking off stuff about power saving and similar, this
369 * is perhaps a bit crudely done as there is probably some relatively harmless
370 * info too in these leaves (like words about having a constant TSC).
371 */
372 if (pCPUM->aGuestCpuIdStd[0].eax > 2)
373 pCPUM->aGuestCpuIdStd[0].eax = 2;
374 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
375 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
376
377 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000006))
378 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000006);
379 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
380 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
381 : 0;
382 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
383 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
384
385 /*
386 * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
387 * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
388 * We currently don't support more than 1 processor.
389 */
390 pCPUM->aGuestCpuIdStd[4].eax = 0;
391
392 /*
393 * Centaur stuff (VIA).
394 *
395 * The important part here (we think) is to make sure the 0xc0000000
396 * function returns 0xc0000001. As for the features, we don't currently
397 * let on about any of those... 0xc0000002 seems to be some
398 * temperature/hz/++ stuff, include it as well (static).
399 */
400 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
401 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
402 {
403 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
404 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
405 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
406 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
407 i++)
408 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
409 }
410 else
411 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
412 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
413
414
415 /*
416 * Load CPUID overrides from configuration.
417 */
418 PCPUMCPUID pCpuId = &pCPUM->aGuestCpuIdStd[0];
419 uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
420 for (i=0;; )
421 {
422 while (cElements-- > 0)
423 {
424 PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
425 if (pNode)
426 {
427 uint32_t u32;
428 int rc = CFGMR3QueryU32(pNode, "eax", &u32);
429 if (VBOX_SUCCESS(rc))
430 pCpuId->eax = u32;
431 else
432 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
433
434 rc = CFGMR3QueryU32(pNode, "ebx", &u32);
435 if (VBOX_SUCCESS(rc))
436 pCpuId->ebx = u32;
437 else
438 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
439
440 rc = CFGMR3QueryU32(pNode, "ecx", &u32);
441 if (VBOX_SUCCESS(rc))
442 pCpuId->ecx = u32;
443 else
444 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
445
446 rc = CFGMR3QueryU32(pNode, "edx", &u32);
447 if (VBOX_SUCCESS(rc))
448 pCpuId->edx = u32;
449 else
450 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
451 }
452 pCpuId++;
453 i++;
454 }
455
456 /* next */
457 if ((i & UINT32_C(0xc0000000)) == 0)
458 {
459 pCpuId = &pCPUM->aGuestCpuIdExt[0];
460 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
461 i = UINT32_C(0x80000000);
462 }
463 else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
464 {
465 pCpuId = &pCPUM->aGuestCpuIdCentaur[0];
466 cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
467 i = UINT32_C(0xc0000000);
468 }
469 else
470 break;
471 }
472
473 /* Check if PAE was explicitely enabled by the user. */
474 bool fEnable = false;
475 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
476 if (VBOX_SUCCESS(rc) && fEnable)
477 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
478
479 /*
480 * Log the cpuid and we're good.
481 */
482 LogRel(("Logical host processors: %d, processor active mask: %08x\n",
483 RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
484 LogRel(("************************* CPUID dump ************************\n"));
485 DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
486 LogRel(("\n"));
487 DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
488 LogRel(("******************** End of CPUID dump **********************\n"));
489 return VINF_SUCCESS;
490}
491
492
493
494
495/**
496 * Applies relocations to data and code managed by this
497 * component. This function will be called at init and
498 * whenever the VMM need to relocate it self inside the GC.
499 *
500 * The CPUM will update the addresses used by the switcher.
501 *
502 * @param pVM The VM.
503 */
504CPUMR3DECL(void) CPUMR3Relocate(PVM pVM)
505{
506 LogFlow(("CPUMR3Relocate\n"));
507 /*
508 * Switcher pointers.
509 */
510 pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
511 pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
512 Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
513}
514
515
516/**
517 * Queries the pointer to the internal CPUMCTX structure
518 *
519 * @returns VBox status code.
520 * @param pVM Handle to the virtual machine.
521 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
522 */
523CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
524{
525 LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
526 /*
527 * Store the address. (Later we might check how's calling, thus the RC.)
528 */
529 *ppCtx = VM_GUEST_ADDR(pVM, &pVM->cpum.s.Guest);
530 return VINF_SUCCESS;
531}
532
533
534/**
535 * Terminates the CPUM.
536 *
537 * Termination means cleaning up and freeing all resources,
538 * the VM it self is at this point powered off or suspended.
539 *
540 * @returns VBox status code.
541 * @param pVM The VM to operate on.
542 */
543CPUMR3DECL(int) CPUMR3Term(PVM pVM)
544{
545 /** @todo ? */
546 return 0;
547}
548
549
550/**
551 * Resets the CPU.
552 *
553 * @returns VINF_SUCCESS.
554 * @param pVM The VM handle.
555 */
556CPUMR3DECL(void) CPUMR3Reset(PVM pVM)
557{
558 PCPUMCTX pCtx = &pVM->cpum.s.Guest;
559
560 /*
561 * Initialize everything to ZERO first.
562 */
563 uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
564 memset(pCtx, 0, sizeof(*pCtx));
565 pVM->cpum.s.fUseFlags = fUseFlags;
566
567 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
568 pCtx->eip = 0x0000fff0;
569 pCtx->edx = 0x00000600; /* P6 processor */
570 pCtx->eflags.Bits.u1Reserved0 = 1;
571
572 pCtx->cs = 0xf000;
573 pCtx->csHid.u64Base = UINT64_C(0xffff0000);
574 pCtx->csHid.u32Limit = 0x0000ffff;
575 pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
576 pCtx->csHid.Attr.n.u1Present = 1;
577 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
578
579 pCtx->dsHid.u32Limit = 0x0000ffff;
580 pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
581 pCtx->dsHid.Attr.n.u1Present = 1;
582 pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
583
584 pCtx->esHid.u32Limit = 0x0000ffff;
585 pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
586 pCtx->esHid.Attr.n.u1Present = 1;
587 pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
588
589 pCtx->fsHid.u32Limit = 0x0000ffff;
590 pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
591 pCtx->fsHid.Attr.n.u1Present = 1;
592 pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
593
594 pCtx->gsHid.u32Limit = 0x0000ffff;
595 pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
596 pCtx->gsHid.Attr.n.u1Present = 1;
597 pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
598
599 pCtx->ssHid.u32Limit = 0x0000ffff;
600 pCtx->ssHid.Attr.n.u1Present = 1;
601 pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
602 pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
603
604 pCtx->idtr.cbIdt = 0xffff;
605 pCtx->gdtr.cbGdt = 0xffff;
606
607 pCtx->ldtrHid.u32Limit = 0xffff;
608 pCtx->ldtrHid.Attr.n.u1Present = 1;
609 pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
610
611 pCtx->trHid.u32Limit = 0xffff;
612 pCtx->trHid.Attr.n.u1Present = 1;
613 pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
614
615 pCtx->dr6 = UINT32_C(0xFFFF0FF0);
616 pCtx->dr7 = 0x400;
617
618 pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
619 pCtx->fpu.FCW = 0x37f;
620
621 /* Init PAT MSR */
622 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
623}
624
625
626/**
627 * Execute state save operation.
628 *
629 * @returns VBox status code.
630 * @param pVM VM Handle.
631 * @param pSSM SSM operation handle.
632 */
633static DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
634{
635 /*
636 * Save.
637 */
638 SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
639 SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
640 SSMR3PutU32(pSSM, pVM->cpum.s.fUseFlags);
641 SSMR3PutU32(pSSM, pVM->cpum.s.fChanged);
642
643 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
644 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
645
646 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
647 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
648
649 SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
650 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
651
652 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
653
654 /* Add the cpuid for checking that the cpu is unchanged. */
655 uint32_t au32CpuId[8] = {0};
656 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
657 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
658 return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
659}
660
661
662/**
663 * Execute state load operation.
664 *
665 * @returns VBox status code.
666 * @param pVM VM Handle.
667 * @param pSSM SSM operation handle.
668 * @param u32Version Data layout version.
669 */
670static DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
671{
672 /*
673 * Validate version.
674 */
675 if (u32Version != CPUM_SAVED_STATE_VERSION)
676 {
677 Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
678 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
679 }
680
681 /*
682 * Restore.
683 */
684 uint32_t uCR3 = pVM->cpum.s.Hyper.cr3;
685 uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
686 SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
687 pVM->cpum.s.Hyper.cr3 = uCR3;
688 pVM->cpum.s.Hyper.esp = uESP;
689 SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
690 SSMR3GetU32(pSSM, &pVM->cpum.s.fUseFlags);
691 SSMR3GetU32(pSSM, &pVM->cpum.s.fChanged);
692
693 uint32_t cElements;
694 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
695 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
696 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
697 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
698
699 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
700 if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
701 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
702 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
703
704 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
705 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
706 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
707 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
708
709 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
710
711 /*
712 * Check that the basic cpuid id information is unchanged.
713 */
714 uint32_t au32CpuId[8] = {0};
715 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
716 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
717 uint32_t au32CpuIdSaved[8];
718 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
719 if (VBOX_SUCCESS(rc))
720 {
721 /* Ignore APIC ID (AMD specs). */
722 au32CpuId[5] &= ~0xff000000;
723 au32CpuIdSaved[5] &= ~0xff000000;
724 /* Ignore the number of Logical CPUs (AMD specs). */
725 au32CpuId[5] &= ~0x00ff0000;
726 au32CpuIdSaved[5] &= ~0x00ff0000;
727
728 /* do the compare */
729 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
730 {
731 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
732 LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
733 "Saved=%.*Vhxs\n"
734 "Real =%.*Vhxs\n",
735 sizeof(au32CpuIdSaved), au32CpuIdSaved,
736 sizeof(au32CpuId), au32CpuId));
737 else
738 {
739 LogRel(("cpumR3Load: CpuId mismatch!\n"
740 "Saved=%.*Vhxs\n"
741 "Real =%.*Vhxs\n",
742 sizeof(au32CpuIdSaved), au32CpuIdSaved,
743 sizeof(au32CpuId), au32CpuId));
744 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
745 }
746 }
747 }
748
749 return rc;
750}
751
752
753/**
754 * Formats the EFLAGS value into mnemonics.
755 *
756 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
757 * @param efl The EFLAGS value.
758 */
759static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
760{
761 /*
762 * Format the flags.
763 */
764 static struct
765 {
766 const char *pszSet; const char *pszClear; uint32_t fFlag;
767 } s_aFlags[] =
768 {
769 { "vip",NULL, X86_EFL_VIP },
770 { "vif",NULL, X86_EFL_VIF },
771 { "ac", NULL, X86_EFL_AC },
772 { "vm", NULL, X86_EFL_VM },
773 { "rf", NULL, X86_EFL_RF },
774 { "nt", NULL, X86_EFL_NT },
775 { "ov", "nv", X86_EFL_OF },
776 { "dn", "up", X86_EFL_DF },
777 { "ei", "di", X86_EFL_IF },
778 { "tf", NULL, X86_EFL_TF },
779 { "nt", "pl", X86_EFL_SF },
780 { "nz", "zr", X86_EFL_ZF },
781 { "ac", "na", X86_EFL_AF },
782 { "po", "pe", X86_EFL_PF },
783 { "cy", "nc", X86_EFL_CF },
784 };
785 char *psz = pszEFlags;
786 for (unsigned i = 0; i < ELEMENTS(s_aFlags); i++)
787 {
788 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
789 if (pszAdd)
790 {
791 strcpy(psz, pszAdd);
792 psz += strlen(pszAdd);
793 *psz++ = ' ';
794 }
795 }
796 psz[-1] = '\0';
797}
798
799
800/**
801 * Formats a full register dump.
802 *
803 * @param pVM VM Handle.
804 * @param pCtx The context to format.
805 * @param pCtxCore The context core to format.
806 * @param pHlp Output functions.
807 * @param enmType The dump type.
808 * @param pszPrefix Register name prefix.
809 */
810static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
811{
812 /*
813 * Format the EFLAGS.
814 */
815 uint32_t efl = pCtxCore->eflags.u32;
816 char szEFlags[80];
817 cpumR3InfoFormatFlags(&szEFlags[0], efl);
818
819 /*
820 * Format the registers.
821 */
822 switch (enmType)
823 {
824 case CPUMDUMPTYPE_TERSE:
825 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
826 {
827 pHlp->pfnPrintf(pHlp,
828 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
829 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
830 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
831 "%sr14=%016RX64 %sr15=%016RX64\n"
832 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
833 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
834 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
835 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
836 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
837 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
838 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
839 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
840 }
841 else
842 pHlp->pfnPrintf(pHlp,
843 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
844 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
845 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
846 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
847 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
848 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
849 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
850 break;
851
852 case CPUMDUMPTYPE_DEFAULT:
853 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
854 {
855 pHlp->pfnPrintf(pHlp,
856 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
857 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
858 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
859 "%sr14=%016RX64 %sr15=%016RX64\n"
860 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
861 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
862 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
863 ,
864 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
865 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
866 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
867 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
868 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
869 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
870 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
871 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
872 }
873 else
874 pHlp->pfnPrintf(pHlp,
875 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
876 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
877 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
878 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
879 ,
880 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
881 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
882 pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
883 pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
884 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
885 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
886 break;
887
888 case CPUMDUMPTYPE_VERBOSE:
889 if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
890 {
891 pHlp->pfnPrintf(pHlp,
892 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
893 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
894 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
895 "%sr14=%016RX64 %sr15=%016RX64\n"
896 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
897 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
898 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
899 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
900 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
901 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
902 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
903 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
904 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
905 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
906 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
907 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
908 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
909 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
910 ,
911 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
912 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
913 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
914 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
915 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
916 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
917 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
918 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
919 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
920 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
921 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
922 pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
923 pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
924 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
925 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
926 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
927 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
928 }
929 else
930 pHlp->pfnPrintf(pHlp,
931 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
932 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
933 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
934 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
935 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
936 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
937 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
938 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
939 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
940 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
941 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
942 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
943 ,
944 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
945 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
946 pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
947 pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
948 pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
949 pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
950 pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
951 pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
952 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
953 pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
954 pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
955 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
956
957 pHlp->pfnPrintf(pHlp,
958 "FPU:\n"
959 "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
960 "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
961 "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
962 ,
963 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
964 pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
965 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
966 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
967
968
969 pHlp->pfnPrintf(pHlp,
970 "MSR:\n"
971 "%sEFER =%016RX64\n"
972 "%sPAT =%016RX64\n"
973 "%sSTAR =%016RX64\n"
974 "%sCSTAR =%016RX64\n"
975 "%sLSTAR =%016RX64\n"
976 "%sSFMASK =%016RX64\n"
977 "%sKERNELGSBASE =%016RX64\n",
978 pszPrefix, pCtx->msrEFER,
979 pszPrefix, pCtx->msrPAT,
980 pszPrefix, pCtx->msrSTAR,
981 pszPrefix, pCtx->msrCSTAR,
982 pszPrefix, pCtx->msrLSTAR,
983 pszPrefix, pCtx->msrSFMASK,
984 pszPrefix, pCtx->msrKERNELGSBASE);
985
986 break;
987 }
988}
989
990
991/**
992 * Display all cpu states and any other cpum info.
993 *
994 * @param pVM VM Handle.
995 * @param pHlp The info helper functions.
996 * @param pszArgs Arguments, ignored.
997 */
998static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
999{
1000 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1001 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1002 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1003 cpumR3InfoHost(pVM, pHlp, pszArgs);
1004}
1005
1006
1007/**
1008 * Parses the info argument.
1009 *
1010 * The argument starts with 'verbose', 'terse' or 'default' and then
1011 * continues with the comment string.
1012 *
1013 * @param pszArgs The pointer to the argument string.
1014 * @param penmType Where to store the dump type request.
1015 * @param ppszComment Where to store the pointer to the comment string.
1016 */
1017static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1018{
1019 if (!pszArgs)
1020 {
1021 *penmType = CPUMDUMPTYPE_DEFAULT;
1022 *ppszComment = "";
1023 }
1024 else
1025 {
1026 if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
1027 {
1028 pszArgs += 5;
1029 *penmType = CPUMDUMPTYPE_VERBOSE;
1030 }
1031 else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
1032 {
1033 pszArgs += 5;
1034 *penmType = CPUMDUMPTYPE_TERSE;
1035 }
1036 else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
1037 {
1038 pszArgs += 7;
1039 *penmType = CPUMDUMPTYPE_DEFAULT;
1040 }
1041 else
1042 *penmType = CPUMDUMPTYPE_DEFAULT;
1043 *ppszComment = RTStrStripL(pszArgs);
1044 }
1045}
1046
1047
1048/**
1049 * Display the guest cpu state.
1050 *
1051 * @param pVM VM Handle.
1052 * @param pHlp The info helper functions.
1053 * @param pszArgs Arguments, ignored.
1054 */
1055static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1056{
1057 CPUMDUMPTYPE enmType;
1058 const char *pszComment;
1059 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1060 pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
1061 cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
1062}
1063
1064/**
1065 * Display the current guest instruction
1066 *
1067 * @param pVM VM Handle.
1068 * @param pHlp The info helper functions.
1069 * @param pszArgs Arguments, ignored.
1070 */
1071static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1072{
1073 char szInstruction[256];
1074 int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
1075 if (VBOX_SUCCESS(rc))
1076 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1077}
1078
1079
1080/**
1081 * Display the hypervisor cpu state.
1082 *
1083 * @param pVM VM Handle.
1084 * @param pHlp The info helper functions.
1085 * @param pszArgs Arguments, ignored.
1086 */
1087static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1088{
1089 CPUMDUMPTYPE enmType;
1090 const char *pszComment;
1091 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1092 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1093 cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
1094 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1095}
1096
1097
1098/**
1099 * Display the host cpu state.
1100 *
1101 * @param pVM VM Handle.
1102 * @param pHlp The info helper functions.
1103 * @param pszArgs Arguments, ignored.
1104 */
1105static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1106{
1107 CPUMDUMPTYPE enmType;
1108 const char *pszComment;
1109 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1110 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1111
1112 /*
1113 * Format the EFLAGS.
1114 */
1115 PCPUMHOSTCTX pCtx = &pVM->cpum.s.Host;
1116#if HC_ARCH_BITS == 32
1117 uint32_t efl = pCtx->eflags.u32;
1118#else
1119 uint64_t efl = pCtx->rflags;
1120#endif
1121 char szEFlags[80];
1122 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1123
1124 /*
1125 * Format the registers.
1126 */
1127#if HC_ARCH_BITS == 32
1128# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1129 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1130# endif
1131 {
1132 pHlp->pfnPrintf(pHlp,
1133 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1134 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1135 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1136 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1137 "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
1138 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1139 ,
1140 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1141 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1142 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1143 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1144 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1145 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
1146 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1147 }
1148# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
1149 else
1150# endif
1151#endif
1152#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
1153 {
1154 pHlp->pfnPrintf(pHlp,
1155 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1156 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1157 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1158 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1159 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1160 "r14=%016RX64 r15=%016RX64\n"
1161 "iopl=%d %31s\n"
1162 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1163 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1164 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1165 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
1166 "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1167 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1168 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1169 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1170 ,
1171 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1172 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1173 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1174 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1175 pCtx->r11, pCtx->r12, pCtx->r13,
1176 pCtx->r14, pCtx->r15,
1177 X86_EFL_GET_IOPL(efl), szEFlags,
1178 (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
1179 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1180 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1181 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1182 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1183 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1184 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1185 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1186 }
1187#endif
1188}
1189
1190
1191/**
1192 * Get L1 cache / TLS associativity.
1193 */
1194static const char *getCacheAss(unsigned u, char *pszBuf)
1195{
1196 if (u == 0)
1197 return "res0 ";
1198 if (u == 1)
1199 return "direct";
1200 if (u >= 256)
1201 return "???";
1202
1203 RTStrPrintf(pszBuf, 16, "%d way", u);
1204 return pszBuf;
1205}
1206
1207
1208/**
1209 * Get L2 cache soociativity.
1210 */
1211const char *getL2CacheAss(unsigned u)
1212{
1213 switch (u)
1214 {
1215 case 0: return "off ";
1216 case 1: return "direct";
1217 case 2: return "2 way ";
1218 case 3: return "res3 ";
1219 case 4: return "4 way ";
1220 case 5: return "res5 ";
1221 case 6: return "8 way "; case 7: return "res7 ";
1222 case 8: return "16 way";
1223 case 9: return "res9 ";
1224 case 10: return "res10 ";
1225 case 11: return "res11 ";
1226 case 12: return "res12 ";
1227 case 13: return "res13 ";
1228 case 14: return "res14 ";
1229 case 15: return "fully ";
1230 default:
1231 return "????";
1232 }
1233}
1234
1235
1236/**
1237 * Display the guest CpuId leaves.
1238 *
1239 * @param pVM VM Handle.
1240 * @param pHlp The info helper functions.
1241 * @param pszArgs "terse", "default" or "verbose".
1242 */
1243static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1244{
1245 /*
1246 * Parse the argument.
1247 */
1248 unsigned iVerbosity = 1;
1249 if (pszArgs)
1250 {
1251 pszArgs = RTStrStripL(pszArgs);
1252 if (!strcmp(pszArgs, "terse"))
1253 iVerbosity--;
1254 else if (!strcmp(pszArgs, "verbose"))
1255 iVerbosity++;
1256 }
1257
1258 /*
1259 * Start cracking.
1260 */
1261 CPUMCPUID Host;
1262 CPUMCPUID Guest;
1263 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
1264
1265 pHlp->pfnPrintf(pHlp,
1266 " RAW Standard CPUIDs\n"
1267 " Function eax ebx ecx edx\n");
1268 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
1269 {
1270 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
1271 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1272
1273 pHlp->pfnPrintf(pHlp,
1274 "Gst: %08x %08x %08x %08x %08x%s\n"
1275 "Hst: %08x %08x %08x %08x\n",
1276 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1277 i <= cStdMax ? "" : "*",
1278 Host.eax, Host.ebx, Host.ecx, Host.edx);
1279 }
1280
1281 /*
1282 * If verbose, decode it.
1283 */
1284 if (iVerbosity)
1285 {
1286 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
1287 pHlp->pfnPrintf(pHlp,
1288 "Name: %.04s%.04s%.04s\n"
1289 "Supports: 0-%x\n",
1290 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1291 }
1292
1293 /*
1294 * Get Features.
1295 */
1296 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
1297 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
1298 pVM->cpum.s.aGuestCpuIdStd[0].edx);
1299 if (cStdMax >= 1 && iVerbosity)
1300 {
1301 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
1302 uint32_t uEAX = Guest.eax;
1303
1304 pHlp->pfnPrintf(pHlp,
1305 "Family: %d \tExtended: %d \tEffective: %d\n"
1306 "Model: %d \tExtended: %d \tEffective: %d\n"
1307 "Stepping: %d\n"
1308 "APIC ID: %#04x\n"
1309 "Logical CPUs: %d\n"
1310 "CLFLUSH Size: %d\n"
1311 "Brand ID: %#04x\n",
1312 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1313 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1314 ASMGetCpuStepping(uEAX),
1315 (Guest.ebx >> 24) & 0xff,
1316 (Guest.ebx >> 16) & 0xff,
1317 (Guest.ebx >> 8) & 0xff,
1318 (Guest.ebx >> 0) & 0xff);
1319 if (iVerbosity == 1)
1320 {
1321 uint32_t uEDX = Guest.edx;
1322 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1323 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1324 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1325 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1326 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1327 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1328 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1329 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1330 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1331 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1332 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1333 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1334 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
1335 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1336 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1337 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1338 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1339 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1340 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1341 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
1342 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
1343 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
1344 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
1345 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
1346 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1347 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1348 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
1349 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
1350 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
1351 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
1352 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
1353 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
1354 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
1355 pHlp->pfnPrintf(pHlp, "\n");
1356
1357 uint32_t uECX = Guest.ecx;
1358 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1359 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
1360 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " 1");
1361 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " 2");
1362 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
1363 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
1364 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
1365 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " 6");
1366 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
1367 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
1368 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " 9");
1369 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
1370 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
1371 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
1372 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
1373 for (unsigned iBit = 14; iBit < 32; iBit++)
1374 if (uECX & RT_BIT(iBit))
1375 pHlp->pfnPrintf(pHlp, " %d", iBit);
1376 pHlp->pfnPrintf(pHlp, "\n");
1377 }
1378 else
1379 {
1380 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1381
1382 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
1383 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
1384 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
1385 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
1386
1387 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1388 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
1389 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
1390 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
1391 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
1392 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
1393 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
1394 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
1395 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
1396 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
1397 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
1398 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
1399 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
1400 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
1401 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
1402 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
1403 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
1404 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
1405 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
1406 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
1407 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
1408 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
1409 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
1410 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
1411 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
1412 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
1413 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
1414 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
1415 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
1416 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
1417 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
1418 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
1419 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
1420
1421 pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
1422 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
1423 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
1424 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
1425 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
1426 pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
1427 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
1428 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
1429 pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
1430 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
1431 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
1432 pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
1433 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
1434 pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
1435 }
1436 }
1437 if (cStdMax >= 2 && iVerbosity)
1438 {
1439 /** @todo */
1440 }
1441
1442 /*
1443 * Extended.
1444 * Implemented after AMD specs.
1445 */
1446 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
1447
1448 pHlp->pfnPrintf(pHlp,
1449 "\n"
1450 " RAW Extended CPUIDs\n"
1451 " Function eax ebx ecx edx\n");
1452 for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
1453 {
1454 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
1455 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1456
1457 pHlp->pfnPrintf(pHlp,
1458 "Gst: %08x %08x %08x %08x %08x%s\n"
1459 "Hst: %08x %08x %08x %08x\n",
1460 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1461 i <= cExtMax ? "" : "*",
1462 Host.eax, Host.ebx, Host.ecx, Host.edx);
1463 }
1464
1465 /*
1466 * Understandable output
1467 */
1468 if (iVerbosity && cExtMax >= 0)
1469 {
1470 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
1471 pHlp->pfnPrintf(pHlp,
1472 "Ext Name: %.4s%.4s%.4s\n"
1473 "Ext Supports: 0x80000000-%#010x\n",
1474 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
1475 }
1476
1477 if (iVerbosity && cExtMax >= 1)
1478 {
1479 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
1480 uint32_t uEAX = Guest.eax;
1481 pHlp->pfnPrintf(pHlp,
1482 "Family: %d \tExtended: %d \tEffective: %d\n"
1483 "Model: %d \tExtended: %d \tEffective: %d\n"
1484 "Stepping: %d\n"
1485 "Brand ID: %#05x\n",
1486 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
1487 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
1488 ASMGetCpuStepping(uEAX),
1489 Guest.ebx & 0xfff);
1490
1491 if (iVerbosity == 1)
1492 {
1493 uint32_t uEDX = Guest.edx;
1494 pHlp->pfnPrintf(pHlp, "Features EDX: ");
1495 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
1496 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
1497 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
1498 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
1499 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
1500 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
1501 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
1502 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
1503 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
1504 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
1505 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
1506 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
1507 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
1508 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
1509 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
1510 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
1511 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
1512 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
1513 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
1514 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
1515 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
1516 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
1517 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
1518 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
1519 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
1520 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
1521 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
1522 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
1523 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
1524 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
1525 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
1526 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
1527 pHlp->pfnPrintf(pHlp, "\n");
1528
1529 uint32_t uECX = Guest.ecx;
1530 pHlp->pfnPrintf(pHlp, "Features ECX: ");
1531 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
1532 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
1533 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
1534 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
1535 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
1536 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
1537 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
1538 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
1539 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
1540 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
1541 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
1542 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
1543 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
1544 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
1545 for (unsigned iBit = 5; iBit < 32; iBit++)
1546 if (uECX & RT_BIT(iBit))
1547 pHlp->pfnPrintf(pHlp, " %d", iBit);
1548 pHlp->pfnPrintf(pHlp, "\n");
1549 }
1550 else
1551 {
1552 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1553
1554 uint32_t uEdxGst = Guest.edx;
1555 uint32_t uEdxHst = Host.edx;
1556 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1557 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1558 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1559 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1560 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1561 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1562 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1563 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1564 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1565 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1566 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1567 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1568 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1569 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1570 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1571 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
1572 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
1573 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
1574 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
1575 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
1576 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
1577 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
1578 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
1579 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
1580 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
1581 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
1582 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
1583 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
1584 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
1585 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
1586 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
1587 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
1588 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
1589
1590 uint32_t uEcxGst = Guest.ecx;
1591 uint32_t uEcxHst = Host.ecx;
1592 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
1593 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
1594 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
1595 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
1596 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
1597 pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
1598 pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
1599 pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
1600 pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
1601 pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
1602 pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
1603 pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
1604 pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
1605 pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
1606 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
1607 }
1608 }
1609
1610 if (iVerbosity && cExtMax >= 2)
1611 {
1612 char szString[4*4*3+1] = {0};
1613 uint32_t *pu32 = (uint32_t *)szString;
1614 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
1615 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
1616 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
1617 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
1618 if (cExtMax >= 3)
1619 {
1620 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
1621 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
1622 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
1623 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
1624 }
1625 if (cExtMax >= 4)
1626 {
1627 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
1628 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
1629 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
1630 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
1631 }
1632 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
1633 }
1634
1635 if (iVerbosity && cExtMax >= 5)
1636 {
1637 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
1638 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
1639 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
1640 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
1641 char sz1[32];
1642 char sz2[32];
1643
1644 pHlp->pfnPrintf(pHlp,
1645 "TLB 2/4M Instr/Uni: %s %3d entries\n"
1646 "TLB 2/4M Data: %s %3d entries\n",
1647 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
1648 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
1649 pHlp->pfnPrintf(pHlp,
1650 "TLB 4K Instr/Uni: %s %3d entries\n"
1651 "TLB 4K Data: %s %3d entries\n",
1652 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
1653 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
1654 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
1655 "L1 Instr Cache Lines Per Tag: %d\n"
1656 "L1 Instr Cache Associativity: %s\n"
1657 "L1 Instr Cache Size: %d KB\n",
1658 (uEDX >> 0) & 0xff,
1659 (uEDX >> 8) & 0xff,
1660 getCacheAss((uEDX >> 16) & 0xff, sz1),
1661 (uEDX >> 24) & 0xff);
1662 pHlp->pfnPrintf(pHlp,
1663 "L1 Data Cache Line Size: %d bytes\n"
1664 "L1 Data Cache Lines Per Tag: %d\n"
1665 "L1 Data Cache Associativity: %s\n"
1666 "L1 Data Cache Size: %d KB\n",
1667 (uECX >> 0) & 0xff,
1668 (uECX >> 8) & 0xff,
1669 getCacheAss((uECX >> 16) & 0xff, sz1),
1670 (uECX >> 24) & 0xff);
1671 }
1672
1673 if (iVerbosity && cExtMax >= 6)
1674 {
1675 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
1676 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
1677 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
1678
1679 pHlp->pfnPrintf(pHlp,
1680 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
1681 "L2 TLB 2/4M Data: %s %4d entries\n",
1682 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
1683 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
1684 pHlp->pfnPrintf(pHlp,
1685 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
1686 "L2 TLB 4K Data: %s %4d entries\n",
1687 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
1688 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
1689 pHlp->pfnPrintf(pHlp,
1690 "L2 Cache Line Size: %d bytes\n"
1691 "L2 Cache Lines Per Tag: %d\n"
1692 "L2 Cache Associativity: %s\n"
1693 "L2 Cache Size: %d KB\n",
1694 (uEDX >> 0) & 0xff,
1695 (uEDX >> 8) & 0xf,
1696 getL2CacheAss((uEDX >> 12) & 0xf),
1697 (uEDX >> 16) & 0xffff);
1698 }
1699
1700 if (iVerbosity && cExtMax >= 7)
1701 {
1702 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
1703
1704 pHlp->pfnPrintf(pHlp, "APM Features: ");
1705 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
1706 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
1707 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
1708 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
1709 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
1710 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
1711 for (unsigned iBit = 6; iBit < 32; iBit++)
1712 if (uEDX & RT_BIT(iBit))
1713 pHlp->pfnPrintf(pHlp, " %d", iBit);
1714 pHlp->pfnPrintf(pHlp, "\n");
1715 }
1716
1717 if (iVerbosity && cExtMax >= 8)
1718 {
1719 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
1720 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
1721
1722 pHlp->pfnPrintf(pHlp,
1723 "Physical Address Width: %d bits\n"
1724 "Virtual Address Width: %d bits\n",
1725 (uEAX >> 0) & 0xff,
1726 (uEAX >> 8) & 0xff);
1727 pHlp->pfnPrintf(pHlp,
1728 "Physical Core Count: %d\n",
1729 (uECX >> 0) & 0xff);
1730 }
1731
1732
1733 /*
1734 * Centaur.
1735 */
1736 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
1737
1738 pHlp->pfnPrintf(pHlp,
1739 "\n"
1740 " RAW Centaur CPUIDs\n"
1741 " Function eax ebx ecx edx\n");
1742 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
1743 {
1744 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
1745 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1746
1747 pHlp->pfnPrintf(pHlp,
1748 "Gst: %08x %08x %08x %08x %08x%s\n"
1749 "Hst: %08x %08x %08x %08x\n",
1750 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
1751 i <= cCentaurMax ? "" : "*",
1752 Host.eax, Host.ebx, Host.ecx, Host.edx);
1753 }
1754
1755 /*
1756 * Understandable output
1757 */
1758 if (iVerbosity && cCentaurMax >= 0)
1759 {
1760 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
1761 pHlp->pfnPrintf(pHlp,
1762 "Centaur Supports: 0xc0000000-%#010x\n",
1763 Guest.eax);
1764 }
1765
1766 if (iVerbosity && cCentaurMax >= 1)
1767 {
1768 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
1769 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
1770 uint32_t uEdxHst = Host.edx;
1771
1772 if (iVerbosity == 1)
1773 {
1774 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
1775 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
1776 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
1777 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
1778 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
1779 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
1780 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
1781 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
1782 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
1783 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1784 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
1785 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
1786 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
1787 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
1788 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
1789 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
1790 for (unsigned iBit = 14; iBit < 32; iBit++)
1791 if (uEdxGst & RT_BIT(iBit))
1792 pHlp->pfnPrintf(pHlp, " %d", iBit);
1793 pHlp->pfnPrintf(pHlp, "\n");
1794 }
1795 else
1796 {
1797 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
1798 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
1799 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
1800 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
1801 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
1802 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
1803 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
1804 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
1805 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
1806 /* possibly indicating MM/HE and MM/HE-E on older chips... */
1807 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
1808 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
1809 pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
1810 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
1811 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
1812 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
1813 for (unsigned iBit = 14; iBit < 32; iBit++)
1814 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
1815 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
1816 pHlp->pfnPrintf(pHlp, "\n");
1817 }
1818 }
1819}
1820
1821
1822/**
1823 * Structure used when disassembling and instructions in DBGF.
1824 * This is used so the reader function can get the stuff it needs.
1825 */
1826typedef struct CPUMDISASSTATE
1827{
1828 /** Pointer to the CPU structure. */
1829 PDISCPUSTATE pCpu;
1830 /** The VM handle. */
1831 PVM pVM;
1832 /** Pointer to the first byte in the segemnt. */
1833 RTGCUINTPTR GCPtrSegBase;
1834 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1835 RTGCUINTPTR GCPtrSegEnd;
1836 /** The size of the segment minus 1. */
1837 RTGCUINTPTR cbSegLimit;
1838 /** Pointer to the current page - HC Ptr. */
1839 void const *pvPageHC;
1840 /** Pointer to the current page - GC Ptr. */
1841 RTGCPTR pvPageGC;
1842 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1843 PGMPAGEMAPLOCK PageMapLock;
1844 /** Whether the PageMapLock is valid or not. */
1845 bool fLocked;
1846 /** 64 bits mode or not. */
1847 bool f64Bits;
1848} CPUMDISASSTATE, *PCPUMDISASSTATE;
1849
1850
1851/**
1852 * Instruction reader.
1853 *
1854 * @returns VBox status code.
1855 * @param PtrSrc Address to read from.
1856 * In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
1857 * @param pu8Dst Where to store the bytes.
1858 * @param cbRead Number of bytes to read.
1859 * @param uDisCpu Pointer to the disassembler cpu state.
1860 * In this context it's always pointer to the Core of a DBGFDISASSTATE.
1861 */
1862static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
1863{
1864 PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
1865 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
1866 Assert(cbRead > 0);
1867 for (;;)
1868 {
1869 RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
1870
1871 /* Need to update the page translation? */
1872 if ( !pState->pvPageHC
1873 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1874 {
1875 int rc = VINF_SUCCESS;
1876
1877 /* translate the address */
1878 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1879 if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1880 {
1881 pState->pvPageHC = MMHyperGC2HC(pState->pVM, pState->pvPageGC);
1882 if (!pState->pvPageHC)
1883 rc = VERR_INVALID_POINTER;
1884 }
1885 else
1886 {
1887 /* Release mapping lock previously acquired. */
1888 if (pState->fLocked)
1889 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1890 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
1891 pState->fLocked = RT_SUCCESS_NP(rc);
1892 }
1893 if (VBOX_FAILURE(rc))
1894 {
1895 pState->pvPageHC = NULL;
1896 return rc;
1897 }
1898 }
1899
1900 /* check the segemnt limit */
1901 if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
1902 return VERR_OUT_OF_SELECTOR_BOUNDS;
1903
1904 /* calc how much we can read */
1905 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1906 if (!pState->f64Bits)
1907 {
1908 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1909 if (cb > cbSeg && cbSeg)
1910 cb = cbSeg;
1911 }
1912 if (cb > cbRead)
1913 cb = cbRead;
1914
1915 /* read and advance */
1916 memcpy(pu8Dst, (char *)pState->pvPageHC + (GCPtr & PAGE_OFFSET_MASK), cb);
1917 cbRead -= cb;
1918 if (!cbRead)
1919 return VINF_SUCCESS;
1920 pu8Dst += cb;
1921 PtrSrc += cb;
1922 }
1923}
1924
1925
1926/**
1927 * Disassemble an instruction and return the information in the provided structure.
1928 *
1929 * @returns VBox status code.
1930 * @param pVM VM Handle
1931 * @param pCtx CPU context
1932 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
1933 * @param pCpu Disassembly state
1934 * @param pszPrefix String prefix for logging (debug only)
1935 *
1936 */
1937CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
1938{
1939 CPUMDISASSTATE State;
1940 int rc;
1941
1942 const PGMMODE enmMode = PGMGetGuestMode(pVM);
1943 State.pCpu = pCpu;
1944 State.pvPageGC = 0;
1945 State.pvPageHC = NULL;
1946 State.pVM = pVM;
1947 State.fLocked = false;
1948 State.f64Bits = false;
1949
1950 /*
1951 * Get selector information.
1952 */
1953 if ( (pCtx->cr0 & X86_CR0_PE)
1954 && pCtx->eflags.Bits.u1VM == 0)
1955 {
1956 if (CPUMAreHiddenSelRegsValid(pVM))
1957 {
1958 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
1959 State.GCPtrSegBase = pCtx->csHid.u64Base;
1960 State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
1961 State.cbSegLimit = pCtx->csHid.u32Limit;
1962 pCpu->mode = (State.f64Bits)
1963 ? CPUMODE_64BIT
1964 : pCtx->csHid.Attr.n.u1DefBig
1965 ? CPUMODE_32BIT
1966 : CPUMODE_16BIT;
1967 }
1968 else
1969 {
1970 SELMSELINFO SelInfo;
1971
1972 rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
1973 if (!VBOX_SUCCESS(rc))
1974 {
1975 AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1976 return rc;
1977 }
1978
1979 /*
1980 * Validate the selector.
1981 */
1982 rc = SELMSelInfoValidateCS(&SelInfo, pCtx->ss);
1983 if (!VBOX_SUCCESS(rc))
1984 {
1985 AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
1986 return rc;
1987 }
1988 State.GCPtrSegBase = SelInfo.GCPtrBase;
1989 State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
1990 State.cbSegLimit = SelInfo.cbLimit;
1991 pCpu->mode = SelInfo.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
1992 }
1993 }
1994 else
1995 {
1996 /* real or V86 mode */
1997 pCpu->mode = CPUMODE_16BIT;
1998 State.GCPtrSegBase = pCtx->cs * 16;
1999 State.GCPtrSegEnd = 0xFFFFFFFF;
2000 State.cbSegLimit = 0xFFFFFFFF;
2001 }
2002
2003 /*
2004 * Disassemble the instruction.
2005 */
2006 pCpu->pfnReadBytes = cpumR3DisasInstrRead;
2007 pCpu->apvUserData[0] = &State;
2008
2009 uint32_t cbInstr;
2010#ifndef LOG_ENABLED
2011 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
2012 if (VBOX_SUCCESS(rc))
2013 {
2014#else
2015 char szOutput[160];
2016 rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
2017 if (VBOX_SUCCESS(rc))
2018 {
2019 /* log it */
2020 if (pszPrefix)
2021 Log(("%s: %s", pszPrefix, szOutput));
2022 else
2023 Log(("%s", szOutput));
2024#endif
2025 rc = VINF_SUCCESS;
2026 }
2027 else
2028 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, rc));
2029
2030 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2031 if (State.fLocked)
2032 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2033
2034 return rc;
2035}
2036
2037#ifdef DEBUG
2038
2039/**
2040 * Disassemble an instruction and dump it to the log
2041 *
2042 * @returns VBox status code.
2043 * @param pVM VM Handle
2044 * @param pCtx CPU context
2045 * @param pc GC instruction pointer
2046 * @param prefix String prefix for logging
2047 * @deprecated Use DBGFR3DisasInstrCurrentLog().
2048 *
2049 */
2050CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
2051{
2052 DISCPUSTATE cpu;
2053
2054 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2055}
2056
2057/**
2058 * Disassemble an instruction and dump it to the log
2059 *
2060 * @returns VBox status code.
2061 * @param pVM VM Handle
2062 * @param pCtx CPU context
2063 * @param pc GC instruction pointer
2064 * @param prefix String prefix for logging
2065 * @param nrInstructions
2066 *
2067 */
2068CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
2069{
2070 for(int i=0;i<nrInstructions;i++)
2071 {
2072 DISCPUSTATE cpu;
2073
2074 CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
2075 pc += cpu.opsize;
2076 }
2077}
2078
2079#endif /* DEBUG */
2080
2081#ifdef DEBUG
2082/**
2083 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
2084 *
2085 * @internal
2086 */
2087CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
2088{
2089 pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
2090}
2091#endif /* DEBUG */
2092
2093
2094/**
2095 * API for controlling a few of the CPU features found in CR4.
2096 *
2097 * Currently only X86_CR4_TSD is accepted as input.
2098 *
2099 * @returns VBox status code.
2100 *
2101 * @param pVM The VM handle.
2102 * @param fOr The CR4 OR mask.
2103 * @param fAnd The CR4 AND mask.
2104 */
2105CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2106{
2107 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2108 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2109
2110 pVM->cpum.s.CR4.OrMask &= fAnd;
2111 pVM->cpum.s.CR4.OrMask |= fOr;
2112
2113 return VINF_SUCCESS;
2114}
2115
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