| 1 | ; $Id: tstRTPrfA.asm 98103 2023-01-17 14:15:46Z vboxsync $
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| 2 | ;; @file
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| 3 | ; IPRT - Comparing CPU registers and memory (cache).
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2007-2023 Oracle and/or its affiliates.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox base platform packages, as
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| 10 | ; available from https://www.virtualbox.org.
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| 11 | ;
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| 12 | ; This program is free software; you can redistribute it and/or
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| 13 | ; modify it under the terms of the GNU General Public License
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| 14 | ; as published by the Free Software Foundation, in version 3 of the
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| 15 | ; License.
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| 16 | ;
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| 17 | ; This program is distributed in the hope that it will be useful, but
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| 18 | ; WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | ; General Public License for more details.
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| 21 | ;
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| 22 | ; You should have received a copy of the GNU General Public License
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| 23 | ; along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | ;
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| 25 | ; The contents of this file may alternatively be used under the terms
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| 26 | ; of the Common Development and Distribution License Version 1.0
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| 27 | ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 28 | ; in the VirtualBox distribution, in which case the provisions of the
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| 29 | ; CDDL are applicable instead of those of the GPL.
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| 30 | ;
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| 31 | ; You may elect to license modified versions of this file under the
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| 32 | ; terms and conditions of either the GPL or the CDDL or both.
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| 33 | ;
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| 34 | ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 35 | ;
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| 36 |
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| 37 |
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| 38 |
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| 39 | %include "iprt/asmdefs.mac"
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| 40 |
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| 41 |
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| 42 | %define NUM_LOOPS 10000h
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| 43 |
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| 44 | BEGINCODE
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| 45 |
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| 46 | BEGINPROC tstRTPRfARegisterAccess
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| 47 | push xBP
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| 48 | mov xBP, xSP
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| 49 | and xSP, ~3fh ; 64 byte align xSP
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| 50 | push xBP
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| 51 | mov xBP, xSP
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| 52 | sub xSP, 20h
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| 53 |
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| 54 | mov xAX, 1
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| 55 | mov xDX, 1
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| 56 | mov ecx, NUM_LOOPS
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| 57 | .again:
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| 58 | add eax, ecx
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| 59 | add xDX, xAX
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| 60 | shr xAX, 3
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| 61 | shl xAX, 1
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| 62 | xor xDX, 01010101h
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| 63 |
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| 64 | add eax, ecx
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| 65 | add xDX, xAX
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| 66 | shr xAX, 3
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| 67 | shl xAX, 1
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| 68 | xor xDX, 01010101h
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| 69 |
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| 70 | add eax, ecx
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| 71 | add xDX, xAX
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| 72 | shr xAX, 3
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| 73 | shl xAX, 1
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| 74 | xor xDX, 01010101h
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| 75 |
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| 76 | dec ecx
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| 77 | jnz .again
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| 78 |
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| 79 | leave
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| 80 | leave
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| 81 | ret
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| 82 | ENDPROC tstRTPRfARegisterAccess
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| 83 |
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| 84 |
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| 85 | BEGINPROC tstRTPRfAMemoryAccess
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| 86 | push xBP
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| 87 | mov xBP, xSP
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| 88 | and xSP, ~3fh ; 64 byte align xSP
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| 89 | push xBP
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| 90 | mov xBP, xSP
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| 91 | sub xSP, 20h
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| 92 |
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| 93 | %define VAR_XAX [xBP - xCB*1]
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| 94 | %define VAR_XDX [xBP - xCB*2]
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| 95 | %define VAR_ECX [xBP - xCB*3]
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| 96 |
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| 97 | mov RTCCPTR_PRE VAR_XAX, 1
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| 98 | mov RTCCPTR_PRE VAR_XDX, 1
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| 99 | mov dword VAR_ECX, NUM_LOOPS
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| 100 | .again:
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| 101 |
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| 102 | mov eax, VAR_ECX
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| 103 | add VAR_XAX, eax
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| 104 | mov xAX, VAR_XAX
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| 105 | add VAR_XDX, xAX
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| 106 | shr RTCCPTR_PRE VAR_XAX, 3
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| 107 | shl RTCCPTR_PRE VAR_XAX, 1
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| 108 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 109 |
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| 110 | mov eax, VAR_ECX
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| 111 | add VAR_XAX, eax
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| 112 | mov xAX, VAR_XAX
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| 113 | add VAR_XDX, xAX
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| 114 | shr RTCCPTR_PRE VAR_XAX, 3
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| 115 | shl RTCCPTR_PRE VAR_XAX, 1
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| 116 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 117 |
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| 118 | mov eax, VAR_ECX
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| 119 | add VAR_XAX, eax
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| 120 | mov xAX, VAR_XAX
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| 121 | add VAR_XDX, xAX
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| 122 | shr RTCCPTR_PRE VAR_XAX, 3
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| 123 | shl RTCCPTR_PRE VAR_XAX, 1
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| 124 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 125 |
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| 126 | dec dword VAR_ECX
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| 127 | jnz .again
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| 128 |
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| 129 | %undef VAR_XAX
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| 130 | %undef VAR_XDX
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| 131 | %undef VAR_ECX
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| 132 |
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| 133 | leave
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| 134 | leave
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| 135 | ret
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| 136 | ENDPROC tstRTPRfAMemoryAccess
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| 137 |
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| 138 |
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| 139 | BEGINPROC tstRTPRfAMemoryUnalignedAccess
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| 140 | push xBP
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| 141 | mov xBP, xSP
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| 142 | and xSP, ~3fh ; 64 byte align xSP
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| 143 | push xBP
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| 144 | mov xBP, xSP
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| 145 | sub xSP, 20h
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| 146 |
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| 147 | %define VAR_XAX [xBP - xCB*1 - 1]
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| 148 | %define VAR_XDX [xBP - xCB*2 - 1]
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| 149 | %define VAR_ECX [xBP - xCB*3 - 1]
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| 150 |
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| 151 | mov RTCCPTR_PRE VAR_XAX, 1
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| 152 | mov RTCCPTR_PRE VAR_XDX, 1
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| 153 | mov dword VAR_ECX, NUM_LOOPS
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| 154 | .again:
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| 155 |
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| 156 | mov eax, VAR_ECX
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| 157 | add VAR_XAX, eax
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| 158 | mov xAX, VAR_XAX
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| 159 | add VAR_XDX, xAX
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| 160 | shr RTCCPTR_PRE VAR_XAX, 3
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| 161 | shl RTCCPTR_PRE VAR_XAX, 1
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| 162 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 163 |
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| 164 | mov eax, VAR_ECX
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| 165 | add VAR_XAX, eax
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| 166 | mov xAX, VAR_XAX
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| 167 | add VAR_XDX, xAX
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| 168 | shr RTCCPTR_PRE VAR_XAX, 3
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| 169 | shl RTCCPTR_PRE VAR_XAX, 1
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| 170 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 171 |
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| 172 | mov eax, VAR_ECX
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| 173 | add VAR_XAX, eax
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| 174 | mov xAX, VAR_XAX
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| 175 | add VAR_XDX, xAX
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| 176 | shr RTCCPTR_PRE VAR_XAX, 3
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| 177 | shl RTCCPTR_PRE VAR_XAX, 1
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| 178 | xor RTCCPTR_PRE VAR_XDX, 01010101h
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| 179 |
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| 180 | dec dword VAR_ECX
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| 181 | jnz .again
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| 182 |
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| 183 | %undef VAR_XAX
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| 184 | %undef VAR_XDX
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| 185 | %undef VAR_ECX
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| 186 |
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| 187 | leave
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| 188 | leave
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| 189 | ret
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| 190 | ENDPROC tstRTPRfAMemoryUnalignedAccess
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| 191 |
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