tstRTInlineAsm.cpp@ 106061

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1	/* $Id: tstRTInlineAsm.cpp 106061 2024-09-16 14:03:52Z vboxsync $ */
2	/** @file
3	* IPRT Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* The contents of this file may alternatively be used under the terms
26	* of the Common Development and Distribution License Version 1.0
27	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
28	* in the VirtualBox distribution, in which case the provisions of the
29	* CDDL are applicable instead of those of the GPL.
30	*
31	* You may elect to license modified versions of this file under the
32	* terms and conditions of either the GPL or the CDDL or both.
33	*
34	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
35	*/
36
37
38	/*********************************************************************************************************************************
39	* Header Files *
40	*********************************************************************************************************************************/
41	#include <iprt/asm-mem.h>
42	#include <iprt/asm.h>
43	#include <iprt/asm-math.h>
44
45	/* See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44018. Only gcc version 4.4
46	* is affected. No harm for the VBox code: If the cpuid code compiles, it works
47	* fine. */
48	#if defined(__GNUC__) && defined(RT_ARCH_X86) && defined(__PIC__)
49	# if __GNUC__ == 4 && __GNUC_MINOR__ == 4
50	# define GCC44_32BIT_PIC
51	# endif
52	#endif
53
54	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
55	# include <iprt/asm-amd64-x86.h>
56	# include <iprt/x86.h>
57	#elif defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32)
58	# include <iprt/asm-arm.h>
59	# include <iprt/time.h>
60	#else
61	# include <iprt/time.h>
62	#endif
63	#include <iprt/mem.h>
64	#include <iprt/param.h>
65	#include <iprt/rand.h>
66	#include <iprt/stream.h>
67	#include <iprt/string.h>
68	#include <iprt/thread.h>
69	#include <iprt/test.h>
70	#include <iprt/time.h>
71
72
73
74	/*********************************************************************************************************************************
75	* Defined Constants And Macros *
76	*********************************************************************************************************************************/
77	#define CHECKVAL(val, expect, fmt) \
78	do \
79	{ \
80	if ((val) != (expect)) \
81	{ \
82	RTTestFailed(g_hTest, "%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
83	} \
84	} while (0)
85
86	#define CHECKOP(op, expect, fmt, type) \
87	do \
88	{ \
89	type val = op; \
90	if (val != (type)(expect)) \
91	{ \
92	RTTestFailed(g_hTest, "%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
93	} \
94	} while (0)
95
96	#define CHECK_OP_AND_VAL(a_Type, a_Fmt, a_pVar, a_Operation, a_ExpectRetVal, a_ExpectVarVal) \
97	do { \
98	CHECKOP(a_Operation, a_ExpectRetVal, a_Fmt, a_Type); \
99	CHECKVAL(*a_pVar, a_ExpectVarVal, a_Fmt); \
100	} while (0)
101
102	#define CHECK_OP_AND_VAL_EX(a_TypeRet, a_FmtRet, a_FmtVar, a_pVar, a_Operation, a_ExpectRetVal, a_ExpectVarVal) \
103	do { \
104	CHECKOP(a_Operation, a_ExpectRetVal, a_FmtRet, a_TypeRet); \
105	CHECKVAL(*a_pVar, a_ExpectVarVal, a_FmtVar); \
106	} while (0)
107
108	#define CHECK_OP_AND_VAL_EX2(a_TypeRet, a_FmtRet, a_FmtVar, a_pVar, a_uVar2, a_Operation, a_ExpectRetVal, a_ExpectVarVal, a_ExpectVarVal2) \
109	do { \
110	CHECKOP(a_Operation, a_ExpectRetVal, a_FmtRet, a_TypeRet); \
111	CHECKVAL(*a_pVar, a_ExpectVarVal, a_FmtVar); \
112	CHECKVAL(a_uVar2, a_ExpectVarVal2, a_FmtVar); \
113	} while (0)
114
115	#define CHECKVAL128(a_pu128Val, a_u64HiExpect, a_u64LoExpect) \
116	do \
117	{ \
118	if ((a_pu128Val)->s.Hi != (a_u64HiExpect) \|\| (a_pu128Val)->s.Lo != (a_u64LoExpect)) \
119	RTTestFailed(g_hTest, "%s, %d: " #a_pu128Val ": expected %#RX64'%016RX64 got %#RX64'%016RX64\n", \
120	__FUNCTION__, __LINE__, (a_u64HiExpect), (a_u64LoExpect), (a_pu128Val)->s.Hi, (a_pu128Val)->s.Lo); \
121	} while (0)
122	#define CHECKVAL128_C(a_pu128Val, a_u64HiExpect, a_u64LoExpect) \
123	do \
124	{ \
125	if ((a_pu128Val)->s.Hi != UINT64_C(a_u64HiExpect) \|\| (a_pu128Val)->s.Lo != UINT64_C(a_u64LoExpect)) \
126	RTTestFailed(g_hTest, "%s, %d: " #a_pu128Val ": expected %#RX64'%016RX64 got %#RX64'%016RX64\n", \
127	__FUNCTION__, __LINE__, UINT64_C(a_u64HiExpect), UINT64_C(a_u64LoExpect), \
128	(a_pu128Val)->s.Hi, (a_pu128Val)->s.Lo); \
129	} while (0)
130	#define CHECK_OP_AND_VAL_128(a_TypeRet, a_FmtRet, a_pu128Val, a_Operation, a_ExpectRetVal, a_u64HiExpect, a_u64LoExpect) \
131	do { \
132	CHECKOP(a_Operation, a_ExpectRetVal, a_FmtRet, a_TypeRet); \
133	CHECKVAL128(a_pu128Val, a_u64HiExpect, a_u64LoExpect); \
134	} while (0)
135	#define CHECK_OP_AND_VAL_128_C(a_TypeRet, a_FmtRet, a_pu128Val, a_Operation, a_ExpectRetVal, a_u64HiExpect, a_u64LoExpect) \
136	do { \
137	CHECKOP(a_Operation, a_ExpectRetVal, a_FmtRet, a_TypeRet); \
138	CHECKVAL128_C(a_pu128Val, a_u64HiExpect, a_u64LoExpect); \
139	} while (0)
140
141	/**
142	* Calls a worker function with different worker variable storage types.
143	*/
144	#define DO_SIMPLE_TEST_NO_SUB_NO_STACK(a_WorkerFunction, type) \
145	do \
146	{ \
147	type pVar = (type )RTTestGuardedAllocHead(g_hTest, sizeof(type)); \
148	RTTEST_CHECK_BREAK(g_hTest, pVar); \
149	a_WorkerFunction(pVar); \
150	RTTestGuardedFree(g_hTest, pVar); \
151	\
152	pVar = (type *)RTTestGuardedAllocTail(g_hTest, sizeof(type)); \
153	RTTEST_CHECK_BREAK(g_hTest, pVar); \
154	a_WorkerFunction(pVar); \
155	RTTestGuardedFree(g_hTest, pVar); \
156	} while (0)
157
158
159	/**
160	* Calls a worker function with different worker variable storage types.
161	*/
162	#define DO_SIMPLE_TEST_NO_SUB(a_WorkerFunction, type) \
163	do \
164	{ \
165	type StackVar; \
166	a_WorkerFunction(&StackVar); \
167	DO_SIMPLE_TEST_NO_SUB_NO_STACK(a_WorkerFunction, type); \
168	} while (0)
169
170	/**
171	* Calls a worker function with different worker variable storage types.
172	*/
173	#define DO_SIMPLE_TEST(name, type) \
174	do \
175	{ \
176	RTTestISub(#name); \
177	DO_SIMPLE_TEST_NO_SUB(tst ## name ## Worker, type); \
178	} while (0)
179
180
181	/**
182	* Calls a worker function with different worker variable storage types.
183	*/
184	#define DO_SIMPLE_TEST_NO_STACK(name, type) \
185	do \
186	{ \
187	RTTestISub(#name); \
188	DO_SIMPLE_TEST_NO_SUB_NO_STACK(tst ## name ## Worker, type); \
189	} while (0)
190
191
192	/*********************************************************************************************************************************
193	* Global Variables *
194	*********************************************************************************************************************************/
195	/** The test instance. */
196	static RTTEST g_hTest;
197
198
199
200	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
201
202	static const char *getCacheAss(unsigned u)
203	{
204	if (u == 0)
205	return "res0 ";
206	if (u == 1)
207	return "direct";
208	if (u >= 256)
209	return "???";
210
211	char *pszRet = NULL;
212	RTStrAPrintf(&pszRet, "%d way", u);
213	RTMEM_WILL_LEAK(pszRet);
214	return pszRet;
215	}
216
217
218	static const char *getL2CacheAss(unsigned u)
219	{
220	switch (u)
221	{
222	case 0: return "off ";
223	case 1: return "direct";
224	case 2: return "2 way ";
225	case 3: return "res3 ";
226	case 4: return "4 way ";
227	case 5: return "res5 ";
228	case 6: return "8 way ";
229	case 7: return "res7 ";
230	case 8: return "16 way";
231	case 9: return "res9 ";
232	case 10: return "res10 ";
233	case 11: return "res11 ";
234	case 12: return "res12 ";
235	case 13: return "res13 ";
236	case 14: return "res14 ";
237	case 15: return "fully ";
238	default:
239	return "????";
240	}
241	}
242
243
244	/**
245	* Test and dump all possible info from the CPUID instruction.
246	*
247	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
248	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
249	*/
250	static void tstASMCpuId(void)
251	{
252	RTTestISub("ASMCpuId");
253
254	unsigned iBit;
255	struct
256	{
257	uint32_t uEBX, uEAX, uEDX, uECX;
258	} s;
259	if (!ASMHasCpuId())
260	{
261	RTTestIPrintf(RTTESTLVL_ALWAYS, "warning! CPU doesn't support CPUID\n");
262	return;
263	}
264
265	/*
266	* Try the 0 function and use that for checking the ASMCpuId_* variants.
267	*/
268	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
269
270	uint32_t u32;
271
272	u32 = ASMCpuId_EAX(0);
273	CHECKVAL(u32, s.uEAX, "%x");
274	u32 = ASMCpuId_EBX(0);
275	CHECKVAL(u32, s.uEBX, "%x");
276	u32 = ASMCpuId_ECX(0);
277	CHECKVAL(u32, s.uECX, "%x");
278	u32 = ASMCpuId_EDX(0);
279	CHECKVAL(u32, s.uEDX, "%x");
280
281	uint32_t uECX2 = s.uECX - 1;
282	uint32_t uEDX2 = s.uEDX - 1;
283	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
284	CHECKVAL(uECX2, s.uECX, "%x");
285	CHECKVAL(uEDX2, s.uEDX, "%x");
286
287	uint32_t uEAX2 = s.uEAX - 1;
288	uint32_t uEBX2 = s.uEBX - 1;
289	uECX2 = s.uECX - 1;
290	uEDX2 = s.uEDX - 1;
291	ASMCpuIdExSlow(0, 0, 0, 0, &uEAX2, &uEBX2, &uECX2, &uEDX2);
292	CHECKVAL(uEAX2, s.uEAX, "%x");
293	CHECKVAL(uEBX2, s.uEBX, "%x");
294	CHECKVAL(uECX2, s.uECX, "%x");
295	CHECKVAL(uEDX2, s.uEDX, "%x");
296
297	/*
298	* Check the extended APIC stuff.
299	*/
300	uint32_t idExtApic;
301	if (ASMCpuId_EAX(0) >= 0xb)
302	{
303	uint8_t idApic = ASMGetApicId();
304	do
305	{
306	uEAX2 = uEBX2 = uECX2 = uEDX2 = UINT32_C(0x50486744);
307	ASMCpuIdExSlow(0xb, 0, 0, 0, &uEAX2, &uEBX2, &uECX2, &uEDX2);
308	idExtApic = ASMGetApicIdExt0B();
309	} while (ASMGetApicId() != idApic);
310
311	CHECKVAL(uEDX2, idExtApic, "%x");
312	if (idApic != (uint8_t)idExtApic && uECX2 != 0)
313	RTTestIFailed("ASMGetApicIdExt0B() -> %#x vs ASMGetApicId() -> %#x", idExtApic, idApic);
314	}
315	if (ASMCpuId_EAX(UINT32_C(0x80000000)) >= UINT32_C(0x8000001E))
316	{
317	uint8_t idApic = ASMGetApicId();
318	do
319	{
320	uEAX2 = uEBX2 = uECX2 = uEDX2 = UINT32_C(0x50486744);
321	ASMCpuIdExSlow(0x8000001e, 0, 0, 0, &uEAX2, &uEBX2, &uECX2, &uEDX2);
322	idExtApic = ASMGetApicIdExt8000001E();
323	} while (ASMGetApicId() != idApic);
324	CHECKVAL(uEAX2, idExtApic, "%x");
325	if (idApic != (uint8_t)idExtApic)
326	RTTestIFailed("ASMGetApicIdExt8000001E() -> %#x vs ASMGetApicId() -> %#x", idExtApic, idApic);
327	}
328
329	/*
330	* Done testing, dump the information.
331	*/
332	RTTestIPrintf(RTTESTLVL_ALWAYS, "CPUID Dump\n");
333	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
334	const uint32_t cFunctions = s.uEAX;
335
336	/* raw dump */
337	RTTestIPrintf(RTTESTLVL_ALWAYS,
338	"\n"
339	" RAW Standard CPUIDs\n"
340	"Function eax ebx ecx edx\n");
341	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
342	{
343	ASMCpuId_Idx_ECX(iStd, 0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
344	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
345	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
346
347	/* Some leafs output depend on the initial value of ECX.
348	* The same seems to apply to invalid standard functions */
349	if (iStd > cFunctions)
350	continue;
351	if (iStd == 0x04) /* Deterministic Cache Parameters Leaf */
352	for (uint32_t uECX = 1; s.uEAX & 0x1f; uECX++)
353	{
354	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
355	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
356	RTTESTI_CHECK_BREAK(uECX < 128);
357	}
358	else if (iStd == 0x07) /* Structured Extended Feature Flags */
359	{
360	uint32_t uMax = s.uEAX;
361	for (uint32_t uECX = 1; uECX < uMax; uECX++)
362	{
363	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
364	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
365	RTTESTI_CHECK_BREAK(uECX < 128);
366	}
367	}
368	else if (iStd == 0x0b) /* Extended Topology Enumeration Leafs */
369	for (uint32_t uECX = 1; (s.uEAX & 0x1f) && (s.uEBX & 0xffff); uECX++)
370	{
371	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
372	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
373	RTTESTI_CHECK_BREAK(uECX < 128);
374	}
375	else if (iStd == 0x0d) /* Extended State Enumeration Leafs */
376	for (uint32_t uECX = 1; s.uEAX != 0 \|\| s.uEBX != 0 \|\| s.uECX != 0 \|\| s.uEDX != 0; uECX++)
377	{
378	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
379	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
380	RTTESTI_CHECK_BREAK(uECX < 128);
381	}
382	else if ( iStd == 0x0f /* Platform quality of service monitoring (PQM) */
383	\|\| iStd == 0x10 /* Platform quality of service enforcement (PQE) */
384	\|\| iStd == 0x12 /* SGX Enumeration */
385	\|\| iStd == 0x14 /* Processor Trace Enumeration */
386	\|\| iStd == 0x17 /* SoC Vendor Attribute Enumeration */
387	\|\| iStd == 0x18 /* Deterministic Address Translation Parameters */)
388	{
389	/** @todo */
390	}
391	else
392	{
393	u32 = ASMCpuId_EAX(iStd);
394	CHECKVAL(u32, s.uEAX, "%x");
395
396	uint32_t u32EbxMask = UINT32_MAX;
397	if (iStd == 1)
398	u32EbxMask = UINT32_C(0x00ffffff); /* Omit the local apic ID in case we're rescheduled. */
399	u32 = ASMCpuId_EBX(iStd);
400	CHECKVAL(u32 & u32EbxMask, s.uEBX & u32EbxMask, "%x");
401
402	u32 = ASMCpuId_ECX(iStd);
403	CHECKVAL(u32, s.uECX, "%x");
404	u32 = ASMCpuId_EDX(iStd);
405	CHECKVAL(u32, s.uEDX, "%x");
406
407	uECX2 = s.uECX - 1;
408	uEDX2 = s.uEDX - 1;
409	ASMCpuId_ECX_EDX(iStd, &uECX2, &uEDX2);
410	CHECKVAL(uECX2, s.uECX, "%x");
411	CHECKVAL(uEDX2, s.uEDX, "%x");
412
413	uEAX2 = s.uEAX - 1;
414	uEBX2 = s.uEBX - 1;
415	uECX2 = s.uECX - 1;
416	uEDX2 = s.uEDX - 1;
417	ASMCpuId(iStd, &uEAX2, &uEBX2, &uECX2, &uEDX2);
418	CHECKVAL(uEAX2, s.uEAX, "%x");
419	CHECKVAL(uEBX2 & u32EbxMask, s.uEBX & u32EbxMask, "%x");
420	CHECKVAL(uECX2, s.uECX, "%x");
421	CHECKVAL(uEDX2, s.uEDX, "%x");
422	}
423	}
424
425	/*
426	* Understandable output
427	*/
428	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
429	RTTestIPrintf(RTTESTLVL_ALWAYS,
430	"Name: %.04s%.04s%.04s\n"
431	"Support: 0-%u\n",
432	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
433	bool const fIntel = RTX86IsIntelCpu(s.uEBX, s.uECX, s.uEDX);
434
435	/*
436	* Get Features.
437	*/
438	if (cFunctions >= 1)
439	{
440	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
441	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
442	RTTestIPrintf(RTTESTLVL_ALWAYS,
443	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
444	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
445	"Stepping: %d\n"
446	"Type: %d (%s)\n"
447	"APIC ID: %#04x\n"
448	"Logical CPUs: %d\n"
449	"CLFLUSH Size: %d\n"
450	"Brand ID: %#04x\n",
451	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, RTX86GetCpuFamily(s.uEAX),
452	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, RTX86GetCpuModel(s.uEAX, fIntel),
453	RTX86GetCpuStepping(s.uEAX),
454	(s.uEAX >> 12) & 0x3, s_apszTypes[(s.uEAX >> 12) & 0x3],
455	(s.uEBX >> 24) & 0xff,
456	(s.uEBX >> 16) & 0xff,
457	(s.uEBX >> 8) & 0xff,
458	(s.uEBX >> 0) & 0xff);
459
460	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
461	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
462	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
463	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
464	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
465	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
466	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
467	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
468	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
469	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX8");
470	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
471	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
472	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SEP");
473	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
474	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
475	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
476	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
477	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
478	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
479	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSN");
480	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CLFSH");
481	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 20");
482	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DS");
483	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " ACPI");
484	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
485	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
486	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE");
487	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE2");
488	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SS");
489	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " HTT");
490	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 29");
491	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 30");
492	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 31");
493	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
494
495	/** @todo check intel docs. */
496	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
497	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE3");
498	for (iBit = 1; iBit < 13; iBit++)
499	if (s.uECX & RT_BIT(iBit))
500	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
501	if (s.uECX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX16");
502	for (iBit = 14; iBit < 32; iBit++)
503	if (s.uECX & RT_BIT(iBit))
504	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
505	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
506	}
507	if (ASMCpuId_EAX(0) >= 0xb)
508	RTTestIPrintf(RTTESTLVL_ALWAYS, "APIC ID(Ext 0b): %#010x\n", ASMGetApicIdExt0B());
509
510	/*
511	* Extended.
512	* Implemented after AMD specs.
513	*/
514	/** @todo check out the intel specs. */
515	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
516	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
517	{
518	RTTestIPrintf(RTTESTLVL_ALWAYS, "No extended CPUID info? Check the manual on how to detect this...\n");
519	return;
520	}
521	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
522
523	/* raw dump */
524	RTTestIPrintf(RTTESTLVL_ALWAYS,
525	"\n"
526	" RAW Extended CPUIDs\n"
527	"Function eax ebx ecx edx\n");
528	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
529	{
530	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
531	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
532	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
533
534	if (iExt > cExtFunctions)
535	continue; /* Invalid extended functions seems change the value if ECX changes */
536	if (iExt == 0x8000001d)
537	continue; /* Takes cache level in ecx. */
538
539	u32 = ASMCpuId_EAX(iExt);
540	CHECKVAL(u32, s.uEAX, "%x");
541	u32 = ASMCpuId_EBX(iExt);
542	CHECKVAL(u32, s.uEBX, "%x");
543	u32 = ASMCpuId_ECX(iExt);
544	CHECKVAL(u32, s.uECX, "%x");
545	u32 = ASMCpuId_EDX(iExt);
546	CHECKVAL(u32, s.uEDX, "%x");
547
548	uECX2 = s.uECX - 1;
549	uEDX2 = s.uEDX - 1;
550	ASMCpuId_ECX_EDX(iExt, &uECX2, &uEDX2);
551	CHECKVAL(uECX2, s.uECX, "%x");
552	CHECKVAL(uEDX2, s.uEDX, "%x");
553
554	uEAX2 = s.uEAX - 1;
555	uEBX2 = s.uEBX - 1;
556	uECX2 = s.uECX - 1;
557	uEDX2 = s.uEDX - 1;
558	ASMCpuId(iExt, &uEAX2, &uEBX2, &uECX2, &uEDX2);
559	CHECKVAL(uEAX2, s.uEAX, "%x");
560	CHECKVAL(uEBX2, s.uEBX, "%x");
561	CHECKVAL(uECX2, s.uECX, "%x");
562	CHECKVAL(uEDX2, s.uEDX, "%x");
563	}
564
565	/*
566	* Understandable output
567	*/
568	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
569	RTTestIPrintf(RTTESTLVL_ALWAYS,
570	"Ext Name: %.4s%.4s%.4s\n"
571	"Ext Supports: 0x80000000-%#010x\n",
572	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
573
574	if (cExtFunctions >= 0x80000001)
575	{
576	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
577	RTTestIPrintf(RTTESTLVL_ALWAYS,
578	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
579	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
580	"Stepping: %d\n"
581	"Brand ID: %#05x\n",
582	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, RTX86GetCpuFamily(s.uEAX),
583	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, RTX86GetCpuModel(s.uEAX, fIntel),
584	RTX86GetCpuStepping(s.uEAX),
585	s.uEBX & 0xfff);
586
587	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
588	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
589	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
590	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
591	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
592	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
593	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
594	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
595	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
596	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMPXCHG8B");
597	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
598	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
599	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SysCallSysRet");
600	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
601	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
602	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
603	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
604	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
605	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
606	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 18");
607	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 19");
608	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " NX");
609	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 21");
610	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MmxExt");
611	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
612	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
613	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FastFXSR");
614	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 26");
615	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " RDTSCP");
616	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 28");
617	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LongMode");
618	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNowExt");
619	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNow");
620	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
621
622	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
623	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LahfSahf");
624	if (s.uECX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CmpLegacy");
625	if (s.uECX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SVM");
626	if (s.uECX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3");
627	if (s.uECX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " AltMovCr8");
628	for (iBit = 5; iBit < 32; iBit++)
629	if (s.uECX & RT_BIT(iBit))
630	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
631	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
632	}
633
634	char szString[443+1] = {0};
635	if (cExtFunctions >= 0x80000002)
636	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
637	if (cExtFunctions >= 0x80000003)
638	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
639	if (cExtFunctions >= 0x80000004)
640	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
641	if (cExtFunctions >= 0x80000002)
642	RTTestIPrintf(RTTESTLVL_ALWAYS, "Full Name: %s\n", szString);
643
644	if (cExtFunctions >= 0x80000005)
645	{
646	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
647	RTTestIPrintf(RTTESTLVL_ALWAYS,
648	"TLB 2/4M Instr/Uni: %s %3d entries\n"
649	"TLB 2/4M Data: %s %3d entries\n",
650	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
651	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
652	RTTestIPrintf(RTTESTLVL_ALWAYS,
653	"TLB 4K Instr/Uni: %s %3d entries\n"
654	"TLB 4K Data: %s %3d entries\n",
655	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
656	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
657	RTTestIPrintf(RTTESTLVL_ALWAYS,
658	"L1 Instr Cache Line Size: %d bytes\n"
659	"L1 Instr Cache Lines Per Tag: %d\n"
660	"L1 Instr Cache Associativity: %s\n"
661	"L1 Instr Cache Size: %d KB\n",
662	(s.uEDX >> 0) & 0xff,
663	(s.uEDX >> 8) & 0xff,
664	getCacheAss((s.uEDX >> 16) & 0xff),
665	(s.uEDX >> 24) & 0xff);
666	RTTestIPrintf(RTTESTLVL_ALWAYS,
667	"L1 Data Cache Line Size: %d bytes\n"
668	"L1 Data Cache Lines Per Tag: %d\n"
669	"L1 Data Cache Associativity: %s\n"
670	"L1 Data Cache Size: %d KB\n",
671	(s.uECX >> 0) & 0xff,
672	(s.uECX >> 8) & 0xff,
673	getCacheAss((s.uECX >> 16) & 0xff),
674	(s.uECX >> 24) & 0xff);
675	}
676
677	if (cExtFunctions >= 0x80000006)
678	{
679	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
680	RTTestIPrintf(RTTESTLVL_ALWAYS,
681	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
682	"L2 TLB 2/4M Data: %s %4d entries\n",
683	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
684	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
685	RTTestIPrintf(RTTESTLVL_ALWAYS,
686	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
687	"L2 TLB 4K Data: %s %4d entries\n",
688	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
689	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
690	RTTestIPrintf(RTTESTLVL_ALWAYS,
691	"L2 Cache Line Size: %d bytes\n"
692	"L2 Cache Lines Per Tag: %d\n"
693	"L2 Cache Associativity: %s\n"
694	"L2 Cache Size: %d KB\n",
695	(s.uEDX >> 0) & 0xff,
696	(s.uEDX >> 8) & 0xf,
697	getL2CacheAss((s.uEDX >> 12) & 0xf),
698	(s.uEDX >> 16) & 0xffff);
699	}
700
701	if (cExtFunctions >= 0x80000007)
702	{
703	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
704	RTTestIPrintf(RTTESTLVL_ALWAYS, "APM Features: ");
705	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TS");
706	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FID");
707	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VID");
708	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TTP");
709	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TM");
710	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " STC");
711	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 6");
712	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 7");
713	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TscInvariant");
714	for (iBit = 9; iBit < 32; iBit++)
715	if (s.uEDX & RT_BIT(iBit))
716	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
717	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
718	}
719
720	if (cExtFunctions >= 0x80000008)
721	{
722	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
723	RTTestIPrintf(RTTESTLVL_ALWAYS,
724	"Physical Address Width: %d bits\n"
725	"Virtual Address Width: %d bits\n"
726	"Guest Physical Address Width: %d bits\n",
727	(s.uEAX >> 0) & 0xff,
728	(s.uEAX >> 8) & 0xff,
729	(s.uEAX >> 16) & 0xff);
730	RTTestIPrintf(RTTESTLVL_ALWAYS,
731	"Physical Core Count: %d\n",
732	((s.uECX >> 0) & 0xff) + 1);
733	if ((s.uECX >> 12) & 0xf)
734	RTTestIPrintf(RTTESTLVL_ALWAYS, "ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
735	}
736
737	if (cExtFunctions >= 0x8000000a)
738	{
739	ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
740	RTTestIPrintf(RTTESTLVL_ALWAYS,
741	"SVM Revision: %d (%#x)\n"
742	"Number of Address Space IDs: %d (%#x)\n",
743	s.uEAX & 0xff, s.uEAX & 0xff,
744	s.uEBX, s.uEBX);
745	}
746	if (ASMCpuId_EAX(UINT32_C(0x80000000)) >= UINT32_C(0x8000001E))
747	RTTestIPrintf(RTTESTLVL_ALWAYS, "APIC ID(Ext 8000001b): %#010x\n", ASMGetApicIdExt8000001E());
748	}
749
750	# if 0
751	static void bruteForceCpuId(void)
752	{
753	RTTestISub("brute force CPUID leafs");
754	uint32_t auPrevValues[4] = { 0, 0, 0, 0};
755	uint32_t uLeaf = 0;
756	do
757	{
758	uint32_t auValues[4];
759	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auValues[0], &auValues[1], &auValues[2], &auValues[3]);
760	if ( (auValues[0] != auPrevValues[0] && auValues[0] != uLeaf)
761	\|\| (auValues[1] != auPrevValues[1] && auValues[1] != 0)
762	\|\| (auValues[2] != auPrevValues[2] && auValues[2] != 0)
763	\|\| (auValues[3] != auPrevValues[3] && auValues[3] != 0)
764	\|\| (uLeaf & (UINT32_C(0x08000000) - UINT32_C(1))) == 0)
765	{
766	RTTestIPrintf(RTTESTLVL_ALWAYS,
767	"%08x: %08x %08x %08x %08x\n", uLeaf,
768	auValues[0], auValues[1], auValues[2], auValues[3]);
769	}
770	auPrevValues[0] = auValues[0];
771	auPrevValues[1] = auValues[1];
772	auPrevValues[2] = auValues[2];
773	auPrevValues[3] = auValues[3];
774
775	//uint32_t uSubLeaf = 0;
776	//do
777	//{
778	//
779	//
780	//} while (false);
781	} while (uLeaf++ < UINT32_MAX);
782	}
783	# endif
784
785	#endif /* AMD64 \|\| X86 */
786
787	#define TEST_READ(a_pVar, a_Type, a_Fmt, a_Function, a_Val) \
788	do { a_pVar = a_Val; CHECKOP(a_Function(a_pVar), a_Val, a_Fmt, a_Type); CHECKVAL(a_pVar, a_Val, a_Fmt); } while (0)
789
790	DECLINLINE(void) tstASMAtomicReadU8Worker(uint8_t volatile *pu8)
791	{
792	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 0);
793	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 1);
794	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 2);
795	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 16);
796	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 32);
797	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 32);
798	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 127);
799	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 128);
800	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 169);
801	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 239);
802	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 254);
803	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicReadU8, 255);
804
805	int8_t volatile pi8 = (int8_t volatile )pu8;
806	TEST_READ(pi8, uint8_t, "%d", ASMAtomicReadS8, INT8_MAX);
807	TEST_READ(pi8, uint8_t, "%d", ASMAtomicReadS8, INT8_MIN);
808	TEST_READ(pi8, uint8_t, "%d", ASMAtomicReadS8, 42);
809	TEST_READ(pi8, uint8_t, "%d", ASMAtomicReadS8, -21);
810
811	bool volatile pf = (bool volatile )pu8;
812	TEST_READ(pf, bool, "%d", ASMAtomicReadBool, true);
813	TEST_READ(pf, bool, "%d", ASMAtomicReadBool, false);
814	}
815
816
817	DECLINLINE(void) tstASMAtomicUoReadU8Worker(uint8_t volatile *pu8)
818	{
819	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 0);
820	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 1);
821	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 2);
822	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 16);
823	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 32);
824	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 32);
825	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 127);
826	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 128);
827	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 169);
828	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 239);
829	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 254);
830	TEST_READ(pu8, uint8_t, "%#x", ASMAtomicUoReadU8, 255);
831
832	int8_t volatile pi8 = (int8_t volatile )pu8;
833	TEST_READ(pi8, uint8_t, "%d", ASMAtomicUoReadS8, INT8_MAX);
834	TEST_READ(pi8, uint8_t, "%d", ASMAtomicUoReadS8, INT8_MIN);
835	TEST_READ(pi8, uint8_t, "%d", ASMAtomicUoReadS8, 42);
836	TEST_READ(pi8, uint8_t, "%d", ASMAtomicUoReadS8, -21);
837
838	bool volatile pf = (bool volatile )pu8;
839	TEST_READ(pf, bool, "%d", ASMAtomicUoReadBool, true);
840	TEST_READ(pf, bool, "%d", ASMAtomicUoReadBool, false);
841	}
842
843
844	DECLINLINE(void) tstASMAtomicReadU16Worker(uint16_t volatile *pu16)
845	{
846	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicReadU16, 0);
847	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicReadU16, 19983);
848	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicReadU16, INT16_MAX);
849	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicReadU16, UINT16_MAX);
850
851	int16_t volatile pi16 = (int16_t volatile )pu16;
852	TEST_READ(pi16, uint16_t, "%d", ASMAtomicReadS16, INT16_MAX);
853	TEST_READ(pi16, uint16_t, "%d", ASMAtomicReadS16, INT16_MIN);
854	TEST_READ(pi16, uint16_t, "%d", ASMAtomicReadS16, 42);
855	TEST_READ(pi16, uint16_t, "%d", ASMAtomicReadS16, -21);
856	}
857
858
859	DECLINLINE(void) tstASMAtomicUoReadU16Worker(uint16_t volatile *pu16)
860	{
861	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicUoReadU16, 0);
862	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicUoReadU16, 19983);
863	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicUoReadU16, INT16_MAX);
864	TEST_READ(pu16, uint16_t, "%#x", ASMAtomicUoReadU16, UINT16_MAX);
865
866	int16_t volatile pi16 = (int16_t volatile )pu16;
867	TEST_READ(pi16, uint16_t, "%d", ASMAtomicUoReadS16, INT16_MAX);
868	TEST_READ(pi16, uint16_t, "%d", ASMAtomicUoReadS16, INT16_MIN);
869	TEST_READ(pi16, uint16_t, "%d", ASMAtomicUoReadS16, 42);
870	TEST_READ(pi16, uint16_t, "%d", ASMAtomicUoReadS16, -21);
871	}
872
873
874	DECLINLINE(void) tstASMAtomicReadU32Worker(uint32_t volatile *pu32)
875	{
876	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, 0);
877	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, 19983);
878	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, INT16_MAX);
879	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, UINT16_MAX);
880	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, _1M-1);
881	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, _1M+1);
882	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, _1G-1);
883	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, _1G+1);
884	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, INT32_MAX);
885	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicReadU32, UINT32_MAX);
886
887	int32_t volatile pi32 = (int32_t volatile )pu32;
888	TEST_READ(pi32, uint32_t, "%d", ASMAtomicReadS32, INT32_MAX);
889	TEST_READ(pi32, uint32_t, "%d", ASMAtomicReadS32, INT32_MIN);
890	TEST_READ(pi32, uint32_t, "%d", ASMAtomicReadS32, 42);
891	TEST_READ(pi32, uint32_t, "%d", ASMAtomicReadS32, -21);
892
893	#if ARCH_BITS == 32
894	size_t volatile pcb = (size_t volatile )pu32;
895	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, 0);
896	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, ~(size_t)2);
897	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, ~(size_t)0 / 4);
898
899	void * volatile ppv = (void volatile *)pu32;
900	TEST_READ(ppv, void *, "%p", ASMAtomicReadPtr, NULL);
901	TEST_READ(ppv, void , "%p", ASMAtomicReadPtr, (void )~(uintptr_t)42);
902
903	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
904	RTSEMEVENT hEvt = ASMAtomicReadPtrT(phEvt, RTSEMEVENT);
905	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
906
907	ASMAtomicReadHandle(phEvt, &hEvt);
908	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
909	#endif
910	}
911
912
913	DECLINLINE(void) tstASMAtomicUoReadU32Worker(uint32_t volatile *pu32)
914	{
915	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, 0);
916	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, 19983);
917	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, INT16_MAX);
918	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, UINT16_MAX);
919	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, _1M-1);
920	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, _1M+1);
921	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, _1G-1);
922	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, _1G+1);
923	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, INT32_MAX);
924	TEST_READ(pu32, uint32_t, "%#x", ASMAtomicUoReadU32, UINT32_MAX);
925
926	int32_t volatile pi32 = (int32_t volatile )pu32;
927	TEST_READ(pi32, uint32_t, "%d", ASMAtomicUoReadS32, INT32_MAX);
928	TEST_READ(pi32, uint32_t, "%d", ASMAtomicUoReadS32, INT32_MIN);
929	TEST_READ(pi32, uint32_t, "%d", ASMAtomicUoReadS32, 42);
930	TEST_READ(pi32, uint32_t, "%d", ASMAtomicUoReadS32, -21);
931
932	#if ARCH_BITS == 32
933	size_t volatile pcb = (size_t volatile )pu32;
934	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, 0);
935	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, ~(size_t)2);
936	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, ~(size_t)0 / 4);
937
938	void * volatile ppv = (void volatile *)pu32;
939	TEST_READ(ppv, void *, "%p", ASMAtomicUoReadPtr, NULL);
940	TEST_READ(ppv, void , "%p", ASMAtomicUoReadPtr, (void )~(uintptr_t)42);
941
942	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
943	RTSEMEVENT hEvt = ASMAtomicUoReadPtrT(phEvt, RTSEMEVENT);
944	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
945
946	ASMAtomicUoReadHandle(phEvt, &hEvt);
947	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
948	#endif
949	}
950
951
952	DECLINLINE(void) tstASMAtomicReadU64Worker(uint64_t volatile *pu64)
953	{
954	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, 0);
955	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, 19983);
956	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, INT16_MAX);
957	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, UINT16_MAX);
958	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, _1M-1);
959	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, _1M+1);
960	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, _1G-1);
961	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, _1G+1);
962	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, INT32_MAX);
963	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, UINT32_MAX);
964	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, INT64_MAX);
965	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, UINT64_MAX);
966	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicReadU64, UINT64_C(0x450872549687134));
967
968	int64_t volatile pi64 = (int64_t volatile )pu64;
969	TEST_READ(pi64, uint64_t, "%d", ASMAtomicReadS64, INT64_MAX);
970	TEST_READ(pi64, uint64_t, "%d", ASMAtomicReadS64, INT64_MIN);
971	TEST_READ(pi64, uint64_t, "%d", ASMAtomicReadS64, 42);
972	TEST_READ(pi64, uint64_t, "%d", ASMAtomicReadS64, -21);
973
974	#if ARCH_BITS == 64
975	size_t volatile pcb = (size_t volatile )pu64;
976	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, 0);
977	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, ~(size_t)2);
978	TEST_READ(pcb, size_t, "%#llz", ASMAtomicReadZ, ~(size_t)0 / 4);
979
980	void * volatile ppv = (void volatile *)pu64;
981	TEST_READ(ppv, void *, "%p", ASMAtomicReadPtr, NULL);
982	TEST_READ(ppv, void , "%p", ASMAtomicReadPtr, (void )~(uintptr_t)42);
983
984	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
985	RTSEMEVENT hEvt = ASMAtomicReadPtrT(phEvt, RTSEMEVENT);
986	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
987
988	ASMAtomicReadHandle(phEvt, &hEvt);
989	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
990	#endif
991	}
992
993
994	DECLINLINE(void) tstASMAtomicUoReadU64Worker(uint64_t volatile *pu64)
995	{
996	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, 0);
997	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, 19983);
998	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, INT16_MAX);
999	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, UINT16_MAX);
1000	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, _1M-1);
1001	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, _1M+1);
1002	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, _1G-1);
1003	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, _1G+1);
1004	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, INT32_MAX);
1005	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, UINT32_MAX);
1006	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, INT64_MAX);
1007	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, UINT64_MAX);
1008	TEST_READ(pu64, uint64_t, "%#llx", ASMAtomicUoReadU64, UINT64_C(0x450872549687134));
1009
1010	int64_t volatile pi64 = (int64_t volatile )pu64;
1011	TEST_READ(pi64, uint64_t, "%d", ASMAtomicUoReadS64, INT64_MAX);
1012	TEST_READ(pi64, uint64_t, "%d", ASMAtomicUoReadS64, INT64_MIN);
1013	TEST_READ(pi64, uint64_t, "%d", ASMAtomicUoReadS64, 42);
1014	TEST_READ(pi64, uint64_t, "%d", ASMAtomicUoReadS64, -21);
1015
1016	#if ARCH_BITS == 64
1017	size_t volatile pcb = (size_t volatile )pu64;
1018	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, 0);
1019	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, ~(size_t)2);
1020	TEST_READ(pcb, size_t, "%#llz", ASMAtomicUoReadZ, ~(size_t)0 / 4);
1021
1022	void * volatile ppv = (void volatile *)pu64;
1023	TEST_READ(ppv, void *, "%p", ASMAtomicUoReadPtr, NULL);
1024	TEST_READ(ppv, void , "%p", ASMAtomicUoReadPtr, (void )~(uintptr_t)42);
1025
1026	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
1027	RTSEMEVENT hEvt = ASMAtomicUoReadPtrT(phEvt, RTSEMEVENT);
1028	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
1029
1030	ASMAtomicUoReadHandle(phEvt, &hEvt);
1031	CHECKVAL(hEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
1032	#endif
1033	}
1034
1035	#ifdef RTASM_HAVE_READ_U128
1036	# define TEST_READ_128_EX(a_pVar, a_szFunction, a_CallExpr, a_u64ValHi, a_u64ValLo) do { \
1037	a_pVar->s.Hi = a_u64ValHi; \
1038	a_pVar->s.Lo = a_u64ValLo; \
1039	RTUINT128U uRet; \
1040	a_CallExpr; \
1041	if (uRet.s.Lo != a_u64ValLo \|\| uRet.s.Hi != a_u64ValHi) \
1042	RTTestFailed(g_hTest, "%s, %d: " a_szFunction ": expected %#RX64'%016RX64 got %#RX64'%016RX64\n", \
1043	__FUNCTION__, __LINE__, a_u64ValHi, a_u64ValLo, uRet.s.Hi, uRet.s.Lo); \
1044	CHECKVAL128(a_pVar, a_u64ValHi, a_u64ValLo); \
1045	} while (0)
1046
1047	# define TEST_READ_128U(a_pVar, a_Function, a_u64ValHi, a_u64ValLo) \
1048	TEST_READ_128_EX(a_pVar, #a_Function, uRet = a_Function(a_pVar), a_u64ValHi, a_u64ValLo)
1049	# define TEST_READ_128(a_pVar, a_Function, a_u64ValHi, a_u64ValLo) \
1050	TEST_READ_128_EX(a_pVar, #a_Function, uRet.u = a_Function(&a_pVar->u), a_u64ValHi, a_u64ValLo)
1051
1052	# define TEST_ATOMIC_READ_U128_TMPL(a_TestMacro, a_fn) \
1053	DECLINLINE(void) tst ## a_fn ## Worker(RTUINT128U volatile *pu128) \
1054	{ \
1055	a_TestMacro(pu128, a_fn, 0, 0); \
1056	a_TestMacro(pu128, a_fn, 19983, 20245); \
1057	a_TestMacro(pu128, a_fn, UINT16_MAX, INT16_MAX); \
1058	a_TestMacro(pu128, a_fn, INT16_MAX, UINT16_MAX); \
1059	a_TestMacro(pu128, a_fn, UINT32_MAX, INT32_MAX); \
1060	a_TestMacro(pu128, a_fn, INT32_MAX, UINT32_MAX); \
1061	a_TestMacro(pu128, a_fn, UINT64_MAX, INT64_MAX); \
1062	a_TestMacro(pu128, a_fn, INT64_MAX, UINT64_MAX); \
1063	a_TestMacro(pu128, a_fn, UINT64_C(0xb5a23edcc258ad0a), UINT64_C(0xaf88507eceb58580)); \
1064	a_TestMacro(pu128, a_fn, UINT64_C(0x5dc7d02e4e474fdb), UINT64_C(0x132b375f2b60f4b6)); \
1065	}
1066
1067	TEST_ATOMIC_READ_U128_TMPL(TEST_READ_128, ASMAtomicReadU128)
1068	TEST_ATOMIC_READ_U128_TMPL(TEST_READ_128, ASMAtomicUoReadU128)
1069
1070	TEST_ATOMIC_READ_U128_TMPL(TEST_READ_128U, ASMAtomicReadU128U)
1071	TEST_ATOMIC_READ_U128_TMPL(TEST_READ_128U, ASMAtomicUoReadU128U)
1072
1073	#endif
1074
1075
1076	static void tstASMAtomicRead(void)
1077	{
1078	DO_SIMPLE_TEST(ASMAtomicReadU8, uint8_t);
1079	DO_SIMPLE_TEST(ASMAtomicUoReadU8, uint8_t);
1080
1081	DO_SIMPLE_TEST(ASMAtomicReadU16, uint16_t);
1082	DO_SIMPLE_TEST(ASMAtomicUoReadU16, uint16_t);
1083
1084	DO_SIMPLE_TEST(ASMAtomicReadU32, uint32_t);
1085	DO_SIMPLE_TEST(ASMAtomicUoReadU32, uint32_t);
1086
1087	DO_SIMPLE_TEST(ASMAtomicReadU64, uint64_t);
1088	DO_SIMPLE_TEST(ASMAtomicUoReadU64, uint64_t);
1089
1090	#ifdef RTASM_HAVE_READ_U128
1091	DO_SIMPLE_TEST_NO_STACK(ASMAtomicReadU128, RTUINT128U);
1092	DO_SIMPLE_TEST_NO_STACK(ASMAtomicReadU128U, RTUINT128U);
1093
1094	DO_SIMPLE_TEST_NO_STACK(ASMAtomicUoReadU128, RTUINT128U);
1095	DO_SIMPLE_TEST_NO_STACK(ASMAtomicUoReadU128U, RTUINT128U);
1096	#endif
1097	}
1098
1099
1100	#define TEST_WRITE(a_pVar, a_Type, a_Fmt, a_Function, a_Val) \
1101	do { a_Function(a_pVar, a_Val); CHECKVAL(*a_pVar, a_Val, a_Fmt); } while (0)
1102
1103	DECLINLINE(void) tstASMAtomicWriteU8Worker(uint8_t volatile *pu8)
1104	{
1105	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 0);
1106	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 1);
1107	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 2);
1108	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 16);
1109	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 32);
1110	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 32);
1111	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 127);
1112	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 128);
1113	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 169);
1114	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 239);
1115	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 254);
1116	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicWriteU8, 255);
1117
1118	volatile int8_t pi8 = (volatile int8_t )pu8;
1119	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicWriteS8, INT8_MIN);
1120	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicWriteS8, INT8_MAX);
1121	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicWriteS8, 42);
1122	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicWriteS8, -41);
1123
1124	volatile bool pf = (volatile bool )pu8;
1125	TEST_WRITE(pf, bool, "%d", ASMAtomicWriteBool, true);
1126	TEST_WRITE(pf, bool, "%d", ASMAtomicWriteBool, false);
1127	}
1128
1129
1130	DECLINLINE(void) tstASMAtomicUoWriteU8Worker(uint8_t volatile *pu8)
1131	{
1132	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 0);
1133	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 1);
1134	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 2);
1135	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 16);
1136	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 32);
1137	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 32);
1138	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 127);
1139	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 128);
1140	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 169);
1141	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 239);
1142	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 254);
1143	TEST_WRITE(pu8, uint8_t, "%#x", ASMAtomicUoWriteU8, 255);
1144
1145	volatile int8_t pi8 = (volatile int8_t )pu8;
1146	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicUoWriteS8, INT8_MIN);
1147	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicUoWriteS8, INT8_MAX);
1148	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicUoWriteS8, 42);
1149	TEST_WRITE(pi8, int8_t, "%d", ASMAtomicUoWriteS8, -41);
1150
1151	volatile bool pf = (volatile bool )pu8;
1152	TEST_WRITE(pf, bool, "%d", ASMAtomicUoWriteBool, true);
1153	TEST_WRITE(pf, bool, "%d", ASMAtomicUoWriteBool, false);
1154	}
1155
1156
1157	DECLINLINE(void) tstASMAtomicWriteU16Worker(uint16_t volatile *pu16)
1158	{
1159	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicWriteU16, 0);
1160	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicWriteU16, 19983);
1161	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicWriteU16, INT16_MAX);
1162	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicWriteU16, UINT16_MAX);
1163
1164	volatile int16_t pi16 = (volatile int16_t )pu16;
1165	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicWriteS16, INT16_MIN);
1166	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicWriteS16, INT16_MAX);
1167	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicWriteS16, 42);
1168	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicWriteS16, -41);
1169	}
1170
1171
1172	DECLINLINE(void) tstASMAtomicUoWriteU16Worker(uint16_t volatile *pu16)
1173	{
1174	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicUoWriteU16, 0);
1175	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicUoWriteU16, 19983);
1176	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicUoWriteU16, INT16_MAX);
1177	TEST_WRITE(pu16, uint16_t, "%#x", ASMAtomicUoWriteU16, UINT16_MAX);
1178
1179	volatile int16_t pi16 = (volatile int16_t )pu16;
1180	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicUoWriteS16, INT16_MIN);
1181	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicUoWriteS16, INT16_MAX);
1182	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicUoWriteS16, 42);
1183	TEST_WRITE(pi16, int16_t, "%d", ASMAtomicUoWriteS16, -41);
1184	}
1185
1186
1187	DECLINLINE(void) tstASMAtomicWriteU32Worker(uint32_t volatile *pu32)
1188	{
1189	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, 0);
1190	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, 19983);
1191	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, INT16_MAX);
1192	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, UINT16_MAX);
1193	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, _1M-1);
1194	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, _1M+1);
1195	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, _1G-1);
1196	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, _1G+1);
1197	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, INT32_MAX);
1198	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicWriteU32, UINT32_MAX);
1199
1200	volatile int32_t pi32 = (volatile int32_t )pu32;
1201	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicWriteS32, INT32_MIN);
1202	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicWriteS32, INT32_MAX);
1203	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicWriteS32, 42);
1204	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicWriteS32, -41);
1205
1206	#if ARCH_BITS == 32
1207	size_t volatile pcb = (size_t volatile )pu32;
1208	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicWriteZ, ~(size_t)42);
1209	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicWriteZ, 42);
1210
1211	void * volatile ppv = (void volatile *)pu32;
1212	TEST_WRITE(ppv, void *, "%#zx", ASMAtomicWritePtrVoid, NULL);
1213	TEST_WRITE(ppv, void , "%#zx", ASMAtomicWritePtrVoid, (void )~(uintptr_t)12938754);
1214
1215	ASMAtomicWriteNullPtr(ppv); CHECKVAL(*ppv, NULL, "%p");
1216	ASMAtomicWritePtr(ppv, (void )~(intptr_t)2322434); CHECKVAL(ppv, (void *)~(intptr_t)2322434, "%p");
1217
1218	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
1219	ASMAtomicWriteHandle(phEvt, (RTSEMEVENT)(uintptr_t)99753456); CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)99753456, "%p");
1220	#endif
1221	}
1222
1223
1224	DECLINLINE(void) tstASMAtomicUoWriteU32Worker(uint32_t volatile *pu32)
1225	{
1226	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, 0);
1227	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, 19983);
1228	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, INT16_MAX);
1229	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, UINT16_MAX);
1230	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, _1M-1);
1231	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, _1M+1);
1232	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, _1G-1);
1233	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, _1G+1);
1234	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, INT32_MAX);
1235	TEST_WRITE(pu32, uint32_t, "%#x", ASMAtomicUoWriteU32, UINT32_MAX);
1236
1237	volatile int32_t pi32 = (volatile int32_t )pu32;
1238	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicUoWriteS32, INT32_MIN);
1239	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicUoWriteS32, INT32_MAX);
1240	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicUoWriteS32, 42);
1241	TEST_WRITE(pi32, int32_t, "%d", ASMAtomicUoWriteS32, -41);
1242
1243	#if ARCH_BITS == 32
1244	size_t volatile pcb = (size_t volatile )pu32;
1245	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicUoWriteZ, ~(size_t)42);
1246	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicUoWriteZ, 42);
1247
1248	void * volatile ppv = (void volatile *)pu32;
1249	TEST_WRITE(ppv, void *, "%#zx", ASMAtomicUoWritePtrVoid, NULL);
1250	TEST_WRITE(ppv, void , "%#zx", ASMAtomicUoWritePtrVoid, (void )~(uintptr_t)12938754);
1251
1252	ASMAtomicUoWriteNullPtr(ppv); CHECKVAL(*ppv, NULL, "%p");
1253	ASMAtomicUoWritePtr(ppv, (void )~(intptr_t)2322434); CHECKVAL(ppv, (void *)~(intptr_t)2322434, "%p");
1254
1255	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
1256	ASMAtomicUoWriteHandle(phEvt, (RTSEMEVENT)(uintptr_t)99753456); CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)99753456, "%p");
1257	#endif
1258	}
1259
1260
1261	DECLINLINE(void) tstASMAtomicWriteU64Worker(uint64_t volatile *pu64)
1262	{
1263	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, 0);
1264	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, 19983);
1265	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, INT16_MAX);
1266	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, UINT16_MAX);
1267	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, _1M-1);
1268	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, _1M+1);
1269	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, _1G-1);
1270	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, _1G+1);
1271	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, INT32_MAX);
1272	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, UINT32_MAX);
1273	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, INT64_MAX);
1274	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, UINT64_MAX);
1275	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicWriteU64, UINT64_C(0x450872549687134));
1276
1277	volatile int64_t pi64 = (volatile int64_t )pu64;
1278	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicWriteS64, INT64_MIN);
1279	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicWriteS64, INT64_MAX);
1280	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicWriteS64, 42);
1281
1282	#if ARCH_BITS == 64
1283	size_t volatile pcb = (size_t volatile )pu64;
1284	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicWriteZ, ~(size_t)42);
1285	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicWriteZ, 42);
1286
1287	void * volatile ppv = (void volatile *)pu64;
1288	TEST_WRITE(ppv, void *, "%#zx", ASMAtomicWritePtrVoid, NULL);
1289	TEST_WRITE(ppv, void , "%#zx", ASMAtomicWritePtrVoid, (void )~(uintptr_t)12938754);
1290
1291	ASMAtomicWriteNullPtr(ppv); CHECKVAL(*ppv, NULL, "%p");
1292	ASMAtomicWritePtr(ppv, (void )~(intptr_t)2322434); CHECKVAL(ppv, (void *)~(intptr_t)2322434, "%p");
1293
1294	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
1295	ASMAtomicWriteHandle(phEvt, (RTSEMEVENT)(uintptr_t)99753456); CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)99753456, "%p");
1296	#endif
1297	}
1298
1299
1300	DECLINLINE(void) tstASMAtomicUoWriteU64Worker(uint64_t volatile *pu64)
1301	{
1302	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, 0);
1303	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, 19983);
1304	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, INT16_MAX);
1305	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, UINT16_MAX);
1306	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, _1M-1);
1307	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, _1M+1);
1308	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, _1G-1);
1309	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, _1G+1);
1310	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, INT32_MAX);
1311	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, UINT32_MAX);
1312	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, INT64_MAX);
1313	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, UINT64_MAX);
1314	TEST_WRITE(pu64, uint64_t, "%#llx", ASMAtomicUoWriteU64, UINT64_C(0x450872549687134));
1315
1316	volatile int64_t pi64 = (volatile int64_t )pu64;
1317	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicUoWriteS64, INT64_MIN);
1318	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicUoWriteS64, INT64_MAX);
1319	TEST_WRITE(pi64, int64_t, "%d", ASMAtomicUoWriteS64, 42);
1320
1321	#if ARCH_BITS == 64
1322	size_t volatile pcb = (size_t volatile )pu64;
1323	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicUoWriteZ, ~(size_t)42);
1324	TEST_WRITE(pcb, size_t, "%#zx", ASMAtomicUoWriteZ, 42);
1325
1326	void * volatile ppv = (void volatile *)pu64;
1327	TEST_WRITE(ppv, void *, "%#zx", ASMAtomicUoWritePtrVoid, NULL);
1328	TEST_WRITE(ppv, void , "%#zx", ASMAtomicUoWritePtrVoid, (void )~(uintptr_t)12938754);
1329
1330	ASMAtomicUoWriteNullPtr(ppv); CHECKVAL(*ppv, NULL, "%p");
1331	ASMAtomicUoWritePtr(ppv, (void )~(intptr_t)2322434); CHECKVAL(ppv, (void *)~(intptr_t)2322434, "%p");
1332
1333	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
1334	ASMAtomicUoWriteHandle(phEvt, (RTSEMEVENT)(uintptr_t)99753456); CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)99753456, "%p");
1335	#endif
1336	}
1337
1338	#ifdef RTASM_HAVE_WRITE_U128
1339
1340	# define TEST_WRITE_128(a_pVar, a_Function, a_HiVal, a_LoVal) do { \
1341	RTUINT128U uValTmp; \
1342	a_Function(&a_pVar->u, (uValTmp = RTUINT128_INIT(a_HiVal, a_LoVal)).u); \
1343	CHECKVAL128(a_pVar, a_HiVal, a_LoVal); \
1344	} while (0)
1345
1346	# define TEST_WRITE_128U(a_pVar, a_Function, a_HiVal, a_LoVal) do { \
1347	RTUINT128U uValTmp; \
1348	a_Function(a_pVar, uValTmp = RTUINT128_INIT(a_HiVal, a_LoVal)); \
1349	CHECKVAL128(a_pVar, a_HiVal, a_LoVal); \
1350	} while (0)
1351
1352	# define TEST_WRITE_128v2(a_pVar, a_Function, a_HiVal, a_LoVal) \
1353	do { a_Function(&a_pVar->u, a_HiVal, a_LoVal); CHECKVAL128(a_pVar, a_HiVal, a_LoVal); } while (0)
1354
1355	#define TEST_ATOMIC_WRITE_U128_TMPL(a_TestMacro, a_fn) \
1356	DECLINLINE(void) tst ## a_fn ## Worker(RTUINT128U volatile *pu128) \
1357	{ \
1358	a_TestMacro(pu128, a_fn, 0, 0); \
1359	a_TestMacro(pu128, a_fn, 19983, 20245); \
1360	a_TestMacro(pu128, a_fn, UINT16_MAX, INT16_MAX); \
1361	a_TestMacro(pu128, a_fn, INT16_MAX, UINT16_MAX); \
1362	a_TestMacro(pu128, a_fn, UINT32_MAX, INT32_MAX); \
1363	a_TestMacro(pu128, a_fn, INT32_MAX, UINT32_MAX); \
1364	a_TestMacro(pu128, a_fn, UINT64_MAX, INT64_MAX); \
1365	a_TestMacro(pu128, a_fn, INT64_MAX, UINT64_MAX); \
1366	a_TestMacro(pu128, a_fn, UINT64_C(0xb5a23edcc258ad0a), UINT64_C(0xaf88507eceb58580)); \
1367	a_TestMacro(pu128, a_fn, UINT64_C(0x5dc7d02e4e474fdb), UINT64_C(0x132b375f2b60f4b6)); \
1368	}
1369
1370	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128, ASMAtomicWriteU128)
1371	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128, ASMAtomicUoWriteU128)
1372
1373	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128U, ASMAtomicWriteU128U)
1374	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128U, ASMAtomicUoWriteU128U)
1375
1376	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128v2, ASMAtomicWriteU128v2)
1377	TEST_ATOMIC_WRITE_U128_TMPL(TEST_WRITE_128v2, ASMAtomicUoWriteU128v2)
1378
1379	#endif /* RTASM_HAVE_WRITE_U128 */
1380
1381	static void tstASMAtomicWrite(void)
1382	{
1383	DO_SIMPLE_TEST(ASMAtomicWriteU8, uint8_t);
1384	DO_SIMPLE_TEST(ASMAtomicUoWriteU8, uint8_t);
1385
1386	DO_SIMPLE_TEST(ASMAtomicWriteU16, uint16_t);
1387	DO_SIMPLE_TEST(ASMAtomicUoWriteU16, uint16_t);
1388
1389	DO_SIMPLE_TEST(ASMAtomicWriteU32, uint32_t);
1390	DO_SIMPLE_TEST(ASMAtomicUoWriteU32, uint32_t);
1391
1392	DO_SIMPLE_TEST(ASMAtomicWriteU64, uint64_t);
1393	DO_SIMPLE_TEST(ASMAtomicUoWriteU64, uint64_t);
1394
1395	#ifdef RTASM_HAVE_WRITE_U128
1396	/* Not doing stack here, as it won't be necessarily correctly aligned for cmpxchg16b on MSC. */
1397	DO_SIMPLE_TEST_NO_STACK(ASMAtomicWriteU128, RTUINT128U);
1398	DO_SIMPLE_TEST_NO_STACK(ASMAtomicWriteU128U, RTUINT128U);
1399	DO_SIMPLE_TEST_NO_STACK(ASMAtomicWriteU128v2, RTUINT128U);
1400
1401	DO_SIMPLE_TEST_NO_STACK(ASMAtomicUoWriteU128, RTUINT128U);
1402	DO_SIMPLE_TEST_NO_STACK(ASMAtomicUoWriteU128U, RTUINT128U);
1403	DO_SIMPLE_TEST_NO_STACK(ASMAtomicUoWriteU128v2, RTUINT128U);
1404	#endif
1405	}
1406
1407
1408	DECLINLINE(void) tstASMAtomicXchgU8Worker(uint8_t volatile *pu8)
1409	{
1410	*pu8 = 0;
1411	CHECK_OP_AND_VAL(uint8_t, "%#x", pu8, ASMAtomicXchgU8(pu8, 1), 0, 1);
1412	CHECK_OP_AND_VAL(uint8_t, "%#x", pu8, ASMAtomicXchgU8(pu8, UINT8_C(0xff)), 1, UINT8_C(0xff));
1413	CHECK_OP_AND_VAL(uint8_t, "%#x", pu8, ASMAtomicXchgU8(pu8, UINT8_C(0x87)), UINT8_C(0xff), UINT8_C(0x87));
1414	CHECK_OP_AND_VAL(uint8_t, "%#x", pu8, ASMAtomicXchgU8(pu8, UINT8_C(0xfe)), UINT8_C(0x87), UINT8_C(0xfe));
1415
1416	int8_t volatile pi8 = (int8_t volatile )pu8;
1417	CHECK_OP_AND_VAL(int8_t, "%d", pi8, ASMAtomicXchgS8(pi8, INT8_C(-4)), INT8_C(-2), INT8_C(-4));
1418	CHECK_OP_AND_VAL(int8_t, "%d", pi8, ASMAtomicXchgS8(pi8, INT8_C(4)), INT8_C(-4), INT8_C(4));
1419	CHECK_OP_AND_VAL(int8_t, "%d", pi8, ASMAtomicXchgS8(pi8, INT8_MAX), INT8_C(4), INT8_MAX);
1420	CHECK_OP_AND_VAL(int8_t, "%d", pi8, ASMAtomicXchgS8(pi8, INT8_MIN), INT8_MAX, INT8_MIN);
1421	CHECK_OP_AND_VAL(int8_t, "%d", pi8, ASMAtomicXchgS8(pi8, 1), INT8_MIN, 1);
1422
1423	bool volatile pf = (bool volatile )pu8;
1424	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicXchgBool(pf, false), true, false);
1425	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicXchgBool(pf, false), false, false);
1426	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicXchgBool(pf, true), false, true);
1427	}
1428
1429
1430	DECLINLINE(void) tstASMAtomicXchgU16Worker(uint16_t volatile *pu16)
1431	{
1432	*pu16 = 0;
1433	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, 1), 0, 1);
1434	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, 0), 1, 0);
1435	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, UINT16_MAX), 0, UINT16_MAX);
1436	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, UINT16_C(0x7fff)), UINT16_MAX, UINT16_C(0x7fff));
1437	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, UINT16_C(0x8765)), UINT16_C(0x7fff), UINT16_C(0x8765));
1438	CHECK_OP_AND_VAL(uint16_t, "%#x", pu16, ASMAtomicXchgU16(pu16, UINT16_C(0xfffe)), UINT16_C(0x8765), UINT16_C(0xfffe));
1439
1440	int16_t volatile pi16 = (int16_t volatile )pu16;
1441	CHECK_OP_AND_VAL(int16_t, "%d", pi16, ASMAtomicXchgS16(pi16, INT16_MIN), INT16_C(-2), INT16_MIN);
1442	CHECK_OP_AND_VAL(int16_t, "%d", pi16, ASMAtomicXchgS16(pi16, INT16_MAX), INT16_MIN, INT16_MAX);
1443	CHECK_OP_AND_VAL(int16_t, "%d", pi16, ASMAtomicXchgS16(pi16, -8), INT16_MAX, -8);
1444	CHECK_OP_AND_VAL(int16_t, "%d", pi16, ASMAtomicXchgS16(pi16, 8), -8, 8);
1445	}
1446
1447
1448	DECLINLINE(void) tstASMAtomicXchgU32Worker(uint32_t volatile *pu32)
1449	{
1450	*pu32 = 0;
1451	CHECK_OP_AND_VAL(uint32_t, "%#x", pu32, ASMAtomicXchgU32(pu32, 1), 0, 1);
1452	CHECK_OP_AND_VAL(uint32_t, "%#x", pu32, ASMAtomicXchgU32(pu32, 0), 1, 0);
1453	CHECK_OP_AND_VAL(uint32_t, "%#x", pu32, ASMAtomicXchgU32(pu32, UINT32_MAX), 0, UINT32_MAX);
1454	CHECK_OP_AND_VAL(uint32_t, "%#x", pu32, ASMAtomicXchgU32(pu32, UINT32_C(0x87654321)), UINT32_MAX, UINT32_C(0x87654321));
1455	CHECK_OP_AND_VAL(uint32_t, "%#x", pu32, ASMAtomicXchgU32(pu32, UINT32_C(0xfffffffe)), UINT32_C(0x87654321), UINT32_C(0xfffffffe));
1456
1457	int32_t volatile pi32 = (int32_t volatile )pu32;
1458	CHECK_OP_AND_VAL(int32_t, "%d", pi32, ASMAtomicXchgS32(pi32, INT32_MIN), INT32_C(-2), INT32_MIN);
1459	CHECK_OP_AND_VAL(int32_t, "%d", pi32, ASMAtomicXchgS32(pi32, INT32_MAX), INT32_MIN, INT32_MAX);
1460	CHECK_OP_AND_VAL(int32_t, "%d", pi32, ASMAtomicXchgS32(pi32, -16), INT32_MAX, -16);
1461	CHECK_OP_AND_VAL(int32_t, "%d", pi32, ASMAtomicXchgS32(pi32, 16), -16, 16);
1462
1463	#if ARCH_BITS == 32
1464	size_t volatile pcb = (size_t volatile )pu32;
1465	CHECK_OP_AND_VAL(size_t, "%#zx", pcb, ASMAtomicXchgZ(pcb, UINT32_C(0x9481239b)), 0x10, UINT32_C(0x9481239b));
1466	CHECK_OP_AND_VAL(size_t, "%#zx", pcb, ASMAtomicXchgZ(pcb, UINT32_C(0xcdef1234)), UINT32_C(0x9481239b), UINT32_C(0xcdef1234));
1467	#endif
1468
1469	#if R0_ARCH_BITS == 32
1470	RTR0PTR volatile pR0Ptr = (RTR0PTR volatile )pu32;
1471	CHECK_OP_AND_VAL(size_t, "%#llx", pcb, ASMAtomicXchgR0Ptr(pR0Ptr, UINT32_C(0x80341237)), UINT32_C(0xcdef1234), UINT32_C(0x80341237));
1472	#endif
1473	}
1474
1475
1476	DECLINLINE(void) tstASMAtomicXchgU64Worker(uint64_t volatile *pu64)
1477	{
1478	*pu64 = 0;
1479	CHECK_OP_AND_VAL(uint64_t, "%#llx", pu64, ASMAtomicXchgU64(pu64, 1), 0, 1);
1480	CHECK_OP_AND_VAL(uint64_t, "%#llx", pu64, ASMAtomicXchgU64(pu64, 0), 1, 0);
1481	CHECK_OP_AND_VAL(uint64_t, "%#llx", pu64, ASMAtomicXchgU64(pu64, UINT64_MAX), 0, UINT64_MAX);
1482	CHECK_OP_AND_VAL(uint64_t, "%#llx", pu64, ASMAtomicXchgU64(pu64, UINT64_C(0xfedcba0987654321)), UINT64_MAX, UINT64_C(0xfedcba0987654321));
1483	CHECK_OP_AND_VAL(uint64_t, "%#llx", pu64, ASMAtomicXchgU64(pu64, UINT64_C(0xfffffffffffffffe)), UINT64_C(0xfedcba0987654321), UINT64_C(0xfffffffffffffffe));
1484
1485	int64_t volatile pi64 = (int64_t volatile )pu64;
1486	CHECK_OP_AND_VAL(int64_t, "%lld", pi64, ASMAtomicXchgS64(pi64, INT64_MAX), -2, INT64_MAX);
1487	CHECK_OP_AND_VAL(int64_t, "%lld", pi64, ASMAtomicXchgS64(pi64, INT64_MIN), INT64_MAX, INT64_MIN);
1488	CHECK_OP_AND_VAL(int64_t, "%lld", pi64, ASMAtomicXchgS64(pi64, -32), INT64_MIN, -32);
1489	CHECK_OP_AND_VAL(int64_t, "%lld", pi64, ASMAtomicXchgS64(pi64, 32), -32, 32);
1490
1491	#if ARCH_BITS == 64
1492	size_t volatile pcb = (size_t volatile )pu64;
1493	CHECK_OP_AND_VAL(size_t, "%#zx", pcb, ASMAtomicXchgZ(pcb, UINT64_C(0x94812396759)), 0x20, UINT64_C(0x94812396759));
1494	CHECK_OP_AND_VAL(size_t, "%#zx", pcb, ASMAtomicXchgZ(pcb, UINT64_C(0xcdef1234abdf7896)), UINT64_C(0x94812396759), UINT64_C(0xcdef1234abdf7896));
1495	#endif
1496
1497	#if R0_ARCH_BITS == 64
1498	RTR0PTR volatile pR0Ptr = (RTR0PTR volatile )pu64;
1499	CHECK_OP_AND_VAL(size_t, "%#llx", pcb, ASMAtomicXchgR0Ptr(pR0Ptr, UINT64_C(0xfedc1234567890ab)), UINT64_C(0xcdef1234abdf7896), UINT64_C(0xfedc1234567890ab));
1500	#endif
1501	}
1502
1503
1504	DECLINLINE(void) tstASMAtomicXchgPtrWorker(void * volatile *ppv)
1505	{
1506	*ppv = NULL;
1507	CHECK_OP_AND_VAL(void , "%p", ppv, ASMAtomicXchgPtr(ppv, (void )(~(uintptr_t)0)), NULL, (void *)(~(uintptr_t)0));
1508	CHECK_OP_AND_VAL(void , "%p", ppv, ASMAtomicXchgPtr(ppv, (void )(~(uintptr_t)0x87654321)), (void )(~(uintptr_t)0), (void )(~(uintptr_t)0x87654321));
1509	CHECK_OP_AND_VAL(void , "%p", ppv, ASMAtomicXchgPtr(ppv, NULL), (void )(~(uintptr_t)0x87654321), NULL);
1510
1511	CHECK_OP_AND_VAL(void , "%p", ppv, ASMAtomicXchgR3Ptr(ppv, (void )ppv), NULL, (void *)ppv);
1512
1513	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )ppv;
1514	RTSEMEVENT hRet;
1515	ASMAtomicXchgHandle(phEvt, (RTSEMEVENT)(~(uintptr_t)12345), &hRet);
1516	CHECKVAL(hRet, (RTSEMEVENT)ppv, "%p");
1517	CHECKVAL(*phEvt, (RTSEMEVENT)(~(uintptr_t)12345), "%p");
1518	}
1519
1520
1521	static void tstASMAtomicXchg(void)
1522	{
1523	DO_SIMPLE_TEST(ASMAtomicXchgU8, uint8_t);
1524	DO_SIMPLE_TEST(ASMAtomicXchgU16, uint16_t);
1525	DO_SIMPLE_TEST(ASMAtomicXchgU32, uint32_t);
1526	DO_SIMPLE_TEST(ASMAtomicXchgU64, uint64_t);
1527	DO_SIMPLE_TEST(ASMAtomicXchgPtr, void *);
1528	}
1529
1530
1531	DECLINLINE(void) tstASMAtomicCmpXchgU8Worker(uint8_t volatile *pu8)
1532	{
1533	*pu8 = 0xff;
1534	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu8, ASMAtomicCmpXchgU8(pu8, 0, 0), false, 0xff);
1535	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu8, ASMAtomicCmpXchgU8(pu8, 0, 0xff), true, 0);
1536	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu8, ASMAtomicCmpXchgU8(pu8, 0x97, 0), true, 0x97);
1537	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu8, ASMAtomicCmpXchgU8(pu8, 0x97, 0), false, 0x97);
1538	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu8, ASMAtomicCmpXchgU8(pu8, 0x7f, 0x97), true, 0x7f);
1539
1540	int8_t volatile pi8 = (int8_t volatile )pu8;
1541	CHECK_OP_AND_VAL(bool, "%d", pi8, ASMAtomicCmpXchgS8(pi8, -2, 0x7f), true, -2);
1542	CHECK_OP_AND_VAL(bool, "%d", pi8, ASMAtomicCmpXchgS8(pi8, INT8_MAX, -2), true, INT8_MAX);
1543	CHECK_OP_AND_VAL(bool, "%d", pi8, ASMAtomicCmpXchgS8(pi8, INT8_MAX, INT8_MIN), false, INT8_MAX);
1544	CHECK_OP_AND_VAL(bool, "%d", pi8, ASMAtomicCmpXchgS8(pi8, INT8_MIN, INT8_MAX), true, INT8_MIN);
1545	CHECK_OP_AND_VAL(bool, "%d", pi8, ASMAtomicCmpXchgS8(pi8, 1, INT8_MIN), true, 1);
1546
1547	bool volatile pf = (bool volatile )pu8;
1548	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicCmpXchgBool(pf, true, true), true, true);
1549	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicCmpXchgBool(pf, false, true), true, false);
1550	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicCmpXchgBool(pf, false, true), false, false);
1551	CHECK_OP_AND_VAL(bool, "%d", pf, ASMAtomicCmpXchgBool(pf, false, false), true, false);
1552	}
1553
1554
1555	DECLINLINE(void) tstASMAtomicCmpXchgU32Worker(uint32_t volatile *pu32)
1556	{
1557	*pu32 = UINT32_C(0xffffffff);
1558	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu32, ASMAtomicCmpXchgU32(pu32, 0, 0), false, UINT32_C(0xffffffff));
1559	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu32, ASMAtomicCmpXchgU32(pu32, 0, UINT32_C(0xffffffff)), true, 0);
1560	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu32, ASMAtomicCmpXchgU32(pu32, UINT32_C(0x80088efd), UINT32_C(0x12345678)), false, 0);
1561	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu32, ASMAtomicCmpXchgU32(pu32, UINT32_C(0x80088efd), 0), true, UINT32_C(0x80088efd));
1562	CHECK_OP_AND_VAL_EX(bool, "%d", "%#x", pu32, ASMAtomicCmpXchgU32(pu32, UINT32_C(0xfffffffe), UINT32_C(0x80088efd)), true, UINT32_C(0xfffffffe));
1563
1564	int32_t volatile pi32 = (int32_t volatile )pu32;
1565	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, INT32_MIN, 2), false, -2);
1566	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, INT32_MIN, -2), true, INT32_MIN);
1567	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, -19, -2), false, INT32_MIN);
1568	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, -19, INT32_MIN), true, -19);
1569	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, -19, INT32_MIN), false, -19);
1570	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, 19, -19), true, 19);
1571	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, INT32_MAX, -234), false, 19);
1572	CHECK_OP_AND_VAL_EX(bool, "%d", "%d", pi32, ASMAtomicCmpXchgS32(pi32, INT32_MAX, 19), true, INT32_MAX);
1573
1574	#if ARCH_BITS == 32
1575	*pu32 = 29;
1576	void * volatile ppv = (void volatile *)pu32;
1577	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void )(intptr_t)-29), false, (void )(intptr_t)29);
1578	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void *)(intptr_t)29), true, NULL);
1579	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void *)(intptr_t)29), false, NULL);
1580	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, (void )~(uintptr_t)42, NULL), true, (void )~(uintptr_t)42);
1581
1582	bool fRc;
1583	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
1584	ASMAtomicCmpXchgHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, (RTSEMEVENT)NULL, fRc);
1585	CHECKVAL(fRc, false, "%d");
1586	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
1587
1588	ASMAtomicCmpXchgHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, (RTSEMEVENT)~(uintptr_t)42, fRc);
1589	CHECKVAL(fRc, true, "%d");
1590	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, "%p");
1591	#endif
1592	}
1593
1594
1595	DECLINLINE(void) tstASMAtomicCmpXchgU64Worker(uint64_t volatile *pu64)
1596	{
1597	*pu64 = UINT64_C(0xffffffffffffff);
1598	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, 0, 0), false, UINT64_C(0xffffffffffffff));
1599	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, 0, UINT64_C(0xffffffffffffff)), true, 0);
1600	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 1), false, 0);
1601	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 0), true, UINT64_C(0x80040008008efd));
1602	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 0), false, UINT64_C(0x80040008008efd));
1603	CHECK_OP_AND_VAL_EX(bool, "%d", "%#llx", pu64, ASMAtomicCmpXchgU64(pu64, UINT64_C(0xfffffffffffffffd), UINT64_C(0x80040008008efd)), true, UINT64_C(0xfffffffffffffffd));
1604
1605	int64_t volatile pi64 = (int64_t volatile )pu64;
1606	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, INT64_MAX, 0), false, -3);
1607	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, INT64_MAX, -3), true, INT64_MAX);
1608	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, INT64_MIN, INT64_MIN), false, INT64_MAX);
1609	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, INT64_MIN, INT64_MAX), true, INT64_MIN);
1610	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, -29, -29), false, INT64_MIN);
1611	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, -29, INT64_MIN), true, -29);
1612	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, -29, INT64_MIN), false, -29);
1613	CHECK_OP_AND_VAL_EX(bool, "%d", "%#lld", pi64, ASMAtomicCmpXchgS64(pi64, 29, -29), true, 29);
1614
1615	#if ARCH_BITS == 64
1616	void * volatile ppv = (void volatile *)pu64;
1617	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void )(intptr_t)-29), false, (void )(intptr_t)29);
1618	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void *)(intptr_t)29), true, NULL);
1619	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, NULL, (void *)(intptr_t)29), false, NULL);
1620	CHECK_OP_AND_VAL_EX(bool, "%d", "%p", ppv, ASMAtomicCmpXchgPtrVoid(ppv, (void )~(uintptr_t)42, NULL), true, (void )~(uintptr_t)42);
1621
1622	bool fRc;
1623	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
1624	ASMAtomicCmpXchgHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, (RTSEMEVENT)NULL, fRc);
1625	CHECKVAL(fRc, false, "%d");
1626	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)42, "%p");
1627
1628	ASMAtomicCmpXchgHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, (RTSEMEVENT)~(uintptr_t)42, fRc);
1629	CHECKVAL(fRc, true, "%d");
1630	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)0x12356389, "%p");
1631	#endif
1632	}
1633
1634
1635	#ifdef RTASM_HAVE_CMP_WRITE_U128
1636	DECLINLINE(void) tstASMAtomicCmpWriteU128Worker(RTUINT128U volatile *pu128)
1637	{
1638	pu128->s.Lo = UINT64_C(0xffffffffffffff);
1639	pu128->s.Hi = UINT64_C(0xffffffffffffff);
1640
1641	RTUINT128U u128A, u128B;
1642	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1643	u128A = RTUINT128_INIT_C(0, 0),
1644	u128B = RTUINT128_INIT_C(0, 0)),
1645	false, 0xffffffffffffff, 0xffffffffffffff);
1646	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1647	u128A = RTUINT128_INIT_C(0, 0),
1648	u128B = RTUINT128_INIT_C(0xffffffffffffff, 0xffffffffffffff)),
1649	true, 0, 0);
1650
1651	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1652	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1653	u128B = RTUINT128_INIT_C(0, 1)),
1654	false, 0, 0);
1655	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1656	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1657	u128B = RTUINT128_INIT_C(1, 0)),
1658	false, 0, 0);
1659	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1660	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1661	u128B = RTUINT128_INIT_C(0, 0)),
1662	true, 0x80040008008efd, 0x40080004004def);
1663
1664	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1665	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1666	u128B = RTUINT128_INIT_C(0x80040008008efd, 0)),
1667	false, 0x80040008008efd, 0x40080004004def);
1668	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1669	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1670	u128B = RTUINT128_INIT_C(0, 0x40080004004def)),
1671	false, 0x80040008008efd, 0x40080004004def);
1672	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128U(pu128,
1673	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1674	u128B = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def)),
1675	true, 0xfff40ff8f08ef3, 0x4ee8ee04cc4de4);
1676
1677	/* Make sure the v2 version works too (arm) */
1678	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128v2(&pu128->u,
1679	UINT64_C(0x95487930069587), UINT64_C(0x89958490385964),
1680	UINT64_C(0xfff40ff8f08ef3), UINT64_C(0x4ee8ee04cc4de4)),
1681	true, 0x95487930069587, 0x89958490385964);
1682	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpWriteU128v2(&pu128->u,
1683	UINT64_C(0x99969404869434), UINT64_C(0x11049309994567),
1684	UINT64_C(0x33f40ff8f08eff), UINT64_C(0x99e8ee04cc4dee)),
1685	false, 0x95487930069587, 0x89958490385964);
1686	}
1687	#endif /* RTASM_HAVE_CMP_WRITE_U128 */
1688
1689
1690	static void tstASMAtomicCmpXchg(void)
1691	{
1692	DO_SIMPLE_TEST(ASMAtomicCmpXchgU8, uint8_t);
1693	DO_SIMPLE_TEST(ASMAtomicCmpXchgU32, uint32_t);
1694	DO_SIMPLE_TEST(ASMAtomicCmpXchgU64, uint64_t);
1695	#ifdef RTASM_HAVE_CMP_WRITE_U128
1696	# ifdef RT_ARCH_AMD64
1697	if (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16)
1698	# endif
1699	{
1700	RTTestISub("ASMAtomicCmpWriteU128U");
1701	DO_SIMPLE_TEST_NO_SUB_NO_STACK(tstASMAtomicCmpWriteU128Worker, RTUINT128U);
1702	}
1703	#endif
1704	}
1705
1706
1707	DECLINLINE(void) tstASMAtomicCmpXchgExU8Worker(uint8_t volatile *pu8)
1708	{
1709	*pu8 = UINT8_C(0xff);
1710	uint8_t u8Old = UINT8_C(0x11);
1711	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, 0, 0, &u8Old), false, UINT8_C(0xff), UINT8_C(0xff));
1712	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, 0, UINT8_C(0xff), &u8Old), true, 0, UINT8_C(0xff));
1713	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, 0, UINT8_C(0xff), &u8Old), false, 0, UINT8_C(0x00));
1714	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, UINT8_C(0xfd), 0, &u8Old), true, UINT8_C(0xfd), 0);
1715	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, UINT8_C(0xfd), 0, &u8Old), false, UINT8_C(0xfd), UINT8_C(0xfd));
1716	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu8, u8Old, ASMAtomicCmpXchgExU8(pu8, UINT8_C(0xe0), UINT8_C(0xfd), &u8Old), true, UINT8_C(0xe0), UINT8_C(0xfd));
1717
1718	int8_t volatile pi8 = (int8_t volatile )pu8;
1719	int8_t i8Old = 0;
1720	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, 32, 32, &i8Old), false, -32, -32);
1721	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, 32, -32, &i8Old), true, 32, -32);
1722	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, INT8_MIN, 32, &i8Old), true, INT8_MIN, 32);
1723	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, INT8_MIN, 32, &i8Old), false, INT8_MIN, INT8_MIN);
1724	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, INT8_MAX, INT8_MAX, &i8Old), false, INT8_MIN, INT8_MIN);
1725	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, INT8_MAX, INT8_MIN, &i8Old), true, INT8_MAX, INT8_MIN);
1726	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi8, i8Old, ASMAtomicCmpXchgExS8(pi8, 42, INT8_MAX, &i8Old), true, 42, INT8_MAX);
1727	}
1728
1729
1730	DECLINLINE(void) tstASMAtomicCmpXchgExU16Worker(uint16_t volatile *pu16)
1731	{
1732	*pu16 = UINT16_C(0xffff);
1733	uint16_t u16Old = UINT16_C(0x5111);
1734	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, 0, 0, &u16Old), false, UINT16_C(0xffff), UINT16_C(0xffff));
1735	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, 0, UINT16_C(0xffff), &u16Old), true, 0, UINT16_C(0xffff));
1736	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, 0, UINT16_C(0xffff), &u16Old), false, 0, UINT16_C(0x0000));
1737	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, UINT16_C(0x8efd), 0, &u16Old), true, UINT16_C(0x8efd), 0);
1738	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, UINT16_C(0x8efd), 0, &u16Old), false, UINT16_C(0x8efd), UINT16_C(0x8efd));
1739	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu16, u16Old, ASMAtomicCmpXchgExU16(pu16, UINT16_C(0xffe0), UINT16_C(0x8efd), &u16Old), true, UINT16_C(0xffe0), UINT16_C(0x8efd));
1740
1741	int16_t volatile pi16 = (int16_t volatile )pu16;
1742	int16_t i16Old = 0;
1743	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, 32, 32, &i16Old), false, -32, -32);
1744	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, 32, -32, &i16Old), true, 32, -32);
1745	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, INT16_MIN, 32, &i16Old), true, INT16_MIN, 32);
1746	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, INT16_MIN, 32, &i16Old), false, INT16_MIN, INT16_MIN);
1747	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, INT16_MAX, INT16_MAX, &i16Old), false, INT16_MIN, INT16_MIN);
1748	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, INT16_MAX, INT16_MIN, &i16Old), true, INT16_MAX, INT16_MIN);
1749	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi16, i16Old, ASMAtomicCmpXchgExS16(pi16, 42, INT16_MAX, &i16Old), true, 42, INT16_MAX);
1750	}
1751
1752
1753	DECLINLINE(void) tstASMAtomicCmpXchgExU32Worker(uint32_t volatile *pu32)
1754	{
1755	*pu32 = UINT32_C(0xffffffff);
1756	uint32_t u32Old = UINT32_C(0x80005111);
1757	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, 0, 0, &u32Old), false, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1758	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0xffffffff), &u32Old), true, 0, UINT32_C(0xffffffff));
1759	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0xffffffff), &u32Old), false, 0, UINT32_C(0x00000000));
1760	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x80088efd), 0, &u32Old), true, UINT32_C(0x80088efd), 0);
1761	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x80088efd), 0, &u32Old), false, UINT32_C(0x80088efd), UINT32_C(0x80088efd));
1762	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#x", pu32, u32Old, ASMAtomicCmpXchgExU32(pu32, UINT32_C(0xffffffe0), UINT32_C(0x80088efd), &u32Old), true, UINT32_C(0xffffffe0), UINT32_C(0x80088efd));
1763
1764	int32_t volatile pi32 = (int32_t volatile )pu32;
1765	int32_t i32Old = 0;
1766	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, 32, 32, &i32Old), false, -32, -32);
1767	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, 32, -32, &i32Old), true, 32, -32);
1768	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, INT32_MIN, 32, &i32Old), true, INT32_MIN, 32);
1769	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, INT32_MIN, 32, &i32Old), false, INT32_MIN, INT32_MIN);
1770	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, INT32_MAX, INT32_MAX, &i32Old), false, INT32_MIN, INT32_MIN);
1771	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, INT32_MAX, INT32_MIN, &i32Old), true, INT32_MAX, INT32_MIN);
1772	CHECK_OP_AND_VAL_EX2(bool, "%d", "%d", pi32, i32Old, ASMAtomicCmpXchgExS32(pi32, 42, INT32_MAX, &i32Old), true, 42, INT32_MAX);
1773
1774	#if ARCH_BITS == 32
1775	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu32;
1776	RTSEMEVENT hEvtOld = (RTSEMEVENT)~(uintptr_t)31;
1777	bool fRc = true;
1778	ASMAtomicCmpXchgExHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, (RTSEMEVENT)~(uintptr_t)0, fRc, &hEvtOld);
1779	CHECKVAL(fRc, false, "%d");
1780	CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)42, "%p");
1781	CHECKVAL(hEvtOld, (RTSEMEVENT)(uintptr_t)42, "%p");
1782
1783	ASMAtomicCmpXchgExHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, (RTSEMEVENT)(uintptr_t)42, fRc, &hEvtOld);
1784	CHECKVAL(fRc, true, "%d");
1785	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, "%p");
1786	CHECKVAL(hEvtOld, (RTSEMEVENT)(uintptr_t)42, "%p");
1787	#endif
1788	}
1789
1790
1791	DECLINLINE(void) tstASMAtomicCmpXchgExU64Worker(uint64_t volatile *pu64)
1792	{
1793	*pu64 = UINT64_C(0xffffffffffffffff);
1794	uint64_t u64Old = UINT64_C(0x8000000051111111);
1795	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#llx", pu64, u64Old, ASMAtomicCmpXchgExU64(pu64, 0, 0, &u64Old), false, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
1796	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#llx", pu64, u64Old, ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0xffffffffffffffff), &u64Old), true, 0, UINT64_C(0xffffffffffffffff));
1797	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#llx", pu64, u64Old, ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x0080040008008efd), 0x342, &u64Old), false, 0, 0);
1798	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#llx", pu64, u64Old, ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x0080040008008efd), 0, &u64Old), true, UINT64_C(0x0080040008008efd), 0);
1799	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#llx", pu64, u64Old, ASMAtomicCmpXchgExU64(pu64, UINT64_C(0xffffffffffffffc0), UINT64_C(0x0080040008008efd), &u64Old), true, UINT64_C(0xffffffffffffffc0), UINT64_C(0x0080040008008efd));
1800
1801	int64_t volatile pi64 = (int64_t volatile )pu64;
1802	int64_t i64Old = -3;
1803	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, 64, 64, &i64Old), false, -64, -64);
1804	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, 64, -64, &i64Old), true, 64, -64);
1805	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, 64, -64, &i64Old), false, 64, 64);
1806	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, INT64_MIN, -64, &i64Old), false, 64, 64);
1807	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, INT64_MIN, 64, &i64Old), true, INT64_MIN, 64);
1808	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, INT64_MAX, INT64_MIN, &i64Old), true, INT64_MAX, INT64_MIN);
1809	CHECK_OP_AND_VAL_EX2(bool, "%d", "%#lld", pi64, i64Old, ASMAtomicCmpXchgExS64(pi64, 42, INT64_MAX, &i64Old), true, 42, INT64_MAX);
1810
1811	#if ARCH_BITS == 64
1812	RTSEMEVENT volatile phEvt = (RTSEMEVENT volatile )pu64;
1813	RTSEMEVENT hEvtOld = (RTSEMEVENT)~(uintptr_t)31;
1814	bool fRc = true;
1815	ASMAtomicCmpXchgExHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, (RTSEMEVENT)~(uintptr_t)0, fRc, &hEvtOld);
1816	CHECKVAL(fRc, false, "%d");
1817	CHECKVAL(*phEvt, (RTSEMEVENT)(uintptr_t)42, "%p");
1818	CHECKVAL(hEvtOld, (RTSEMEVENT)(uintptr_t)42, "%p");
1819
1820	ASMAtomicCmpXchgExHandle(phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, (RTSEMEVENT)(uintptr_t)42, fRc, &hEvtOld);
1821	CHECKVAL(fRc, true, "%d");
1822	CHECKVAL(*phEvt, (RTSEMEVENT)~(uintptr_t)0x12380964, "%p");
1823	CHECKVAL(hEvtOld, (RTSEMEVENT)(uintptr_t)42, "%p");
1824
1825	void * volatile ppv = (void volatile *)pu64;
1826	void *pvOld;
1827	CHECK_OP_AND_VAL_EX2(bool, "%d", "%p", ppv, pvOld, ASMAtomicCmpXchgExPtrVoid(ppv, (void )(intptr_t)12345678, NULL, &pvOld), false, (void )~(uintptr_t)0x12380964, (void *)~(uintptr_t)0x12380964);
1828	CHECK_OP_AND_VAL_EX2(bool, "%d", "%p", ppv, pvOld, ASMAtomicCmpXchgExPtrVoid(ppv, (void )(intptr_t)12345678, (void )~(uintptr_t)0x12380964, &pvOld), true, (void )(intptr_t)12345678, (void )~(uintptr_t)0x12380964);
1829
1830	CHECK_OP_AND_VAL_EX2(bool, "%d", "%p", ppv, pvOld, ASMAtomicCmpXchgExPtr(ppv, (void )~(uintptr_t)99, (void )~(uintptr_t)99, &pvOld), false, (void )(intptr_t)12345678, (void )(intptr_t)12345678);
1831	CHECK_OP_AND_VAL_EX2(bool, "%d", "%p", ppv, pvOld, ASMAtomicCmpXchgExPtr(ppv, (void )~(uintptr_t)99, (void )(intptr_t)12345678, &pvOld), true, (void )~(intptr_t)99, (void )(intptr_t)12345678);
1832	#endif
1833	}
1834
1835
1836	#ifdef RTASM_HAVE_CMP_XCHG_U128
1837	DECLINLINE(void) tstASMAtomicCmpXchgU128Worker(RTUINT128U volatile *pu128)
1838	{
1839	pu128->s.Lo = UINT64_C(0xffffffffffffff);
1840	pu128->s.Hi = UINT64_C(0xffffffffffffff);
1841
1842	RTUINT128U u128A, u128B;
1843	RTUINT128U const u128OldInit = RTUINT128_INIT_C(0x4242424242424242, 0x2222222222222222);
1844	RTUINT128U u128Old = u128OldInit;
1845	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1846	u128A = RTUINT128_INIT_C(0, 0),
1847	u128B = RTUINT128_INIT_C(0, 0),
1848	&u128Old),
1849	false, 0xffffffffffffff, 0xffffffffffffff);
1850	CHECKVAL128_C(&u128Old, 0xffffffffffffff, 0xffffffffffffff);
1851
1852	u128Old = u128OldInit;
1853	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1854	u128A = RTUINT128_INIT_C(0, 0),
1855	u128B = RTUINT128_INIT_C(0xffffffffffffff, 0xffffffffffffff),
1856	&u128Old),
1857	true, 0, 0);
1858	CHECKVAL128_C(&u128Old, 0xffffffffffffff, 0xffffffffffffff);
1859
1860	u128Old = u128OldInit;
1861	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1862	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1863	u128B = RTUINT128_INIT_C(0, 1),
1864	&u128Old),
1865	false, 0, 0);
1866	CHECKVAL128_C(&u128Old, 0, 0);
1867
1868	u128Old = u128OldInit;
1869	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1870	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1871	u128B = RTUINT128_INIT_C(1, 0),
1872	&u128Old),
1873	false, 0, 0);
1874	CHECKVAL128_C(&u128Old, 0, 0);
1875
1876	u128Old = u128OldInit;
1877	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1878	u128A = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1879	u128B = RTUINT128_INIT_C(0, 0),
1880	&u128Old),
1881	true, 0x80040008008efd, 0x40080004004def);
1882	CHECKVAL128_C(&u128Old, 0, 0);
1883
1884	u128Old = u128OldInit;
1885	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1886	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1887	u128B = RTUINT128_INIT_C(0x80040008008efd, 0),
1888	&u128Old),
1889	false, 0x80040008008efd, 0x40080004004def);
1890	CHECKVAL128_C(&u128Old, 0x80040008008efd, 0x40080004004def);
1891
1892	u128Old = u128OldInit;
1893	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1894	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1895	u128B = RTUINT128_INIT_C(0, 0x40080004004def),
1896	&u128Old),
1897	false, 0x80040008008efd, 0x40080004004def);
1898	CHECKVAL128_C(&u128Old, 0x80040008008efd, 0x40080004004def);
1899
1900	u128Old = u128OldInit;
1901	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128U(pu128,
1902	u128A = RTUINT128_INIT_C(0xfff40ff8f08ef3, 0x4ee8ee04cc4de4),
1903	u128B = RTUINT128_INIT_C(0x80040008008efd, 0x40080004004def),
1904	&u128Old),
1905	true, 0xfff40ff8f08ef3, 0x4ee8ee04cc4de4);
1906	CHECKVAL128_C(&u128Old, 0x80040008008efd, 0x40080004004def);
1907
1908	/* Make sure the v2 version works too (arm) */
1909	u128Old = u128OldInit;
1910	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128v2(&pu128->u,
1911	UINT64_C(0x78039485960543), UINT64_C(0x97058437294586),
1912	UINT64_C(0xfff40ff8f08ef3), UINT64_C(0x4ee8ee04cc4de4),
1913	&u128Old.u),
1914	true, 0x78039485960543, 0x97058437294586);
1915	CHECKVAL128_C(&u128Old, 0xfff40ff8f08ef3, 0x4ee8ee04cc4de4);
1916
1917	u128Old = u128OldInit;
1918	CHECK_OP_AND_VAL_128_C(bool, "%d", pu128, ASMAtomicCmpXchgU128v2(&pu128->u,
1919	UINT64_C(0x13495874560495), UINT64_C(0x12304896098597),
1920	UINT64_C(0xfff40ff8f08ef3), UINT64_C(0x4ee8ee04cc4de4),
1921	&u128Old.u),
1922	false, 0x78039485960543, 0x97058437294586);
1923	CHECKVAL128_C(&u128Old, 0x78039485960543, 0x97058437294586);
1924	}
1925	#endif /* RTASM_HAVE_CMP_XCHG_U128 */
1926
1927
1928	static void tstASMAtomicCmpXchgEx(void)
1929	{
1930	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU8, uint8_t);
1931	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU16, uint16_t);
1932	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU32, uint32_t);
1933	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU64, uint64_t);
1934	#ifdef RTASM_HAVE_CMP_XCHG_U128
1935	# ifdef RT_ARCH_AMD64
1936	if (ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16)
1937	# endif
1938	{
1939	RTTestISub("ASMAtomicCmpXchgU128");
1940	DO_SIMPLE_TEST_NO_SUB_NO_STACK(tstASMAtomicCmpXchgU128Worker, RTUINT128U);
1941	}
1942	#endif
1943	}
1944
1945
1946	#define TEST_RET_OLD(a_Type, a_Fmt, a_pVar, a_Function, a_uVal, a_VarExpect) do { \
1947	a_Type const uOldExpect = *(a_pVar); \
1948	a_Type uOldRet = a_Function(a_pVar, a_uVal); \
1949	if (RT_LIKELY( uOldRet == (uOldExpect) && *(a_pVar) == (a_VarExpect) )) { } \
1950	else RTTestFailed(g_hTest, "%s, %d: FAILURE: %s(%s," a_Fmt ") -> " a_Fmt ", expected " a_Fmt "; %s=" a_Fmt ", expected " a_Fmt "\n", \
1951	__FUNCTION__, __LINE__, #a_Function, #a_pVar, a_uVal, uOldRet, uOldExpect, #a_pVar, *(a_pVar), (a_VarExpect)); \
1952	} while (0)
1953
1954
1955	DECLINLINE(void) tstASMAtomicAddU32Worker(uint32_t *pu32)
1956	{
1957	*pu32 = 10;
1958	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, 1, 11);
1959	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, UINT32_C(0xfffffffe), 9);
1960	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, UINT32_C(0xfffffff7), 0);
1961	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, UINT32_C(0x7fffffff), UINT32_C(0x7fffffff));
1962	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, 1, UINT32_C(0x80000000));
1963	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, 1, UINT32_C(0x80000001));
1964	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, UINT32_C(0x7fffffff), 0);
1965	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAddU32, 0, 0);
1966
1967	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicSubU32, 0, 0);
1968	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicSubU32, 32, UINT32_C(0xffffffe0));
1969	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicSubU32, UINT32_C(0x7fffffff), UINT32_C(0x7fffffe1));
1970	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicSubU32, UINT32_C(0x7fffffde), UINT32_C(0x00000003));
1971	}
1972
1973
1974	DECLINLINE(void) tstASMAtomicAddS32Worker(int32_t *pi32)
1975	{
1976	*pi32 = 10;
1977	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, 1, 11);
1978	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, -2, 9);
1979	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, -9, 0);
1980	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, -0x7fffffff, -0x7fffffff);
1981	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, 0, -0x7fffffff);
1982	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, 0x7fffffff, 0);
1983	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicAddS32, 0, 0);
1984
1985	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicSubS32, 0, 0);
1986	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicSubS32, 1, -1);
1987	TEST_RET_OLD(int32_t, "%d", pi32, ASMAtomicSubS32, INT32_MIN, INT32_MAX);
1988	}
1989
1990
1991	DECLINLINE(void) tstASMAtomicAddU64Worker(uint64_t volatile *pu64)
1992	{
1993	*pu64 = 10;
1994	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, 1, 11);
1995	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0xfffffffffffffffe), UINT64_C(0x0000000000000009));
1996	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0xfffffffffffffff7), UINT64_C(0x0000000000000000));
1997	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0x7ffffffffffffff0), UINT64_C(0x7ffffffffffffff0));
1998	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0x7ffffffffffffff0), UINT64_C(0xffffffffffffffe0));
1999	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0x0000000000000000), UINT64_C(0xffffffffffffffe0));
2000	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0x000000000000001f), UINT64_C(0xffffffffffffffff));
2001	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicAddU64, UINT64_C(0x0000000000000001), UINT64_C(0x0000000000000000));
2002
2003	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicSubU64, UINT64_C(0x0000000000000000), UINT64_C(0x0000000000000000));
2004	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicSubU64, UINT64_C(0x0000000000000020), UINT64_C(0xffffffffffffffe0));
2005	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicSubU64, UINT64_C(0x7fffffffffffffff), UINT64_C(0x7fffffffffffffe1));
2006	TEST_RET_OLD(uint64_t, "%llx", pu64, ASMAtomicSubU64, UINT64_C(0x7fffffffffffffdd), UINT64_C(0x0000000000000004));
2007	}
2008
2009
2010	DECLINLINE(void) tstASMAtomicAddS64Worker(int64_t volatile *pi64)
2011	{
2012	*pi64 = 10;
2013	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, 1, 11);
2014	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, -2, 9);
2015	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, -9, 0);
2016	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, -INT64_MAX, -INT64_MAX);
2017	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, 0, -INT64_MAX);
2018	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, -1, INT64_MIN);
2019	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, INT64_MAX, -1);
2020	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, 1, 0);
2021	TEST_RET_OLD(int64_t, "%lld", pi64, ASMAtomicAddS64, 0, 0);
2022
2023	TEST_RET_OLD(int64_t, "%d", pi64, ASMAtomicSubS64, 0, 0);
2024	TEST_RET_OLD(int64_t, "%d", pi64, ASMAtomicSubS64, 1, -1);
2025	TEST_RET_OLD(int64_t, "%d", pi64, ASMAtomicSubS64, INT64_MIN, INT64_MAX);
2026	}
2027
2028
2029
2030	DECLINLINE(void) tstASMAtomicAddZWorker(size_t volatile *pcb)
2031	{
2032	*pcb = 10;
2033	TEST_RET_OLD(size_t, "%zx", pcb, ASMAtomicAddZ, 1, 11);
2034	TEST_RET_OLD(size_t, "%zx", pcb, ASMAtomicAddZ, ~(size_t)1, 9);
2035	TEST_RET_OLD(size_t, "%zx", pcb, ASMAtomicAddZ, ~(size_t)8, 0);
2036
2037	TEST_RET_OLD(size_t, "%zx", pcb, ASMAtomicSubZ, 0, 0);
2038	TEST_RET_OLD(size_t, "%zx", pcb, ASMAtomicSubZ, 10, ~(size_t)9);
2039	}
2040
2041	static void tstASMAtomicAdd(void)
2042	{
2043	DO_SIMPLE_TEST(ASMAtomicAddU32, uint32_t);
2044	DO_SIMPLE_TEST(ASMAtomicAddS32, int32_t);
2045	DO_SIMPLE_TEST(ASMAtomicAddU64, uint64_t);
2046	DO_SIMPLE_TEST(ASMAtomicAddS64, int64_t);
2047	DO_SIMPLE_TEST(ASMAtomicAddZ, size_t);
2048	}
2049
2050
2051	#define TEST_RET_NEW_NV(a_Type, a_Fmt, a_pVar, a_Function, a_VarExpect) do { \
2052	a_Type uNewRet = a_Function(a_pVar); \
2053	if (RT_LIKELY( uNewRet == (a_VarExpect) && *(a_pVar) == (a_VarExpect) )) { } \
2054	else RTTestFailed(g_hTest, "%s, %d: FAILURE: %s(%s) -> " a_Fmt " and %s=" a_Fmt ", expected both " a_Fmt "\n", \
2055	__FUNCTION__, __LINE__, #a_Function, #a_pVar, uNewRet, #a_pVar, *(a_pVar), (a_VarExpect)); \
2056	} while (0)
2057
2058
2059	DECLINLINE(void) tstASMAtomicDecIncU32Worker(uint32_t volatile *pu32)
2060	{
2061	*pu32 = 3;
2062	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, 2);
2063	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, 1);
2064	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, 0);
2065	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, UINT32_MAX);
2066	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, UINT32_MAX - 1);
2067	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, UINT32_MAX - 2);
2068	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, UINT32_MAX - 1);
2069	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, UINT32_MAX);
2070	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, 0);
2071	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, 1);
2072	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, 2);
2073	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, 1);
2074	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, 2);
2075	*pu32 = _1M;
2076	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicDecU32, _1M - 1);
2077	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, _1M);
2078	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicIncU32, _1M + 1);
2079	}
2080
2081	DECLINLINE(void) tstASMAtomicUoDecIncU32Worker(uint32_t volatile *pu32)
2082	{
2083	*pu32 = 3;
2084	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, 2);
2085	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, 1);
2086	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, 0);
2087	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, UINT32_MAX);
2088	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, UINT32_MAX - 1);
2089	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, UINT32_MAX - 2);
2090	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, UINT32_MAX - 1);
2091	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, UINT32_MAX);
2092	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, 0);
2093	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, 1);
2094	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, 2);
2095	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, 1);
2096	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, 2);
2097	*pu32 = _1M;
2098	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoDecU32, _1M - 1);
2099	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, _1M);
2100	TEST_RET_NEW_NV(uint32_t, "%#x", pu32, ASMAtomicUoIncU32, _1M + 1);
2101	}
2102
2103
2104	DECLINLINE(void) tstASMAtomicDecIncS32Worker(int32_t volatile *pi32)
2105	{
2106	*pi32 = 10;
2107	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 9);
2108	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 8);
2109	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 7);
2110	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 6);
2111	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 5);
2112	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 4);
2113	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 3);
2114	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 2);
2115	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 1);
2116	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 0);
2117	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, -1);
2118	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, -2);
2119	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, -1);
2120	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 0);
2121	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 1);
2122	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 2);
2123	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 3);
2124	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 2);
2125	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 3);
2126	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, 2);
2127	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, 3);
2128	*pi32 = INT32_MAX;
2129	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicDecS32, INT32_MAX - 1);
2130	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, INT32_MAX);
2131	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicIncS32, INT32_MIN);
2132	}
2133
2134
2135	#if 0
2136	DECLINLINE(void) tstASMAtomicUoDecIncS32Worker(int32_t volatile *pi32)
2137	{
2138	*pi32 = 10;
2139	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 9);
2140	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 8);
2141	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 7);
2142	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 6);
2143	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 5);
2144	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 4);
2145	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 3);
2146	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 2);
2147	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 1);
2148	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 0);
2149	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, -1);
2150	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, -2);
2151	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, -1);
2152	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 0);
2153	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 1);
2154	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 2);
2155	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 3);
2156	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 2);
2157	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 3);
2158	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, 2);
2159	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, 3);
2160	*pi32 = INT32_MAX;
2161	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoDecS32, INT32_MAX - 1);
2162	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, INT32_MAX);
2163	TEST_RET_NEW_NV(int32_t, "%d", pi32, ASMAtomicUoIncS32, INT32_MIN);
2164	}
2165	#endif
2166
2167
2168	DECLINLINE(void) tstASMAtomicDecIncU64Worker(uint64_t volatile *pu64)
2169	{
2170	*pu64 = 3;
2171	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, 2);
2172	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, 1);
2173	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, 0);
2174	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, UINT64_MAX);
2175	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, UINT64_MAX - 1);
2176	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, UINT64_MAX - 2);
2177	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, UINT64_MAX - 1);
2178	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, UINT64_MAX);
2179	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, 0);
2180	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, 1);
2181	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, 2);
2182	*pu64 = _4G - 1;
2183	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, _4G - 2);
2184	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, _4G - 1);
2185	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, _4G);
2186	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicIncU64, _4G + 1);
2187	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicDecU64, _4G);
2188	}
2189
2190
2191	#if 0
2192	DECLINLINE(void) tstASMAtomicUoDecIncU64Worker(uint64_t volatile *pu64)
2193	{
2194	*pu64 = 3;
2195	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, 2);
2196	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, 1);
2197	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, 0);
2198	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, UINT64_MAX);
2199	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, UINT64_MAX - 1);
2200	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, UINT64_MAX - 2);
2201	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, UINT64_MAX - 1);
2202	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, UINT64_MAX);
2203	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, 0);
2204	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, 1);
2205	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, 2);
2206	*pu64 = _4G - 1;
2207	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, _4G - 2);
2208	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, _4G - 1);
2209	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, _4G);
2210	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoIncU64, _4G + 1);
2211	TEST_RET_NEW_NV(uint64_t, "%lld", pu64, ASMAtomicUoDecU64, _4G);
2212	}
2213	#endif
2214
2215
2216	DECLINLINE(void) tstASMAtomicDecIncS64Worker(int64_t volatile *pi64)
2217	{
2218	*pi64 = 10;
2219	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 9);
2220	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 8);
2221	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 7);
2222	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 6);
2223	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 5);
2224	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 4);
2225	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 3);
2226	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 2);
2227	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 1);
2228	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 0);
2229	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, -1);
2230	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, -2);
2231	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, -1);
2232	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 0);
2233	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 1);
2234	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 2);
2235	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 3);
2236	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 2);
2237	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 3);
2238	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, 2);
2239	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicIncS64, 3);
2240	*pi64 = INT64_MAX;
2241	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicDecS64, INT64_MAX - 1);
2242	}
2243
2244
2245	#if 0
2246	DECLINLINE(void) tstASMAtomicUoDecIncS64Worker(int64_t volatile *pi64)
2247	{
2248	*pi64 = 10;
2249	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 9);
2250	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 8);
2251	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 7);
2252	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 6);
2253	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 5);
2254	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 4);
2255	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 3);
2256	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 2);
2257	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 1);
2258	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 0);
2259	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, -1);
2260	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, -2);
2261	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, -1);
2262	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 0);
2263	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 1);
2264	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 2);
2265	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 3);
2266	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 2);
2267	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 3);
2268	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, 2);
2269	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoIncS64, 3);
2270	*pi64 = INT64_MAX;
2271	TEST_RET_NEW_NV(int64_t, "%lld", pi64, ASMAtomicUoDecS64, INT64_MAX - 1);
2272	}
2273	#endif
2274
2275
2276	DECLINLINE(void) tstASMAtomicDecIncZWorker(size_t volatile *pcb)
2277	{
2278	size_t const uBaseVal = ~(size_t)0 >> 7;
2279	*pcb = uBaseVal;
2280	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicDecZ, uBaseVal - 1);
2281	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicDecZ, uBaseVal - 2);
2282	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicDecZ, uBaseVal - 3);
2283	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicIncZ, uBaseVal - 2);
2284	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicIncZ, uBaseVal - 1);
2285	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicIncZ, uBaseVal);
2286	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicIncZ, uBaseVal + 1);
2287	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicDecZ, uBaseVal);
2288	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicDecZ, uBaseVal - 1);
2289	TEST_RET_NEW_NV(size_t, "%zx", pcb, ASMAtomicIncZ, uBaseVal);
2290	}
2291
2292
2293	static void tstASMAtomicDecInc(void)
2294	{
2295	DO_SIMPLE_TEST(ASMAtomicDecIncU32, uint32_t);
2296	DO_SIMPLE_TEST(ASMAtomicUoDecIncU32, uint32_t);
2297	DO_SIMPLE_TEST(ASMAtomicDecIncS32, int32_t);
2298	//DO_SIMPLE_TEST(ASMAtomicUoDecIncS32, int32_t);
2299	DO_SIMPLE_TEST(ASMAtomicDecIncU64, uint64_t);
2300	//DO_SIMPLE_TEST(ASMAtomicUoDecIncU64, uint64_t);
2301	DO_SIMPLE_TEST(ASMAtomicDecIncS64, int64_t);
2302	//DO_SIMPLE_TEST(ASMAtomicUoDecIncS64, int64_t);
2303	DO_SIMPLE_TEST(ASMAtomicDecIncZ, size_t);
2304	}
2305
2306
2307	#define TEST_RET_VOID(a_Type, a_Fmt, a_pVar, a_Function, a_uVal, a_VarExpect) do { \
2308	a_Function(a_pVar, a_uVal); \
2309	if (RT_LIKELY( *(a_pVar) == (a_VarExpect) )) { } \
2310	else RTTestFailed(g_hTest, "%s, %d: FAILURE: %s(%s, " a_Fmt ") -> %s=" a_Fmt ", expected " a_Fmt "\n", \
2311	__FUNCTION__, __LINE__, #a_Function, #a_pVar, a_uVal, #a_pVar, *(a_pVar), (a_VarExpect)); \
2312	} while (0)
2313
2314	#define TEST_RET_NEW(a_Type, a_Fmt, a_pVar, a_Function, a_uVal, a_VarExpect) do { \
2315	a_Type uNewRet = a_Function(a_pVar, a_uVal); \
2316	if (RT_LIKELY( uNewRet == (a_VarExpect) && *(a_pVar) == (a_VarExpect) )) { } \
2317	else RTTestFailed(g_hTest, "%s, %d: FAILURE: %s(%s, " a_Fmt ") -> " a_Fmt " and %s=" a_Fmt ", expected both " a_Fmt "\n", \
2318	__FUNCTION__, __LINE__, #a_Function, #a_pVar, a_uVal, uNewRet, #a_pVar, *(a_pVar), (a_VarExpect)); \
2319	} while (0)
2320
2321
2322	DECLINLINE(void) tstASMAtomicAndOrXorU32Worker(uint32_t volatile *pu32)
2323	{
2324	*pu32 = UINT32_C(0xffffffff);
2325	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicOrU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2326	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2327	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(0x8f8f8f8f), UINT32_C(0x8f8f8f8f));
2328	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicOrU32, UINT32_C(0x70707070), UINT32_C(0xffffffff));
2329	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(1), UINT32_C(1));
2330	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicOrU32, UINT32_C(0x80000000), UINT32_C(0x80000001));
2331	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(0x80000000), UINT32_C(0x80000000));
2332	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(0), UINT32_C(0));
2333	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicOrU32, UINT32_C(0x42424242), UINT32_C(0x42424242));
2334	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicAndU32, UINT32_C(0x00ff0f00), UINT32_C(0x00420200));
2335	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicXorU32, UINT32_C(0x42004042), UINT32_C(0x42424242));
2336	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicXorU32, UINT32_C(0xff024200), UINT32_C(0xbd400042));
2337	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicXorU32, UINT32_C(0x00000000), UINT32_C(0xbd400042));
2338	}
2339
2340
2341	DECLINLINE(void) tstASMAtomicUoAndOrXorU32Worker(uint32_t volatile *pu32)
2342	{
2343	*pu32 = UINT32_C(0xffffffff);
2344	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoOrU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2345	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2346	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(0x8f8f8f8f), UINT32_C(0x8f8f8f8f));
2347	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoOrU32, UINT32_C(0x70707070), UINT32_C(0xffffffff));
2348	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(1), UINT32_C(1));
2349	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoOrU32, UINT32_C(0x80000000), UINT32_C(0x80000001));
2350	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(0x80000000), UINT32_C(0x80000000));
2351	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(0), UINT32_C(0));
2352	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoOrU32, UINT32_C(0x42424242), UINT32_C(0x42424242));
2353	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoAndU32, UINT32_C(0x00ff0f00), UINT32_C(0x00420200));
2354	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoXorU32, UINT32_C(0x42004042), UINT32_C(0x42424242));
2355	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoXorU32, UINT32_C(0xff024200), UINT32_C(0xbd400042));
2356	TEST_RET_VOID(uint32_t, "%#x", pu32, ASMAtomicUoXorU32, UINT32_C(0x00000000), UINT32_C(0xbd400042));
2357	}
2358
2359
2360	DECLINLINE(void) tstASMAtomicAndOrXorExU32Worker(uint32_t volatile *pu32)
2361	{
2362	*pu32 = UINT32_C(0xffffffff);
2363	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicOrExU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2364	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2365	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(0x8f8f8f8f), UINT32_C(0x8f8f8f8f));
2366	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicOrExU32, UINT32_C(0x70707070), UINT32_C(0xffffffff));
2367	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(1), UINT32_C(1));
2368	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicOrExU32, UINT32_C(0x80000000), UINT32_C(0x80000001));
2369	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(0x80000000), UINT32_C(0x80000000));
2370	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(0), UINT32_C(0));
2371	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicOrExU32, UINT32_C(0x42424242), UINT32_C(0x42424242));
2372	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicAndExU32, UINT32_C(0x00ff0f00), UINT32_C(0x00420200));
2373	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicXorExU32, UINT32_C(0x42004042), UINT32_C(0x42424242));
2374	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicXorExU32, UINT32_C(0xff024200), UINT32_C(0xbd400042));
2375	TEST_RET_OLD(uint32_t, "%#x", pu32, ASMAtomicXorExU32, UINT32_C(0x00000000), UINT32_C(0xbd400042));
2376	}
2377
2378
2379	DECLINLINE(void) tstASMAtomicAndOrXorU64Worker(uint64_t volatile *pu64)
2380	{
2381	*pu64 = UINT64_C(0xffffffff);
2382	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2383	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2384	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x8f8f8f8f), UINT64_C(0x8f8f8f8f));
2385	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x70707070), UINT64_C(0xffffffff));
2386	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(1), UINT64_C(1));
2387	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x80000000), UINT64_C(0x80000001));
2388	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x80000000), UINT64_C(0x80000000));
2389	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0), UINT64_C(0));
2390	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x42424242), UINT64_C(0x42424242));
2391	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x00ff0f00), UINT64_C(0x00420200));
2392	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0x42004042), UINT64_C(0x42424242));
2393	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0xff024200), UINT64_C(0xbd400042));
2394	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0x00000000), UINT64_C(0xbd400042));
2395
2396	/* full 64-bit */
2397	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x0000000000000000), UINT64_C(0x0000000000000000));
2398	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2399	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2400	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x8f8f8f8f8f8f8f8f), UINT64_C(0x8f8f8f8f8f8f8f8f));
2401	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x7070707070707070), UINT64_C(0xffffffffffffffff));
2402	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x0000000000000001), UINT64_C(0x0000000000000001));
2403	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000001));
2404	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000000));
2405	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0), UINT64_C(0));
2406	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicOrU64, UINT64_C(0x4242424242424242), UINT64_C(0x4242424242424242));
2407	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicAndU64, UINT64_C(0x00ff0f00ff0f0000), UINT64_C(0x0042020042020000));
2408	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0x4200404242040000), UINT64_C(0x4242424242420000));
2409	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0xff02420000ff2127), UINT64_C(0xbd40004242bd2127));
2410	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicXorU64, UINT64_C(0x0000000000000000), UINT64_C(0xbd40004242bd2127));
2411	}
2412
2413
2414	DECLINLINE(void) tstASMAtomicUoAndOrXorU64Worker(uint64_t volatile *pu64)
2415	{
2416	*pu64 = UINT64_C(0xffffffff);
2417	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2418	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2419	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x8f8f8f8f), UINT64_C(0x8f8f8f8f));
2420	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x70707070), UINT64_C(0xffffffff));
2421	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(1), UINT64_C(1));
2422	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x80000000), UINT64_C(0x80000001));
2423	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x80000000), UINT64_C(0x80000000));
2424	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0), UINT64_C(0));
2425	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x42424242), UINT64_C(0x42424242));
2426	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x00ff0f00), UINT64_C(0x00420200));
2427	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0x42004042), UINT64_C(0x42424242));
2428	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0xff024200), UINT64_C(0xbd400042));
2429	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0x00000000), UINT64_C(0xbd400042));
2430
2431	/* full 64-bit */
2432	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x0000000000000000), UINT64_C(0x0000000000000000));
2433	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2434	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2435	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x8f8f8f8f8f8f8f8f), UINT64_C(0x8f8f8f8f8f8f8f8f));
2436	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x7070707070707070), UINT64_C(0xffffffffffffffff));
2437	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x0000000000000001), UINT64_C(0x0000000000000001));
2438	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000001));
2439	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000000));
2440	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0), UINT64_C(0));
2441	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoOrU64, UINT64_C(0x4242424242424242), UINT64_C(0x4242424242424242));
2442	TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoAndU64, UINT64_C(0x00ff0f00ff0f0000), UINT64_C(0x0042020042020000));
2443	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0x4200404242040000), UINT64_C(0x4242424242420000));
2444	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0xff02420000ff2127), UINT64_C(0xbd40004242bd2127));
2445	//TEST_RET_VOID(uint64_t, "%#llx", pu64, ASMAtomicUoXorU64, UINT64_C(0x0000000000000000), UINT64_C(0xbd40004242bd2127));
2446	}
2447
2448
2449	#if 0
2450	DECLINLINE(void) tstASMAtomicAndOrXorExU64Worker(uint64_t volatile *pu64)
2451	{
2452	*pu64 = UINT64_C(0xffffffff);
2453	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2454	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0xffffffff), UINT64_C(0xffffffff));
2455	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x8f8f8f8f), UINT64_C(0x8f8f8f8f));
2456	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x70707070), UINT64_C(0xffffffff));
2457	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(1), UINT64_C(1));
2458	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x80000000), UINT64_C(0x80000001));
2459	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x80000000), UINT64_C(0x80000000));
2460	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0), UINT64_C(0));
2461	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x42424242), UINT64_C(0x42424242));
2462	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x00ff0f00), UINT64_C(0x00420200));
2463	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0x42004042), UINT64_C(0x42424242));
2464	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0xff024200), UINT64_C(0xbd400042));
2465	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0x00000000), UINT64_C(0xbd400042));
2466
2467	/* full 64-bit */
2468	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x0000000000000000), UINT64_C(0x0000000000000000));
2469	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2470	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0xffffffffffffffff), UINT64_C(0xffffffffffffffff));
2471	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x8f8f8f8f8f8f8f8f), UINT64_C(0x8f8f8f8f8f8f8f8f));
2472	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x7070707070707070), UINT64_C(0xffffffffffffffff));
2473	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x0000000000000001), UINT64_C(0x0000000000000001));
2474	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000001));
2475	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x8000000000000000), UINT64_C(0x8000000000000000));
2476	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0), UINT64_C(0));
2477	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicOrExU64, UINT64_C(0x4242424242424242), UINT64_C(0x4242424242424242));
2478	TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicAndExU64, UINT64_C(0x00ff0f00ff0f0000), UINT64_C(0x0042020042020000));
2479	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0x4200404242040000), UINT64_C(0x4242424242420000));
2480	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0xff02420000ff2127), UINT64_C(0xbd40004242bd2127));
2481	//TEST_RET_OLD(uint64_t, "%#llx", pu64, ASMAtomicXorExU64, UINT64_C(0x0000000000000000), UINT64_C(0xbd40004242bd2127));
2482	}
2483	#endif
2484
2485
2486	static void tstASMAtomicAndOrXor(void)
2487	{
2488	DO_SIMPLE_TEST(ASMAtomicAndOrXorU32, uint32_t);
2489	DO_SIMPLE_TEST(ASMAtomicUoAndOrXorU32, uint32_t);
2490	DO_SIMPLE_TEST(ASMAtomicAndOrXorExU32, uint32_t);
2491	DO_SIMPLE_TEST(ASMAtomicAndOrXorU64, uint64_t);
2492	DO_SIMPLE_TEST(ASMAtomicUoAndOrXorU64, uint64_t);
2493	//DO_SIMPLE_TEST(ASMAtomicAndOrXorExU64, uint64_t);
2494	}
2495
2496
2497	static void tstASMMemFirstMismatchingU8(RTTEST hTest)
2498	{
2499	RTTestSub(hTest, "ASMMemFirstMismatchingU8");
2500
2501	uint8_t pbPage1 = (uint8_t )RTTestGuardedAllocHead(hTest, PAGE_SIZE);
2502	uint8_t pbPage2 = (uint8_t )RTTestGuardedAllocTail(hTest, PAGE_SIZE);
2503	RTTESTI_CHECK_RETV(pbPage1 && pbPage2);
2504
2505	memset(pbPage1, 0, PAGE_SIZE);
2506	memset(pbPage2, 0, PAGE_SIZE);
2507	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0) == NULL);
2508	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0) == NULL);
2509	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 1) == pbPage1);
2510	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 1) == pbPage2);
2511	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0x87) == pbPage1);
2512	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0x87) == pbPage2);
2513	RTTESTI_CHECK(ASMMemIsZero(pbPage1, PAGE_SIZE));
2514	RTTESTI_CHECK(ASMMemIsZero(pbPage2, PAGE_SIZE));
2515	RTTESTI_CHECK(ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0));
2516	RTTESTI_CHECK(ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0));
2517	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0x34));
2518	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0x88));
2519	unsigned cbSub = 32;
2520	while (cbSub-- > 0)
2521	{
2522	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0) == NULL);
2523	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0) == NULL);
2524	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0) == NULL);
2525	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0) == NULL);
2526
2527	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0x34) == &pbPage1[PAGE_SIZE - cbSub] \|\| !cbSub);
2528	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0x99) == &pbPage2[PAGE_SIZE - cbSub] \|\| !cbSub);
2529	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0x42) == pbPage1 \|\| !cbSub);
2530	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0x88) == pbPage2 \|\| !cbSub);
2531	}
2532
2533	memset(pbPage1, 0xff, PAGE_SIZE);
2534	memset(pbPage2, 0xff, PAGE_SIZE);
2535	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0xff) == NULL);
2536	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0xff) == NULL);
2537	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0xfe) == pbPage1);
2538	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0xfe) == pbPage2);
2539	RTTESTI_CHECK(!ASMMemIsZero(pbPage1, PAGE_SIZE));
2540	RTTESTI_CHECK(!ASMMemIsZero(pbPage2, PAGE_SIZE));
2541	RTTESTI_CHECK(ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0xff));
2542	RTTESTI_CHECK(ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0xff));
2543	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0));
2544	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0));
2545	cbSub = 32;
2546	while (cbSub-- > 0)
2547	{
2548	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0xff) == NULL);
2549	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0xff) == NULL);
2550	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0xff) == NULL);
2551	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0xff) == NULL);
2552
2553	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0xfe) == &pbPage1[PAGE_SIZE - cbSub] \|\| !cbSub);
2554	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0xfe) == &pbPage2[PAGE_SIZE - cbSub] \|\| !cbSub);
2555	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0xfe) == pbPage1 \|\| !cbSub);
2556	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0xfe) == pbPage2 \|\| !cbSub);
2557	}
2558
2559
2560	/*
2561	* Various alignments and sizes.
2562	*/
2563	uint8_t const bFiller1 = 0x00;
2564	uint8_t const bFiller2 = 0xf6;
2565	size_t const cbBuf = 128;
2566	uint8_t *pbBuf1 = pbPage1;
2567	uint8_t pbBuf2 = &pbPage2[PAGE_SIZE - cbBuf]; / Put it up against the tail guard */
2568	memset(pbPage1, (uint8_t)~bFiller1, PAGE_SIZE);
2569	memset(pbPage2, (uint8_t)~bFiller2, PAGE_SIZE);
2570	memset(pbBuf1, bFiller1, cbBuf);
2571	memset(pbBuf2, bFiller2, cbBuf);
2572	for (size_t offNonZero = 0; offNonZero < cbBuf; offNonZero++)
2573	{
2574	uint8_t bRand = (uint8_t)RTRandU32();
2575	pbBuf1[offNonZero] = bRand \| 1;
2576	pbBuf2[offNonZero] = (0x80 \| bRand) ^ 0xf6;
2577
2578	for (size_t offStart = 0; offStart < 32; offStart++)
2579	{
2580	size_t const cbMax = cbBuf - offStart;
2581	for (size_t cb = 0; cb < cbMax; cb++)
2582	{
2583	size_t const offEnd = offStart + cb;
2584	uint8_t bSaved1, bSaved2;
2585	if (offEnd < PAGE_SIZE)
2586	{
2587	bSaved1 = pbBuf1[offEnd];
2588	bSaved2 = pbBuf2[offEnd];
2589	pbBuf1[offEnd] = 0xff;
2590	pbBuf2[offEnd] = 0xff;
2591	}
2592	#ifdef _MSC_VER /* simple stupid compiler warnings */
2593	else
2594	bSaved1 = bSaved2 = 0;
2595	#endif
2596
2597	uint8_t pbRet = (uint8_t )ASMMemFirstMismatchingU8(pbBuf1 + offStart, cb, bFiller1);
2598	RTTESTI_CHECK(offNonZero - offStart < cb ? pbRet == &pbBuf1[offNonZero] : pbRet == NULL);
2599
2600	pbRet = (uint8_t *)ASMMemFirstMismatchingU8(pbBuf2 + offStart, cb, bFiller2);
2601	RTTESTI_CHECK(offNonZero - offStart < cb ? pbRet == &pbBuf2[offNonZero] : pbRet == NULL);
2602
2603	if (offEnd < PAGE_SIZE)
2604	{
2605	pbBuf1[offEnd] = bSaved1;
2606	pbBuf2[offEnd] = bSaved2;
2607	}
2608	}
2609	}
2610
2611	pbBuf1[offNonZero] = 0;
2612	pbBuf2[offNonZero] = 0xf6;
2613	}
2614
2615	RTTestSubDone(hTest);
2616	}
2617
2618
2619	typedef struct TSTBUF32 { uint32_t au32[384]; } TSTBUF32;
2620
2621	DECLINLINE(void) tstASMMemZero32Worker(TSTBUF32 *pBuf)
2622	{
2623	ASMMemZero32(pBuf, sizeof(*pBuf));
2624	for (unsigned i = 0; i < RT_ELEMENTS(pBuf->au32); i++)
2625	if (pBuf->au32[i])
2626	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear dword at index %#x!\n", i);
2627	if (ASMMemFirstNonZero(pBuf, sizeof(*pBuf)) != NULL)
2628	RTTestFailed(g_hTest, "ASMMemFirstNonZero return non-NULL after ASMMemZero32\n");
2629	if (!ASMMemIsZero(pBuf, sizeof(*pBuf)))
2630	RTTestFailed(g_hTest, "ASMMemIsZero return false after ASMMemZero32\n");
2631
2632	memset(pBuf, 0xfe, sizeof(*pBuf));
2633	ASMMemZero32(pBuf, sizeof(*pBuf));
2634	for (unsigned i = 0; i < RT_ELEMENTS(pBuf->au32); i++)
2635	if (pBuf->au32[i])
2636	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear dword at index %#x!\n", i);
2637	if (ASMMemFirstNonZero(pBuf, sizeof(*pBuf)) != NULL)
2638	RTTestFailed(g_hTest, "ASMMemFirstNonZero return non-NULL after ASMMemZero32\n");
2639	if (!ASMMemIsZero(pBuf, sizeof(*pBuf)))
2640	RTTestFailed(g_hTest, "ASMMemIsZero return false after ASMMemZero32\n");
2641	}
2642
2643
2644	static void tstASMMemZero32(void)
2645	{
2646	RTTestSub(g_hTest, "ASMMemZero32");
2647
2648	struct
2649	{
2650	uint64_t u64Magic1;
2651	uint8_t abPage[PAGE_SIZE - 32];
2652	uint64_t u64Magic2;
2653	} Buf1, Buf2, Buf3;
2654
2655	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
2656	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
2657	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
2658	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
2659	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
2660	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
2661	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
2662	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
2663	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
2664	ASMMemZero32(Buf1.abPage, sizeof(Buf1.abPage));
2665	ASMMemZero32(Buf2.abPage, sizeof(Buf2.abPage));
2666	ASMMemZero32(Buf3.abPage, sizeof(Buf3.abPage));
2667	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
2668	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
2669	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
2670	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
2671	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
2672	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
2673	{
2674	RTTestFailed(g_hTest, "ASMMemZero32 violated one/both magic(s)!\n");
2675	}
2676	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.abPage); i++)
2677	if (Buf1.abPage[i])
2678	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
2679	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.abPage); i++)
2680	if (Buf2.abPage[i])
2681	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
2682	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.abPage); i++)
2683	if (Buf3.abPage[i])
2684	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
2685
2686	DO_SIMPLE_TEST_NO_SUB(tstASMMemZero32Worker, TSTBUF32);
2687	}
2688
2689
2690	DECLINLINE(void) tstASMMemFill32Worker(TSTBUF32 *pBuf)
2691	{
2692	ASMMemFill32(pBuf, sizeof(*pBuf), UINT32_C(0xf629bce1));
2693	for (unsigned i = 0; i < RT_ELEMENTS(pBuf->au32); i++)
2694	if (pBuf->au32[i] != UINT32_C(0xf629bce1))
2695	RTTestFailed(g_hTest, "ASMMemFill32 didn't set dword at index %#x correctly!\n", i);
2696	if (ASMMemFirstMismatchingU32(pBuf, sizeof(*pBuf), UINT32_C(0xf629bce1)) != NULL)
2697	RTTestFailed(g_hTest, "ASMMemFirstMismatchingU32(,,UINT32_C(0xf629bce1)) returns non-NULL after ASMMemFill32!\n");
2698
2699	memset(pBuf, 0xfe, sizeof(*pBuf));
2700	ASMMemFill32(pBuf, sizeof(*pBuf), UINT32_C(0x12345678));
2701	for (unsigned i = 0; i < RT_ELEMENTS(pBuf->au32); i++)
2702	if (pBuf->au32[i] != UINT32_C(0x12345678))
2703	RTTestFailed(g_hTest, "ASMMemFill32 didn't set dword at index %#x correctly!\n", i);
2704	if (ASMMemFirstMismatchingU32(pBuf, sizeof(*pBuf), UINT32_C(0x12345678)) != NULL)
2705	RTTestFailed(g_hTest, "ASMMemFirstMismatchingU32(,,UINT32_C(0x12345678)) returns non-NULL after ASMMemFill32!\n");
2706	}
2707
2708	static void tstASMMemFill32(void)
2709	{
2710	RTTestSub(g_hTest, "ASMMemFill32");
2711
2712	struct
2713	{
2714	uint64_t u64Magic1;
2715	uint32_t au32Page[PAGE_SIZE / 4];
2716	uint64_t u64Magic2;
2717	} Buf1;
2718	struct
2719	{
2720	uint64_t u64Magic1;
2721	uint32_t au32Page[(PAGE_SIZE / 4) - 3];
2722	uint64_t u64Magic2;
2723	} Buf2;
2724	struct
2725	{
2726	uint64_t u64Magic1;
2727	uint32_t au32Page[(PAGE_SIZE / 4) - 1];
2728	uint64_t u64Magic2;
2729	} Buf3;
2730
2731	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
2732	memset(Buf1.au32Page, 0x55, sizeof(Buf1.au32Page));
2733	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
2734	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
2735	memset(Buf2.au32Page, 0x77, sizeof(Buf2.au32Page));
2736	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
2737	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
2738	memset(Buf3.au32Page, 0x99, sizeof(Buf3.au32Page));
2739	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
2740	ASMMemFill32(Buf1.au32Page, sizeof(Buf1.au32Page), 0xdeadbeef);
2741	ASMMemFill32(Buf2.au32Page, sizeof(Buf2.au32Page), 0xcafeff01);
2742	ASMMemFill32(Buf3.au32Page, sizeof(Buf3.au32Page), 0xf00dd00f);
2743	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
2744	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
2745	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
2746	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
2747	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
2748	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
2749	RTTestFailed(g_hTest, "ASMMemFill32 violated one/both magic(s)!\n");
2750	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.au32Page); i++)
2751	if (Buf1.au32Page[i] != 0xdeadbeef)
2752	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf1.au32Page[i], 0xdeadbeef);
2753	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.au32Page); i++)
2754	if (Buf2.au32Page[i] != 0xcafeff01)
2755	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf2.au32Page[i], 0xcafeff01);
2756	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.au32Page); i++)
2757	if (Buf3.au32Page[i] != 0xf00dd00f)
2758	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf3.au32Page[i], 0xf00dd00f);
2759
2760	DO_SIMPLE_TEST_NO_SUB(tstASMMemFill32Worker, TSTBUF32);
2761	}
2762
2763
2764	static void tstASMProbe(RTTEST hTest)
2765	{
2766	RTTestSub(hTest, "ASMProbeReadByte");
2767
2768	uint8_t b = 42;
2769	RTTESTI_CHECK(ASMProbeReadByte(&b) == 42);
2770
2771	for (uint32_t cPages = 1; cPages < 16; cPages++)
2772	{
2773	uint8_t pbBuf1 = (uint8_t )RTTestGuardedAllocHead(hTest, cPages * PAGE_SIZE);
2774	uint8_t pbBuf2 = (uint8_t )RTTestGuardedAllocTail(hTest, cPages * PAGE_SIZE);
2775	RTTESTI_CHECK_RETV(pbBuf1 && pbBuf2);
2776
2777	memset(pbBuf1, 0xf6, cPages * PAGE_SIZE);
2778	memset(pbBuf2, 0x42, cPages * PAGE_SIZE);
2779
2780	RTTESTI_CHECK(ASMProbeReadByte(&pbBuf1[cPages * PAGE_SIZE - 1]) == 0xf6);
2781	RTTESTI_CHECK(ASMProbeReadByte(&pbBuf2[cPages * PAGE_SIZE - 1]) == 0x42);
2782	RTTESTI_CHECK(ASMProbeReadByte(&pbBuf1[0]) == 0xf6);
2783	RTTESTI_CHECK(ASMProbeReadByte(&pbBuf2[0]) == 0x42);
2784	}
2785	}
2786
2787
2788	static void tstASMMisc(void)
2789	{
2790	RTTestSub(g_hTest, "Misc");
2791	for (uint32_t i = 0; i < 20; i++)
2792	{
2793	ASMWriteFence();
2794	ASMCompilerBarrier();
2795	ASMReadFence();
2796	ASMNopPause();
2797	ASMSerializeInstruction();
2798	ASMMemoryFence();
2799	}
2800	}
2801
2802
2803	static void tstASMBit(void)
2804	{
2805	RTTestSub(g_hTest, "ASMBitFirstSetU16");
2806	RTTESTI_CHECK(ASMBitFirstSetU16(0x0000) == 0);
2807	RTTESTI_CHECK(ASMBitFirstSetU16(0x0001) == 1);
2808	RTTESTI_CHECK(ASMBitFirstSetU16(0x8000) == 16);
2809	RTTESTI_CHECK(ASMBitFirstSetU16(0x0ef0) == 5);
2810	for (unsigned iBit = 0; iBit < 16; iBit++)
2811	{
2812	RTTESTI_CHECK(ASMBitFirstSetU16((uint16_t)1 << iBit) == iBit + 1);
2813	RTTESTI_CHECK(ASMBitFirstSetU16(UINT16_MAX << iBit) == iBit + 1);
2814	}
2815
2816	RTTestSub(g_hTest, "ASMBitFirstSetU32");
2817	RTTESTI_CHECK(ASMBitFirstSetU32(UINT32_C(0x00000000)) == 0);
2818	RTTESTI_CHECK(ASMBitFirstSetU32(UINT32_C(0x00000001)) == 1);
2819	RTTESTI_CHECK(ASMBitFirstSetU32(UINT32_C(0x80000000)) == 32);
2820	RTTESTI_CHECK(ASMBitFirstSetU32(UINT32_C(0x0efff0f0)) == 5);
2821	for (unsigned iBit = 0; iBit < 32; iBit++)
2822	{
2823	RTTESTI_CHECK(ASMBitFirstSetU32((uint32_t)1 << iBit) == iBit + 1);
2824	RTTESTI_CHECK(ASMBitFirstSetU32(UINT32_MAX << iBit) == iBit + 1);
2825	}
2826
2827	RTTestSub(g_hTest, "ASMBitFirstSetU64");
2828	RTTESTI_CHECK(ASMBitFirstSetU64(UINT64_C(0x0000000000000000)) == 0);
2829	RTTESTI_CHECK(ASMBitFirstSetU64(UINT64_C(0x0000000000000001)) == 1);
2830	RTTESTI_CHECK(ASMBitFirstSetU64(UINT64_C(0x8000000000000000)) == 64);
2831	RTTESTI_CHECK(ASMBitFirstSetU64(UINT64_C(0x0effffff0ffff0f0)) == 5);
2832	for (unsigned iBit = 0; iBit < 64; iBit++)
2833	{
2834	RTTESTI_CHECK(ASMBitFirstSetU64((uint64_t)1 << iBit) == iBit + 1);
2835	RTTESTI_CHECK(ASMBitFirstSetU64(UINT64_MAX << iBit) == iBit + 1);
2836	}
2837
2838	RTTestSub(g_hTest, "ASMBitLastSetU16");
2839	RTTESTI_CHECK(ASMBitLastSetU16(0x0000) == 0);
2840	RTTESTI_CHECK(ASMBitLastSetU16(0x0001) == 1);
2841	RTTESTI_CHECK(ASMBitLastSetU16(0x8000) == 16);
2842	RTTESTI_CHECK(ASMBitLastSetU16(0x0fe0) == 12);
2843	for (unsigned iBit = 0; iBit < 16; iBit++)
2844	{
2845	RTTESTI_CHECK(ASMBitLastSetU16(UINT16_C(0x8000) >> (15 - iBit)) == iBit + 1);
2846	RTTESTI_CHECK(ASMBitLastSetU16(UINT16_MAX >> (15 - iBit)) == iBit + 1);
2847	}
2848
2849	RTTestSub(g_hTest, "ASMBitLastSetU32");
2850	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_C(0x00000000)) == 0);
2851	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_C(0x00000001)) == 1);
2852	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_C(0x80000000)) == 32);
2853	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_C(0x0fffffe0)) == 28);
2854	for (unsigned iBit = 0; iBit < 32; iBit++)
2855	{
2856	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_C(0x80000000) >> (31 - iBit)) == iBit + 1);
2857	RTTESTI_CHECK(ASMBitLastSetU32(UINT32_MAX >> (31 - iBit)) == iBit + 1);
2858	}
2859
2860	RTTestSub(g_hTest, "ASMBitLastSetU64");
2861	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_C(0x0000000000000000)) == 0);
2862	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_C(0x0000000000000001)) == 1);
2863	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_C(0x8000000000000000)) == 64);
2864	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_C(0x0ffffefff0ffffe0)) == 60);
2865	for (unsigned iBit = 0; iBit < 64; iBit++)
2866	{
2867	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_C(0x8000000000000000) >> (63 - iBit)) == iBit + 1);
2868	RTTESTI_CHECK(ASMBitLastSetU64(UINT64_MAX >> (63 - iBit)) == iBit + 1);
2869	}
2870
2871	RTTestSub(g_hTest, "ASMCountLeadingZerosU16");
2872	RTTESTI_CHECK(ASMCountLeadingZerosU16(0x0000) == 16);
2873	RTTESTI_CHECK(ASMCountLeadingZerosU16(0x0001) == 15);
2874	RTTESTI_CHECK(ASMCountLeadingZerosU16(0x8000) == 0);
2875	RTTESTI_CHECK(ASMCountLeadingZerosU16(0x0fe0) == 4);
2876	for (unsigned iBit = 0; iBit < 16; iBit++)
2877	{
2878	RTTESTI_CHECK(ASMCountLeadingZerosU16(UINT16_C(0x8000) >> iBit) == iBit);
2879	RTTESTI_CHECK(ASMCountLeadingZerosU16(UINT16_MAX >> iBit) == iBit);
2880	}
2881
2882	RTTestSub(g_hTest, "ASMCountLeadingZerosU32");
2883	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_C(0x00000000)) == 32);
2884	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_C(0x00000001)) == 31);
2885	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_C(0x80000000)) == 0);
2886	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_C(0x0fffffe0)) == 4);
2887	for (unsigned iBit = 0; iBit < 32; iBit++)
2888	{
2889	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_C(0x80000000) >> iBit) == iBit);
2890	RTTESTI_CHECK(ASMCountLeadingZerosU32(UINT32_MAX >> iBit) == iBit);
2891	}
2892
2893	RTTestSub(g_hTest, "ASMCountLeadingZerosU64");
2894	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_C(0x0000000000000000)) == 64);
2895	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_C(0x0000000000000001)) == 63);
2896	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_C(0x8000000000000000)) == 0);
2897	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_C(0x0fffffff0f0fffe0)) == 4);
2898	for (unsigned iBit = 0; iBit < 64; iBit++)
2899	{
2900	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_C(0x8000000000000000) >> iBit) == iBit);
2901	RTTESTI_CHECK(ASMCountLeadingZerosU64(UINT64_MAX >> iBit) == iBit);
2902	}
2903
2904	RTTestSub(g_hTest, "ASMCountTrailingZerosU16");
2905	RTTESTI_CHECK(ASMCountTrailingZerosU16(0x0000) == 16);
2906	RTTESTI_CHECK(ASMCountTrailingZerosU16(0x0001) == 0);
2907	RTTESTI_CHECK(ASMCountTrailingZerosU16(0x8000) == 15);
2908	RTTESTI_CHECK(ASMCountTrailingZerosU16(0x0ef0) == 4);
2909	for (unsigned iBit = 0; iBit < 16; iBit++)
2910	{
2911	RTTESTI_CHECK(ASMCountTrailingZerosU16((uint16_t)1 << iBit) == iBit);
2912	RTTESTI_CHECK(ASMCountTrailingZerosU16(UINT16_MAX << iBit) == iBit);
2913	}
2914
2915	RTTestSub(g_hTest, "ASMCountTrailingZerosU32");
2916	RTTESTI_CHECK(ASMCountTrailingZerosU32(UINT32_C(0x00000000)) == 32);
2917	RTTESTI_CHECK(ASMCountTrailingZerosU32(UINT32_C(0x00000001)) == 0);
2918	RTTESTI_CHECK(ASMCountTrailingZerosU32(UINT32_C(0x80000000)) == 31);
2919	RTTESTI_CHECK(ASMCountTrailingZerosU32(UINT32_C(0x0efffff0)) == 4);
2920	for (unsigned iBit = 0; iBit < 32; iBit++)
2921	{
2922	RTTESTI_CHECK(ASMCountTrailingZerosU32((uint32_t)1 << iBit) == iBit);
2923	RTTESTI_CHECK(ASMCountTrailingZerosU32(UINT32_MAX << iBit) == iBit);
2924	}
2925
2926	RTTestSub(g_hTest, "ASMCountTrailingZerosU64");
2927	RTTESTI_CHECK(ASMCountTrailingZerosU64(UINT64_C(0x0000000000000000)) == 64);
2928	RTTESTI_CHECK(ASMCountTrailingZerosU64(UINT64_C(0x0000000000000001)) == 0);
2929	RTTESTI_CHECK(ASMCountTrailingZerosU64(UINT64_C(0x8000000000000000)) == 63);
2930	RTTESTI_CHECK(ASMCountTrailingZerosU64(UINT64_C(0x0effff0fefef0ff0)) == 4);
2931	for (unsigned iBit = 0; iBit < 64; iBit++)
2932	{
2933	RTTESTI_CHECK(ASMCountTrailingZerosU64((uint64_t)1 << iBit) == iBit);
2934	RTTESTI_CHECK(ASMCountTrailingZerosU64(UINT64_MAX << iBit) == iBit);
2935	}
2936	}
2937
2938
2939	static void tstASMMath(void)
2940	{
2941	RTTestSub(g_hTest, "Math");
2942
2943	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
2944	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
2945
2946	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
2947	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
2948
2949	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x00000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
2950	CHECKVAL(u32, UINT32_C(0x00000001), "%#018RX32");
2951	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10000000), UINT32_C(0x80000000), UINT32_C(0x20000000));
2952	CHECKVAL(u32, UINT32_C(0x40000000), "%#018RX32");
2953	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x76543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2954	CHECKVAL(u32, UINT32_C(0x76543210), "%#018RX32");
2955	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0xffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2956	CHECKVAL(u32, UINT32_C(0xffffffff), "%#018RX32");
2957	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0xffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
2958	CHECKVAL(u32, UINT32_C(0xfffffff0), "%#018RX32");
2959	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
2960	CHECKVAL(u32, UINT32_C(0x05c584ce), "%#018RX32");
2961	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
2962	CHECKVAL(u32, UINT32_C(0x2d860795), "%#018RX32");
2963
2964	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2965	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
2966	CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
2967	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
2968	CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
2969	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2970	CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
2971	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
2972	CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
2973	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
2974	CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
2975	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
2976	CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
2977	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
2978	CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
2979
2980	# if 0 /* bird: question is whether this should trap or not:
2981	*
2982	* frank: Of course it must trap:
2983	*
2984	* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
2985	*
2986	* During the following division, the quotient must fit into a 32-bit register.
2987	* Therefore the smallest valid divisor is
2988	*
2989	* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
2990	*
2991	* which is definitely greater than 0x3b9aca00.
2992	*
2993	* bird: No, the C version does not crash. So, the question is whether there's any
2994	* code depending on it not crashing.
2995	*
2996	* Of course the assembly versions of the code crash right now for the reasons you've
2997	* given, but the 32-bit MSC version does not crash.
2998	*
2999	* frank: The C version does not crash but delivers incorrect results for this case.
3000	* The reason is
3001	*
3002	* u.s.Hi = (unsigned long)(u64Hi / u32C);
3003	*
3004	* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
3005	* to 32 bit. If using this (optimized and fast) function we should just be sure that
3006	* the operands are in a valid range.
3007	*/
3008	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
3009	CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
3010	# endif
3011	#endif /* AMD64 \|\| X86 */
3012
3013	u32 = ASMModU64ByU32RetU32(UINT64_C(0x0ffffff8c65d6731), UINT32_C(0x77d7daf8));
3014	CHECKVAL(u32, UINT32_C(0x3B642451), "%#010RX32");
3015
3016	int32_t i32;
3017	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(-2));
3018	CHECKVAL(i32, INT32_C(-1), "%010RI32");
3019	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(2));
3020	CHECKVAL(i32, INT32_C(-1), "%010RI32");
3021	i32 = ASMModS64ByS32RetS32(INT64_C(11), INT32_C(-2));
3022	CHECKVAL(i32, INT32_C(1), "%010RI32");
3023
3024	i32 = ASMModS64ByS32RetS32(INT64_C(92233720368547758), INT32_C(2147483647));
3025	CHECKVAL(i32, INT32_C(2104533974), "%010RI32");
3026	i32 = ASMModS64ByS32RetS32(INT64_C(-92233720368547758), INT32_C(2147483647));
3027	CHECKVAL(i32, INT32_C(-2104533974), "%010RI32");
3028	}
3029
3030
3031	static void tstASMByteSwap(void)
3032	{
3033	RTTestSub(g_hTest, "ASMByteSwap*");
3034
3035	uint64_t u64In = UINT64_C(0x0011223344556677);
3036	uint64_t u64Out = ASMByteSwapU64(u64In);
3037	CHECKVAL(u64In, UINT64_C(0x0011223344556677), "%#018RX64");
3038	CHECKVAL(u64Out, UINT64_C(0x7766554433221100), "%#018RX64");
3039	u64Out = ASMByteSwapU64(u64Out);
3040	CHECKVAL(u64Out, u64In, "%#018RX64");
3041	u64In = UINT64_C(0x0123456789abcdef);
3042	u64Out = ASMByteSwapU64(u64In);
3043	CHECKVAL(u64In, UINT64_C(0x0123456789abcdef), "%#018RX64");
3044	CHECKVAL(u64Out, UINT64_C(0xefcdab8967452301), "%#018RX64");
3045	u64Out = ASMByteSwapU64(u64Out);
3046	CHECKVAL(u64Out, u64In, "%#018RX64");
3047	u64In = 0;
3048	u64Out = ASMByteSwapU64(u64In);
3049	CHECKVAL(u64Out, u64In, "%#018RX64");
3050	u64In = UINT64_MAX;
3051	u64Out = ASMByteSwapU64(u64In);
3052	CHECKVAL(u64Out, u64In, "%#018RX64");
3053
3054	uint32_t u32In = UINT32_C(0x00112233);
3055	uint32_t u32Out = ASMByteSwapU32(u32In);
3056	CHECKVAL(u32In, UINT32_C(0x00112233), "%#010RX32");
3057	CHECKVAL(u32Out, UINT32_C(0x33221100), "%#010RX32");
3058	u32Out = ASMByteSwapU32(u32Out);
3059	CHECKVAL(u32Out, u32In, "%#010RX32");
3060	u32In = UINT32_C(0x12345678);
3061	u32Out = ASMByteSwapU32(u32In);
3062	CHECKVAL(u32In, UINT32_C(0x12345678), "%#010RX32");
3063	CHECKVAL(u32Out, UINT32_C(0x78563412), "%#010RX32");
3064	u32Out = ASMByteSwapU32(u32Out);
3065	CHECKVAL(u32Out, u32In, "%#010RX32");
3066	u32In = 0;
3067	u32Out = ASMByteSwapU32(u32In);
3068	CHECKVAL(u32Out, u32In, "%#010RX32");
3069	u32In = UINT32_MAX;
3070	u32Out = ASMByteSwapU32(u32In);
3071	CHECKVAL(u32Out, u32In, "%#010RX32");
3072
3073	uint16_t u16In = UINT16_C(0x0011);
3074	uint16_t u16Out = ASMByteSwapU16(u16In);
3075	CHECKVAL(u16In, UINT16_C(0x0011), "%#06RX16");
3076	CHECKVAL(u16Out, UINT16_C(0x1100), "%#06RX16");
3077	u16Out = ASMByteSwapU16(u16Out);
3078	CHECKVAL(u16Out, u16In, "%#06RX16");
3079	u16In = UINT16_C(0x1234);
3080	u16Out = ASMByteSwapU16(u16In);
3081	CHECKVAL(u16In, UINT16_C(0x1234), "%#06RX16");
3082	CHECKVAL(u16Out, UINT16_C(0x3412), "%#06RX16");
3083	u16Out = ASMByteSwapU16(u16Out);
3084	CHECKVAL(u16Out, u16In, "%#06RX16");
3085	u16In = 0;
3086	u16Out = ASMByteSwapU16(u16In);
3087	CHECKVAL(u16Out, u16In, "%#06RX16");
3088	u16In = UINT16_MAX;
3089	u16Out = ASMByteSwapU16(u16In);
3090	CHECKVAL(u16Out, u16In, "%#06RX16");
3091	}
3092
3093
3094	static void tstASMBench(void)
3095	{
3096	/*
3097	* Make this static. We don't want to have this located on the stack.
3098	*/
3099	static uint8_t volatile s_u8;
3100	static int8_t volatile s_i8;
3101	static uint16_t volatile s_u16;
3102	static int16_t volatile s_i16;
3103	static uint32_t volatile s_u32;
3104	static int32_t volatile s_i32;
3105	static uint64_t volatile s_u64;
3106	static int64_t volatile s_i64;
3107	#if defined(RTASM_HAVE_CMP_WRITE_U128) \|\| defined(RTASM_HAVE_CMP_XCHG_U128)
3108	static RTUINT128U volatile s_u128;
3109	#endif
3110	static uint8_t s_u8Old;
3111	static int8_t s_i8Old;
3112	static uint16_t s_u16Old;
3113	static int16_t s_i16Old;
3114	static uint32_t s_u32Old;
3115	static int32_t s_i32Old;
3116	static uint64_t s_u64Old;
3117	static int64_t s_i64Old;
3118	#if defined(RTASM_HAVE_CMP_WRITE_U128) \|\| defined(RTASM_HAVE_CMP_XCHG_U128)
3119	static RTUINT128U s_u128Old;
3120	RTUINT128U u128Tmp1, u128Tmp2;
3121	# ifdef RT_ARCH_AMD64
3122	bool const fHaveCmpXchg128 = RT_BOOL(ASMCpuId_ECX(1) & X86_CPUID_FEATURE_ECX_CX16);
3123	# else
3124	bool const fHaveCmpXchg128 = true;
3125	# endif
3126	#endif
3127	unsigned i;
3128	const unsigned cRounds = _16M; /* Must be multiple of 8 */
3129	uint64_t u64Elapsed;
3130
3131	RTTestSub(g_hTest, "Benchmarking");
3132
3133	#if 0 && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32))
3134	# define BENCH(op, str) \
3135	do { \
3136	RTThreadYield(); \
3137	u64Elapsed = ASMReadTSC(); \
3138	for (i = cRounds; i > 0; i--) \
3139	op; \
3140	u64Elapsed = ASMReadTSC() - u64Elapsed; \
3141	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_TICKS_PER_CALL); \
3142	} while (0)
3143	#else
3144	# define BENCH(op, str) \
3145	do { \
3146	RTThreadYield(); \
3147	u64Elapsed = RTTimeNanoTS(); \
3148	for (i = cRounds / 8; i > 0; i--) \
3149	{ \
3150	op; \
3151	op; \
3152	op; \
3153	op; \
3154	op; \
3155	op; \
3156	op; \
3157	op; \
3158	} \
3159	u64Elapsed = RTTimeNanoTS() - u64Elapsed; \
3160	RTTestValue(g_hTest, str, u64Elapsed * 1000 / cRounds, RTTESTUNIT_PS_PER_CALL); \
3161	} while (0)
3162	#endif
3163	#if (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32)) && !defined(GCC44_32BIT_PIC)
3164	# define BENCH_TSC(op, str) \
3165	do { \
3166	RTThreadYield(); \
3167	u64Elapsed = ASMReadTSC(); \
3168	for (i = cRounds / 8; i > 0; i--) \
3169	{ \
3170	op; \
3171	op; \
3172	op; \
3173	op; \
3174	op; \
3175	op; \
3176	op; \
3177	op; \
3178	} \
3179	u64Elapsed = ASMReadTSC() - u64Elapsed; \
3180	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_TICKS_PER_CALL); \
3181	} while (0)
3182	#else
3183	# define BENCH_TSC(op, str) BENCH(op, str)
3184	#endif
3185
3186	BENCH(s_u32 = 0, "s_u32 = 0");
3187	BENCH(ASMAtomicUoReadU8(&s_u8), "ASMAtomicUoReadU8");
3188	BENCH(ASMAtomicUoReadS8(&s_i8), "ASMAtomicUoReadS8");
3189	BENCH(ASMAtomicUoReadU16(&s_u16), "ASMAtomicUoReadU16");
3190	BENCH(ASMAtomicUoReadS16(&s_i16), "ASMAtomicUoReadS16");
3191	BENCH(ASMAtomicUoReadU32(&s_u32), "ASMAtomicUoReadU32");
3192	BENCH(ASMAtomicUoReadS32(&s_i32), "ASMAtomicUoReadS32");
3193	BENCH(ASMAtomicUoReadU64(&s_u64), "ASMAtomicUoReadU64");
3194	BENCH(ASMAtomicUoReadS64(&s_i64), "ASMAtomicUoReadS64");
3195	#ifdef RTASM_HAVE_READ_U128
3196	if (fHaveCmpXchg128)
3197	{
3198	BENCH(ASMAtomicUoReadU128(&s_u128.u), "ASMAtomicUoReadU128");
3199	BENCH(ASMAtomicUoReadU128U(&s_u128), "ASMAtomicUoReadU128U");
3200	}
3201	#endif
3202	BENCH(ASMAtomicReadU8(&s_u8), "ASMAtomicReadU8");
3203	BENCH(ASMAtomicReadS8(&s_i8), "ASMAtomicReadS8");
3204	BENCH(ASMAtomicReadU16(&s_u16), "ASMAtomicReadU16");
3205	BENCH(ASMAtomicReadS16(&s_i16), "ASMAtomicReadS16");
3206	BENCH(ASMAtomicReadU32(&s_u32), "ASMAtomicReadU32");
3207	BENCH(ASMAtomicReadS32(&s_i32), "ASMAtomicReadS32");
3208	BENCH(ASMAtomicReadU64(&s_u64), "ASMAtomicReadU64");
3209	BENCH(ASMAtomicReadS64(&s_i64), "ASMAtomicReadS64");
3210	#ifdef RTASM_HAVE_READ_U128
3211	if (fHaveCmpXchg128)
3212	{
3213	BENCH(ASMAtomicReadU128(&s_u128.u), "ASMAtomicReadU128");
3214	BENCH(ASMAtomicReadU128U(&s_u128), "ASMAtomicReadU128U");
3215	}
3216	#endif
3217	BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8");
3218	BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8");
3219	BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16");
3220	BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16");
3221	BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32");
3222	BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32");
3223	BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64");
3224	BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64");
3225	#ifdef RTASM_HAVE_WRITE_U128
3226	if (fHaveCmpXchg128)
3227	{
3228	BENCH(ASMAtomicUoWriteU128(&s_u128.u, (u128Tmp1 = RTUINT128_INIT_C(0, 0)).u), "ASMAtomicUoWriteU128");
3229	BENCH(ASMAtomicUoWriteU128v2(&s_u128.u, 0, 0), "ASMAtomicUoWriteU128v2");
3230	BENCH(ASMAtomicUoWriteU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0)), "ASMAtomicUoWriteU128U");
3231	}
3232	#endif
3233	BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8");
3234	BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8");
3235	BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16");
3236	BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16");
3237	BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32");
3238	BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32");
3239	BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64");
3240	BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64");
3241	#ifdef RTASM_HAVE_WRITE_U128
3242	if (fHaveCmpXchg128)
3243	{
3244	BENCH(ASMAtomicWriteU128(&s_u128.u, (u128Tmp1 = RTUINT128_INIT_C(0, 0)).u), "ASMAtomicWriteU128");
3245	BENCH(ASMAtomicWriteU128v2(&s_u128.u, 0, 0), "ASMAtomicWriteU128v2");
3246	BENCH(ASMAtomicWriteU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0)), "ASMAtomicWriteU128U");
3247	}
3248	#endif
3249	BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8");
3250	BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8");
3251	BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16");
3252	BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16");
3253	BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32");
3254	BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32");
3255	BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64");
3256	BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64");
3257	BENCH(ASMAtomicCmpXchgU8(&s_u8, 0, 0), "ASMAtomicCmpXchgU8");
3258	BENCH(ASMAtomicCmpXchgS8(&s_i8, 0, 0), "ASMAtomicCmpXchgS8");
3259	//BENCH(ASMAtomicCmpXchgU16(&s_u16, 0, 0), "ASMAtomicCmpXchgU16");
3260	//BENCH(ASMAtomicCmpXchgS16(&s_i16, 0, 0), "ASMAtomicCmpXchgS16");
3261	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32");
3262	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32");
3263	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64");
3264	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64");
3265	#ifdef RTASM_HAVE_CMP_WRITE_U128
3266	if (fHaveCmpXchg128)
3267	BENCH(ASMAtomicCmpWriteU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0), u128Tmp2 = RTUINT128_INIT_C(0, 0)),
3268	"ASMAtomicCmpWriteU128U");
3269	#endif
3270	BENCH(ASMAtomicCmpXchgU8(&s_u8, 0, 1), "ASMAtomicCmpXchgU8/neg");
3271	BENCH(ASMAtomicCmpXchgS8(&s_i8, 0, 1), "ASMAtomicCmpXchgS8/neg");
3272	//BENCH(ASMAtomicCmpXchgU16(&s_u16, 0, 1), "ASMAtomicCmpXchgU16/neg");
3273	//BENCH(ASMAtomicCmpXchgS16(&s_s16, 0, 1), "ASMAtomicCmpXchgS16/neg");
3274	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg");
3275	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg");
3276	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg");
3277	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg");
3278	#ifdef RTASM_HAVE_CMP_WRITE_U128
3279	if (fHaveCmpXchg128)
3280	BENCH(ASMAtomicCmpWriteU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0), u128Tmp2 = RTUINT128_INIT_C(0, 1)),
3281	"ASMAtomicCmpWriteU128U/neg");
3282	#endif
3283	BENCH(ASMAtomicCmpXchgExU8(&s_u8, 0, 0, &s_u8Old), "ASMAtomicCmpXchgExU8");
3284	BENCH(ASMAtomicCmpXchgExS8(&s_i8, 0, 0, &s_i8Old), "ASMAtomicCmpXchgExS8");
3285	BENCH(ASMAtomicCmpXchgExU16(&s_u16, 0, 0, &s_u16Old), "ASMAtomicCmpXchgExU16");
3286	BENCH(ASMAtomicCmpXchgExS16(&s_i16, 0, 0, &s_i16Old), "ASMAtomicCmpXchgExS16");
3287	BENCH(ASMAtomicCmpXchgExU32(&s_u32, 0, 0, &s_u32Old), "ASMAtomicCmpXchgExU32");
3288	BENCH(ASMAtomicCmpXchgExS32(&s_i32, 0, 0, &s_i32Old), "ASMAtomicCmpXchgExS32");
3289	BENCH(ASMAtomicCmpXchgExU64(&s_u64, 0, 0, &s_u64Old), "ASMAtomicCmpXchgExU64");
3290	BENCH(ASMAtomicCmpXchgExS64(&s_i64, 0, 0, &s_i64Old), "ASMAtomicCmpXchgExS64");
3291	#ifdef RTASM_HAVE_CMP_XCHG_U128
3292	if (fHaveCmpXchg128)
3293	BENCH(ASMAtomicCmpXchgU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0), u128Tmp2 = RTUINT128_INIT_C(0, 0), &s_u128Old),
3294	"ASMAtomicCmpXchgU128U");
3295	#endif
3296	BENCH(ASMAtomicCmpXchgExU8(&s_u8, 0, 1, &s_u8Old), "ASMAtomicCmpXchgExU8/neg");
3297	BENCH(ASMAtomicCmpXchgExS8(&s_i8, 0, 1, &s_i8Old), "ASMAtomicCmpXchgExS8/neg");
3298	BENCH(ASMAtomicCmpXchgExU16(&s_u16, 0, 1, &s_u16Old), "ASMAtomicCmpXchgExU16/neg");
3299	BENCH(ASMAtomicCmpXchgExS16(&s_i16, 0, 1, &s_i16Old), "ASMAtomicCmpXchgExS16/neg");
3300	BENCH(ASMAtomicCmpXchgExU32(&s_u32, 0, 1, &s_u32Old), "ASMAtomicCmpXchgExU32/neg");
3301	BENCH(ASMAtomicCmpXchgExS32(&s_i32, 0, 1, &s_i32Old), "ASMAtomicCmpXchgExS32/neg");
3302	BENCH(ASMAtomicCmpXchgExU64(&s_u64, 0, 1, &s_u64Old), "ASMAtomicCmpXchgExU64/neg");
3303	BENCH(ASMAtomicCmpXchgExS64(&s_i64, 0, 1, &s_i64Old), "ASMAtomicCmpXchgExS64/neg");
3304	#ifdef RTASM_HAVE_CMP_XCHG_U128
3305	if (fHaveCmpXchg128)
3306	BENCH(ASMAtomicCmpXchgU128U(&s_u128, u128Tmp1 = RTUINT128_INIT_C(0, 0), u128Tmp2 = RTUINT128_INIT_C(0, 1), &s_u128Old),
3307	"ASMAtomicCmpXchgU128U/neg");
3308	#endif
3309	BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32");
3310	BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32");
3311	BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32");
3312	BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32");
3313	BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32");
3314	BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32");
3315	BENCH(ASMAtomicUoIncU32(&s_u32), "ASMAtomicUoIncU32");
3316	BENCH(ASMAtomicUoDecU32(&s_u32), "ASMAtomicUoDecU32");
3317	BENCH(ASMAtomicUoAndU32(&s_u32, 0xffffffff), "ASMAtomicUoAndU32");
3318	BENCH(ASMAtomicUoOrU32(&s_u32, 0xffffffff), "ASMAtomicUoOrU32");
3319	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3320	BENCH_TSC(ASMSerializeInstructionCpuId(), "ASMSerializeInstructionCpuId");
3321	BENCH_TSC(ASMSerializeInstructionIRet(), "ASMSerializeInstructionIRet");
3322	#endif
3323	BENCH(ASMReadFence(), "ASMReadFence");
3324	BENCH(ASMWriteFence(), "ASMWriteFence");
3325	BENCH(ASMMemoryFence(), "ASMMemoryFence");
3326	BENCH(ASMSerializeInstruction(), "ASMSerializeInstruction");
3327	BENCH(ASMNopPause(), "ASMNopPause");
3328
3329	BENCH(ASMBitFirstSetU16(s_u16), "ASMBitFirstSetU16");
3330	BENCH(ASMBitFirstSetU32(s_u32), "ASMBitFirstSetU32");
3331	BENCH(ASMBitFirstSetU64(s_u32), "ASMBitFirstSetU64");
3332	BENCH(ASMBitLastSetU16(s_u16), "ASMBitLastSetU16");
3333	BENCH(ASMBitLastSetU32(s_u32), "ASMBitLastSetU32");
3334	BENCH(ASMBitLastSetU64(s_u32), "ASMBitLastSetU64");
3335	BENCH(ASMCountLeadingZerosU16(s_u16), "ASMCountLeadingZerosU16");
3336	BENCH(ASMCountLeadingZerosU32(s_u32), "ASMCountLeadingZerosU32");
3337	BENCH(ASMCountLeadingZerosU64(s_u64), "ASMCountLeadingZerosU64");
3338	BENCH(ASMCountTrailingZerosU16(s_u16), "ASMCountTrailingZerosU16");
3339	BENCH(ASMCountTrailingZerosU32(s_u32), "ASMCountTrailingZerosU32");
3340	BENCH(ASMCountTrailingZerosU64(s_u64), "ASMCountTrailingZerosU64");
3341
3342	/* The Darwin gcc does not like this ... */
3343	#if !defined(RT_OS_DARWIN) && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
3344	BENCH(s_u8 = ASMGetApicId(), "ASMGetApicId");
3345	BENCH(s_u32 = ASMGetApicIdExt0B(), "ASMGetApicIdExt0B");
3346	BENCH(s_u32 = ASMGetApicIdExt8000001E(), "ASMGetApicIdExt8000001E");
3347	#endif
3348	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(RT_ARCH_ARM64) \|\| defined(RT_ARCH_ARM32))
3349	BENCH(s_u64 = ASMReadTSC(), "ASMReadTSC");
3350	#endif
3351	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
3352	uint32_t uAux;
3353	if ( ASMHasCpuId()
3354	&& RTX86IsValidExtRange(ASMCpuId_EAX(0x80000000))
3355	&& (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) )
3356	{
3357	BENCH_TSC(ASMSerializeInstructionRdTscp(), "ASMSerializeInstructionRdTscp");
3358	BENCH(s_u64 = ASMReadTscWithAux(&uAux), "ASMReadTscWithAux");
3359	}
3360	union
3361	{
3362	uint64_t u64[2];
3363	RTIDTR Unaligned;
3364	struct
3365	{
3366	uint16_t abPadding[3];
3367	RTIDTR Aligned;
3368	} s;
3369	} uBuf;
3370	Assert(((uintptr_t)&uBuf.Unaligned.pIdt & (sizeof(uintptr_t) - 1)) != 0);
3371	BENCH(ASMGetIDTR(&uBuf.Unaligned), "ASMGetIDTR/unaligned");
3372	Assert(((uintptr_t)&uBuf.s.Aligned.pIdt & (sizeof(uintptr_t) - 1)) == 0);
3373	BENCH(ASMGetIDTR(&uBuf.s.Aligned), "ASMGetIDTR/aligned");
3374	#endif
3375
3376	#undef BENCH
3377	}
3378
3379
3380	int main(int argc, char **argv)
3381	{
3382	RT_NOREF_PV(argc); RT_NOREF_PV(argv);
3383
3384	int rc = RTTestInitAndCreate("tstRTInlineAsm", &g_hTest);
3385	if (rc)
3386	return rc;
3387	RTTestBanner(g_hTest);
3388
3389	/*
3390	* Execute the tests.
3391	*/
3392	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
3393	tstASMCpuId();
3394	//bruteForceCpuId();
3395	#endif
3396	#if 1
3397	tstASMAtomicRead();
3398	tstASMAtomicWrite();
3399	tstASMAtomicXchg();
3400	tstASMAtomicCmpXchg();
3401	tstASMAtomicCmpXchgEx();
3402
3403	tstASMAtomicAdd();
3404	tstASMAtomicDecInc();
3405	tstASMAtomicAndOrXor();
3406
3407	tstASMMemFirstMismatchingU8(g_hTest);
3408	tstASMMemZero32();
3409	tstASMMemFill32();
3410	tstASMProbe(g_hTest);
3411
3412	tstASMMisc();
3413
3414	tstASMBit();
3415
3416	tstASMMath();
3417
3418	tstASMByteSwap();
3419
3420	tstASMBench();
3421	#endif
3422
3423	/*
3424	* Show the result.
3425	*/
3426	return RTTestSummaryAndDestroy(g_hTest);
3427	}
3428

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source: vbox/trunk/src/VBox/Runtime/testcase/tstRTInlineAsm.cpp@ 106061

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