tstRTInlineAsm.cpp@ 66404

Last change on this file since 66404 was 65161, checked in by vboxsync, 8 years ago
tstRTInlineAsm: Skylake fix
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File size: 73.7 KB

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1	/* $Id: tstRTInlineAsm.cpp 65161 2017-01-05 17:15:36Z vboxsync $ */
2	/** @file
3	* IPRT Testcase - inline assembly.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27
28	/*********************************************************************************************************************************
29	* Header Files *
30	*********************************************************************************************************************************/
31	#include <iprt/asm.h>
32	#include <iprt/asm-math.h>
33
34	/* See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44018. Only gcc version 4.4
35	* is affected. No harm for the VBox code: If the cpuid code compiles, it works
36	* fine. */
37	#if defined(__GNUC__) && defined(RT_ARCH_X86) && defined(__PIC__)
38	# if __GNUC__ == 4 && __GNUC_MINOR__ == 4
39	# define GCC44_32BIT_PIC
40	# endif
41	#endif
42
43	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
44	# include <iprt/asm-amd64-x86.h>
45	# include <iprt/x86.h>
46	#else
47	# include <iprt/time.h>
48	#endif
49	#include <iprt/rand.h>
50	#include <iprt/stream.h>
51	#include <iprt/string.h>
52	#include <iprt/param.h>
53	#include <iprt/thread.h>
54	#include <iprt/test.h>
55	#include <iprt/time.h>
56
57
58
59	/*********************************************************************************************************************************
60	* Defined Constants And Macros *
61	*********************************************************************************************************************************/
62	#define CHECKVAL(val, expect, fmt) \
63	do \
64	{ \
65	if ((val) != (expect)) \
66	{ \
67	RTTestFailed(g_hTest, "%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
68	} \
69	} while (0)
70
71	#define CHECKOP(op, expect, fmt, type) \
72	do \
73	{ \
74	type val = op; \
75	if (val != (type)(expect)) \
76	{ \
77	RTTestFailed(g_hTest, "%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
78	} \
79	} while (0)
80
81	/**
82	* Calls a worker function with different worker variable storage types.
83	*/
84	#define DO_SIMPLE_TEST(name, type) \
85	do \
86	{ \
87	RTTestISub(#name); \
88	type StackVar; \
89	tst ## name ## Worker(&StackVar); \
90	\
91	type pVar = (type )RTTestGuardedAllocHead(g_hTest, sizeof(type)); \
92	RTTEST_CHECK_BREAK(g_hTest, pVar); \
93	tst ## name ## Worker(pVar); \
94	RTTestGuardedFree(g_hTest, pVar); \
95	\
96	pVar = (type *)RTTestGuardedAllocTail(g_hTest, sizeof(type)); \
97	RTTEST_CHECK_BREAK(g_hTest, pVar); \
98	tst ## name ## Worker(pVar); \
99	RTTestGuardedFree(g_hTest, pVar); \
100	} while (0)
101
102
103	/*********************************************************************************************************************************
104	* Global Variables *
105	*********************************************************************************************************************************/
106	/** The test instance. */
107	static RTTEST g_hTest;
108
109
110
111	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
112
113	const char *getCacheAss(unsigned u)
114	{
115	if (u == 0)
116	return "res0 ";
117	if (u == 1)
118	return "direct";
119	if (u >= 256)
120	return "???";
121
122	char *pszRet;
123	RTStrAPrintf(&pszRet, "%d way", u); /* intentional leak! */
124	return pszRet;
125	}
126
127
128	const char *getL2CacheAss(unsigned u)
129	{
130	switch (u)
131	{
132	case 0: return "off ";
133	case 1: return "direct";
134	case 2: return "2 way ";
135	case 3: return "res3 ";
136	case 4: return "4 way ";
137	case 5: return "res5 ";
138	case 6: return "8 way ";
139	case 7: return "res7 ";
140	case 8: return "16 way";
141	case 9: return "res9 ";
142	case 10: return "res10 ";
143	case 11: return "res11 ";
144	case 12: return "res12 ";
145	case 13: return "res13 ";
146	case 14: return "res14 ";
147	case 15: return "fully ";
148	default:
149	return "????";
150	}
151	}
152
153
154	/**
155	* Test and dump all possible info from the CPUID instruction.
156	*
157	* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
158	* @todo transform the dumping into a generic runtime function. We'll need it for logging!
159	*/
160	void tstASMCpuId(void)
161	{
162	RTTestISub("ASMCpuId");
163
164	unsigned iBit;
165	struct
166	{
167	uint32_t uEBX, uEAX, uEDX, uECX;
168	} s;
169	if (!ASMHasCpuId())
170	{
171	RTTestIPrintf(RTTESTLVL_ALWAYS, "warning! CPU doesn't support CPUID\n");
172	return;
173	}
174
175	/*
176	* Try the 0 function and use that for checking the ASMCpuId_* variants.
177	*/
178	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
179
180	uint32_t u32;
181
182	u32 = ASMCpuId_EAX(0);
183	CHECKVAL(u32, s.uEAX, "%x");
184	u32 = ASMCpuId_EBX(0);
185	CHECKVAL(u32, s.uEBX, "%x");
186	u32 = ASMCpuId_ECX(0);
187	CHECKVAL(u32, s.uECX, "%x");
188	u32 = ASMCpuId_EDX(0);
189	CHECKVAL(u32, s.uEDX, "%x");
190
191	uint32_t uECX2 = s.uECX - 1;
192	uint32_t uEDX2 = s.uEDX - 1;
193	ASMCpuId_ECX_EDX(0, &uECX2, &uEDX2);
194	CHECKVAL(uECX2, s.uECX, "%x");
195	CHECKVAL(uEDX2, s.uEDX, "%x");
196
197	uint32_t uEAX2 = s.uEAX - 1;
198	uint32_t uEBX2 = s.uEBX - 1;
199	uECX2 = s.uECX - 1;
200	uEDX2 = s.uEDX - 1;
201	ASMCpuIdExSlow(0, 0, 0, 0, &uEAX2, &uEBX2, &uECX2, &uEDX2);
202	CHECKVAL(uEAX2, s.uEAX, "%x");
203	CHECKVAL(uEBX2, s.uEBX, "%x");
204	CHECKVAL(uECX2, s.uECX, "%x");
205	CHECKVAL(uEDX2, s.uEDX, "%x");
206
207	/*
208	* Done testing, dump the information.
209	*/
210	RTTestIPrintf(RTTESTLVL_ALWAYS, "CPUID Dump\n");
211	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
212	const uint32_t cFunctions = s.uEAX;
213
214	/* raw dump */
215	RTTestIPrintf(RTTESTLVL_ALWAYS,
216	"\n"
217	" RAW Standard CPUIDs\n"
218	"Function eax ebx ecx edx\n");
219	for (unsigned iStd = 0; iStd <= cFunctions + 3; iStd++)
220	{
221	ASMCpuId_Idx_ECX(iStd, 0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
222	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
223	iStd, s.uEAX, s.uEBX, s.uECX, s.uEDX, iStd <= cFunctions ? "" : "*");
224
225	/* Some leafs output depend on the initial value of ECX.
226	* The same seems to apply to invalid standard functions */
227	if (iStd > cFunctions)
228	continue;
229	if ( iStd != 0x04 /* Deterministic Cache Parameters Leaf */
230	&& iStd != 0x07 /* Structured Extended Feature Flags */
231	&& iStd != 0x0b /* Extended Topology Enumeration Leafs */
232	&& iStd != 0x0d /* Extended State Enumeration Leafs */
233	&& iStd != 0x14 /* Trace Enumeration Leafs */)
234	{
235	u32 = ASMCpuId_EAX(iStd);
236	CHECKVAL(u32, s.uEAX, "%x");
237
238	uint32_t u32EbxMask = UINT32_MAX;
239	if (iStd == 1)
240	u32EbxMask = UINT32_C(0x00ffffff); /* Omit the local apic ID in case we're rescheduled. */
241	u32 = ASMCpuId_EBX(iStd);
242	CHECKVAL(u32 & u32EbxMask, s.uEBX & u32EbxMask, "%x");
243
244	u32 = ASMCpuId_ECX(iStd);
245	CHECKVAL(u32, s.uECX, "%x");
246	u32 = ASMCpuId_EDX(iStd);
247	CHECKVAL(u32, s.uEDX, "%x");
248
249	uECX2 = s.uECX - 1;
250	uEDX2 = s.uEDX - 1;
251	ASMCpuId_ECX_EDX(iStd, &uECX2, &uEDX2);
252	CHECKVAL(uECX2, s.uECX, "%x");
253	CHECKVAL(uEDX2, s.uEDX, "%x");
254	}
255
256	if (iStd == 0x04)
257	for (uint32_t uECX = 1; s.uEAX & 0x1f; uECX++)
258	{
259	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
260	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
261	RTTESTI_CHECK_BREAK(uECX < 128);
262	}
263	else if (iStd == 0x07)
264	{
265	uint32_t uMax = s.uEAX;
266	for (uint32_t uECX = 1; uECX < uMax; uECX++)
267	{
268	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
269	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
270	RTTESTI_CHECK_BREAK(uECX < 128);
271	}
272	}
273	else if (iStd == 0x0b)
274	for (uint32_t uECX = 1; (s.uEAX & 0x1f) && (s.uEBX & 0xffff); uECX++)
275	{
276	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
277	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
278	RTTESTI_CHECK_BREAK(uECX < 128);
279	}
280	else if (iStd == 0x0d)
281	for (uint32_t uECX = 1; s.uEAX != 0 \|\| s.uEBX != 0 \|\| s.uECX != 0 \|\| s.uEDX != 0; uECX++)
282	{
283	ASMCpuId_Idx_ECX(iStd, uECX, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
284	RTTestIPrintf(RTTESTLVL_ALWAYS, " [%02x] %08x %08x %08x %08x\n", uECX, s.uEAX, s.uEBX, s.uECX, s.uEDX);
285	RTTESTI_CHECK_BREAK(uECX < 128);
286	}
287	}
288
289	/*
290	* Understandable output
291	*/
292	ASMCpuId(0, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
293	RTTestIPrintf(RTTESTLVL_ALWAYS,
294	"Name: %.04s%.04s%.04s\n"
295	"Support: 0-%u\n",
296	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
297	bool const fIntel = ASMIsIntelCpuEx(s.uEBX, s.uECX, s.uEDX);
298
299	/*
300	* Get Features.
301	*/
302	if (cFunctions >= 1)
303	{
304	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
305	ASMCpuId(1, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
306	RTTestIPrintf(RTTESTLVL_ALWAYS,
307	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
308	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
309	"Stepping: %d\n"
310	"Type: %d (%s)\n"
311	"APIC ID: %#04x\n"
312	"Logical CPUs: %d\n"
313	"CLFLUSH Size: %d\n"
314	"Brand ID: %#04x\n",
315	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
316	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
317	ASMGetCpuStepping(s.uEAX),
318	(s.uEAX >> 12) & 0x3, s_apszTypes[(s.uEAX >> 12) & 0x3],
319	(s.uEBX >> 24) & 0xff,
320	(s.uEBX >> 16) & 0xff,
321	(s.uEBX >> 8) & 0xff,
322	(s.uEBX >> 0) & 0xff);
323
324	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
325	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
326	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
327	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
328	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
329	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
330	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
331	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
332	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
333	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX8");
334	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
335	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
336	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SEP");
337	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
338	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
339	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
340	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
341	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
342	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
343	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSN");
344	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CLFSH");
345	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 20");
346	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DS");
347	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " ACPI");
348	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
349	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
350	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE");
351	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE2");
352	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SS");
353	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " HTT");
354	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 29");
355	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 30");
356	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 31");
357	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
358
359	/** @todo check intel docs. */
360	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
361	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SSE3");
362	for (iBit = 1; iBit < 13; iBit++)
363	if (s.uECX & RT_BIT(iBit))
364	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
365	if (s.uECX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CX16");
366	for (iBit = 14; iBit < 32; iBit++)
367	if (s.uECX & RT_BIT(iBit))
368	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
369	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
370	}
371
372	/*
373	* Extended.
374	* Implemented after AMD specs.
375	*/
376	/** @todo check out the intel specs. */
377	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
378	if (!s.uEAX && !s.uEBX && !s.uECX && !s.uEDX)
379	{
380	RTTestIPrintf(RTTESTLVL_ALWAYS, "No extended CPUID info? Check the manual on how to detect this...\n");
381	return;
382	}
383	const uint32_t cExtFunctions = s.uEAX \| 0x80000000;
384
385	/* raw dump */
386	RTTestIPrintf(RTTESTLVL_ALWAYS,
387	"\n"
388	" RAW Extended CPUIDs\n"
389	"Function eax ebx ecx edx\n");
390	for (unsigned iExt = 0x80000000; iExt <= cExtFunctions + 3; iExt++)
391	{
392	ASMCpuId(iExt, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
393	RTTestIPrintf(RTTESTLVL_ALWAYS, "%08x %08x %08x %08x %08x%s\n",
394	iExt, s.uEAX, s.uEBX, s.uECX, s.uEDX, iExt <= cExtFunctions ? "" : "*");
395
396	if (iExt > cExtFunctions)
397	continue; /* Invalid extended functions seems change the value if ECX changes */
398	if (iExt == 0x8000001d)
399	continue; /* Takes cache level in ecx. */
400
401	u32 = ASMCpuId_EAX(iExt);
402	CHECKVAL(u32, s.uEAX, "%x");
403	u32 = ASMCpuId_EBX(iExt);
404	CHECKVAL(u32, s.uEBX, "%x");
405	u32 = ASMCpuId_ECX(iExt);
406	CHECKVAL(u32, s.uECX, "%x");
407	u32 = ASMCpuId_EDX(iExt);
408	CHECKVAL(u32, s.uEDX, "%x");
409
410	uECX2 = s.uECX - 1;
411	uEDX2 = s.uEDX - 1;
412	ASMCpuId_ECX_EDX(iExt, &uECX2, &uEDX2);
413	CHECKVAL(uECX2, s.uECX, "%x");
414	CHECKVAL(uEDX2, s.uEDX, "%x");
415	}
416
417	/*
418	* Understandable output
419	*/
420	ASMCpuId(0x80000000, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
421	RTTestIPrintf(RTTESTLVL_ALWAYS,
422	"Ext Name: %.4s%.4s%.4s\n"
423	"Ext Supports: 0x80000000-%#010x\n",
424	&s.uEBX, &s.uEDX, &s.uECX, s.uEAX);
425
426	if (cExtFunctions >= 0x80000001)
427	{
428	ASMCpuId(0x80000001, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
429	RTTestIPrintf(RTTESTLVL_ALWAYS,
430	"Family: %#x \tExtended: %#x \tEffective: %#x\n"
431	"Model: %#x \tExtended: %#x \tEffective: %#x\n"
432	"Stepping: %d\n"
433	"Brand ID: %#05x\n",
434	(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ASMGetCpuFamily(s.uEAX),
435	(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ASMGetCpuModel(s.uEAX, fIntel),
436	ASMGetCpuStepping(s.uEAX),
437	s.uEBX & 0xfff);
438
439	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features EDX: ");
440	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FPU");
441	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VME");
442	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " DE");
443	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE");
444	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TSC");
445	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MSR");
446	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAE");
447	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCE");
448	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMPXCHG8B");
449	if (s.uEDX & RT_BIT(9)) RTTestIPrintf(RTTESTLVL_ALWAYS, " APIC");
450	if (s.uEDX & RT_BIT(10)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 10");
451	if (s.uEDX & RT_BIT(11)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SysCallSysRet");
452	if (s.uEDX & RT_BIT(12)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MTRR");
453	if (s.uEDX & RT_BIT(13)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PGE");
454	if (s.uEDX & RT_BIT(14)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MCA");
455	if (s.uEDX & RT_BIT(15)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CMOV");
456	if (s.uEDX & RT_BIT(16)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PAT");
457	if (s.uEDX & RT_BIT(17)) RTTestIPrintf(RTTESTLVL_ALWAYS, " PSE36");
458	if (s.uEDX & RT_BIT(18)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 18");
459	if (s.uEDX & RT_BIT(19)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 19");
460	if (s.uEDX & RT_BIT(20)) RTTestIPrintf(RTTESTLVL_ALWAYS, " NX");
461	if (s.uEDX & RT_BIT(21)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 21");
462	if (s.uEDX & RT_BIT(22)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MmxExt");
463	if (s.uEDX & RT_BIT(23)) RTTestIPrintf(RTTESTLVL_ALWAYS, " MMX");
464	if (s.uEDX & RT_BIT(24)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FXSR");
465	if (s.uEDX & RT_BIT(25)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FastFXSR");
466	if (s.uEDX & RT_BIT(26)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 26");
467	if (s.uEDX & RT_BIT(27)) RTTestIPrintf(RTTESTLVL_ALWAYS, " RDTSCP");
468	if (s.uEDX & RT_BIT(28)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 28");
469	if (s.uEDX & RT_BIT(29)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LongMode");
470	if (s.uEDX & RT_BIT(30)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNowExt");
471	if (s.uEDX & RT_BIT(31)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3DNow");
472	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
473
474	RTTestIPrintf(RTTESTLVL_ALWAYS, "Features ECX: ");
475	if (s.uECX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " LahfSahf");
476	if (s.uECX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " CmpLegacy");
477	if (s.uECX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " SVM");
478	if (s.uECX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 3");
479	if (s.uECX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " AltMovCr8");
480	for (iBit = 5; iBit < 32; iBit++)
481	if (s.uECX & RT_BIT(iBit))
482	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
483	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
484	}
485
486	char szString[443+1] = {0};
487	if (cExtFunctions >= 0x80000002)
488	ASMCpuId(0x80000002, &szString[0 + 0], &szString[0 + 4], &szString[0 + 8], &szString[0 + 12]);
489	if (cExtFunctions >= 0x80000003)
490	ASMCpuId(0x80000003, &szString[16 + 0], &szString[16 + 4], &szString[16 + 8], &szString[16 + 12]);
491	if (cExtFunctions >= 0x80000004)
492	ASMCpuId(0x80000004, &szString[32 + 0], &szString[32 + 4], &szString[32 + 8], &szString[32 + 12]);
493	if (cExtFunctions >= 0x80000002)
494	RTTestIPrintf(RTTESTLVL_ALWAYS, "Full Name: %s\n", szString);
495
496	if (cExtFunctions >= 0x80000005)
497	{
498	ASMCpuId(0x80000005, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
499	RTTestIPrintf(RTTESTLVL_ALWAYS,
500	"TLB 2/4M Instr/Uni: %s %3d entries\n"
501	"TLB 2/4M Data: %s %3d entries\n",
502	getCacheAss((s.uEAX >> 8) & 0xff), (s.uEAX >> 0) & 0xff,
503	getCacheAss((s.uEAX >> 24) & 0xff), (s.uEAX >> 16) & 0xff);
504	RTTestIPrintf(RTTESTLVL_ALWAYS,
505	"TLB 4K Instr/Uni: %s %3d entries\n"
506	"TLB 4K Data: %s %3d entries\n",
507	getCacheAss((s.uEBX >> 8) & 0xff), (s.uEBX >> 0) & 0xff,
508	getCacheAss((s.uEBX >> 24) & 0xff), (s.uEBX >> 16) & 0xff);
509	RTTestIPrintf(RTTESTLVL_ALWAYS,
510	"L1 Instr Cache Line Size: %d bytes\n"
511	"L1 Instr Cache Lines Per Tag: %d\n"
512	"L1 Instr Cache Associativity: %s\n"
513	"L1 Instr Cache Size: %d KB\n",
514	(s.uEDX >> 0) & 0xff,
515	(s.uEDX >> 8) & 0xff,
516	getCacheAss((s.uEDX >> 16) & 0xff),
517	(s.uEDX >> 24) & 0xff);
518	RTTestIPrintf(RTTESTLVL_ALWAYS,
519	"L1 Data Cache Line Size: %d bytes\n"
520	"L1 Data Cache Lines Per Tag: %d\n"
521	"L1 Data Cache Associativity: %s\n"
522	"L1 Data Cache Size: %d KB\n",
523	(s.uECX >> 0) & 0xff,
524	(s.uECX >> 8) & 0xff,
525	getCacheAss((s.uECX >> 16) & 0xff),
526	(s.uECX >> 24) & 0xff);
527	}
528
529	if (cExtFunctions >= 0x80000006)
530	{
531	ASMCpuId(0x80000006, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
532	RTTestIPrintf(RTTESTLVL_ALWAYS,
533	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
534	"L2 TLB 2/4M Data: %s %4d entries\n",
535	getL2CacheAss((s.uEAX >> 12) & 0xf), (s.uEAX >> 0) & 0xfff,
536	getL2CacheAss((s.uEAX >> 28) & 0xf), (s.uEAX >> 16) & 0xfff);
537	RTTestIPrintf(RTTESTLVL_ALWAYS,
538	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
539	"L2 TLB 4K Data: %s %4d entries\n",
540	getL2CacheAss((s.uEBX >> 12) & 0xf), (s.uEBX >> 0) & 0xfff,
541	getL2CacheAss((s.uEBX >> 28) & 0xf), (s.uEBX >> 16) & 0xfff);
542	RTTestIPrintf(RTTESTLVL_ALWAYS,
543	"L2 Cache Line Size: %d bytes\n"
544	"L2 Cache Lines Per Tag: %d\n"
545	"L2 Cache Associativity: %s\n"
546	"L2 Cache Size: %d KB\n",
547	(s.uEDX >> 0) & 0xff,
548	(s.uEDX >> 8) & 0xf,
549	getL2CacheAss((s.uEDX >> 12) & 0xf),
550	(s.uEDX >> 16) & 0xffff);
551	}
552
553	if (cExtFunctions >= 0x80000007)
554	{
555	ASMCpuId(0x80000007, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
556	RTTestIPrintf(RTTESTLVL_ALWAYS, "APM Features: ");
557	if (s.uEDX & RT_BIT(0)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TS");
558	if (s.uEDX & RT_BIT(1)) RTTestIPrintf(RTTESTLVL_ALWAYS, " FID");
559	if (s.uEDX & RT_BIT(2)) RTTestIPrintf(RTTESTLVL_ALWAYS, " VID");
560	if (s.uEDX & RT_BIT(3)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TTP");
561	if (s.uEDX & RT_BIT(4)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TM");
562	if (s.uEDX & RT_BIT(5)) RTTestIPrintf(RTTESTLVL_ALWAYS, " STC");
563	if (s.uEDX & RT_BIT(6)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 6");
564	if (s.uEDX & RT_BIT(7)) RTTestIPrintf(RTTESTLVL_ALWAYS, " 7");
565	if (s.uEDX & RT_BIT(8)) RTTestIPrintf(RTTESTLVL_ALWAYS, " TscInvariant");
566	for (iBit = 9; iBit < 32; iBit++)
567	if (s.uEDX & RT_BIT(iBit))
568	RTTestIPrintf(RTTESTLVL_ALWAYS, " %d", iBit);
569	RTTestIPrintf(RTTESTLVL_ALWAYS, "\n");
570	}
571
572	if (cExtFunctions >= 0x80000008)
573	{
574	ASMCpuId(0x80000008, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
575	RTTestIPrintf(RTTESTLVL_ALWAYS,
576	"Physical Address Width: %d bits\n"
577	"Virtual Address Width: %d bits\n"
578	"Guest Physical Address Width: %d bits\n",
579	(s.uEAX >> 0) & 0xff,
580	(s.uEAX >> 8) & 0xff,
581	(s.uEAX >> 16) & 0xff);
582	RTTestIPrintf(RTTESTLVL_ALWAYS,
583	"Physical Core Count: %d\n",
584	((s.uECX >> 0) & 0xff) + 1);
585	if ((s.uECX >> 12) & 0xf)
586	RTTestIPrintf(RTTESTLVL_ALWAYS, "ApicIdCoreIdSize: %d bits\n", (s.uECX >> 12) & 0xf);
587	}
588
589	if (cExtFunctions >= 0x8000000a)
590	{
591	ASMCpuId(0x8000000a, &s.uEAX, &s.uEBX, &s.uECX, &s.uEDX);
592	RTTestIPrintf(RTTESTLVL_ALWAYS,
593	"SVM Revision: %d (%#x)\n"
594	"Number of Address Space IDs: %d (%#x)\n",
595	s.uEAX & 0xff, s.uEAX & 0xff,
596	s.uEBX, s.uEBX);
597	}
598	}
599
600	# if 0
601	static void bruteForceCpuId(void)
602	{
603	RTTestISub("brute force CPUID leafs");
604	uint32_t auPrevValues[4] = { 0, 0, 0, 0};
605	uint32_t uLeaf = 0;
606	do
607	{
608	uint32_t auValues[4];
609	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auValues[0], &auValues[1], &auValues[2], &auValues[3]);
610	if ( (auValues[0] != auPrevValues[0] && auValues[0] != uLeaf)
611	\|\| (auValues[1] != auPrevValues[1] && auValues[1] != 0)
612	\|\| (auValues[2] != auPrevValues[2] && auValues[2] != 0)
613	\|\| (auValues[3] != auPrevValues[3] && auValues[3] != 0)
614	\|\| (uLeaf & (UINT32_C(0x08000000) - UINT32_C(1))) == 0)
615	{
616	RTTestIPrintf(RTTESTLVL_ALWAYS,
617	"%08x: %08x %08x %08x %08x\n", uLeaf,
618	auValues[0], auValues[1], auValues[2], auValues[3]);
619	}
620	auPrevValues[0] = auValues[0];
621	auPrevValues[1] = auValues[1];
622	auPrevValues[2] = auValues[2];
623	auPrevValues[3] = auValues[3];
624
625	//uint32_t uSubLeaf = 0;
626	//do
627	//{
628	//
629	//
630	//} while (false);
631	} while (uLeaf++ < UINT32_MAX);
632	}
633	# endif
634
635	#endif /* AMD64 \|\| X86 */
636
637	DECLINLINE(void) tstASMAtomicXchgU8Worker(uint8_t volatile *pu8)
638	{
639	*pu8 = 0;
640	CHECKOP(ASMAtomicXchgU8(pu8, 1), 0, "%#x", uint8_t);
641	CHECKVAL(*pu8, 1, "%#x");
642
643	CHECKOP(ASMAtomicXchgU8(pu8, 0), 1, "%#x", uint8_t);
644	CHECKVAL(*pu8, 0, "%#x");
645
646	CHECKOP(ASMAtomicXchgU8(pu8, UINT8_C(0xff)), 0, "%#x", uint8_t);
647	CHECKVAL(*pu8, 0xff, "%#x");
648
649	CHECKOP(ASMAtomicXchgU8(pu8, UINT8_C(0x87)), UINT8_C(0xff), "%#x", uint8_t);
650	CHECKVAL(*pu8, 0x87, "%#x");
651	}
652
653
654	static void tstASMAtomicXchgU8(void)
655	{
656	DO_SIMPLE_TEST(ASMAtomicXchgU8, uint8_t);
657	}
658
659
660	DECLINLINE(void) tstASMAtomicXchgU16Worker(uint16_t volatile *pu16)
661	{
662	*pu16 = 0;
663
664	CHECKOP(ASMAtomicXchgU16(pu16, 1), 0, "%#x", uint16_t);
665	CHECKVAL(*pu16, 1, "%#x");
666
667	CHECKOP(ASMAtomicXchgU16(pu16, 0), 1, "%#x", uint16_t);
668	CHECKVAL(*pu16, 0, "%#x");
669
670	CHECKOP(ASMAtomicXchgU16(pu16, 0xffff), 0, "%#x", uint16_t);
671	CHECKVAL(*pu16, 0xffff, "%#x");
672
673	CHECKOP(ASMAtomicXchgU16(pu16, 0x8765), 0xffff, "%#x", uint16_t);
674	CHECKVAL(*pu16, 0x8765, "%#x");
675	}
676
677
678	static void tstASMAtomicXchgU16(void)
679	{
680	DO_SIMPLE_TEST(ASMAtomicXchgU16, uint16_t);
681	}
682
683
684	DECLINLINE(void) tstASMAtomicXchgU32Worker(uint32_t volatile *pu32)
685	{
686	*pu32 = 0;
687
688	CHECKOP(ASMAtomicXchgU32(pu32, 1), 0, "%#x", uint32_t);
689	CHECKVAL(*pu32, 1, "%#x");
690
691	CHECKOP(ASMAtomicXchgU32(pu32, 0), 1, "%#x", uint32_t);
692	CHECKVAL(*pu32, 0, "%#x");
693
694	CHECKOP(ASMAtomicXchgU32(pu32, ~UINT32_C(0)), 0, "%#x", uint32_t);
695	CHECKVAL(*pu32, ~UINT32_C(0), "%#x");
696
697	CHECKOP(ASMAtomicXchgU32(pu32, 0x87654321), ~UINT32_C(0), "%#x", uint32_t);
698	CHECKVAL(*pu32, 0x87654321, "%#x");
699	}
700
701
702	static void tstASMAtomicXchgU32(void)
703	{
704	DO_SIMPLE_TEST(ASMAtomicXchgU32, uint32_t);
705	}
706
707
708	DECLINLINE(void) tstASMAtomicXchgU64Worker(uint64_t volatile *pu64)
709	{
710	*pu64 = 0;
711
712	CHECKOP(ASMAtomicXchgU64(pu64, 1), UINT64_C(0), "%#llx", uint64_t);
713	CHECKVAL(*pu64, UINT64_C(1), "%#llx");
714
715	CHECKOP(ASMAtomicXchgU64(pu64, 0), UINT64_C(1), "%#llx", uint64_t);
716	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
717
718	CHECKOP(ASMAtomicXchgU64(pu64, ~UINT64_C(0)), UINT64_C(0), "%#llx", uint64_t);
719	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
720
721	CHECKOP(ASMAtomicXchgU64(pu64, UINT64_C(0xfedcba0987654321)), ~UINT64_C(0), "%#llx", uint64_t);
722	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
723	}
724
725
726	static void tstASMAtomicXchgU64(void)
727	{
728	DO_SIMPLE_TEST(ASMAtomicXchgU64, uint64_t);
729	}
730
731
732	DECLINLINE(void) tstASMAtomicXchgPtrWorker(void * volatile *ppv)
733	{
734	*ppv = NULL;
735
736	CHECKOP(ASMAtomicXchgPtr(ppv, (void )(~(uintptr_t)0)), NULL, "%p", void );
737	CHECKVAL(ppv, (void )(~(uintptr_t)0), "%p");
738
739	CHECKOP(ASMAtomicXchgPtr(ppv, (void )0x87654321), (void )(~(uintptr_t)0), "%p", void *);
740	CHECKVAL(ppv, (void )0x87654321, "%p");
741
742	CHECKOP(ASMAtomicXchgPtr(ppv, NULL), (void )0x87654321, "%p", void );
743	CHECKVAL(*ppv, NULL, "%p");
744	}
745
746
747	static void tstASMAtomicXchgPtr(void)
748	{
749	DO_SIMPLE_TEST(ASMAtomicXchgPtr, void *);
750	}
751
752
753	DECLINLINE(void) tstASMAtomicCmpXchgU8Worker(uint8_t volatile *pu8)
754	{
755	*pu8 = 0xff;
756
757	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0), false, "%d", bool);
758	CHECKVAL(*pu8, 0xff, "%x");
759
760	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0, 0xff), true, "%d", bool);
761	CHECKVAL(*pu8, 0, "%x");
762
763	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x79, 0xff), false, "%d", bool);
764	CHECKVAL(*pu8, 0, "%x");
765
766	CHECKOP(ASMAtomicCmpXchgU8(pu8, 0x97, 0), true, "%d", bool);
767	CHECKVAL(*pu8, 0x97, "%x");
768	}
769
770
771	static void tstASMAtomicCmpXchgU8(void)
772	{
773	DO_SIMPLE_TEST(ASMAtomicCmpXchgU8, uint8_t);
774	}
775
776
777	DECLINLINE(void) tstASMAtomicCmpXchgU32Worker(uint32_t volatile *pu32)
778	{
779	*pu32 = UINT32_C(0xffffffff);
780
781	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, 0), false, "%d", bool);
782	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
783
784	CHECKOP(ASMAtomicCmpXchgU32(pu32, 0, UINT32_C(0xffffffff)), true, "%d", bool);
785	CHECKVAL(*pu32, 0, "%x");
786
787	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff)), false, "%d", bool);
788	CHECKVAL(*pu32, 0, "%x");
789
790	CHECKOP(ASMAtomicCmpXchgU32(pu32, UINT32_C(0x8008efd), 0), true, "%d", bool);
791	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
792	}
793
794
795	static void tstASMAtomicCmpXchgU32(void)
796	{
797	DO_SIMPLE_TEST(ASMAtomicCmpXchgU32, uint32_t);
798	}
799
800
801
802	DECLINLINE(void) tstASMAtomicCmpXchgU64Worker(uint64_t volatile *pu64)
803	{
804	*pu64 = UINT64_C(0xffffffffffffff);
805
806	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, 0), false, "%d", bool);
807	CHECKVAL(*pu64, UINT64_C(0xffffffffffffff), "%#llx");
808
809	CHECKOP(ASMAtomicCmpXchgU64(pu64, 0, UINT64_C(0xffffffffffffff)), true, "%d", bool);
810	CHECKVAL(*pu64, 0, "%x");
811
812	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff)), false, "%d", bool);
813	CHECKVAL(*pu64, 0, "%x");
814
815	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000)), false, "%d", bool);
816	CHECKVAL(*pu64, 0, "%x");
817
818	CHECKOP(ASMAtomicCmpXchgU64(pu64, UINT64_C(0x80040008008efd), 0), true, "%d", bool);
819	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%#llx");
820	}
821
822
823	static void tstASMAtomicCmpXchgU64(void)
824	{
825	DO_SIMPLE_TEST(ASMAtomicCmpXchgU64, uint64_t);
826	}
827
828
829	DECLINLINE(void) tstASMAtomicCmpXchgExU32Worker(uint32_t volatile *pu32)
830	{
831	*pu32 = UINT32_C(0xffffffff);
832	uint32_t u32Old = UINT32_C(0x80005111);
833
834	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, 0, &u32Old), false, "%d", bool);
835	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
836	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
837
838	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0xffffffff), &u32Old), true, "%d", bool);
839	CHECKVAL(*pu32, 0, "%x");
840	CHECKVAL(u32Old, UINT32_C(0xffffffff), "%x");
841
842	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), UINT32_C(0xffffffff), &u32Old), false, "%d", bool);
843	CHECKVAL(*pu32, 0, "%x");
844	CHECKVAL(u32Old, 0, "%x");
845
846	CHECKOP(ASMAtomicCmpXchgExU32(pu32, UINT32_C(0x8008efd), 0, &u32Old), true, "%d", bool);
847	CHECKVAL(*pu32, UINT32_C(0x8008efd), "%x");
848	CHECKVAL(u32Old, 0, "%x");
849
850	CHECKOP(ASMAtomicCmpXchgExU32(pu32, 0, UINT32_C(0x8008efd), &u32Old), true, "%d", bool);
851	CHECKVAL(*pu32, 0, "%x");
852	CHECKVAL(u32Old, UINT32_C(0x8008efd), "%x");
853	}
854
855
856	static void tstASMAtomicCmpXchgExU32(void)
857	{
858	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU32, uint32_t);
859	}
860
861
862	DECLINLINE(void) tstASMAtomicCmpXchgExU64Worker(uint64_t volatile *pu64)
863	{
864	*pu64 = UINT64_C(0xffffffffffffffff);
865	uint64_t u64Old = UINT64_C(0x8000000051111111);
866
867	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, 0, &u64Old), false, "%d", bool);
868	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%llx");
869	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
870
871	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0xffffffffffffffff), &u64Old), true, "%d", bool);
872	CHECKVAL(*pu64, UINT64_C(0), "%llx");
873	CHECKVAL(u64Old, UINT64_C(0xffffffffffffffff), "%llx");
874
875	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0xffffffff, &u64Old), false, "%d", bool);
876	CHECKVAL(*pu64, UINT64_C(0), "%llx");
877	CHECKVAL(u64Old, UINT64_C(0), "%llx");
878
879	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), UINT64_C(0xffffffff00000000), &u64Old), false, "%d", bool);
880	CHECKVAL(*pu64, UINT64_C(0), "%llx");
881	CHECKVAL(u64Old, UINT64_C(0), "%llx");
882
883	CHECKOP(ASMAtomicCmpXchgExU64(pu64, UINT64_C(0x80040008008efd), 0, &u64Old), true, "%d", bool);
884	CHECKVAL(*pu64, UINT64_C(0x80040008008efd), "%llx");
885	CHECKVAL(u64Old, UINT64_C(0), "%llx");
886
887	CHECKOP(ASMAtomicCmpXchgExU64(pu64, 0, UINT64_C(0x80040008008efd), &u64Old), true, "%d", bool);
888	CHECKVAL(*pu64, UINT64_C(0), "%llx");
889	CHECKVAL(u64Old, UINT64_C(0x80040008008efd), "%llx");
890	}
891
892
893	static void tstASMAtomicCmpXchgExU64(void)
894	{
895	DO_SIMPLE_TEST(ASMAtomicCmpXchgExU64, uint64_t);
896	}
897
898
899	DECLINLINE(void) tstASMAtomicReadU64Worker(uint64_t volatile *pu64)
900	{
901	*pu64 = 0;
902
903	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
904	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
905
906	*pu64 = ~UINT64_C(0);
907	CHECKOP(ASMAtomicReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
908	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
909
910	*pu64 = UINT64_C(0xfedcba0987654321);
911	CHECKOP(ASMAtomicReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
912	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
913	}
914
915
916	static void tstASMAtomicReadU64(void)
917	{
918	DO_SIMPLE_TEST(ASMAtomicReadU64, uint64_t);
919	}
920
921
922	DECLINLINE(void) tstASMAtomicUoReadU64Worker(uint64_t volatile *pu64)
923	{
924	*pu64 = 0;
925
926	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0), "%#llx", uint64_t);
927	CHECKVAL(*pu64, UINT64_C(0), "%#llx");
928
929	*pu64 = ~UINT64_C(0);
930	CHECKOP(ASMAtomicUoReadU64(pu64), ~UINT64_C(0), "%#llx", uint64_t);
931	CHECKVAL(*pu64, ~UINT64_C(0), "%#llx");
932
933	*pu64 = UINT64_C(0xfedcba0987654321);
934	CHECKOP(ASMAtomicUoReadU64(pu64), UINT64_C(0xfedcba0987654321), "%#llx", uint64_t);
935	CHECKVAL(*pu64, UINT64_C(0xfedcba0987654321), "%#llx");
936	}
937
938
939	static void tstASMAtomicUoReadU64(void)
940	{
941	DO_SIMPLE_TEST(ASMAtomicUoReadU64, uint64_t);
942	}
943
944
945	DECLINLINE(void) tstASMAtomicAddS32Worker(int32_t *pi32)
946	{
947	int32_t i32Rc;
948	*pi32 = 10;
949	#define MYCHECK(op, rc, val) \
950	do { \
951	i32Rc = op; \
952	if (i32Rc != (rc)) \
953	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
954	if (*pi32 != (val)) \
955	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, val); \
956	} while (0)
957	MYCHECK(ASMAtomicAddS32(pi32, 1), 10, 11);
958	MYCHECK(ASMAtomicAddS32(pi32, -2), 11, 9);
959	MYCHECK(ASMAtomicAddS32(pi32, -9), 9, 0);
960	MYCHECK(ASMAtomicAddS32(pi32, -0x7fffffff), 0, -0x7fffffff);
961	MYCHECK(ASMAtomicAddS32(pi32, 0), -0x7fffffff, -0x7fffffff);
962	MYCHECK(ASMAtomicAddS32(pi32, 0x7fffffff), -0x7fffffff, 0);
963	MYCHECK(ASMAtomicAddS32(pi32, 0), 0, 0);
964	#undef MYCHECK
965	}
966
967
968	static void tstASMAtomicAddS32(void)
969	{
970	DO_SIMPLE_TEST(ASMAtomicAddS32, int32_t);
971	}
972
973
974	DECLINLINE(void) tstASMAtomicUoIncU32Worker(uint32_t volatile *pu32)
975	{
976	*pu32 = 0;
977
978	CHECKOP(ASMAtomicUoIncU32(pu32), UINT32_C(1), "%#x", uint32_t);
979	CHECKVAL(*pu32, UINT32_C(1), "%#x");
980
981	*pu32 = ~UINT32_C(0);
982	CHECKOP(ASMAtomicUoIncU32(pu32), 0, "%#x", uint32_t);
983	CHECKVAL(*pu32, 0, "%#x");
984
985	*pu32 = UINT32_C(0x7fffffff);
986	CHECKOP(ASMAtomicUoIncU32(pu32), UINT32_C(0x80000000), "%#x", uint32_t);
987	CHECKVAL(*pu32, UINT32_C(0x80000000), "%#x");
988	}
989
990
991	static void tstASMAtomicUoIncU32(void)
992	{
993	DO_SIMPLE_TEST(ASMAtomicUoIncU32, uint32_t);
994	}
995
996
997	DECLINLINE(void) tstASMAtomicUoDecU32Worker(uint32_t volatile *pu32)
998	{
999	*pu32 = 0;
1000
1001	CHECKOP(ASMAtomicUoDecU32(pu32), ~UINT32_C(0), "%#x", uint32_t);
1002	CHECKVAL(*pu32, ~UINT32_C(0), "%#x");
1003
1004	*pu32 = ~UINT32_C(0);
1005	CHECKOP(ASMAtomicUoDecU32(pu32), UINT32_C(0xfffffffe), "%#x", uint32_t);
1006	CHECKVAL(*pu32, UINT32_C(0xfffffffe), "%#x");
1007
1008	*pu32 = UINT32_C(0x80000000);
1009	CHECKOP(ASMAtomicUoDecU32(pu32), UINT32_C(0x7fffffff), "%#x", uint32_t);
1010	CHECKVAL(*pu32, UINT32_C(0x7fffffff), "%#x");
1011	}
1012
1013
1014	static void tstASMAtomicUoDecU32(void)
1015	{
1016	DO_SIMPLE_TEST(ASMAtomicUoDecU32, uint32_t);
1017	}
1018
1019
1020	DECLINLINE(void) tstASMAtomicAddS64Worker(int64_t volatile *pi64)
1021	{
1022	int64_t i64Rc;
1023	*pi64 = 10;
1024	#define MYCHECK(op, rc, val) \
1025	do { \
1026	i64Rc = op; \
1027	if (i64Rc != (rc)) \
1028	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %llx expected %llx\n", __FUNCTION__, __LINE__, #op, i64Rc, (int64_t)rc); \
1029	if (*pi64 != (val)) \
1030	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%llx expected %llx\n", __FUNCTION__, __LINE__, #op, pi64, (int64_t)(val)); \
1031	} while (0)
1032	MYCHECK(ASMAtomicAddS64(pi64, 1), 10, 11);
1033	MYCHECK(ASMAtomicAddS64(pi64, -2), 11, 9);
1034	MYCHECK(ASMAtomicAddS64(pi64, -9), 9, 0);
1035	MYCHECK(ASMAtomicAddS64(pi64, -INT64_MAX), 0, -INT64_MAX);
1036	MYCHECK(ASMAtomicAddS64(pi64, 0), -INT64_MAX, -INT64_MAX);
1037	MYCHECK(ASMAtomicAddS64(pi64, -1), -INT64_MAX, INT64_MIN);
1038	MYCHECK(ASMAtomicAddS64(pi64, INT64_MAX), INT64_MIN, -1);
1039	MYCHECK(ASMAtomicAddS64(pi64, 1), -1, 0);
1040	MYCHECK(ASMAtomicAddS64(pi64, 0), 0, 0);
1041	#undef MYCHECK
1042	}
1043
1044
1045	static void tstASMAtomicAddS64(void)
1046	{
1047	DO_SIMPLE_TEST(ASMAtomicAddS64, int64_t);
1048	}
1049
1050
1051	DECLINLINE(void) tstASMAtomicDecIncS32Worker(int32_t volatile *pi32)
1052	{
1053	int32_t i32Rc;
1054	*pi32 = 10;
1055	#define MYCHECK(op, rc) \
1056	do { \
1057	i32Rc = op; \
1058	if (i32Rc != (rc)) \
1059	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %d expected %d\n", __FUNCTION__, __LINE__, #op, i32Rc, rc); \
1060	if (*pi32 != (rc)) \
1061	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi32=%d expected %d\n", __FUNCTION__, __LINE__, #op, pi32, rc); \
1062	} while (0)
1063	MYCHECK(ASMAtomicDecS32(pi32), 9);
1064	MYCHECK(ASMAtomicDecS32(pi32), 8);
1065	MYCHECK(ASMAtomicDecS32(pi32), 7);
1066	MYCHECK(ASMAtomicDecS32(pi32), 6);
1067	MYCHECK(ASMAtomicDecS32(pi32), 5);
1068	MYCHECK(ASMAtomicDecS32(pi32), 4);
1069	MYCHECK(ASMAtomicDecS32(pi32), 3);
1070	MYCHECK(ASMAtomicDecS32(pi32), 2);
1071	MYCHECK(ASMAtomicDecS32(pi32), 1);
1072	MYCHECK(ASMAtomicDecS32(pi32), 0);
1073	MYCHECK(ASMAtomicDecS32(pi32), -1);
1074	MYCHECK(ASMAtomicDecS32(pi32), -2);
1075	MYCHECK(ASMAtomicIncS32(pi32), -1);
1076	MYCHECK(ASMAtomicIncS32(pi32), 0);
1077	MYCHECK(ASMAtomicIncS32(pi32), 1);
1078	MYCHECK(ASMAtomicIncS32(pi32), 2);
1079	MYCHECK(ASMAtomicIncS32(pi32), 3);
1080	MYCHECK(ASMAtomicDecS32(pi32), 2);
1081	MYCHECK(ASMAtomicIncS32(pi32), 3);
1082	MYCHECK(ASMAtomicDecS32(pi32), 2);
1083	MYCHECK(ASMAtomicIncS32(pi32), 3);
1084	#undef MYCHECK
1085	}
1086
1087
1088	static void tstASMAtomicDecIncS32(void)
1089	{
1090	DO_SIMPLE_TEST(ASMAtomicDecIncS32, int32_t);
1091	}
1092
1093
1094	DECLINLINE(void) tstASMAtomicDecIncS64Worker(int64_t volatile *pi64)
1095	{
1096	int64_t i64Rc;
1097	*pi64 = 10;
1098	#define MYCHECK(op, rc) \
1099	do { \
1100	i64Rc = op; \
1101	if (i64Rc != (rc)) \
1102	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s -> %lld expected %lld\n", __FUNCTION__, __LINE__, #op, i64Rc, rc); \
1103	if (*pi64 != (rc)) \
1104	RTTestFailed(g_hTest, "%s, %d: FAILURE: %s => pi64=%lld expected %lld\n", __FUNCTION__, __LINE__, #op, pi64, rc); \
1105	} while (0)
1106	MYCHECK(ASMAtomicDecS64(pi64), 9);
1107	MYCHECK(ASMAtomicDecS64(pi64), 8);
1108	MYCHECK(ASMAtomicDecS64(pi64), 7);
1109	MYCHECK(ASMAtomicDecS64(pi64), 6);
1110	MYCHECK(ASMAtomicDecS64(pi64), 5);
1111	MYCHECK(ASMAtomicDecS64(pi64), 4);
1112	MYCHECK(ASMAtomicDecS64(pi64), 3);
1113	MYCHECK(ASMAtomicDecS64(pi64), 2);
1114	MYCHECK(ASMAtomicDecS64(pi64), 1);
1115	MYCHECK(ASMAtomicDecS64(pi64), 0);
1116	MYCHECK(ASMAtomicDecS64(pi64), -1);
1117	MYCHECK(ASMAtomicDecS64(pi64), -2);
1118	MYCHECK(ASMAtomicIncS64(pi64), -1);
1119	MYCHECK(ASMAtomicIncS64(pi64), 0);
1120	MYCHECK(ASMAtomicIncS64(pi64), 1);
1121	MYCHECK(ASMAtomicIncS64(pi64), 2);
1122	MYCHECK(ASMAtomicIncS64(pi64), 3);
1123	MYCHECK(ASMAtomicDecS64(pi64), 2);
1124	MYCHECK(ASMAtomicIncS64(pi64), 3);
1125	MYCHECK(ASMAtomicDecS64(pi64), 2);
1126	MYCHECK(ASMAtomicIncS64(pi64), 3);
1127	#undef MYCHECK
1128	}
1129
1130
1131	static void tstASMAtomicDecIncS64(void)
1132	{
1133	DO_SIMPLE_TEST(ASMAtomicDecIncS64, int64_t);
1134	}
1135
1136
1137	DECLINLINE(void) tstASMAtomicAndOrU32Worker(uint32_t volatile *pu32)
1138	{
1139	*pu32 = UINT32_C(0xffffffff);
1140
1141	ASMAtomicOrU32(pu32, UINT32_C(0xffffffff));
1142	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1143
1144	ASMAtomicAndU32(pu32, UINT32_C(0xffffffff));
1145	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1146
1147	ASMAtomicAndU32(pu32, UINT32_C(0x8f8f8f8f));
1148	CHECKVAL(*pu32, UINT32_C(0x8f8f8f8f), "%x");
1149
1150	ASMAtomicOrU32(pu32, UINT32_C(0x70707070));
1151	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%x");
1152
1153	ASMAtomicAndU32(pu32, UINT32_C(1));
1154	CHECKVAL(*pu32, UINT32_C(1), "%x");
1155
1156	ASMAtomicOrU32(pu32, UINT32_C(0x80000000));
1157	CHECKVAL(*pu32, UINT32_C(0x80000001), "%x");
1158
1159	ASMAtomicAndU32(pu32, UINT32_C(0x80000000));
1160	CHECKVAL(*pu32, UINT32_C(0x80000000), "%x");
1161
1162	ASMAtomicAndU32(pu32, UINT32_C(0));
1163	CHECKVAL(*pu32, UINT32_C(0), "%x");
1164
1165	ASMAtomicOrU32(pu32, UINT32_C(0x42424242));
1166	CHECKVAL(*pu32, UINT32_C(0x42424242), "%x");
1167	}
1168
1169
1170	static void tstASMAtomicAndOrU32(void)
1171	{
1172	DO_SIMPLE_TEST(ASMAtomicAndOrU32, uint32_t);
1173	}
1174
1175
1176	DECLINLINE(void) tstASMAtomicAndOrU64Worker(uint64_t volatile *pu64)
1177	{
1178	*pu64 = UINT64_C(0xffffffff);
1179
1180	ASMAtomicOrU64(pu64, UINT64_C(0xffffffff));
1181	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1182
1183	ASMAtomicAndU64(pu64, UINT64_C(0xffffffff));
1184	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1185
1186	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f));
1187	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f), "%x");
1188
1189	ASMAtomicOrU64(pu64, UINT64_C(0x70707070));
1190	CHECKVAL(*pu64, UINT64_C(0xffffffff), "%x");
1191
1192	ASMAtomicAndU64(pu64, UINT64_C(1));
1193	CHECKVAL(*pu64, UINT64_C(1), "%x");
1194
1195	ASMAtomicOrU64(pu64, UINT64_C(0x80000000));
1196	CHECKVAL(*pu64, UINT64_C(0x80000001), "%x");
1197
1198	ASMAtomicAndU64(pu64, UINT64_C(0x80000000));
1199	CHECKVAL(*pu64, UINT64_C(0x80000000), "%x");
1200
1201	ASMAtomicAndU64(pu64, UINT64_C(0));
1202	CHECKVAL(*pu64, UINT64_C(0), "%x");
1203
1204	ASMAtomicOrU64(pu64, UINT64_C(0x42424242));
1205	CHECKVAL(*pu64, UINT64_C(0x42424242), "%x");
1206
1207	// Same as above, but now 64-bit wide.
1208	ASMAtomicAndU64(pu64, UINT64_C(0));
1209	CHECKVAL(*pu64, UINT64_C(0), "%x");
1210
1211	ASMAtomicOrU64(pu64, UINT64_C(0xffffffffffffffff));
1212	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1213
1214	ASMAtomicAndU64(pu64, UINT64_C(0xffffffffffffffff));
1215	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1216
1217	ASMAtomicAndU64(pu64, UINT64_C(0x8f8f8f8f8f8f8f8f));
1218	CHECKVAL(*pu64, UINT64_C(0x8f8f8f8f8f8f8f8f), "%x");
1219
1220	ASMAtomicOrU64(pu64, UINT64_C(0x7070707070707070));
1221	CHECKVAL(*pu64, UINT64_C(0xffffffffffffffff), "%x");
1222
1223	ASMAtomicAndU64(pu64, UINT64_C(1));
1224	CHECKVAL(*pu64, UINT64_C(1), "%x");
1225
1226	ASMAtomicOrU64(pu64, UINT64_C(0x8000000000000000));
1227	CHECKVAL(*pu64, UINT64_C(0x8000000000000001), "%x");
1228
1229	ASMAtomicAndU64(pu64, UINT64_C(0x8000000000000000));
1230	CHECKVAL(*pu64, UINT64_C(0x8000000000000000), "%x");
1231
1232	ASMAtomicAndU64(pu64, UINT64_C(0));
1233	CHECKVAL(*pu64, UINT64_C(0), "%x");
1234
1235	ASMAtomicOrU64(pu64, UINT64_C(0x4242424242424242));
1236	CHECKVAL(*pu64, UINT64_C(0x4242424242424242), "%x");
1237	}
1238
1239
1240	static void tstASMAtomicAndOrU64(void)
1241	{
1242	DO_SIMPLE_TEST(ASMAtomicAndOrU64, uint64_t);
1243	}
1244
1245
1246	DECLINLINE(void) tstASMAtomicUoAndOrU32Worker(uint32_t volatile *pu32)
1247	{
1248	*pu32 = UINT32_C(0xffffffff);
1249
1250	ASMAtomicUoOrU32(pu32, UINT32_C(0xffffffff));
1251	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%#x");
1252
1253	ASMAtomicUoAndU32(pu32, UINT32_C(0xffffffff));
1254	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%#x");
1255
1256	ASMAtomicUoAndU32(pu32, UINT32_C(0x8f8f8f8f));
1257	CHECKVAL(*pu32, UINT32_C(0x8f8f8f8f), "%#x");
1258
1259	ASMAtomicUoOrU32(pu32, UINT32_C(0x70707070));
1260	CHECKVAL(*pu32, UINT32_C(0xffffffff), "%#x");
1261
1262	ASMAtomicUoAndU32(pu32, UINT32_C(1));
1263	CHECKVAL(*pu32, UINT32_C(1), "%#x");
1264
1265	ASMAtomicUoOrU32(pu32, UINT32_C(0x80000000));
1266	CHECKVAL(*pu32, UINT32_C(0x80000001), "%#x");
1267
1268	ASMAtomicUoAndU32(pu32, UINT32_C(0x80000000));
1269	CHECKVAL(*pu32, UINT32_C(0x80000000), "%#x");
1270
1271	ASMAtomicUoAndU32(pu32, UINT32_C(0));
1272	CHECKVAL(*pu32, UINT32_C(0), "%#x");
1273
1274	ASMAtomicUoOrU32(pu32, UINT32_C(0x42424242));
1275	CHECKVAL(*pu32, UINT32_C(0x42424242), "%#x");
1276	}
1277
1278
1279	static void tstASMAtomicUoAndOrU32(void)
1280	{
1281	DO_SIMPLE_TEST(ASMAtomicUoAndOrU32, uint32_t);
1282	}
1283
1284
1285	typedef struct
1286	{
1287	uint8_t ab[PAGE_SIZE];
1288	} TSTPAGE;
1289
1290
1291	DECLINLINE(void) tstASMMemZeroPageWorker(TSTPAGE *pPage)
1292	{
1293	for (unsigned j = 0; j < 16; j++)
1294	{
1295	memset(pPage, 0x11 * j, sizeof(*pPage));
1296	ASMMemZeroPage(pPage);
1297	for (unsigned i = 0; i < sizeof(pPage->ab); i++)
1298	if (pPage->ab[i])
1299	RTTestFailed(g_hTest, "ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
1300	}
1301	}
1302
1303
1304	static void tstASMMemZeroPage(void)
1305	{
1306	DO_SIMPLE_TEST(ASMMemZeroPage, TSTPAGE);
1307	}
1308
1309
1310	void tstASMMemIsZeroPage(RTTEST hTest)
1311	{
1312	RTTestSub(hTest, "ASMMemIsZeroPage");
1313
1314	void *pvPage1 = RTTestGuardedAllocHead(hTest, PAGE_SIZE);
1315	void *pvPage2 = RTTestGuardedAllocTail(hTest, PAGE_SIZE);
1316	RTTESTI_CHECK_RETV(pvPage1 && pvPage2);
1317
1318	memset(pvPage1, 0, PAGE_SIZE);
1319	memset(pvPage2, 0, PAGE_SIZE);
1320	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage1));
1321	RTTESTI_CHECK(ASMMemIsZeroPage(pvPage2));
1322
1323	memset(pvPage1, 0xff, PAGE_SIZE);
1324	memset(pvPage2, 0xff, PAGE_SIZE);
1325	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1326	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1327
1328	memset(pvPage1, 0, PAGE_SIZE);
1329	memset(pvPage2, 0, PAGE_SIZE);
1330	for (unsigned off = 0; off < PAGE_SIZE; off++)
1331	{
1332	((uint8_t *)pvPage1)[off] = 1;
1333	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage1));
1334	((uint8_t *)pvPage1)[off] = 0;
1335
1336	((uint8_t *)pvPage2)[off] = 0x80;
1337	RTTESTI_CHECK(!ASMMemIsZeroPage(pvPage2));
1338	((uint8_t *)pvPage2)[off] = 0;
1339	}
1340
1341	RTTestSubDone(hTest);
1342	}
1343
1344
1345	void tstASMMemFirstMismatchingU8(RTTEST hTest)
1346	{
1347	RTTestSub(hTest, "ASMMemFirstMismatchingU8");
1348
1349	uint8_t pbPage1 = (uint8_t )RTTestGuardedAllocHead(hTest, PAGE_SIZE);
1350	uint8_t pbPage2 = (uint8_t )RTTestGuardedAllocTail(hTest, PAGE_SIZE);
1351	RTTESTI_CHECK_RETV(pbPage1 && pbPage2);
1352
1353	memset(pbPage1, 0, PAGE_SIZE);
1354	memset(pbPage2, 0, PAGE_SIZE);
1355	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0) == NULL);
1356	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0) == NULL);
1357	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 1) == pbPage1);
1358	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 1) == pbPage2);
1359	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0x87) == pbPage1);
1360	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0x87) == pbPage2);
1361	RTTESTI_CHECK(ASMMemIsZero(pbPage1, PAGE_SIZE));
1362	RTTESTI_CHECK(ASMMemIsZero(pbPage2, PAGE_SIZE));
1363	RTTESTI_CHECK(ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0));
1364	RTTESTI_CHECK(ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0));
1365	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0x34));
1366	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0x88));
1367	unsigned cbSub = 32;
1368	while (cbSub-- > 0)
1369	{
1370	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0) == NULL);
1371	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0) == NULL);
1372	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0) == NULL);
1373	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0) == NULL);
1374
1375	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0x34) == &pbPage1[PAGE_SIZE - cbSub] \|\| !cbSub);
1376	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0x99) == &pbPage2[PAGE_SIZE - cbSub] \|\| !cbSub);
1377	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0x42) == pbPage1 \|\| !cbSub);
1378	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0x88) == pbPage2 \|\| !cbSub);
1379	}
1380
1381	memset(pbPage1, 0xff, PAGE_SIZE);
1382	memset(pbPage2, 0xff, PAGE_SIZE);
1383	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0xff) == NULL);
1384	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0xff) == NULL);
1385	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, PAGE_SIZE, 0xfe) == pbPage1);
1386	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, PAGE_SIZE, 0xfe) == pbPage2);
1387	RTTESTI_CHECK(!ASMMemIsZero(pbPage1, PAGE_SIZE));
1388	RTTESTI_CHECK(!ASMMemIsZero(pbPage2, PAGE_SIZE));
1389	RTTESTI_CHECK(ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0xff));
1390	RTTESTI_CHECK(ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0xff));
1391	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage1, PAGE_SIZE, 0));
1392	RTTESTI_CHECK(!ASMMemIsAllU8(pbPage2, PAGE_SIZE, 0));
1393	cbSub = 32;
1394	while (cbSub-- > 0)
1395	{
1396	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0xff) == NULL);
1397	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0xff) == NULL);
1398	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0xff) == NULL);
1399	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0xff) == NULL);
1400
1401	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage1[PAGE_SIZE - cbSub], cbSub, 0xfe) == &pbPage1[PAGE_SIZE - cbSub] \|\| !cbSub);
1402	RTTESTI_CHECK(ASMMemFirstMismatchingU8(&pbPage2[PAGE_SIZE - cbSub], cbSub, 0xfe) == &pbPage2[PAGE_SIZE - cbSub] \|\| !cbSub);
1403	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage1, cbSub, 0xfe) == pbPage1 \|\| !cbSub);
1404	RTTESTI_CHECK(ASMMemFirstMismatchingU8(pbPage2, cbSub, 0xfe) == pbPage2 \|\| !cbSub);
1405	}
1406
1407
1408	/*
1409	* Various alignments and sizes.
1410	*/
1411	uint8_t const bFiller1 = 0x00;
1412	uint8_t const bFiller2 = 0xf6;
1413	size_t const cbBuf = 128;
1414	uint8_t *pbBuf1 = pbPage1;
1415	uint8_t pbBuf2 = &pbPage2[PAGE_SIZE - cbBuf]; / Put it up against the tail guard */
1416	memset(pbPage1, ~bFiller1, PAGE_SIZE);
1417	memset(pbPage2, ~bFiller2, PAGE_SIZE);
1418	memset(pbBuf1, bFiller1, cbBuf);
1419	memset(pbBuf2, bFiller2, cbBuf);
1420	for (size_t offNonZero = 0; offNonZero < cbBuf; offNonZero++)
1421	{
1422	uint8_t bRand = (uint8_t)RTRandU32();
1423	pbBuf1[offNonZero] = bRand \| 1;
1424	pbBuf2[offNonZero] = (0x80 \| bRand) ^ 0xf6;
1425
1426	for (size_t offStart = 0; offStart < 32; offStart++)
1427	{
1428	size_t const cbMax = cbBuf - offStart;
1429	for (size_t cb = 0; cb < cbMax; cb++)
1430	{
1431	size_t const offEnd = offStart + cb;
1432	uint8_t bSaved1, bSaved2;
1433	if (offEnd < PAGE_SIZE)
1434	{
1435	bSaved1 = pbBuf1[offEnd];
1436	bSaved2 = pbBuf2[offEnd];
1437	pbBuf1[offEnd] = 0xff;
1438	pbBuf2[offEnd] = 0xff;
1439	}
1440	#ifdef _MSC_VER /* simple stupid compiler warnings */
1441	else
1442	bSaved1 = bSaved2 = 0;
1443	#endif
1444
1445	uint8_t pbRet = (uint8_t )ASMMemFirstMismatchingU8(pbBuf1 + offStart, cb, bFiller1);
1446	RTTESTI_CHECK(offNonZero - offStart < cb ? pbRet == &pbBuf1[offNonZero] : pbRet == NULL);
1447
1448	pbRet = (uint8_t *)ASMMemFirstMismatchingU8(pbBuf2 + offStart, cb, bFiller2);
1449	RTTESTI_CHECK(offNonZero - offStart < cb ? pbRet == &pbBuf2[offNonZero] : pbRet == NULL);
1450
1451	if (offEnd < PAGE_SIZE)
1452	{
1453	pbBuf1[offEnd] = bSaved1;
1454	pbBuf2[offEnd] = bSaved2;
1455	}
1456	}
1457	}
1458
1459	pbBuf1[offNonZero] = 0;
1460	pbBuf2[offNonZero] = 0xf6;
1461	}
1462
1463	RTTestSubDone(hTest);
1464	}
1465
1466
1467	void tstASMMemZero32(void)
1468	{
1469	RTTestSub(g_hTest, "ASMMemFill32");
1470
1471	struct
1472	{
1473	uint64_t u64Magic1;
1474	uint8_t abPage[PAGE_SIZE - 32];
1475	uint64_t u64Magic2;
1476	} Buf1, Buf2, Buf3;
1477
1478	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1479	memset(Buf1.abPage, 0x55, sizeof(Buf1.abPage));
1480	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1481	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1482	memset(Buf2.abPage, 0x77, sizeof(Buf2.abPage));
1483	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1484	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1485	memset(Buf3.abPage, 0x99, sizeof(Buf3.abPage));
1486	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1487	ASMMemZero32(Buf1.abPage, sizeof(Buf1.abPage));
1488	ASMMemZero32(Buf2.abPage, sizeof(Buf2.abPage));
1489	ASMMemZero32(Buf3.abPage, sizeof(Buf3.abPage));
1490	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1491	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1492	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1493	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1494	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1495	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1496	{
1497	RTTestFailed(g_hTest, "ASMMemZero32 violated one/both magic(s)!\n");
1498	}
1499	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.abPage); i++)
1500	if (Buf1.abPage[i])
1501	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1502	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.abPage); i++)
1503	if (Buf2.abPage[i])
1504	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1505	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.abPage); i++)
1506	if (Buf3.abPage[i])
1507	RTTestFailed(g_hTest, "ASMMemZero32 didn't clear byte at offset %#x!\n", i);
1508	}
1509
1510
1511	void tstASMMemFill32(void)
1512	{
1513	RTTestSub(g_hTest, "ASMMemFill32");
1514
1515	struct
1516	{
1517	uint64_t u64Magic1;
1518	uint32_t au32Page[PAGE_SIZE / 4];
1519	uint64_t u64Magic2;
1520	} Buf1;
1521	struct
1522	{
1523	uint64_t u64Magic1;
1524	uint32_t au32Page[(PAGE_SIZE / 4) - 3];
1525	uint64_t u64Magic2;
1526	} Buf2;
1527	struct
1528	{
1529	uint64_t u64Magic1;
1530	uint32_t au32Page[(PAGE_SIZE / 4) - 1];
1531	uint64_t u64Magic2;
1532	} Buf3;
1533
1534	Buf1.u64Magic1 = UINT64_C(0xffffffffffffffff);
1535	memset(Buf1.au32Page, 0x55, sizeof(Buf1.au32Page));
1536	Buf1.u64Magic2 = UINT64_C(0xffffffffffffffff);
1537	Buf2.u64Magic1 = UINT64_C(0xffffffffffffffff);
1538	memset(Buf2.au32Page, 0x77, sizeof(Buf2.au32Page));
1539	Buf2.u64Magic2 = UINT64_C(0xffffffffffffffff);
1540	Buf3.u64Magic1 = UINT64_C(0xffffffffffffffff);
1541	memset(Buf3.au32Page, 0x99, sizeof(Buf3.au32Page));
1542	Buf3.u64Magic2 = UINT64_C(0xffffffffffffffff);
1543	ASMMemFill32(Buf1.au32Page, sizeof(Buf1.au32Page), 0xdeadbeef);
1544	ASMMemFill32(Buf2.au32Page, sizeof(Buf2.au32Page), 0xcafeff01);
1545	ASMMemFill32(Buf3.au32Page, sizeof(Buf3.au32Page), 0xf00dd00f);
1546	if ( Buf1.u64Magic1 != UINT64_C(0xffffffffffffffff)
1547	\|\| Buf1.u64Magic2 != UINT64_C(0xffffffffffffffff)
1548	\|\| Buf2.u64Magic1 != UINT64_C(0xffffffffffffffff)
1549	\|\| Buf2.u64Magic2 != UINT64_C(0xffffffffffffffff)
1550	\|\| Buf3.u64Magic1 != UINT64_C(0xffffffffffffffff)
1551	\|\| Buf3.u64Magic2 != UINT64_C(0xffffffffffffffff))
1552	RTTestFailed(g_hTest, "ASMMemFill32 violated one/both magic(s)!\n");
1553	for (unsigned i = 0; i < RT_ELEMENTS(Buf1.au32Page); i++)
1554	if (Buf1.au32Page[i] != 0xdeadbeef)
1555	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf1.au32Page[i], 0xdeadbeef);
1556	for (unsigned i = 0; i < RT_ELEMENTS(Buf2.au32Page); i++)
1557	if (Buf2.au32Page[i] != 0xcafeff01)
1558	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf2.au32Page[i], 0xcafeff01);
1559	for (unsigned i = 0; i < RT_ELEMENTS(Buf3.au32Page); i++)
1560	if (Buf3.au32Page[i] != 0xf00dd00f)
1561	RTTestFailed(g_hTest, "ASMMemFill32 %#x: %#x exepcted %#x\n", i, Buf3.au32Page[i], 0xf00dd00f);
1562	}
1563
1564
1565
1566	void tstASMMath(void)
1567	{
1568	RTTestSub(g_hTest, "Math");
1569
1570	uint64_t u64 = ASMMult2xU32RetU64(UINT32_C(0x80000000), UINT32_C(0x10000000));
1571	CHECKVAL(u64, UINT64_C(0x0800000000000000), "%#018RX64");
1572
1573	uint32_t u32 = ASMDivU64ByU32RetU32(UINT64_C(0x0800000000000000), UINT32_C(0x10000000));
1574	CHECKVAL(u32, UINT32_C(0x80000000), "%#010RX32");
1575
1576	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x00000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
1577	CHECKVAL(u32, UINT32_C(0x00000001), "%#018RX32");
1578	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10000000), UINT32_C(0x80000000), UINT32_C(0x20000000));
1579	CHECKVAL(u32, UINT32_C(0x40000000), "%#018RX32");
1580	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x76543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1581	CHECKVAL(u32, UINT32_C(0x76543210), "%#018RX32");
1582	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0xffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1583	CHECKVAL(u32, UINT32_C(0xffffffff), "%#018RX32");
1584	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0xffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
1585	CHECKVAL(u32, UINT32_C(0xfffffff0), "%#018RX32");
1586	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
1587	CHECKVAL(u32, UINT32_C(0x05c584ce), "%#018RX32");
1588	u32 = ASMMultU32ByU32DivByU32(UINT32_C(0x10359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
1589	CHECKVAL(u32, UINT32_C(0x2d860795), "%#018RX32");
1590
1591	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1592	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
1593	CHECKVAL(u64, UINT64_C(0x0000000000000001), "%#018RX64");
1594	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
1595	CHECKVAL(u64, UINT64_C(0x4000000000000000), "%#018RX64");
1596	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1597	CHECKVAL(u64, UINT64_C(0xfedcba9876543210), "%#018RX64");
1598	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
1599	CHECKVAL(u64, UINT64_C(0xffffffffffffffff), "%#018RX64");
1600	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
1601	CHECKVAL(u64, UINT64_C(0xfffffff0fffffff0), "%#018RX64");
1602	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
1603	CHECKVAL(u64, UINT64_C(0x128b9c3d43184763), "%#018RX64");
1604	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
1605	CHECKVAL(u64, UINT64_C(0x924719355cd35a27), "%#018RX64");
1606
1607	# if 0 /* bird: question is whether this should trap or not:
1608	*
1609	* frank: Of course it must trap:
1610	*
1611	* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
1612	*
1613	* During the following division, the quotient must fit into a 32-bit register.
1614	* Therefore the smallest valid divisor is
1615	*
1616	* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
1617	*
1618	* which is definitely greater than 0x3b9aca00.
1619	*
1620	* bird: No, the C version does not crash. So, the question is whether there's any
1621	* code depending on it not crashing.
1622	*
1623	* Of course the assembly versions of the code crash right now for the reasons you've
1624	* given, but the 32-bit MSC version does not crash.
1625	*
1626	* frank: The C version does not crash but delivers incorrect results for this case.
1627	* The reason is
1628	*
1629	* u.s.Hi = (unsigned long)(u64Hi / u32C);
1630	*
1631	* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
1632	* to 32 bit. If using this (optimized and fast) function we should just be sure that
1633	* the operands are in a valid range.
1634	*/
1635	u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
1636	CHECKVAL(u64, UINT64_C(0x02b8f9a2aa74e3dc), "%#018RX64");
1637	# endif
1638	#endif /* AMD64 \|\| X86 */
1639
1640	u32 = ASMModU64ByU32RetU32(UINT64_C(0x0ffffff8c65d6731), UINT32_C(0x77d7daf8));
1641	CHECKVAL(u32, UINT32_C(0x3B642451), "%#010RX32");
1642
1643	int32_t i32;
1644	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(-2));
1645	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1646	i32 = ASMModS64ByS32RetS32(INT64_C(-11), INT32_C(2));
1647	CHECKVAL(i32, INT32_C(-1), "%010RI32");
1648	i32 = ASMModS64ByS32RetS32(INT64_C(11), INT32_C(-2));
1649	CHECKVAL(i32, INT32_C(1), "%010RI32");
1650
1651	i32 = ASMModS64ByS32RetS32(INT64_C(92233720368547758), INT32_C(2147483647));
1652	CHECKVAL(i32, INT32_C(2104533974), "%010RI32");
1653	i32 = ASMModS64ByS32RetS32(INT64_C(-92233720368547758), INT32_C(2147483647));
1654	CHECKVAL(i32, INT32_C(-2104533974), "%010RI32");
1655	}
1656
1657
1658	void tstASMByteSwap(void)
1659	{
1660	RTTestSub(g_hTest, "ASMByteSwap*");
1661
1662	uint64_t u64In = UINT64_C(0x0011223344556677);
1663	uint64_t u64Out = ASMByteSwapU64(u64In);
1664	CHECKVAL(u64In, UINT64_C(0x0011223344556677), "%#018RX64");
1665	CHECKVAL(u64Out, UINT64_C(0x7766554433221100), "%#018RX64");
1666	u64Out = ASMByteSwapU64(u64Out);
1667	CHECKVAL(u64Out, u64In, "%#018RX64");
1668	u64In = UINT64_C(0x0123456789abcdef);
1669	u64Out = ASMByteSwapU64(u64In);
1670	CHECKVAL(u64In, UINT64_C(0x0123456789abcdef), "%#018RX64");
1671	CHECKVAL(u64Out, UINT64_C(0xefcdab8967452301), "%#018RX64");
1672	u64Out = ASMByteSwapU64(u64Out);
1673	CHECKVAL(u64Out, u64In, "%#018RX64");
1674	u64In = 0;
1675	u64Out = ASMByteSwapU64(u64In);
1676	CHECKVAL(u64Out, u64In, "%#018RX64");
1677	u64In = UINT64_MAX;
1678	u64Out = ASMByteSwapU64(u64In);
1679	CHECKVAL(u64Out, u64In, "%#018RX64");
1680
1681	uint32_t u32In = UINT32_C(0x00112233);
1682	uint32_t u32Out = ASMByteSwapU32(u32In);
1683	CHECKVAL(u32In, UINT32_C(0x00112233), "%#010RX32");
1684	CHECKVAL(u32Out, UINT32_C(0x33221100), "%#010RX32");
1685	u32Out = ASMByteSwapU32(u32Out);
1686	CHECKVAL(u32Out, u32In, "%#010RX32");
1687	u32In = UINT32_C(0x12345678);
1688	u32Out = ASMByteSwapU32(u32In);
1689	CHECKVAL(u32In, UINT32_C(0x12345678), "%#010RX32");
1690	CHECKVAL(u32Out, UINT32_C(0x78563412), "%#010RX32");
1691	u32Out = ASMByteSwapU32(u32Out);
1692	CHECKVAL(u32Out, u32In, "%#010RX32");
1693	u32In = 0;
1694	u32Out = ASMByteSwapU32(u32In);
1695	CHECKVAL(u32Out, u32In, "%#010RX32");
1696	u32In = UINT32_MAX;
1697	u32Out = ASMByteSwapU32(u32In);
1698	CHECKVAL(u32Out, u32In, "%#010RX32");
1699
1700	uint16_t u16In = UINT16_C(0x0011);
1701	uint16_t u16Out = ASMByteSwapU16(u16In);
1702	CHECKVAL(u16In, UINT16_C(0x0011), "%#06RX16");
1703	CHECKVAL(u16Out, UINT16_C(0x1100), "%#06RX16");
1704	u16Out = ASMByteSwapU16(u16Out);
1705	CHECKVAL(u16Out, u16In, "%#06RX16");
1706	u16In = UINT16_C(0x1234);
1707	u16Out = ASMByteSwapU16(u16In);
1708	CHECKVAL(u16In, UINT16_C(0x1234), "%#06RX16");
1709	CHECKVAL(u16Out, UINT16_C(0x3412), "%#06RX16");
1710	u16Out = ASMByteSwapU16(u16Out);
1711	CHECKVAL(u16Out, u16In, "%#06RX16");
1712	u16In = 0;
1713	u16Out = ASMByteSwapU16(u16In);
1714	CHECKVAL(u16Out, u16In, "%#06RX16");
1715	u16In = UINT16_MAX;
1716	u16Out = ASMByteSwapU16(u16In);
1717	CHECKVAL(u16Out, u16In, "%#06RX16");
1718	}
1719
1720
1721	void tstASMBench(void)
1722	{
1723	/*
1724	* Make this static. We don't want to have this located on the stack.
1725	*/
1726	static uint8_t volatile s_u8;
1727	static int8_t volatile s_i8;
1728	static uint16_t volatile s_u16;
1729	static int16_t volatile s_i16;
1730	static uint32_t volatile s_u32;
1731	static int32_t volatile s_i32;
1732	static uint64_t volatile s_u64;
1733	static int64_t volatile s_i64;
1734	register unsigned i;
1735	const unsigned cRounds = _2M; /* Must be multiple of 8 */
1736	register uint64_t u64Elapsed;
1737
1738	RTTestSub(g_hTest, "Benchmarking");
1739
1740	#if 0 && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1741	# define BENCH(op, str) \
1742	do { \
1743	RTThreadYield(); \
1744	u64Elapsed = ASMReadTSC(); \
1745	for (i = cRounds; i > 0; i--) \
1746	op; \
1747	u64Elapsed = ASMReadTSC() - u64Elapsed; \
1748	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_TICKS_PER_CALL); \
1749	} while (0)
1750	#else
1751	# define BENCH(op, str) \
1752	do { \
1753	RTThreadYield(); \
1754	u64Elapsed = RTTimeNanoTS(); \
1755	for (i = cRounds / 8; i > 0; i--) \
1756	{ \
1757	op; \
1758	op; \
1759	op; \
1760	op; \
1761	op; \
1762	op; \
1763	op; \
1764	op; \
1765	} \
1766	u64Elapsed = RTTimeNanoTS() - u64Elapsed; \
1767	RTTestValue(g_hTest, str, u64Elapsed / cRounds, RTTESTUNIT_NS_PER_CALL); \
1768	} while (0)
1769	#endif
1770	#if (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)) && !defined(GCC44_32BIT_PIC)
1771	# define BENCH_TSC(op, str) \
1772	do { \
1773	RTThreadYield(); \
1774	u64Elapsed = ASMReadTSC(); \
1775	for (i = cRounds / 8; i > 0; i--) \
1776	{ \
1777	op; \
1778	op; \
1779	op; \
1780	op; \
1781	op; \
1782	op; \
1783	op; \
1784	op; \
1785	} \
1786	u64Elapsed = ASMReadTSC() - u64Elapsed; \
1787	RTTestValue(g_hTest, str, u64Elapsed / cRounds, /RTTESTUNIT_TICKS_PER_CALL/ RTTESTUNIT_NONE); \
1788	} while (0)
1789	#else
1790	# define BENCH_TSC(op, str) BENCH(op, str)
1791	#endif
1792
1793	BENCH(s_u32 = 0, "s_u32 = 0");
1794	BENCH(ASMAtomicUoReadU8(&s_u8), "ASMAtomicUoReadU8");
1795	BENCH(ASMAtomicUoReadS8(&s_i8), "ASMAtomicUoReadS8");
1796	BENCH(ASMAtomicUoReadU16(&s_u16), "ASMAtomicUoReadU16");
1797	BENCH(ASMAtomicUoReadS16(&s_i16), "ASMAtomicUoReadS16");
1798	BENCH(ASMAtomicUoReadU32(&s_u32), "ASMAtomicUoReadU32");
1799	BENCH(ASMAtomicUoReadS32(&s_i32), "ASMAtomicUoReadS32");
1800	BENCH(ASMAtomicUoReadU64(&s_u64), "ASMAtomicUoReadU64");
1801	BENCH(ASMAtomicUoReadS64(&s_i64), "ASMAtomicUoReadS64");
1802	BENCH(ASMAtomicReadU8(&s_u8), "ASMAtomicReadU8");
1803	BENCH(ASMAtomicReadS8(&s_i8), "ASMAtomicReadS8");
1804	BENCH(ASMAtomicReadU16(&s_u16), "ASMAtomicReadU16");
1805	BENCH(ASMAtomicReadS16(&s_i16), "ASMAtomicReadS16");
1806	BENCH(ASMAtomicReadU32(&s_u32), "ASMAtomicReadU32");
1807	BENCH(ASMAtomicReadS32(&s_i32), "ASMAtomicReadS32");
1808	BENCH(ASMAtomicReadU64(&s_u64), "ASMAtomicReadU64");
1809	BENCH(ASMAtomicReadS64(&s_i64), "ASMAtomicReadS64");
1810	BENCH(ASMAtomicUoWriteU8(&s_u8, 0), "ASMAtomicUoWriteU8");
1811	BENCH(ASMAtomicUoWriteS8(&s_i8, 0), "ASMAtomicUoWriteS8");
1812	BENCH(ASMAtomicUoWriteU16(&s_u16, 0), "ASMAtomicUoWriteU16");
1813	BENCH(ASMAtomicUoWriteS16(&s_i16, 0), "ASMAtomicUoWriteS16");
1814	BENCH(ASMAtomicUoWriteU32(&s_u32, 0), "ASMAtomicUoWriteU32");
1815	BENCH(ASMAtomicUoWriteS32(&s_i32, 0), "ASMAtomicUoWriteS32");
1816	BENCH(ASMAtomicUoWriteU64(&s_u64, 0), "ASMAtomicUoWriteU64");
1817	BENCH(ASMAtomicUoWriteS64(&s_i64, 0), "ASMAtomicUoWriteS64");
1818	BENCH(ASMAtomicWriteU8(&s_u8, 0), "ASMAtomicWriteU8");
1819	BENCH(ASMAtomicWriteS8(&s_i8, 0), "ASMAtomicWriteS8");
1820	BENCH(ASMAtomicWriteU16(&s_u16, 0), "ASMAtomicWriteU16");
1821	BENCH(ASMAtomicWriteS16(&s_i16, 0), "ASMAtomicWriteS16");
1822	BENCH(ASMAtomicWriteU32(&s_u32, 0), "ASMAtomicWriteU32");
1823	BENCH(ASMAtomicWriteS32(&s_i32, 0), "ASMAtomicWriteS32");
1824	BENCH(ASMAtomicWriteU64(&s_u64, 0), "ASMAtomicWriteU64");
1825	BENCH(ASMAtomicWriteS64(&s_i64, 0), "ASMAtomicWriteS64");
1826	BENCH(ASMAtomicXchgU8(&s_u8, 0), "ASMAtomicXchgU8");
1827	BENCH(ASMAtomicXchgS8(&s_i8, 0), "ASMAtomicXchgS8");
1828	BENCH(ASMAtomicXchgU16(&s_u16, 0), "ASMAtomicXchgU16");
1829	BENCH(ASMAtomicXchgS16(&s_i16, 0), "ASMAtomicXchgS16");
1830	BENCH(ASMAtomicXchgU32(&s_u32, 0), "ASMAtomicXchgU32");
1831	BENCH(ASMAtomicXchgS32(&s_i32, 0), "ASMAtomicXchgS32");
1832	BENCH(ASMAtomicXchgU64(&s_u64, 0), "ASMAtomicXchgU64");
1833	BENCH(ASMAtomicXchgS64(&s_i64, 0), "ASMAtomicXchgS64");
1834	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 0), "ASMAtomicCmpXchgU32");
1835	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 0), "ASMAtomicCmpXchgS32");
1836	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 0), "ASMAtomicCmpXchgU64");
1837	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 0), "ASMAtomicCmpXchgS64");
1838	BENCH(ASMAtomicCmpXchgU32(&s_u32, 0, 1), "ASMAtomicCmpXchgU32/neg");
1839	BENCH(ASMAtomicCmpXchgS32(&s_i32, 0, 1), "ASMAtomicCmpXchgS32/neg");
1840	BENCH(ASMAtomicCmpXchgU64(&s_u64, 0, 1), "ASMAtomicCmpXchgU64/neg");
1841	BENCH(ASMAtomicCmpXchgS64(&s_i64, 0, 1), "ASMAtomicCmpXchgS64/neg");
1842	BENCH(ASMAtomicIncU32(&s_u32), "ASMAtomicIncU32");
1843	BENCH(ASMAtomicIncS32(&s_i32), "ASMAtomicIncS32");
1844	BENCH(ASMAtomicDecU32(&s_u32), "ASMAtomicDecU32");
1845	BENCH(ASMAtomicDecS32(&s_i32), "ASMAtomicDecS32");
1846	BENCH(ASMAtomicAddU32(&s_u32, 5), "ASMAtomicAddU32");
1847	BENCH(ASMAtomicAddS32(&s_i32, 5), "ASMAtomicAddS32");
1848	BENCH(ASMAtomicUoIncU32(&s_u32), "ASMAtomicUoIncU32");
1849	BENCH(ASMAtomicUoDecU32(&s_u32), "ASMAtomicUoDecU32");
1850	BENCH(ASMAtomicUoAndU32(&s_u32, 0xffffffff), "ASMAtomicUoAndU32");
1851	BENCH(ASMAtomicUoOrU32(&s_u32, 0xffffffff), "ASMAtomicUoOrU32");
1852	BENCH_TSC(ASMSerializeInstructionCpuId(), "ASMSerializeInstructionCpuId");
1853	BENCH_TSC(ASMSerializeInstructionIRet(), "ASMSerializeInstructionIRet");
1854
1855	/* The Darwin gcc does not like this ... */
1856	#if !defined(RT_OS_DARWIN) && !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1857	BENCH(s_u8 = ASMGetApicId(), "ASMGetApicId");
1858	#endif
1859	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1860	uint32_t uAux;
1861	if ( ASMHasCpuId()
1862	&& ASMIsValidExtRange(ASMCpuId_EAX(0x80000000))
1863	&& (ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP) )
1864	{
1865	BENCH_TSC(ASMSerializeInstructionRdTscp(), "ASMSerializeInstructionRdTscp");
1866	BENCH(s_u64 = ASMReadTscWithAux(&uAux), "ASMReadTscWithAux");
1867	}
1868	BENCH(s_u64 = ASMReadTSC(), "ASMReadTSC");
1869	union
1870	{
1871	uint64_t u64[2];
1872	RTIDTR Unaligned;
1873	struct
1874	{
1875	uint16_t abPadding[3];
1876	RTIDTR Aligned;
1877	} s;
1878	} uBuf;
1879	Assert(((uintptr_t)&uBuf.Unaligned.pIdt & (sizeof(uintptr_t) - 1)) != 0);
1880	BENCH(ASMGetIDTR(&uBuf.Unaligned), "ASMGetIDTR/unaligned");
1881	Assert(((uintptr_t)&uBuf.s.Aligned.pIdt & (sizeof(uintptr_t) - 1)) == 0);
1882	BENCH(ASMGetIDTR(&uBuf.s.Aligned), "ASMGetIDTR/aligned");
1883	#endif
1884
1885	#undef BENCH
1886	}
1887
1888
1889	int main(int argc, char **argv)
1890	{
1891	RT_NOREF_PV(argc); RT_NOREF_PV(argv);
1892
1893	int rc = RTTestInitAndCreate("tstRTInlineAsm", &g_hTest);
1894	if (rc)
1895	return rc;
1896	RTTestBanner(g_hTest);
1897
1898	/*
1899	* Execute the tests.
1900	*/
1901	#if !defined(GCC44_32BIT_PIC) && (defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86))
1902	tstASMCpuId();
1903	//bruteForceCpuId();
1904	#endif
1905	#if 1
1906	tstASMAtomicXchgU8();
1907	tstASMAtomicXchgU16();
1908	tstASMAtomicXchgU32();
1909	tstASMAtomicXchgU64();
1910	tstASMAtomicXchgPtr();
1911	tstASMAtomicCmpXchgU8();
1912	tstASMAtomicCmpXchgU32();
1913	tstASMAtomicCmpXchgU64();
1914	tstASMAtomicCmpXchgExU32();
1915	tstASMAtomicCmpXchgExU64();
1916	tstASMAtomicReadU64();
1917	tstASMAtomicUoReadU64();
1918
1919	tstASMAtomicAddS32();
1920	tstASMAtomicAddS64();
1921	tstASMAtomicDecIncS32();
1922	tstASMAtomicDecIncS64();
1923	tstASMAtomicAndOrU32();
1924	tstASMAtomicAndOrU64();
1925
1926	tstASMAtomicUoIncU32();
1927	tstASMAtomicUoDecU32();
1928	tstASMAtomicUoAndOrU32();
1929
1930	tstASMMemZeroPage();
1931	tstASMMemIsZeroPage(g_hTest);
1932	tstASMMemFirstMismatchingU8(g_hTest);
1933	tstASMMemZero32();
1934	tstASMMemFill32();
1935
1936	tstASMMath();
1937
1938	tstASMByteSwap();
1939
1940	tstASMBench();
1941	#endif
1942
1943	/*
1944	* Show the result.
1945	*/
1946	return RTTestSummaryAndDestroy(g_hTest);
1947	}
1948

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source: vbox/trunk/src/VBox/Runtime/testcase/tstRTInlineAsm.cpp@ 66404

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