ConsoleImplConfigX86.cpp@ 104760

Last change on this file since 104760 was 104702, checked in by vboxsync, 8 months ago
Main: Rebranding changes. bugref:10690
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1	/* $Id: ConsoleImplConfigX86.cpp 104702 2024-05-17 09:15:08Z vboxsync $ */
2	/** @file
3	* VBox Console COM Class implementation - VM Configuration Bits.
4	*
5	* @remark We've split out the code that the 64-bit VC++ v8 compiler finds
6	* problematic to optimize so we can disable optimizations and later,
7	* perhaps, find a real solution for it (like rewriting the code and
8	* to stop resemble a tonne of spaghetti).
9	*/
10
11	/*
12	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
13	*
14	* This file is part of VirtualBox base platform packages, as
15	* available from https://www.virtualbox.org.
16	*
17	* This program is free software; you can redistribute it and/or
18	* modify it under the terms of the GNU General Public License
19	* as published by the Free Software Foundation, in version 3 of the
20	* License.
21	*
22	* This program is distributed in the hope that it will be useful, but
23	* WITHOUT ANY WARRANTY; without even the implied warranty of
24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25	* General Public License for more details.
26	*
27	* You should have received a copy of the GNU General Public License
28	* along with this program; if not, see <https://www.gnu.org/licenses>.
29	*
30	* SPDX-License-Identifier: GPL-3.0-only
31	*/
32
33
34	/*********************************************************************************************************************************
35	* Header Files *
36	*********************************************************************************************************************************/
37	#define LOG_GROUP LOG_GROUP_MAIN_CONSOLE
38	#include "LoggingNew.h"
39
40	#include "ConsoleImpl.h"
41	#include "DisplayImpl.h"
42	#include "NvramStoreImpl.h"
43	#include "PlatformImpl.h"
44	#include "VMMDev.h"
45	#include "Global.h"
46	#ifdef VBOX_WITH_PCI_PASSTHROUGH
47	# include "PCIRawDevImpl.h"
48	#endif
49
50	// generated header
51	#include "SchemaDefs.h"
52
53	#include "AutoCaller.h"
54
55	#include <iprt/base64.h>
56	#include <iprt/buildconfig.h>
57	#include <iprt/ctype.h>
58	#include <iprt/dir.h>
59	#include <iprt/file.h>
60	#include <iprt/param.h>
61	#include <iprt/path.h>
62	#include <iprt/string.h>
63	#include <iprt/system.h>
64	#if 0 /* enable to play with lots of memory. */
65	# include <iprt/env.h>
66	#endif
67	#include <iprt/stream.h>
68
69	#include <iprt/http.h>
70	#include <iprt/socket.h>
71	#include <iprt/uri.h>
72
73	#include <VBox/vmm/vmmr3vtable.h>
74	#include <VBox/vmm/vmapi.h>
75	#include <VBox/err.h>
76	#include <VBox/param.h>
77	#include <VBox/settings.h> /* For MachineConfigFile::getHostDefaultAudioDriver(). */
78	#include <VBox/vmm/pdmapi.h> /* For PDMR3DriverAttach/PDMR3DriverDetach. */
79	#include <VBox/vmm/pdmusb.h> /* For PDMR3UsbCreateEmulatedDevice. */
80	#include <VBox/vmm/pdmdev.h> /* For PDMAPICMODE enum. */
81	#include <VBox/vmm/pdmstorageifs.h>
82	#include <VBox/version.h>
83
84	#include <VBox/com/com.h>
85	#include <VBox/com/string.h>
86	#include <VBox/com/array.h>
87
88	#include "NetworkServiceRunner.h"
89	#include "BusAssignmentManager.h"
90	#ifdef VBOX_WITH_EXTPACK
91	# include "ExtPackManagerImpl.h"
92	#endif
93
94
95	/*********************************************************************************************************************************
96	* Internal Functions *
97	*********************************************************************************************************************************/
98
99	/* Darwin compile kludge */
100	#undef PVM
101
102	/**
103	* @throws HRESULT on extra data retrival error.
104	*/
105	static int getSmcDeviceKey(IVirtualBox pVirtualBox, IMachine pMachine, Utf8Str pStrKey, bool pfGetKeyFromRealSMC)
106	{
107	*pfGetKeyFromRealSMC = false;
108
109	/*
110	* The extra data takes precedence (if non-zero).
111	*/
112	GetExtraDataBoth(pVirtualBox, pMachine, "VBoxInternal2/SmcDeviceKey", pStrKey);
113	if (pStrKey->isNotEmpty())
114	return VINF_SUCCESS;
115
116	#ifdef RT_OS_DARWIN
117
118	/*
119	* Work done in EFI/DevSmc
120	*/
121	*pfGetKeyFromRealSMC = true;
122	int vrc = VINF_SUCCESS;
123
124	#else
125	/*
126	* Is it apple hardware in bootcamp?
127	*/
128	/** @todo implement + test RTSYSDMISTR_MANUFACTURER on all hosts.
129	* Currently falling back on the product name. */
130	char szManufacturer[256];
131	szManufacturer[0] = '\0';
132	RTSystemQueryDmiString(RTSYSDMISTR_MANUFACTURER, szManufacturer, sizeof(szManufacturer));
133	if (szManufacturer[0] != '\0')
134	{
135	if ( !strcmp(szManufacturer, "Apple Computer, Inc.")
136	\|\| !strcmp(szManufacturer, "Apple Inc.")
137	)
138	*pfGetKeyFromRealSMC = true;
139	}
140	else
141	{
142	char szProdName[256];
143	szProdName[0] = '\0';
144	RTSystemQueryDmiString(RTSYSDMISTR_PRODUCT_NAME, szProdName, sizeof(szProdName));
145	if ( ( !strncmp(szProdName, RT_STR_TUPLE("Mac"))
146	\|\| !strncmp(szProdName, RT_STR_TUPLE("iMac"))
147	\|\| !strncmp(szProdName, RT_STR_TUPLE("Xserve"))
148	)
149	&& !strchr(szProdName, ' ') /* no spaces */
150	&& RT_C_IS_DIGIT(szProdName[strlen(szProdName) - 1]) /* version number */
151	)
152	*pfGetKeyFromRealSMC = true;
153	}
154
155	int vrc = VINF_SUCCESS;
156	#endif
157
158	return vrc;
159	}
160
161
162	/*
163	* VC++ 8 / amd64 has some serious trouble with the next functions.
164	* As a temporary measure, we'll drop global optimizations.
165	*/
166	#if defined(_MSC_VER) && defined(RT_ARCH_AMD64)
167	# if _MSC_VER >= RT_MSC_VER_VC80 && _MSC_VER < RT_MSC_VER_VC100
168	# pragma optimize("g", off)
169	# endif
170	#endif
171
172	/** Helper that finds out the next HBA port used
173	*/
174	static LONG GetNextUsedPort(LONG aPortUsed[30], LONG lBaseVal, uint32_t u32Size)
175	{
176	LONG lNextPortUsed = 30;
177	for (size_t j = 0; j < u32Size; ++j)
178	{
179	if ( aPortUsed[j] > lBaseVal
180	&& aPortUsed[j] <= lNextPortUsed)
181	lNextPortUsed = aPortUsed[j];
182	}
183	return lNextPortUsed;
184	}
185
186	#define MAX_BIOS_LUN_COUNT 4
187
188	int Console::SetBiosDiskInfo(ComPtr<IMachine> pMachine, PCFGMNODE pCfg, PCFGMNODE pBiosCfg,
189	Bstr controllerName, const char * const s_apszBiosConfig[4])
190	{
191	RT_NOREF(pCfg);
192	HRESULT hrc;
193	#define MAX_DEVICES 30
194	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
195	#define VRC() AssertLogRelMsgReturn(RT_SUCCESS(vrc), ("vrc=%Rrc\n", vrc), vrc)
196
197	LONG lPortLUN[MAX_BIOS_LUN_COUNT];
198	LONG lPortUsed[MAX_DEVICES];
199	uint32_t u32HDCount = 0;
200
201	/* init to max value */
202	lPortLUN[0] = MAX_DEVICES;
203
204	com::SafeIfaceArray<IMediumAttachment> atts;
205	hrc = pMachine->GetMediumAttachmentsOfController(controllerName.raw(),
206	ComSafeArrayAsOutParam(atts)); H();
207	size_t uNumAttachments = atts.size();
208	if (uNumAttachments > MAX_DEVICES)
209	{
210	LogRel(("Number of Attachments > Max=%d.\n", uNumAttachments));
211	uNumAttachments = MAX_DEVICES;
212	}
213
214	/* Find the relevant ports/IDs, i.e the ones to which a HD is attached. */
215	for (size_t j = 0; j < uNumAttachments; ++j)
216	{
217	IMediumAttachment *pMediumAtt = atts[j];
218	LONG lPortNum = 0;
219	hrc = pMediumAtt->COMGETTER(Port)(&lPortNum); H();
220	if (SUCCEEDED(hrc))
221	{
222	DeviceType_T lType;
223	hrc = pMediumAtt->COMGETTER(Type)(&lType); H();
224	if (SUCCEEDED(hrc) && lType == DeviceType_HardDisk)
225	{
226	/* find min port number used for HD */
227	if (lPortNum < lPortLUN[0])
228	lPortLUN[0] = lPortNum;
229	lPortUsed[u32HDCount++] = lPortNum;
230	LogFlowFunc(("HD port Count=%d\n", u32HDCount));
231	}
232	}
233	}
234
235
236	/* Pick only the top 4 used HD Ports as CMOS doesn't have space
237	* to save details for all 30 ports
238	*/
239	uint32_t u32MaxPortCount = MAX_BIOS_LUN_COUNT;
240	if (u32HDCount < MAX_BIOS_LUN_COUNT)
241	u32MaxPortCount = u32HDCount;
242	for (size_t j = 1; j < u32MaxPortCount; j++)
243	lPortLUN[j] = GetNextUsedPort(lPortUsed, lPortLUN[j-1], u32HDCount);
244	if (pBiosCfg)
245	{
246	for (size_t j = 0; j < u32MaxPortCount; j++)
247	{
248	InsertConfigInteger(pBiosCfg, s_apszBiosConfig[j], lPortLUN[j]);
249	LogFlowFunc(("Top %d HBA ports = %s, %d\n", j, s_apszBiosConfig[j], lPortLUN[j]));
250	}
251	}
252	return VINF_SUCCESS;
253	}
254
255	#ifdef VBOX_WITH_PCI_PASSTHROUGH
256	HRESULT Console::i_attachRawPCIDevices(PUVM pUVM, BusAssignmentManager *pBusMgr, PCFGMNODE pDevices)
257	{
258	# ifndef VBOX_WITH_EXTPACK
259	RT_NOREF(pUVM);
260	# endif
261	HRESULT hrc = S_OK;
262	PCFGMNODE pInst, pCfg, pLunL0, pLunL1;
263
264	SafeIfaceArray<IPCIDeviceAttachment> assignments;
265	ComPtr<IMachine> aMachine = i_machine();
266
267	hrc = aMachine->COMGETTER(PCIDeviceAssignments)(ComSafeArrayAsOutParam(assignments));
268	if ( hrc != S_OK
269	\|\| assignments.size() < 1)
270	return hrc;
271
272	/*
273	* PCI passthrough is only available if the proper ExtPack is installed.
274	*
275	* Note. Configuring PCI passthrough here and providing messages about
276	* the missing extpack isn't exactly clean, but it is a necessary evil
277	* to patch over legacy compatability issues introduced by the new
278	* distribution model.
279	*/
280	# ifdef VBOX_WITH_EXTPACK
281	static const char *s_pszPCIRawExtPackName = VBOX_PUEL_PRODUCT;
282	if ( !mptrExtPackManager->i_isExtPackUsable(s_pszPCIRawExtPackName)
283	&& !mptrExtPackManager->i_isExtPackUsable("Oracle VM VirtualBox Extension Pack")) /* Legacy name -- see @bugref{10690}. */
284	/* Always fatal! */
285	return pVMM->pfnVMR3SetError(pUVM, VERR_NOT_FOUND, RT_SRC_POS,
286	N_("Implementation of the PCI passthrough framework not found!\n"
287	"The VM cannot be started. To fix this problem, either "
288	"install the '%s' or disable PCI passthrough via VBoxManage"),
289	s_pszPCIRawExtPackName);
290	# endif
291
292	/* Now actually add devices */
293	PCFGMNODE pPCIDevs = NULL;
294
295	if (assignments.size() > 0)
296	{
297	InsertConfigNode(pDevices, "pciraw", &pPCIDevs);
298
299	PCFGMNODE pRoot = CFGMR3GetParent(pDevices); Assert(pRoot);
300
301	/* Tell PGM to tell GPCIRaw about guest mappings. */
302	CFGMR3InsertNode(pRoot, "PGM", NULL);
303	InsertConfigInteger(CFGMR3GetChild(pRoot, "PGM"), "PciPassThrough", 1);
304
305	/*
306	* Currently, using IOMMU needed for PCI passthrough
307	* requires RAM preallocation.
308	*/
309	/** @todo check if we can lift this requirement */
310	CFGMR3RemoveValue(pRoot, "RamPreAlloc");
311	InsertConfigInteger(pRoot, "RamPreAlloc", 1);
312	}
313
314	for (size_t iDev = 0; iDev < assignments.size(); iDev++)
315	{
316	ComPtr<IPCIDeviceAttachment> const assignment = assignments[iDev];
317
318	LONG host;
319	hrc = assignment->COMGETTER(HostAddress)(&host); H();
320	LONG guest;
321	hrc = assignment->COMGETTER(GuestAddress)(&guest); H();
322	Bstr bstrDevName;
323	hrc = assignment->COMGETTER(Name)(bstrDevName.asOutParam()); H();
324
325	InsertConfigNodeF(pPCIDevs, &pInst, "%d", iDev);
326	InsertConfigInteger(pInst, "Trusted", 1);
327
328	PCIBusAddress HostPCIAddress(host);
329	Assert(HostPCIAddress.valid());
330	InsertConfigNode(pInst, "Config", &pCfg);
331	InsertConfigString(pCfg, "DeviceName", bstrDevName);
332
333	InsertConfigInteger(pCfg, "DetachHostDriver", 1);
334	InsertConfigInteger(pCfg, "HostPCIBusNo", HostPCIAddress.miBus);
335	InsertConfigInteger(pCfg, "HostPCIDeviceNo", HostPCIAddress.miDevice);
336	InsertConfigInteger(pCfg, "HostPCIFunctionNo", HostPCIAddress.miFn);
337
338	PCIBusAddress GuestPCIAddress(guest);
339	Assert(GuestPCIAddress.valid());
340	hrc = pBusMgr->assignHostPCIDevice("pciraw", pInst, HostPCIAddress, GuestPCIAddress, true);
341	if (hrc != S_OK)
342	return hrc;
343
344	InsertConfigInteger(pCfg, "GuestPCIBusNo", GuestPCIAddress.miBus);
345	InsertConfigInteger(pCfg, "GuestPCIDeviceNo", GuestPCIAddress.miDevice);
346	InsertConfigInteger(pCfg, "GuestPCIFunctionNo", GuestPCIAddress.miFn);
347
348	/* the driver */
349	InsertConfigNode(pInst, "LUN#0", &pLunL0);
350	InsertConfigString(pLunL0, "Driver", "pciraw");
351	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
352
353	/* the Main driver */
354	InsertConfigString(pLunL1, "Driver", "MainPciRaw");
355	InsertConfigNode(pLunL1, "Config", &pCfg);
356	PCIRawDev *pMainDev = new PCIRawDev(this);
357	# error This is not allowed any more
358	InsertConfigInteger(pCfg, "Object", (uintptr_t)pMainDev);
359	}
360
361	return hrc;
362	}
363	#endif
364
365
366	/**
367	* Worker for configConstructor.
368	*
369	* @return VBox status code.
370	* @param pUVM The user mode VM handle.
371	* @param pVM The cross context VM handle.
372	* @param pVMM The VMM vtable.
373	* @param pAlock The automatic lock instance. This is for when we have
374	* to leave it in order to avoid deadlocks (ext packs and
375	* more).
376	*/
377	int Console::i_configConstructorX86(PUVM pUVM, PVM pVM, PCVMMR3VTABLE pVMM, AutoWriteLock *pAlock)
378	{
379	RT_NOREF(pVM /* when everything is disabled */);
380	ComPtr<IMachine> pMachine = i_machine();
381
382	int vrc;
383	HRESULT hrc;
384	Utf8Str strTmp;
385	Bstr bstr;
386
387	#define H() AssertLogRelMsgReturn(!FAILED(hrc), ("hrc=%Rhrc\n", hrc), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR)
388
389	/*
390	* Get necessary objects and frequently used parameters.
391	*/
392	ComPtr<IVirtualBox> virtualBox;
393	hrc = pMachine->COMGETTER(Parent)(virtualBox.asOutParam()); H();
394
395	ComPtr<IHost> host;
396	hrc = virtualBox->COMGETTER(Host)(host.asOutParam()); H();
397
398	ComPtr<ISystemProperties> systemProperties;
399	hrc = virtualBox->COMGETTER(SystemProperties)(systemProperties.asOutParam()); H();
400
401	ComPtr<IFirmwareSettings> firmwareSettings;
402	hrc = pMachine->COMGETTER(FirmwareSettings)(firmwareSettings.asOutParam()); H();
403
404	ComPtr<INvramStore> nvramStore;
405	hrc = pMachine->COMGETTER(NonVolatileStore)(nvramStore.asOutParam()); H();
406
407	hrc = pMachine->COMGETTER(HardwareUUID)(bstr.asOutParam()); H();
408	RTUUID HardwareUuid;
409	vrc = RTUuidFromUtf16(&HardwareUuid, bstr.raw());
410	AssertRCReturn(vrc, vrc);
411
412	ULONG cRamMBs;
413	hrc = pMachine->COMGETTER(MemorySize)(&cRamMBs); H();
414	#if 0 /* enable to play with lots of memory. */
415	if (RTEnvExist("VBOX_RAM_SIZE"))
416	cRamMBs = RTStrToUInt64(RTEnvGet("VBOX_RAM_SIZE"));
417	#endif
418	uint64_t const cbRam = cRamMBs * (uint64_t)_1M;
419	uint32_t cbRamHole = MM_RAM_HOLE_SIZE_DEFAULT;
420	uint64_t uMcfgBase = 0;
421	uint32_t cbMcfgLength = 0;
422
423	ParavirtProvider_T enmParavirtProvider;
424	hrc = pMachine->GetEffectiveParavirtProvider(&enmParavirtProvider); H();
425
426	Bstr strParavirtDebug;
427	hrc = pMachine->COMGETTER(ParavirtDebug)(strParavirtDebug.asOutParam()); H();
428
429	BOOL fIOAPIC;
430	uint32_t uIoApicPciAddress = NIL_PCIBDF;
431	hrc = firmwareSettings->COMGETTER(IOAPICEnabled)(&fIOAPIC); H();
432
433	ComPtr<IPlatform> platform;
434	pMachine->COMGETTER(Platform)(platform.asOutParam()); H();
435
436	ChipsetType_T chipsetType;
437	hrc = platform->COMGETTER(ChipsetType)(&chipsetType); H();
438	if (chipsetType == ChipsetType_ICH9)
439	{
440	/* We'd better have 0x10000000 region, to cover 256 buses but this put
441	* too much load on hypervisor heap. Linux 4.8 currently complains with
442	* ``acpi PNP0A03:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f]
443	* only partially covers this bridge'' */
444	cbMcfgLength = 0x4000000; //0x10000000;
445	cbRamHole += cbMcfgLength;
446	uMcfgBase = _4G - cbRamHole;
447	}
448
449	/* Get the CPU profile name. */
450	Bstr bstrCpuProfile;
451	hrc = pMachine->COMGETTER(CPUProfile)(bstrCpuProfile.asOutParam()); H();
452
453	/* Get the X86 platform object. */
454	ComPtr<IPlatformX86> platformX86;
455	hrc = platform->COMGETTER(X86)(platformX86.asOutParam()); H();
456
457	/* Check if long mode is enabled. */
458	BOOL fIsGuest64Bit;
459	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_LongMode, &fIsGuest64Bit); H();
460
461	/*
462	* Figure out the IOMMU config.
463	*/
464	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
465	IommuType_T enmIommuType;
466	hrc = platform->COMGETTER(IommuType)(&enmIommuType); H();
467
468	/* Resolve 'automatic' type to an Intel or AMD IOMMU based on the host CPU. */
469	if (enmIommuType == IommuType_Automatic)
470	{
471	if ( bstrCpuProfile.startsWith("AMD")
472	\|\| bstrCpuProfile.startsWith("Quad-Core AMD")
473	\|\| bstrCpuProfile.startsWith("Hygon"))
474	enmIommuType = IommuType_AMD;
475	else if (bstrCpuProfile.startsWith("Intel"))
476	{
477	if ( bstrCpuProfile.equals("Intel 8086")
478	\|\| bstrCpuProfile.equals("Intel 80186")
479	\|\| bstrCpuProfile.equals("Intel 80286")
480	\|\| bstrCpuProfile.equals("Intel 80386")
481	\|\| bstrCpuProfile.equals("Intel 80486"))
482	enmIommuType = IommuType_None;
483	else
484	enmIommuType = IommuType_Intel;
485	}
486	# if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
487	else if (ASMIsAmdCpu())
488	enmIommuType = IommuType_AMD;
489	else if (ASMIsIntelCpu())
490	enmIommuType = IommuType_Intel;
491	# endif
492	else
493	{
494	/** @todo Should we handle other CPUs like Shanghai, VIA etc. here? */
495	LogRel(("WARNING! Unrecognized CPU type, IOMMU disabled.\n"));
496	enmIommuType = IommuType_None;
497	}
498	}
499
500	if (enmIommuType == IommuType_AMD)
501	{
502	# ifdef VBOX_WITH_IOMMU_AMD
503	/*
504	* Reserve the specific PCI address of the "SB I/O APIC" when using
505	* an AMD IOMMU. Required by Linux guests, see @bugref{9654#c23}.
506	*/
507	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
508	# else
509	LogRel(("WARNING! AMD IOMMU not supported, IOMMU disabled.\n"));
510	enmIommuType = IommuType_None;
511	# endif
512	}
513
514	if (enmIommuType == IommuType_Intel)
515	{
516	# ifdef VBOX_WITH_IOMMU_INTEL
517	/*
518	* Reserve a unique PCI address for the I/O APIC when using
519	* an Intel IOMMU. For convenience we use the same address as
520	* we do on AMD, see @bugref{9967#c13}.
521	*/
522	uIoApicPciAddress = VBOX_PCI_BDF_SB_IOAPIC;
523	# else
524	LogRel(("WARNING! Intel IOMMU not supported, IOMMU disabled.\n"));
525	enmIommuType = IommuType_None;
526	# endif
527	}
528
529	if ( enmIommuType == IommuType_AMD
530	\|\| enmIommuType == IommuType_Intel)
531	{
532	if (chipsetType != ChipsetType_ICH9)
533	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
534	N_("IOMMU uses MSIs which requires the ICH9 chipset implementation."));
535	if (!fIOAPIC)
536	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
537	N_("IOMMU requires an I/O APIC for remapping interrupts."));
538	}
539	#else
540	IommuType_T const enmIommuType = IommuType_None;
541	#endif
542
543	/* Instantiate the bus assignment manager. */
544	Assert(enmIommuType != IommuType_Automatic);
545	BusAssignmentManager *pBusMgr = mBusMgr = BusAssignmentManager::createInstance(pVMM, chipsetType, enmIommuType);
546
547	ULONG cCpus = 1;
548	hrc = pMachine->COMGETTER(CPUCount)(&cCpus); H();
549
550	ULONG ulCpuExecutionCap = 100;
551	hrc = pMachine->COMGETTER(CPUExecutionCap)(&ulCpuExecutionCap); H();
552
553	VMExecutionEngine_T enmExecEngine = VMExecutionEngine_NotSet;
554	hrc = pMachine->COMGETTER(VMExecutionEngine)(&enmExecEngine); H();
555
556	LogRel(("Guest architecture: x86\n"));
557
558	Bstr osTypeId;
559	hrc = pMachine->COMGETTER(OSTypeId)(osTypeId.asOutParam()); H();
560	LogRel(("Guest OS type: '%s'\n", Utf8Str(osTypeId).c_str()));
561
562	APICMode_T apicMode;
563	hrc = firmwareSettings->COMGETTER(APICMode)(&apicMode); H();
564	uint32_t uFwAPIC;
565	switch (apicMode)
566	{
567	case APICMode_Disabled:
568	uFwAPIC = 0;
569	break;
570	case APICMode_APIC:
571	uFwAPIC = 1;
572	break;
573	case APICMode_X2APIC:
574	uFwAPIC = 2;
575	break;
576	default:
577	AssertMsgFailed(("Invalid APICMode=%d\n", apicMode));
578	uFwAPIC = 1;
579	break;
580	}
581
582	ComPtr<IGuestOSType> pGuestOSType;
583	virtualBox->GetGuestOSType(osTypeId.raw(), pGuestOSType.asOutParam());
584
585	BOOL fOsXGuest = FALSE;
586	BOOL fWinGuest = FALSE;
587	BOOL fOs2Guest = FALSE;
588	BOOL fW9xGuest = FALSE;
589	BOOL fDosGuest = FALSE;
590	if (pGuestOSType.isNotNull())
591	{
592	Bstr guestTypeFamilyId;
593	hrc = pGuestOSType->COMGETTER(FamilyId)(guestTypeFamilyId.asOutParam()); H();
594	fOsXGuest = guestTypeFamilyId == Bstr("MacOS");
595	fWinGuest = guestTypeFamilyId == Bstr("Windows");
596	fOs2Guest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("OS2"));
597	fW9xGuest = osTypeId.startsWith(GUEST_OS_ID_STR_PARTIAL("Windows9")); /* Does not include Windows Me. */
598	fDosGuest = osTypeId.equals(GUEST_OS_ID_STR_X86("DOS")) \|\| osTypeId.equals(GUEST_OS_ID_STR_X86("Windows31"));
599	}
600
601	ComPtr<IPlatformProperties> platformProperties;
602	virtualBox->GetPlatformProperties(PlatformArchitecture_x86, platformProperties.asOutParam());
603
604	/*
605	* Get root node first.
606	* This is the only node in the tree.
607	*/
608	PCFGMNODE pRoot = pVMM->pfnCFGMR3GetRootU(pUVM);
609	Assert(pRoot);
610
611	// catching throws from InsertConfigString and friends.
612	try
613	{
614
615	/*
616	* Set the root (and VMM) level values.
617	*/
618	hrc = pMachine->COMGETTER(Name)(bstr.asOutParam()); H();
619	InsertConfigString(pRoot, "Name", bstr);
620	InsertConfigBytes(pRoot, "UUID", &HardwareUuid, sizeof(HardwareUuid));
621	InsertConfigInteger(pRoot, "RamSize", cbRam);
622	InsertConfigInteger(pRoot, "RamHoleSize", cbRamHole);
623	InsertConfigInteger(pRoot, "NumCPUs", cCpus);
624	InsertConfigInteger(pRoot, "CpuExecutionCap", ulCpuExecutionCap);
625	InsertConfigInteger(pRoot, "TimerMillies", 10);
626
627	BOOL fPageFusion = FALSE;
628	hrc = pMachine->COMGETTER(PageFusionEnabled)(&fPageFusion); H();
629	InsertConfigInteger(pRoot, "PageFusionAllowed", fPageFusion); /* boolean */
630
631	/* Not necessary, but makes sure this setting ends up in the release log. */
632	ULONG ulBalloonSize = 0;
633	hrc = pMachine->COMGETTER(MemoryBalloonSize)(&ulBalloonSize); H();
634	InsertConfigInteger(pRoot, "MemBalloonSize", ulBalloonSize);
635
636	/*
637	* EM values (before CPUM as it may need to set IemExecutesAll).
638	*/
639	PCFGMNODE pEM;
640	InsertConfigNode(pRoot, "EM", &pEM);
641
642	/* Triple fault behavior. */
643	BOOL fTripleFaultReset = false;
644	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_TripleFaultReset, &fTripleFaultReset); H();
645	InsertConfigInteger(pEM, "TripleFaultReset", fTripleFaultReset);
646
647	/*
648	* CPUM values.
649	*/
650	PCFGMNODE pCPUM;
651	InsertConfigNode(pRoot, "CPUM", &pCPUM);
652	PCFGMNODE pIsaExts;
653	InsertConfigNode(pCPUM, "IsaExts", &pIsaExts);
654
655	/* Host CPUID leaf overrides. */
656	for (uint32_t iOrdinal = 0; iOrdinal < _4K; iOrdinal++)
657	{
658	ULONG uLeaf, uSubLeaf, uEax, uEbx, uEcx, uEdx;
659	hrc = platformX86->GetCPUIDLeafByOrdinal(iOrdinal, &uLeaf, &uSubLeaf, &uEax, &uEbx, &uEcx, &uEdx);
660	if (hrc == E_INVALIDARG)
661	break;
662	H();
663	PCFGMNODE pLeaf;
664	InsertConfigNode(pCPUM, Utf8StrFmt("HostCPUID/%RX32", uLeaf).c_str(), &pLeaf);
665	/** @todo Figure out how to tell the VMM about uSubLeaf */
666	InsertConfigInteger(pLeaf, "eax", uEax);
667	InsertConfigInteger(pLeaf, "ebx", uEbx);
668	InsertConfigInteger(pLeaf, "ecx", uEcx);
669	InsertConfigInteger(pLeaf, "edx", uEdx);
670	}
671
672	/* We must limit CPUID count for Windows NT 4, as otherwise it stops
673	with error 0x3e (MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED). */
674	if (osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4"))
675	{
676	LogRel(("Limiting CPUID leaf count for NT4 guests\n"));
677	InsertConfigInteger(pCPUM, "NT4LeafLimit", true);
678	}
679
680	if (fOsXGuest)
681	{
682	/* Expose extended MWAIT features to Mac OS X guests. */
683	LogRel(("Using MWAIT extensions\n"));
684	InsertConfigInteger(pIsaExts, "MWaitExtensions", true);
685
686	/* Fake the CPU family/model so the guest works. This is partly
687	because older mac releases really doesn't work on newer cpus,
688	and partly because mac os x expects more from systems with newer
689	cpus (MSRs, power features, whatever). */
690	uint32_t uMaxIntelFamilyModelStep = UINT32_MAX;
691	if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS")
692	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS"))
693	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482. */
694	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS106")
695	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS106"))
696	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 */
697	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS107")
698	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS107"))
699	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
700	what is required here. */
701	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS108")
702	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS108"))
703	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure out
704	what is required here. */
705	else if ( osTypeId == GUEST_OS_ID_STR_X86("MacOS109")
706	\|\| osTypeId == GUEST_OS_ID_STR_X64("MacOS109"))
707	uMaxIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(1, 23, 6, 0); /* Penryn / X5482 / /* @todo figure
708	out what is required here. */
709	if (uMaxIntelFamilyModelStep != UINT32_MAX)
710	InsertConfigInteger(pCPUM, "MaxIntelFamilyModelStep", uMaxIntelFamilyModelStep);
711	}
712
713	/* CPU Portability level, */
714	ULONG uCpuIdPortabilityLevel = 0;
715	hrc = pMachine->COMGETTER(CPUIDPortabilityLevel)(&uCpuIdPortabilityLevel); H();
716	InsertConfigInteger(pCPUM, "PortableCpuIdLevel", uCpuIdPortabilityLevel);
717
718	/* Physical Address Extension (PAE) */
719	BOOL fEnablePAE = false;
720	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_PAE, &fEnablePAE); H();
721	fEnablePAE \|= fIsGuest64Bit;
722	InsertConfigInteger(pRoot, "EnablePAE", fEnablePAE);
723
724	/* 64-bit guests (long mode) */
725	InsertConfigInteger(pCPUM, "Enable64bit", fIsGuest64Bit);
726
727	/* APIC/X2APIC configuration */
728	BOOL fEnableAPIC = true;
729	BOOL fEnableX2APIC = true;
730	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_APIC, &fEnableAPIC); H();
731	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_X2APIC, &fEnableX2APIC); H();
732	if (fEnableX2APIC)
733	Assert(fEnableAPIC);
734
735	/* CPUM profile name. */
736	InsertConfigString(pCPUM, "GuestCpuName", bstrCpuProfile);
737
738	/*
739	* Temporary(?) hack to make sure we emulate the ancient 16-bit CPUs
740	* correctly. There are way too many #UDs we'll miss using VT-x,
741	* raw-mode or qemu for the 186 and 286, while we'll get undefined opcodes
742	* dead wrong on 8086 (see http://www.os2museum.com/wp/undocumented-8086-opcodes/).
743	*/
744	if ( bstrCpuProfile.equals("Intel 80386") /* just for now */
745	\|\| bstrCpuProfile.equals("Intel 80286")
746	\|\| bstrCpuProfile.equals("Intel 80186")
747	\|\| bstrCpuProfile.equals("Nec V20")
748	\|\| bstrCpuProfile.equals("Intel 8086") )
749	{
750	InsertConfigInteger(pEM, "IemExecutesAll", true);
751	if (!bstrCpuProfile.equals("Intel 80386"))
752	{
753	fEnableAPIC = false;
754	fIOAPIC = false;
755	}
756	fEnableX2APIC = false;
757	}
758
759	/* Adjust firmware APIC handling to stay within the VCPU limits. */
760	if (uFwAPIC == 2 && !fEnableX2APIC)
761	{
762	if (fEnableAPIC)
763	uFwAPIC = 1;
764	else
765	uFwAPIC = 0;
766	LogRel(("Limiting the firmware APIC level from x2APIC to %s\n", fEnableAPIC ? "APIC" : "Disabled"));
767	}
768	else if (uFwAPIC == 1 && !fEnableAPIC)
769	{
770	uFwAPIC = 0;
771	LogRel(("Limiting the firmware APIC level from APIC to Disabled\n"));
772	}
773
774	/* Speculation Control. */
775	BOOL fSpecCtrl = FALSE;
776	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrl, &fSpecCtrl); H();
777	InsertConfigInteger(pCPUM, "SpecCtrl", fSpecCtrl);
778
779	/* Nested VT-x / AMD-V. */
780	BOOL fNestedHWVirt = FALSE;
781	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_HWVirt, &fNestedHWVirt); H();
782	InsertConfigInteger(pCPUM, "NestedHWVirt", fNestedHWVirt ? true : false);
783
784	/*
785	* Hardware virtualization extensions.
786	*/
787	/* Sanitize valid/useful APIC combinations, see @bugref{8868}. */
788	if (!fEnableAPIC)
789	{
790	if (fIsGuest64Bit)
791	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
792	N_("Cannot disable the APIC for a 64-bit guest."));
793	if (cCpus > 1)
794	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
795	N_("Cannot disable the APIC for an SMP guest."));
796	if (fIOAPIC)
797	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
798	N_("Cannot disable the APIC when the I/O APIC is present."));
799	}
800
801	BOOL fHMEnabled;
802	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Enabled, &fHMEnabled); H();
803	if (cCpus > 1 && !fHMEnabled)
804	{
805	LogRel(("Forced fHMEnabled to TRUE by SMP guest.\n"));
806	fHMEnabled = TRUE;
807	}
808
809	BOOL fHMForced;
810	fHMEnabled = fHMForced = TRUE;
811	LogRel(("fHMForced=true - No raw-mode support in this build!\n"));
812	if (!fHMForced) /* No need to query if already forced above. */
813	{
814	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_Force, &fHMForced); H();
815	if (fHMForced)
816	LogRel(("fHMForced=true - HWVirtExPropertyType_Force\n"));
817	}
818	InsertConfigInteger(pRoot, "HMEnabled", fHMEnabled);
819
820	/* /HM/xyz */
821	PCFGMNODE pHM;
822	InsertConfigNode(pRoot, "HM", &pHM);
823	InsertConfigInteger(pHM, "HMForced", fHMForced);
824	if (fHMEnabled)
825	{
826	/* Indicate whether 64-bit guests are supported or not. */
827	InsertConfigInteger(pHM, "64bitEnabled", fIsGuest64Bit);
828
829	/** @todo Not exactly pretty to check strings; VBOXOSTYPE would be better,
830	but that requires quite a bit of API change in Main. */
831	if ( fIOAPIC
832	&& ( osTypeId == GUEST_OS_ID_STR_X86("WindowsNT4")
833	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2000")
834	\|\| osTypeId == GUEST_OS_ID_STR_X86("WindowsXP")
835	\|\| osTypeId == GUEST_OS_ID_STR_X86("Windows2003")))
836	{
837	/* Only allow TPR patching for NT, Win2k, XP and Windows Server 2003. (32 bits mode)
838	* We may want to consider adding more guest OSes (Solaris) later on.
839	*/
840	InsertConfigInteger(pHM, "TPRPatchingEnabled", 1);
841	}
842	}
843
844	/*
845	* Set VM execution engine.
846	*/
847	/** @todo r=aeichner Maybe provide a better VMM API for this instead of the different CFGM knobs. */
848	LogRel(("Using execution engine %u\n", enmExecEngine));
849	switch (enmExecEngine)
850	{
851	case VMExecutionEngine_HwVirt:
852	InsertConfigInteger(pEM, "IemExecutesAll", 0);
853	InsertConfigInteger(pEM, "IemRecompiled", 0);
854	InsertConfigInteger(pHM, "UseNEMInstead", 0);
855	InsertConfigInteger(pHM, "FallbackToNEM", 0);
856	InsertConfigInteger(pHM, "FallbackToIEM", 0);
857	break;
858	case VMExecutionEngine_NativeApi:
859	InsertConfigInteger(pEM, "IemExecutesAll", 0);
860	InsertConfigInteger(pEM, "IemRecompiled", 0);
861	InsertConfigInteger(pHM, "UseNEMInstead", 1);
862	InsertConfigInteger(pHM, "FallbackToNEM", 1);
863	InsertConfigInteger(pHM, "FallbackToIEM", 0);
864	break;
865	case VMExecutionEngine_Interpreter:
866	case VMExecutionEngine_Recompiler:
867	InsertConfigInteger(pEM, "IemExecutesAll", 1);
868	InsertConfigInteger(pEM, "IemRecompiled", enmExecEngine == VMExecutionEngine_Recompiler);
869	InsertConfigInteger(pHM, "UseNEMInstead", 0);
870	InsertConfigInteger(pHM, "FallbackToNEM", 0);
871	InsertConfigInteger(pHM, "FallbackToIEM", 1);
872	break;
873	case VMExecutionEngine_Default:
874	break; /* Nothing to do, let VMM decide. */
875	default:
876	AssertLogRelFailed();
877	}
878
879	/* HWVirtEx exclusive mode */
880	BOOL fHMExclusive = true;
881	hrc = platformProperties->COMGETTER(ExclusiveHwVirt)(&fHMExclusive); H();
882	InsertConfigInteger(pHM, "Exclusive", fHMExclusive);
883
884	/* Nested paging (VT-x/AMD-V) */
885	BOOL fEnableNestedPaging = false;
886	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_NestedPaging, &fEnableNestedPaging); H();
887	InsertConfigInteger(pHM, "EnableNestedPaging", fEnableNestedPaging);
888
889	/* Large pages; requires nested paging */
890	BOOL fEnableLargePages = false;
891	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_LargePages, &fEnableLargePages); H();
892	InsertConfigInteger(pHM, "EnableLargePages", fEnableLargePages);
893
894	/* VPID (VT-x) */
895	BOOL fEnableVPID = false;
896	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_VPID, &fEnableVPID); H();
897	InsertConfigInteger(pHM, "EnableVPID", fEnableVPID);
898
899	/* Unrestricted execution aka UX (VT-x) */
900	BOOL fEnableUX = false;
901	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UnrestrictedExecution, &fEnableUX); H();
902	InsertConfigInteger(pHM, "EnableUX", fEnableUX);
903
904	/* Virtualized VMSAVE/VMLOAD (AMD-V) */
905	BOOL fVirtVmsaveVmload = true;
906	hrc = host->GetProcessorFeature(ProcessorFeature_VirtVmsaveVmload, &fVirtVmsaveVmload); H();
907	InsertConfigInteger(pHM, "SvmVirtVmsaveVmload", fVirtVmsaveVmload);
908
909	/* Indirect branch prediction boundraries. */
910	BOOL fIBPBOnVMExit = false;
911	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMExit, &fIBPBOnVMExit); H();
912	InsertConfigInteger(pHM, "IBPBOnVMExit", fIBPBOnVMExit);
913
914	BOOL fIBPBOnVMEntry = false;
915	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_IBPBOnVMEntry, &fIBPBOnVMEntry); H();
916	InsertConfigInteger(pHM, "IBPBOnVMEntry", fIBPBOnVMEntry);
917
918	BOOL fSpecCtrlByHost = false;
919	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_SpecCtrlByHost, &fSpecCtrlByHost); H();
920	InsertConfigInteger(pHM, "SpecCtrlByHost", fSpecCtrlByHost);
921
922	BOOL fL1DFlushOnSched = true;
923	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnEMTScheduling, &fL1DFlushOnSched); H();
924	InsertConfigInteger(pHM, "L1DFlushOnSched", fL1DFlushOnSched);
925
926	BOOL fL1DFlushOnVMEntry = false;
927	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
928	InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
929
930	BOOL fMDSClearOnSched = true;
931	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
932	InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
933
934	BOOL fMDSClearOnVMEntry = false;
935	hrc = platformX86->GetCPUProperty(CPUPropertyTypeX86_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
936	InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
937
938	/* Reset overwrite. */
939	mfTurnResetIntoPowerOff = GetExtraDataBoth(virtualBox, pMachine,
940	"VBoxInternal2/TurnResetIntoPowerOff", &strTmp)->equals("1");
941	if (mfTurnResetIntoPowerOff)
942	InsertConfigInteger(pRoot, "PowerOffInsteadOfReset", 1);
943
944	/** @todo This is a bit redundant but in order to avoid forcing setting version bumps later on
945	* and don't magically change behavior of old VMs we have to keep this for now. As soon as the user sets
946	* the execution to anything else than Default the execution engine setting takes precedence.
947	*/
948	if (enmExecEngine == VMExecutionEngine_Default)
949	{
950	/* Use NEM rather than HM. */
951	BOOL fUseNativeApi = false;
952	hrc = platformX86->GetHWVirtExProperty(HWVirtExPropertyType_UseNativeApi, &fUseNativeApi); H();
953	InsertConfigInteger(pHM, "UseNEMInstead", fUseNativeApi);
954	}
955
956	/* Enable workaround for missing TLB flush for OS/2 guests, see ticketref:20625. */
957	if (fOs2Guest)
958	InsertConfigInteger(pHM, "MissingOS2TlbFlushWorkaround", 1);
959
960	/*
961	* NEM
962	*/
963	PCFGMNODE pNEM;
964	InsertConfigNode(pRoot, "NEM", &pNEM);
965	InsertConfigInteger(pNEM, "Allow64BitGuests", fIsGuest64Bit);
966
967	/*
968	* Paravirt. provider.
969	*/
970	PCFGMNODE pParavirtNode;
971	InsertConfigNode(pRoot, "GIM", &pParavirtNode);
972	const char *pcszParavirtProvider;
973	bool fGimDeviceNeeded = true;
974	switch (enmParavirtProvider)
975	{
976	case ParavirtProvider_None:
977	pcszParavirtProvider = "None";
978	fGimDeviceNeeded = false;
979	break;
980
981	case ParavirtProvider_Minimal:
982	pcszParavirtProvider = "Minimal";
983	break;
984
985	case ParavirtProvider_HyperV:
986	pcszParavirtProvider = "HyperV";
987	break;
988
989	case ParavirtProvider_KVM:
990	pcszParavirtProvider = "KVM";
991	break;
992
993	default:
994	AssertMsgFailed(("Invalid enmParavirtProvider=%d\n", enmParavirtProvider));
995	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, N_("Invalid paravirt. provider '%d'"),
996	enmParavirtProvider);
997	}
998	InsertConfigString(pParavirtNode, "Provider", pcszParavirtProvider);
999
1000	/*
1001	* Parse paravirt. debug options.
1002	*/
1003	bool fGimDebug = false;
1004	com::Utf8Str strGimDebugAddress = "127.0.0.1";
1005	uint32_t uGimDebugPort = 50000;
1006	if (strParavirtDebug.isNotEmpty())
1007	{
1008	/* Hyper-V debug options. */
1009	if (enmParavirtProvider == ParavirtProvider_HyperV)
1010	{
1011	bool fGimHvDebug = false;
1012	com::Utf8Str strGimHvVendor;
1013	bool fGimHvVsIf = false;
1014	bool fGimHvHypercallIf = false;
1015
1016	size_t uPos = 0;
1017	com::Utf8Str strDebugOptions = strParavirtDebug;
1018	com::Utf8Str strKey;
1019	com::Utf8Str strVal;
1020	while ((uPos = strDebugOptions.parseKeyValue(strKey, strVal, uPos)) != com::Utf8Str::npos)
1021	{
1022	if (strKey == "enabled")
1023	{
1024	if (strVal.toUInt32() == 1)
1025	{
1026	/* Apply defaults.
1027	The defaults are documented in the user manual,
1028	changes need to be reflected accordingly. */
1029	fGimHvDebug = true;
1030	strGimHvVendor = "Microsoft Hv";
1031	fGimHvVsIf = true;
1032	fGimHvHypercallIf = false;
1033	}
1034	/* else: ignore, i.e. don't assert below with 'enabled=0'. */
1035	}
1036	else if (strKey == "address")
1037	strGimDebugAddress = strVal;
1038	else if (strKey == "port")
1039	uGimDebugPort = strVal.toUInt32();
1040	else if (strKey == "vendor")
1041	strGimHvVendor = strVal;
1042	else if (strKey == "vsinterface")
1043	fGimHvVsIf = RT_BOOL(strVal.toUInt32());
1044	else if (strKey == "hypercallinterface")
1045	fGimHvHypercallIf = RT_BOOL(strVal.toUInt32());
1046	else
1047	{
1048	AssertMsgFailed(("Unrecognized Hyper-V debug option '%s'\n", strKey.c_str()));
1049	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1050	N_("Unrecognized Hyper-V debug option '%s' in '%s'"), strKey.c_str(),
1051	strDebugOptions.c_str());
1052	}
1053	}
1054
1055	/* Update HyperV CFGM node with active debug options. */
1056	if (fGimHvDebug)
1057	{
1058	PCFGMNODE pHvNode;
1059	InsertConfigNode(pParavirtNode, "HyperV", &pHvNode);
1060	InsertConfigString(pHvNode, "VendorID", strGimHvVendor);
1061	InsertConfigInteger(pHvNode, "VSInterface", fGimHvVsIf ? 1 : 0);
1062	InsertConfigInteger(pHvNode, "HypercallDebugInterface", fGimHvHypercallIf ? 1 : 0);
1063	fGimDebug = true;
1064	}
1065	}
1066	}
1067
1068	/*
1069	* Guest Compatibility Manager.
1070	*/
1071	PCFGMNODE pGcmNode;
1072	InsertConfigNode(pRoot, "GCM", &pGcmNode);
1073	/* OS/2 and Win9x guests can run DOS apps so they get the DOS specific
1074	fixes as well. */
1075	if (fDosGuest \|\| fOs2Guest \|\| fW9xGuest)
1076	InsertConfigInteger(pGcmNode, "DivByZeroDOS", 1);
1077	if (fOs2Guest)
1078	InsertConfigInteger(pGcmNode, "DivByZeroOS2", 1);
1079	if (fW9xGuest)
1080	InsertConfigInteger(pGcmNode, "DivByZeroWin9x", 1);
1081	/* MesaVmsvgaDrv (formerly LovelyMesaDrvWorkaround) is set futher down. */
1082
1083	/*
1084	* MM values.
1085	*/
1086	PCFGMNODE pMM;
1087	InsertConfigNode(pRoot, "MM", &pMM);
1088	InsertConfigInteger(pMM, "CanUseLargerHeap", chipsetType == ChipsetType_ICH9);
1089
1090	/*
1091	* PDM config.
1092	* Load drivers in VBoxC.[so\|dll]
1093	*/
1094	vrc = i_configPdm(pMachine, pVMM, pUVM, pRoot); VRC();
1095
1096	/*
1097	* Devices
1098	*/
1099	PCFGMNODE pDevices = NULL; /* /Devices */
1100	PCFGMNODE pDev = NULL; /* /Devices/Dev/ */
1101	PCFGMNODE pInst = NULL; /* /Devices/Dev/0/ */
1102	PCFGMNODE pCfg = NULL; /* /Devices/Dev/.../Config/ */
1103	PCFGMNODE pLunL0 = NULL; /* /Devices/Dev/0/LUN#0/ */
1104	PCFGMNODE pLunL1 = NULL; /* /Devices/Dev/0/LUN#0/AttachedDriver/ */
1105	PCFGMNODE pBiosCfg = NULL; /* /Devices/pcbios/0/Config/ */
1106	PCFGMNODE pNetBootCfg = NULL; /* /Devices/pcbios/0/Config/NetBoot/ */
1107
1108	InsertConfigNode(pRoot, "Devices", &pDevices);
1109
1110	/*
1111	* GIM Device
1112	*/
1113	if (fGimDeviceNeeded)
1114	{
1115	InsertConfigNode(pDevices, "GIMDev", &pDev);
1116	InsertConfigNode(pDev, "0", &pInst);
1117	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1118	//InsertConfigNode(pInst, "Config", &pCfg);
1119
1120	if (fGimDebug)
1121	{
1122	InsertConfigNode(pInst, "LUN#998", &pLunL0);
1123	InsertConfigString(pLunL0, "Driver", "UDP");
1124	InsertConfigNode(pLunL0, "Config", &pLunL1);
1125	InsertConfigString(pLunL1, "ServerAddress", strGimDebugAddress);
1126	InsertConfigInteger(pLunL1, "ServerPort", uGimDebugPort);
1127	}
1128	}
1129
1130	/*
1131	* PC Arch.
1132	*/
1133	InsertConfigNode(pDevices, "pcarch", &pDev);
1134	InsertConfigNode(pDev, "0", &pInst);
1135	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1136	InsertConfigNode(pInst, "Config", &pCfg);
1137
1138	/*
1139	* The time offset
1140	*/
1141	LONG64 timeOffset;
1142	hrc = firmwareSettings->COMGETTER(TimeOffset)(&timeOffset); H();
1143	PCFGMNODE pTMNode;
1144	InsertConfigNode(pRoot, "TM", &pTMNode);
1145	InsertConfigInteger(pTMNode, "UTCOffset", timeOffset * 1000000);
1146
1147	/*
1148	* DMA
1149	*/
1150	InsertConfigNode(pDevices, "8237A", &pDev);
1151	InsertConfigNode(pDev, "0", &pInst);
1152	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1153
1154	/*
1155	* PCI buses.
1156	*/
1157	uint32_t uIocPCIAddress, uHbcPCIAddress;
1158	switch (chipsetType)
1159	{
1160	default:
1161	AssertFailed();
1162	RT_FALL_THRU();
1163	case ChipsetType_PIIX3:
1164	/* Create the base for adding bridges on demand */
1165	InsertConfigNode(pDevices, "pcibridge", NULL);
1166
1167	InsertConfigNode(pDevices, "pci", &pDev);
1168	uHbcPCIAddress = (0x0 << 16) \| 0;
1169	uIocPCIAddress = (0x1 << 16) \| 0; // ISA controller
1170	break;
1171	case ChipsetType_ICH9:
1172	/* Create the base for adding bridges on demand */
1173	InsertConfigNode(pDevices, "ich9pcibridge", NULL);
1174
1175	InsertConfigNode(pDevices, "ich9pci", &pDev);
1176	uHbcPCIAddress = (0x1e << 16) \| 0;
1177	uIocPCIAddress = (0x1f << 16) \| 0; // LPC controller
1178	break;
1179	}
1180	InsertConfigNode(pDev, "0", &pInst);
1181	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1182	InsertConfigNode(pInst, "Config", &pCfg);
1183	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1184	if (chipsetType == ChipsetType_ICH9)
1185	{
1186	/* Provide MCFG info */
1187	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1188	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1189
1190	#ifdef VBOX_WITH_PCI_PASSTHROUGH
1191	/* Add PCI passthrough devices */
1192	hrc = i_attachRawPCIDevices(pUVM, pBusMgr, pDevices); H();
1193	#endif
1194
1195	if (enmIommuType == IommuType_AMD)
1196	{
1197	/* AMD IOMMU. */
1198	InsertConfigNode(pDevices, "iommu-amd", &pDev);
1199	InsertConfigNode(pDev, "0", &pInst);
1200	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1201	InsertConfigNode(pInst, "Config", &pCfg);
1202	hrc = pBusMgr->assignPCIDevice("iommu-amd", pInst); H();
1203
1204	/* The AMD IOMMU device needs to know which PCI slot it's in, see @bugref{9654#c104}. */
1205	{
1206	PCIBusAddress Address;
1207	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1208	{
1209	uint32_t const u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1210	InsertConfigInteger(pCfg, "PCIAddress", u32IommuAddress);
1211	}
1212	else
1213	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1214	N_("Failed to find PCI address of the assigned IOMMU device!"));
1215	}
1216
1217	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1218	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1219	}
1220	else if (enmIommuType == IommuType_Intel)
1221	{
1222	/* Intel IOMMU. */
1223	InsertConfigNode(pDevices, "iommu-intel", &pDev);
1224	InsertConfigNode(pDev, "0", &pInst);
1225	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1226	InsertConfigNode(pInst, "Config", &pCfg);
1227	hrc = pBusMgr->assignPCIDevice("iommu-intel", pInst); H();
1228
1229	PCIBusAddress PCIAddr = PCIBusAddress((int32_t)uIoApicPciAddress);
1230	hrc = pBusMgr->assignPCIDevice("sb-ioapic", NULL /* pCfg /, PCIAddr, true /fGuestAddressRequired*/); H();
1231	}
1232	}
1233
1234	/*
1235	* Enable the following devices: HPET, SMC and LPC on MacOS X guests or on ICH9 chipset
1236	*/
1237
1238	/*
1239	* High Precision Event Timer (HPET)
1240	*/
1241	BOOL fHPETEnabled;
1242	/* Other guests may wish to use HPET too, but MacOS X not functional without it */
1243	hrc = platformX86->COMGETTER(HPETEnabled)(&fHPETEnabled); H();
1244	/* so always enable HPET in extended profile */
1245	fHPETEnabled \|= fOsXGuest;
1246	/* HPET is always present on ICH9 */
1247	fHPETEnabled \|= (chipsetType == ChipsetType_ICH9);
1248	if (fHPETEnabled)
1249	{
1250	InsertConfigNode(pDevices, "hpet", &pDev);
1251	InsertConfigNode(pDev, "0", &pInst);
1252	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1253	InsertConfigNode(pInst, "Config", &pCfg);
1254	InsertConfigInteger(pCfg, "ICH9", (chipsetType == ChipsetType_ICH9) ? 1 : 0); /* boolean */
1255	}
1256
1257	/*
1258	* System Management Controller (SMC)
1259	*/
1260	BOOL fSmcEnabled;
1261	fSmcEnabled = fOsXGuest;
1262	if (fSmcEnabled)
1263	{
1264	InsertConfigNode(pDevices, "smc", &pDev);
1265	InsertConfigNode(pDev, "0", &pInst);
1266	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1267	InsertConfigNode(pInst, "Config", &pCfg);
1268
1269	bool fGetKeyFromRealSMC;
1270	Utf8Str strKey;
1271	vrc = getSmcDeviceKey(virtualBox, pMachine, &strKey, &fGetKeyFromRealSMC);
1272	AssertRCReturn(vrc, vrc);
1273
1274	if (!fGetKeyFromRealSMC)
1275	InsertConfigString(pCfg, "DeviceKey", strKey);
1276	InsertConfigInteger(pCfg, "GetKeyFromRealSMC", fGetKeyFromRealSMC);
1277	}
1278
1279	/*
1280	* Low Pin Count (LPC) bus
1281	*/
1282	BOOL fLpcEnabled;
1283	/** @todo implement appropriate getter */
1284	fLpcEnabled = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1285	if (fLpcEnabled)
1286	{
1287	InsertConfigNode(pDevices, "lpc", &pDev);
1288	InsertConfigNode(pDev, "0", &pInst);
1289	hrc = pBusMgr->assignPCIDevice("lpc", pInst); H();
1290	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1291	}
1292
1293	BOOL fShowRtc;
1294	fShowRtc = fOsXGuest \|\| (chipsetType == ChipsetType_ICH9);
1295
1296	/*
1297	* PS/2 keyboard & mouse.
1298	*/
1299	InsertConfigNode(pDevices, "pckbd", &pDev);
1300	InsertConfigNode(pDev, "0", &pInst);
1301	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1302	InsertConfigNode(pInst, "Config", &pCfg);
1303
1304	KeyboardHIDType_T aKbdHID;
1305	hrc = pMachine->COMGETTER(KeyboardHIDType)(&aKbdHID); H();
1306	if (aKbdHID != KeyboardHIDType_None)
1307	{
1308	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1309	InsertConfigString(pLunL0, "Driver", "KeyboardQueue");
1310	InsertConfigNode(pLunL0, "Config", &pCfg);
1311	InsertConfigInteger(pCfg, "QueueSize", 64);
1312
1313	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1314	InsertConfigString(pLunL1, "Driver", "MainKeyboard");
1315	}
1316
1317	PointingHIDType_T aPointingHID;
1318	hrc = pMachine->COMGETTER(PointingHIDType)(&aPointingHID); H();
1319	if (aPointingHID != PointingHIDType_None)
1320	{
1321	InsertConfigNode(pInst, "LUN#1", &pLunL0);
1322	InsertConfigString(pLunL0, "Driver", "MouseQueue");
1323	InsertConfigNode(pLunL0, "Config", &pCfg);
1324	InsertConfigInteger(pCfg, "QueueSize", 128);
1325
1326	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1327	InsertConfigString(pLunL1, "Driver", "MainMouse");
1328	}
1329
1330	/*
1331	* i8254 Programmable Interval Timer And Dummy Speaker
1332	*/
1333	InsertConfigNode(pDevices, "i8254", &pDev);
1334	InsertConfigNode(pDev, "0", &pInst);
1335	InsertConfigNode(pInst, "Config", &pCfg);
1336	#ifdef DEBUG
1337	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1338	#endif
1339
1340	/*
1341	* i8259 Programmable Interrupt Controller.
1342	*/
1343	InsertConfigNode(pDevices, "i8259", &pDev);
1344	InsertConfigNode(pDev, "0", &pInst);
1345	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1346	InsertConfigNode(pInst, "Config", &pCfg);
1347
1348	/*
1349	* Advanced Programmable Interrupt Controller.
1350	* SMP: Each CPU has a LAPIC, but we have a single device representing all LAPICs states,
1351	* thus only single insert
1352	*/
1353	if (fEnableAPIC)
1354	{
1355	InsertConfigNode(pDevices, "apic", &pDev);
1356	InsertConfigNode(pDev, "0", &pInst);
1357	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1358	InsertConfigNode(pInst, "Config", &pCfg);
1359	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1360	PDMAPICMODE enmAPICMode = PDMAPICMODE_APIC;
1361	if (fEnableX2APIC)
1362	enmAPICMode = PDMAPICMODE_X2APIC;
1363	else if (!fEnableAPIC)
1364	enmAPICMode = PDMAPICMODE_NONE;
1365	InsertConfigInteger(pCfg, "Mode", enmAPICMode);
1366	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1367
1368	if (fIOAPIC)
1369	{
1370	/*
1371	* I/O Advanced Programmable Interrupt Controller.
1372	*/
1373	InsertConfigNode(pDevices, "ioapic", &pDev);
1374	InsertConfigNode(pDev, "0", &pInst);
1375	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1376	InsertConfigNode(pInst, "Config", &pCfg);
1377	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1378	if (enmIommuType == IommuType_AMD)
1379	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1380	else if (enmIommuType == IommuType_Intel)
1381	{
1382	InsertConfigString(pCfg, "ChipType", "DMAR");
1383	InsertConfigInteger(pCfg, "PCIAddress", uIoApicPciAddress);
1384	}
1385	}
1386	}
1387
1388	/*
1389	* RTC MC146818.
1390	*/
1391	InsertConfigNode(pDevices, "mc146818", &pDev);
1392	InsertConfigNode(pDev, "0", &pInst);
1393	InsertConfigNode(pInst, "Config", &pCfg);
1394	BOOL fRTCUseUTC;
1395	hrc = platform->COMGETTER(RTCUseUTC)(&fRTCUseUTC); H();
1396	InsertConfigInteger(pCfg, "UseUTC", fRTCUseUTC ? 1 : 0);
1397
1398	/*
1399	* VGA.
1400	*/
1401	ComPtr<IGraphicsAdapter> pGraphicsAdapter;
1402	hrc = pMachine->COMGETTER(GraphicsAdapter)(pGraphicsAdapter.asOutParam()); H();
1403	GraphicsControllerType_T enmGraphicsController;
1404	hrc = pGraphicsAdapter->COMGETTER(GraphicsControllerType)(&enmGraphicsController); H();
1405	switch (enmGraphicsController)
1406	{
1407	case GraphicsControllerType_Null:
1408	break;
1409	#ifdef VBOX_WITH_VMSVGA
1410	case GraphicsControllerType_VMSVGA:
1411	InsertConfigInteger(pHM, "LovelyMesaDrvWorkaround", 1); /* hits someone else's logging backdoor. */
1412	InsertConfigInteger(pNEM, "LovelyMesaDrvWorkaround", 1); /* hits someone else's logging backdoor. */
1413	InsertConfigInteger(pGcmNode, "MesaVmsvgaDrv", 1); /* hits someone else's logging backdoor. */
1414	RT_FALL_THROUGH();
1415	case GraphicsControllerType_VBoxSVGA:
1416	#endif
1417	case GraphicsControllerType_VBoxVGA:
1418	vrc = i_configGraphicsController(pDevices, enmGraphicsController, pBusMgr, pMachine, pGraphicsAdapter, firmwareSettings);
1419	if (FAILED(vrc))
1420	return vrc;
1421	break;
1422	default:
1423	AssertMsgFailed(("Invalid graphicsController=%d\n", enmGraphicsController));
1424	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1425	N_("Invalid graphics controller type '%d'"), enmGraphicsController);
1426	}
1427
1428	/*
1429	* Firmware.
1430	*/
1431	FirmwareType_T eFwType = FirmwareType_BIOS;
1432	hrc = firmwareSettings->COMGETTER(FirmwareType)(&eFwType); H();
1433
1434	#ifdef VBOX_WITH_EFI
1435	BOOL fEfiEnabled = (eFwType >= FirmwareType_EFI) && (eFwType <= FirmwareType_EFIDUAL);
1436	#else
1437	BOOL fEfiEnabled = false;
1438	#endif
1439	if (!fEfiEnabled)
1440	{
1441	/*
1442	* PC Bios.
1443	*/
1444	InsertConfigNode(pDevices, "pcbios", &pDev);
1445	InsertConfigNode(pDev, "0", &pInst);
1446	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1447	InsertConfigNode(pInst, "Config", &pBiosCfg);
1448	InsertConfigInteger(pBiosCfg, "NumCPUs", cCpus);
1449	InsertConfigString(pBiosCfg, "HardDiskDevice", "piix3ide");
1450	InsertConfigString(pBiosCfg, "FloppyDevice", "i82078");
1451	InsertConfigInteger(pBiosCfg, "IOAPIC", fIOAPIC);
1452	InsertConfigInteger(pBiosCfg, "APIC", uFwAPIC);
1453	BOOL fPXEDebug;
1454	hrc = firmwareSettings->COMGETTER(PXEDebugEnabled)(&fPXEDebug); H();
1455	InsertConfigInteger(pBiosCfg, "PXEDebug", fPXEDebug);
1456	InsertConfigBytes(pBiosCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1457	BOOL fUuidLe;
1458	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1459	InsertConfigInteger(pBiosCfg, "UuidLe", fUuidLe);
1460	BOOL fAutoSerialNumGen;
1461	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1462	if (fAutoSerialNumGen)
1463	InsertConfigString(pBiosCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1464	InsertConfigNode(pBiosCfg, "NetBoot", &pNetBootCfg);
1465	InsertConfigInteger(pBiosCfg, "McfgBase", uMcfgBase);
1466	InsertConfigInteger(pBiosCfg, "McfgLength", cbMcfgLength);
1467
1468	AssertMsgReturn(SchemaDefs::MaxBootPosition <= 9, ("Too many boot devices %d\n", SchemaDefs::MaxBootPosition),
1469	VERR_INVALID_PARAMETER);
1470
1471	for (ULONG pos = 1; pos <= SchemaDefs::MaxBootPosition; ++pos)
1472	{
1473	DeviceType_T enmBootDevice;
1474	hrc = pMachine->GetBootOrder(pos, &enmBootDevice); H();
1475
1476	char szParamName[] = "BootDeviceX";
1477	szParamName[sizeof(szParamName) - 2] = (char)(pos - 1 + '0');
1478
1479	const char *pszBootDevice;
1480	switch (enmBootDevice)
1481	{
1482	case DeviceType_Null:
1483	pszBootDevice = "NONE";
1484	break;
1485	case DeviceType_HardDisk:
1486	pszBootDevice = "IDE";
1487	break;
1488	case DeviceType_DVD:
1489	pszBootDevice = "DVD";
1490	break;
1491	case DeviceType_Floppy:
1492	pszBootDevice = "FLOPPY";
1493	break;
1494	case DeviceType_Network:
1495	pszBootDevice = "LAN";
1496	break;
1497	default:
1498	AssertMsgFailed(("Invalid enmBootDevice=%d\n", enmBootDevice));
1499	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1500	N_("Invalid boot device '%d'"), enmBootDevice);
1501	}
1502	InsertConfigString(pBiosCfg, szParamName, pszBootDevice);
1503	}
1504
1505	/** @todo @bugref{7145}: We might want to enable this by default for new VMs. For now,
1506	* this is required for Windows 2012 guests. */
1507	if (osTypeId == GUEST_OS_ID_STR_X64("Windows2012"))
1508	InsertConfigInteger(pBiosCfg, "DmiExposeMemoryTable", 1); /* boolean */
1509	}
1510	else
1511	{
1512	/* Autodetect firmware type, basing on guest type */
1513	if (eFwType == FirmwareType_EFI)
1514	eFwType = fIsGuest64Bit ? FirmwareType_EFI64 : FirmwareType_EFI32;
1515	bool const f64BitEntry = eFwType == FirmwareType_EFI64;
1516
1517	Assert(eFwType == FirmwareType_EFI64 \|\| eFwType == FirmwareType_EFI32 \|\| eFwType == FirmwareType_EFIDUAL);
1518	#ifdef VBOX_WITH_EFI_IN_DD2
1519	const char *pszEfiRomFile = eFwType == FirmwareType_EFIDUAL ? "VBoxEFIDual.fd"
1520	: eFwType == FirmwareType_EFI32 ? "VBoxEFI32.fd"
1521	: "VBoxEFI64.fd";
1522	#else
1523	Utf8Str efiRomFile;
1524	vrc = findEfiRom(virtualBox, PlatformArchitecture_x86, eFwType, &efiRomFile);
1525	AssertRCReturn(vrc, vrc);
1526	const char *pszEfiRomFile = efiRomFile.c_str();
1527	#endif
1528
1529	/* Get boot args */
1530	Utf8Str bootArgs;
1531	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiBootArgs", &bootArgs);
1532
1533	/* Get device props */
1534	Utf8Str deviceProps;
1535	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiDeviceProps", &deviceProps);
1536
1537	/* Get NVRAM file name */
1538	Utf8Str strNvram = mptrNvramStore->i_getNonVolatileStorageFile();
1539
1540	BOOL fUuidLe;
1541	hrc = firmwareSettings->COMGETTER(SMBIOSUuidLittleEndian)(&fUuidLe); H();
1542
1543	BOOL fAutoSerialNumGen;
1544	hrc = firmwareSettings->COMGETTER(AutoSerialNumGen)(&fAutoSerialNumGen); H();
1545
1546	/* Get graphics mode settings */
1547	uint32_t u32GraphicsMode = UINT32_MAX;
1548	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsMode", &strTmp);
1549	if (strTmp.isEmpty())
1550	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGopMode", &strTmp);
1551	if (!strTmp.isEmpty())
1552	u32GraphicsMode = strTmp.toUInt32();
1553
1554	/* Get graphics resolution settings, with some sanity checking */
1555	Utf8Str strResolution;
1556	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiGraphicsResolution", &strResolution);
1557	if (!strResolution.isEmpty())
1558	{
1559	size_t pos = strResolution.find("x");
1560	if (pos != strResolution.npos)
1561	{
1562	Utf8Str strH, strV;
1563	strH.assignEx(strResolution, 0, pos);
1564	strV.assignEx(strResolution, pos+1, strResolution.length()-pos-1);
1565	uint32_t u32H = strH.toUInt32();
1566	uint32_t u32V = strV.toUInt32();
1567	if (u32H == 0 \|\| u32V == 0)
1568	strResolution.setNull();
1569	}
1570	else
1571	strResolution.setNull();
1572	}
1573	else
1574	{
1575	uint32_t u32H = 0;
1576	uint32_t u32V = 0;
1577	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiHorizontalResolution", &strTmp);
1578	if (strTmp.isEmpty())
1579	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaHorizontalResolution", &strTmp);
1580	if (!strTmp.isEmpty())
1581	u32H = strTmp.toUInt32();
1582
1583	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiVerticalResolution", &strTmp);
1584	if (strTmp.isEmpty())
1585	GetExtraDataBoth(virtualBox, pMachine, "VBoxInternal2/EfiUgaVerticalResolution", &strTmp);
1586	if (!strTmp.isEmpty())
1587	u32V = strTmp.toUInt32();
1588	if (u32H != 0 && u32V != 0)
1589	strResolution = Utf8StrFmt("%ux%u", u32H, u32V);
1590	}
1591
1592	/*
1593	* EFI subtree.
1594	*/
1595	InsertConfigNode(pDevices, "efi", &pDev);
1596	InsertConfigNode(pDev, "0", &pInst);
1597	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1598	InsertConfigNode(pInst, "Config", &pCfg);
1599	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1600	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1601	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1602	InsertConfigString(pCfg, "EfiRom", pszEfiRomFile);
1603	InsertConfigString(pCfg, "BootArgs", bootArgs);
1604	InsertConfigString(pCfg, "DeviceProps", deviceProps);
1605	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1606	InsertConfigInteger(pCfg, "APIC", uFwAPIC);
1607	InsertConfigBytes(pCfg, "UUID", &HardwareUuid,sizeof(HardwareUuid));
1608	InsertConfigInteger(pCfg, "UuidLe", fUuidLe);
1609	if (fAutoSerialNumGen)
1610	InsertConfigString(pCfg, "DmiSystemSerial", "VirtualBox-<DmiSystemUuid>");
1611	InsertConfigInteger(pCfg, "64BitEntry", f64BitEntry); /* boolean */
1612	InsertConfigString(pCfg, "NvramFile", strNvram);
1613	if (u32GraphicsMode != UINT32_MAX)
1614	InsertConfigInteger(pCfg, "GraphicsMode", u32GraphicsMode);
1615	if (!strResolution.isEmpty())
1616	InsertConfigString(pCfg, "GraphicsResolution", strResolution);
1617
1618	/* For OS X guests we'll force passing host's DMI info to the guest */
1619	if (fOsXGuest)
1620	{
1621	InsertConfigInteger(pCfg, "DmiUseHostInfo", 1);
1622	InsertConfigInteger(pCfg, "DmiExposeMemoryTable", 1);
1623	}
1624
1625	/* Attach the NVRAM storage driver. */
1626	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1627	InsertConfigString(pLunL0, "Driver", "NvramStore");
1628	}
1629
1630	/*
1631	* The USB Controllers.
1632	*/
1633	PCFGMNODE pUsbDevices = NULL;
1634	vrc = i_configUsb(pMachine, pBusMgr, pRoot, pDevices, aKbdHID, aPointingHID, &pUsbDevices);
1635
1636	/*
1637	* Storage controllers.
1638	*/
1639	bool fFdcEnabled = false;
1640	vrc = i_configStorageCtrls(pMachine, pBusMgr, pVMM, pUVM,
1641	pDevices, pUsbDevices, pBiosCfg, &fFdcEnabled); VRC();
1642
1643	/*
1644	* Network adapters
1645	*/
1646	std::list<BootNic> llBootNics;
1647	vrc = i_configNetworkCtrls(pMachine, platformProperties, chipsetType, pBusMgr,
1648	pVMM, pUVM, pDevices, llBootNics); VRC();
1649
1650	/*
1651	* Build network boot information and transfer it to the BIOS.
1652	*/
1653	if (pNetBootCfg && !llBootNics.empty()) /* NetBoot node doesn't exist for EFI! */
1654	{
1655	llBootNics.sort(); /* Sort the list by boot priority. */
1656
1657	char achBootIdx[] = "0";
1658	unsigned uBootIdx = 0;
1659
1660	for (std::list<BootNic>::iterator it = llBootNics.begin(); it != llBootNics.end(); ++it)
1661	{
1662	/* A NIC with priority 0 is only used if it's first in the list. */
1663	if (it->mBootPrio == 0 && uBootIdx != 0)
1664	break;
1665
1666	PCFGMNODE pNetBtDevCfg;
1667	achBootIdx[0] = (char)('0' + uBootIdx++); /* Boot device order. */
1668	InsertConfigNode(pNetBootCfg, achBootIdx, &pNetBtDevCfg);
1669	InsertConfigInteger(pNetBtDevCfg, "NIC", it->mInstance);
1670	InsertConfigInteger(pNetBtDevCfg, "PCIBusNo", it->mPCIAddress.miBus);
1671	InsertConfigInteger(pNetBtDevCfg, "PCIDeviceNo", it->mPCIAddress.miDevice);
1672	InsertConfigInteger(pNetBtDevCfg, "PCIFunctionNo", it->mPCIAddress.miFn);
1673	}
1674	}
1675
1676	/*
1677	* Serial (UART) Ports
1678	*/
1679	/* serial enabled mask to be passed to dev ACPI */
1680	uint16_t auSerialIoPortBase[SchemaDefs::SerialPortCount] = {0};
1681	uint8_t auSerialIrq[SchemaDefs::SerialPortCount] = {0};
1682	InsertConfigNode(pDevices, "serial", &pDev);
1683	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::SerialPortCount; ++ulInstance)
1684	{
1685	ComPtr<ISerialPort> serialPort;
1686	hrc = pMachine->GetSerialPort(ulInstance, serialPort.asOutParam()); H();
1687	BOOL fEnabledSerPort = FALSE;
1688	if (serialPort)
1689	{
1690	hrc = serialPort->COMGETTER(Enabled)(&fEnabledSerPort); H();
1691	}
1692	if (!fEnabledSerPort)
1693	{
1694	m_aeSerialPortMode[ulInstance] = PortMode_Disconnected;
1695	continue;
1696	}
1697
1698	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1699	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1700	InsertConfigNode(pInst, "Config", &pCfg);
1701
1702	ULONG ulIRQ;
1703	hrc = serialPort->COMGETTER(IRQ)(&ulIRQ); H();
1704	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1705	auSerialIrq[ulInstance] = (uint8_t)ulIRQ;
1706
1707	ULONG ulIOBase;
1708	hrc = serialPort->COMGETTER(IOAddress)(&ulIOBase); H();
1709	InsertConfigInteger(pCfg, "IOAddress", ulIOBase);
1710	auSerialIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1711
1712	BOOL fServer;
1713	hrc = serialPort->COMGETTER(Server)(&fServer); H();
1714	hrc = serialPort->COMGETTER(Path)(bstr.asOutParam()); H();
1715	UartType_T eUartType;
1716	const char *pszUartType;
1717	hrc = serialPort->COMGETTER(UartType)(&eUartType); H();
1718	switch (eUartType)
1719	{
1720	case UartType_U16450: pszUartType = "16450"; break;
1721	case UartType_U16750: pszUartType = "16750"; break;
1722	default: AssertFailed(); RT_FALL_THRU();
1723	case UartType_U16550A: pszUartType = "16550A"; break;
1724	}
1725	InsertConfigString(pCfg, "UartType", pszUartType);
1726
1727	PortMode_T eHostMode;
1728	hrc = serialPort->COMGETTER(HostMode)(&eHostMode); H();
1729
1730	m_aeSerialPortMode[ulInstance] = eHostMode;
1731	if (eHostMode != PortMode_Disconnected)
1732	{
1733	vrc = i_configSerialPort(pInst, eHostMode, Utf8Str(bstr).c_str(), RT_BOOL(fServer));
1734	if (RT_FAILURE(vrc))
1735	return vrc;
1736	}
1737	}
1738
1739	/*
1740	* Parallel (LPT) Ports
1741	*/
1742	/* parallel enabled mask to be passed to dev ACPI */
1743	uint16_t auParallelIoPortBase[SchemaDefs::ParallelPortCount] = {0};
1744	uint8_t auParallelIrq[SchemaDefs::ParallelPortCount] = {0};
1745	InsertConfigNode(pDevices, "parallel", &pDev);
1746	for (ULONG ulInstance = 0; ulInstance < SchemaDefs::ParallelPortCount; ++ulInstance)
1747	{
1748	ComPtr<IParallelPort> parallelPort;
1749	hrc = pMachine->GetParallelPort(ulInstance, parallelPort.asOutParam()); H();
1750	BOOL fEnabledParPort = FALSE;
1751	if (parallelPort)
1752	{
1753	hrc = parallelPort->COMGETTER(Enabled)(&fEnabledParPort); H();
1754	}
1755	if (!fEnabledParPort)
1756	continue;
1757
1758	InsertConfigNode(pDev, Utf8StrFmt("%u", ulInstance).c_str(), &pInst);
1759	InsertConfigNode(pInst, "Config", &pCfg);
1760
1761	ULONG ulIRQ;
1762	hrc = parallelPort->COMGETTER(IRQ)(&ulIRQ); H();
1763	InsertConfigInteger(pCfg, "IRQ", ulIRQ);
1764	auParallelIrq[ulInstance] = (uint8_t)ulIRQ;
1765	ULONG ulIOBase;
1766	hrc = parallelPort->COMGETTER(IOBase)(&ulIOBase); H();
1767	InsertConfigInteger(pCfg, "IOBase", ulIOBase);
1768	auParallelIoPortBase[ulInstance] = (uint16_t)ulIOBase;
1769
1770	hrc = parallelPort->COMGETTER(Path)(bstr.asOutParam()); H();
1771	if (!bstr.isEmpty())
1772	{
1773	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1774	InsertConfigString(pLunL0, "Driver", "HostParallel");
1775	InsertConfigNode(pLunL0, "Config", &pLunL1);
1776	InsertConfigString(pLunL1, "DevicePath", bstr);
1777	}
1778	}
1779
1780	vrc = i_configVmmDev(pMachine, pBusMgr, pDevices); VRC();
1781
1782	/*
1783	* Audio configuration.
1784	*/
1785	bool fAudioEnabled = false;
1786	vrc = i_configAudioCtrl(virtualBox, pMachine, pBusMgr, pDevices,
1787	fOsXGuest, &fAudioEnabled); VRC();
1788
1789	#if defined(VBOX_WITH_TPM)
1790	/*
1791	* Configure the Trusted Platform Module.
1792	*/
1793	ComObjPtr<ITrustedPlatformModule> ptrTpm;
1794	TpmType_T enmTpmType = TpmType_None;
1795
1796	hrc = pMachine->COMGETTER(TrustedPlatformModule)(ptrTpm.asOutParam()); H();
1797	hrc = ptrTpm->COMGETTER(Type)(&enmTpmType); H();
1798	if (enmTpmType != TpmType_None)
1799	{
1800	InsertConfigNode(pDevices, "tpm", &pDev);
1801	InsertConfigNode(pDev, "0", &pInst);
1802	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1803	InsertConfigNode(pInst, "Config", &pCfg);
1804	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1805
1806	switch (enmTpmType)
1807	{
1808	case TpmType_v1_2:
1809	case TpmType_v2_0:
1810	InsertConfigString(pLunL0, "Driver", "TpmEmuTpms");
1811	InsertConfigNode(pLunL0, "Config", &pCfg);
1812	InsertConfigInteger(pCfg, "TpmVersion", enmTpmType == TpmType_v1_2 ? 1 : 2);
1813	InsertConfigNode(pLunL0, "AttachedDriver", &pLunL1);
1814	InsertConfigString(pLunL1, "Driver", "NvramStore");
1815	break;
1816	case TpmType_Host:
1817	#if defined(RT_OS_LINUX) \|\| defined(RT_OS_WINDOWS)
1818	InsertConfigString(pLunL0, "Driver", "TpmHost");
1819	InsertConfigNode(pLunL0, "Config", &pCfg);
1820	#endif
1821	break;
1822	case TpmType_Swtpm:
1823	hrc = ptrTpm->COMGETTER(Location)(bstr.asOutParam()); H();
1824	InsertConfigString(pLunL0, "Driver", "TpmEmu");
1825	InsertConfigNode(pLunL0, "Config", &pCfg);
1826	InsertConfigString(pCfg, "Location", bstr);
1827	break;
1828	default:
1829	AssertFailedBreak();
1830	}
1831	}
1832	#endif
1833
1834	/*
1835	* ACPI
1836	*/
1837	BOOL fACPI;
1838	hrc = firmwareSettings->COMGETTER(ACPIEnabled)(&fACPI); H();
1839	if (fACPI)
1840	{
1841	/* Always show the CPU leafs when we have multiple VCPUs or when the IO-APIC is enabled.
1842	* The Windows SMP kernel needs a CPU leaf or else its idle loop will burn cpu cycles; the
1843	* intelppm driver refuses to register an idle state handler.
1844	* Always show CPU leafs for OS X guests. */
1845	BOOL fShowCpu = fOsXGuest;
1846	if (cCpus > 1 \|\| fIOAPIC)
1847	fShowCpu = true;
1848
1849	BOOL fCpuHotPlug;
1850	hrc = pMachine->COMGETTER(CPUHotPlugEnabled)(&fCpuHotPlug); H();
1851
1852	InsertConfigNode(pDevices, "acpi", &pDev);
1853	InsertConfigNode(pDev, "0", &pInst);
1854	InsertConfigInteger(pInst, "Trusted", 1); /* boolean */
1855	InsertConfigNode(pInst, "Config", &pCfg);
1856	hrc = pBusMgr->assignPCIDevice("acpi", pInst); H();
1857
1858	InsertConfigInteger(pCfg, "NumCPUs", cCpus);
1859
1860	InsertConfigInteger(pCfg, "IOAPIC", fIOAPIC);
1861	InsertConfigInteger(pCfg, "FdcEnabled", fFdcEnabled);
1862	InsertConfigInteger(pCfg, "HpetEnabled", fHPETEnabled);
1863	InsertConfigInteger(pCfg, "SmcEnabled", fSmcEnabled);
1864	InsertConfigInteger(pCfg, "ShowRtc", fShowRtc);
1865	if (fOsXGuest && !llBootNics.empty())
1866	{
1867	BootNic aNic = llBootNics.front();
1868	uint32_t u32NicPCIAddr = (aNic.mPCIAddress.miDevice << 16) \| aNic.mPCIAddress.miFn;
1869	InsertConfigInteger(pCfg, "NicPciAddress", u32NicPCIAddr);
1870	}
1871	if (fOsXGuest && fAudioEnabled)
1872	{
1873	PCIBusAddress Address;
1874	if (pBusMgr->findPCIAddress("hda", 0, Address))
1875	{
1876	uint32_t u32AudioPCIAddr = (Address.miDevice << 16) \| Address.miFn;
1877	InsertConfigInteger(pCfg, "AudioPciAddress", u32AudioPCIAddr);
1878	}
1879	}
1880	if (fOsXGuest)
1881	{
1882	PCIBusAddress Address;
1883	if (pBusMgr->findPCIAddress("nvme", 0, Address))
1884	{
1885	uint32_t u32NvmePCIAddr = (Address.miDevice << 16) \| Address.miFn;
1886	InsertConfigInteger(pCfg, "NvmePciAddress", u32NvmePCIAddr);
1887	}
1888	}
1889	if (enmIommuType == IommuType_AMD)
1890	{
1891	PCIBusAddress Address;
1892	if (pBusMgr->findPCIAddress("iommu-amd", 0, Address))
1893	{
1894	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1895	InsertConfigInteger(pCfg, "IommuAmdEnabled", true);
1896	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1897	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1898	{
1899	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1900	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1901	}
1902	else
1903	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1904	N_("AMD IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1905	}
1906	}
1907	else if (enmIommuType == IommuType_Intel)
1908	{
1909	PCIBusAddress Address;
1910	if (pBusMgr->findPCIAddress("iommu-intel", 0, Address))
1911	{
1912	uint32_t u32IommuAddress = (Address.miDevice << 16) \| Address.miFn;
1913	InsertConfigInteger(pCfg, "IommuIntelEnabled", true);
1914	InsertConfigInteger(pCfg, "IommuPciAddress", u32IommuAddress);
1915	if (pBusMgr->findPCIAddress("sb-ioapic", 0, Address))
1916	{
1917	uint32_t const u32SbIoapicAddress = (Address.miDevice << 16) \| Address.miFn;
1918	InsertConfigInteger(pCfg, "SbIoApicPciAddress", u32SbIoapicAddress);
1919	}
1920	else
1921	return pVMM->pfnVMR3SetError(pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
1922	N_("Intel IOMMU is enabled, but the I/O APIC is not assigned a PCI address!"));
1923	}
1924	}
1925
1926	InsertConfigInteger(pCfg, "IocPciAddress", uIocPCIAddress);
1927	if (chipsetType == ChipsetType_ICH9)
1928	{
1929	InsertConfigInteger(pCfg, "McfgBase", uMcfgBase);
1930	InsertConfigInteger(pCfg, "McfgLength", cbMcfgLength);
1931	/* 64-bit prefetch window root resource: Only for ICH9 and if PAE or Long Mode is enabled (@bugref{5454}). */
1932	if (fIsGuest64Bit \|\| fEnablePAE)
1933	InsertConfigInteger(pCfg, "PciPref64Enabled", 1);
1934	}
1935	InsertConfigInteger(pCfg, "HostBusPciAddress", uHbcPCIAddress);
1936	InsertConfigInteger(pCfg, "ShowCpu", fShowCpu);
1937	InsertConfigInteger(pCfg, "CpuHotPlug", fCpuHotPlug);
1938
1939	InsertConfigInteger(pCfg, "Serial0IoPortBase", auSerialIoPortBase[0]);
1940	InsertConfigInteger(pCfg, "Serial0Irq", auSerialIrq[0]);
1941
1942	InsertConfigInteger(pCfg, "Serial1IoPortBase", auSerialIoPortBase[1]);
1943	InsertConfigInteger(pCfg, "Serial1Irq", auSerialIrq[1]);
1944
1945	if (auSerialIoPortBase[2])
1946	{
1947	InsertConfigInteger(pCfg, "Serial2IoPortBase", auSerialIoPortBase[2]);
1948	InsertConfigInteger(pCfg, "Serial2Irq", auSerialIrq[2]);
1949	}
1950
1951	if (auSerialIoPortBase[3])
1952	{
1953	InsertConfigInteger(pCfg, "Serial3IoPortBase", auSerialIoPortBase[3]);
1954	InsertConfigInteger(pCfg, "Serial3Irq", auSerialIrq[3]);
1955	}
1956
1957	InsertConfigInteger(pCfg, "Parallel0IoPortBase", auParallelIoPortBase[0]);
1958	InsertConfigInteger(pCfg, "Parallel0Irq", auParallelIrq[0]);
1959
1960	InsertConfigInteger(pCfg, "Parallel1IoPortBase", auParallelIoPortBase[1]);
1961	InsertConfigInteger(pCfg, "Parallel1Irq", auParallelIrq[1]);
1962
1963	#if defined(VBOX_WITH_TPM)
1964	switch (enmTpmType)
1965	{
1966	case TpmType_v1_2:
1967	InsertConfigString(pCfg, "TpmMode", "tis1.2");
1968	break;
1969	case TpmType_v2_0:
1970	InsertConfigString(pCfg, "TpmMode", "fifo2.0");
1971	break;
1972	/** @todo Host and swtpm. */
1973	default:
1974	break;
1975	}
1976	#endif
1977
1978	InsertConfigNode(pInst, "LUN#0", &pLunL0);
1979	InsertConfigString(pLunL0, "Driver", "ACPIHost");
1980	InsertConfigNode(pLunL0, "Config", &pCfg);
1981
1982	/* Attach the dummy CPU drivers */
1983	for (ULONG iCpuCurr = 1; iCpuCurr < cCpus; iCpuCurr++)
1984	{
1985	BOOL fCpuAttached = true;
1986
1987	if (fCpuHotPlug)
1988	{
1989	hrc = pMachine->GetCPUStatus(iCpuCurr, &fCpuAttached); H();
1990	}
1991
1992	if (fCpuAttached)
1993	{
1994	InsertConfigNode(pInst, Utf8StrFmt("LUN#%u", iCpuCurr).c_str(), &pLunL0);
1995	InsertConfigString(pLunL0, "Driver", "ACPICpu");
1996	InsertConfigNode(pLunL0, "Config", &pCfg);
1997	}
1998	}
1999	}
2000
2001	/*
2002	* Configure DBGF (Debug(ger) Facility) and DBGC (Debugger Console).
2003	*/
2004	vrc = i_configGuestDbg(virtualBox, pMachine, pRoot); VRC();
2005	}
2006	catch (ConfigError &x)
2007	{
2008	// InsertConfig threw something:
2009	pVMM->pfnVMR3SetError(pUVM, x.m_vrc, RT_SRC_POS, "Caught ConfigError: %Rrc - %s", x.m_vrc, x.what());
2010	return x.m_vrc;
2011	}
2012	catch (HRESULT hrcXcpt)
2013	{
2014	AssertLogRelMsgFailedReturn(("hrc=%Rhrc\n", hrcXcpt), VERR_MAIN_CONFIG_CONSTRUCTOR_COM_ERROR);
2015	}
2016
2017	#ifdef VBOX_WITH_EXTPACK
2018	/*
2019	* Call the extension pack hooks if everything went well thus far.
2020	*/
2021	if (RT_SUCCESS(vrc))
2022	{
2023	pAlock->release();
2024	vrc = mptrExtPackManager->i_callAllVmConfigureVmmHooks(this, pVM, pVMM);
2025	pAlock->acquire();
2026	}
2027	#endif
2028
2029	/*
2030	* Apply the CFGM overlay.
2031	*/
2032	if (RT_SUCCESS(vrc))
2033	vrc = i_configCfgmOverlay(pRoot, virtualBox, pMachine);
2034
2035	/*
2036	* Dump all extradata API settings tweaks, both global and per VM.
2037	*/
2038	if (RT_SUCCESS(vrc))
2039	vrc = i_configDumpAPISettingsTweaks(virtualBox, pMachine);
2040
2041	#undef H
2042
2043	pAlock->release(); /* Avoid triggering the lock order inversion check. */
2044
2045	/*
2046	* Register VM state change handler.
2047	*/
2048	int vrc2 = pVMM->pfnVMR3AtStateRegister(pUVM, Console::i_vmstateChangeCallback, this);
2049	AssertRC(vrc2);
2050	if (RT_SUCCESS(vrc))
2051	vrc = vrc2;
2052
2053	/*
2054	* Register VM runtime error handler.
2055	*/
2056	vrc2 = pVMM->pfnVMR3AtRuntimeErrorRegister(pUVM, Console::i_atVMRuntimeErrorCallback, this);
2057	AssertRC(vrc2);
2058	if (RT_SUCCESS(vrc))
2059	vrc = vrc2;
2060
2061	pAlock->acquire();
2062
2063	LogFlowFunc(("vrc = %Rrc\n", vrc));
2064	LogFlowFuncLeave();
2065
2066	return vrc;
2067	}

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source: vbox/trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp@ 104760

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